Features

• 32-bit RISC Architecture

• Two Instruction Sets:
– ARM® High-performance 32-bit Instruction Set
– Thumb® High-code-density 16-bit Instruction Set
• Very Low Power Consumption: Industry-leader in MIPS/Watt
• 4G Bytes Linear Address Space
• Von Neumann Load/Store Architecture:
– Single 32-bit Data Bus for Instructions and Data
• 3-Stage Pipeline Architecture:

•
– Fetch, Decode and Execute Stage
8-, 16-, and 32-bit Data Types
Embedded RISC
• Single Cycle 32x8 Hardware Multiplier:
– Multiplication is Accelerated when Upper Bytes Are All Zero or One
Microcontroller
• On-chip JTAG Debug and In Circuit Emulation
• Extensive Range of Third-party Application Development Tools Core
Description
The ARM7TDMI™ embedded microcontroller core is a member of the Advanced
ARM7TDMI™
RISC Machines (ARM®) family of general purpose 32-bit microprocessors, which offer
high performance and very lower power consumption. Its outstanding feature is the
16-bit Thumb ® subset of the most commonly used 32-bit instructions. These are
expanded at run time with no degradation of system performance. This gives 16-bit
code density (saving memory area and cost) coupled with 32-bit processor
performance.
The ARM architecture is based on Reduced Instruction Set Computer (RISC) princi-
ples, and the instruction set and related decode mechanism are much simpler than
those of microprogrammed Complex Instruction Set Computers. This simplicity results
in a high instruction throughput and impressive real-time interrupt response from a
small and cost-effective chip.
Pipelining is employed so that all parts of the processing and memory systems can
operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM memory interface has been designed to allow the performance potential to
be realized without incurring high costs in the memory system. Speed-critical control
signals are pipelined to allow system control functions to be implemented in standard
low-power logic, and these control signals facilitate the exploitation of the fast local
access modes offered by industry standard dynamic RAMs.
The ARM memory interface is also ideally suited to interfacing, either on-chip or off-
chip, with Atmel’s Flash memory blocks. These give the benefits of in-system pro-
grammability and security, reducing time-to-market and system cost.
The ARM7TDMI core is supported by an extensive range of application development
tools. These are fully described in the AT91Business Partners section of Atmels’s
Web site (www.atmel.com).

Rev. 0673CS–11/99

Note: This is a summary document. For the complete 204-page

document, please visit our web site at www.atmel.com or e-mail at1
literature@atmel.com and request literature #0673B.
ARM7TDMI Input/Output Signals
Figure 1. ARM7TDMI Input/Output Signals

MCLK TCK
TMS
Clocks nWAIT TDI
ECLK nTRST
TDO
nIRQ Boundary
TAPSM[3:0]
IR[3:0] Scan
nFIQ
Interrupts nTDOEN
ISYNC TCK1
TCK2
nRESET SCREG[3:0]
BUSEN 11 Boundary Scan
Control Signals
HIGHZ
nM[4:0] Processor
BIGEND Mode
nENIN
nENOUT
ARM7TDMI TBIT Processor
State
Bus
nENOUTI
Controls A[31:0]
ABE
APE
ALE
DOUT[31:0]
APE
DBE
TBE Memory
BUSDIS Interface
D[31:0]
ECAPCLK

VDD
Power DIN[31:0]
VSS
DBGRQ nMREQ
SEQ
BREAKPT
nRW
DBGACK MAS[1:0]
nEXEC
BL[3:0]
EXTERN 1
Debug LOCK
EXTERN 0
nTRANS Memory
DBGEN
ABORT Management
RANGEOUT0
Interface
RANGEOUT1 nOPC
DBGRQI nCPI
CPA Coprocessor
COMMRX
CPB Interface
COMMTX

2 ARM7TDMI
 ARM7TDMI

ARM7TDMI Block Diagram

Figure 2. ARM7TDMI Block Diagram

Scan Chain 2 Scan Chain 0

RANGEOUT0
RANGEOUT1
EXTERN1
ICEBreaker
EXTERN0
nOPC
nRW
MAS[1:0] All
nTRANS Core Other
nMREQ Signals
A[31:0]
•
Scan Chain 1
Bus Splitter

D[31:0]

DIN[31:0]
•
DOUT[31:0]

TCK TDO
TMS TAP TAPSM[3:0]
nTRST Controller IR[3:0]
TDI SCREG[3:0]

As shown in Figure 1 and Figure 2, the ARM7TDMI con- data bus D[31:0] is split into uni-directional input and output
sists of a processor, a TAP controller for boundary scan, buses for compatibility with a wide range of external
and an in-circuit emulator (ICEBreaker). The bi-directional memories.

3
ARM7TDMI Processor Operating Modes
ARM7TDMI supports seven modes of operation:
Figure 3. ARM7TDMI Processor • User (usr):
The normal ARM program execution state
32-Bit Address Bus • FIQ (fiq):
Designed to support a data transfer or channel process
• IRQ (irq):
Address Register
Increment Bus Used for general-purpose interrupt handling
ARM • Supervisor (svc):
PC Bus

Address Instruction Decoder Protected mode for the operating system

&
Incrementer
Control Logic • Abort mode (abt):
Entered after a data or instruction prefetch abort
ALU Bus

37 32-bit Registers
(including 6 status registers) • System (sys):
A privileged user mode for the operating system
B-Bus

32 x 8 Multiplier • Undefined (und):

Instruction
Entered when an undefined instruction is executed
Barrel Shifter
A-Bus

Thumb Mode changes may be made under software control, or

Instruction may be brought about by external interrupts or exception
Decompressor
32-bit ALU processing. Most application programs will execute in User
mode. The non-user modes - known as privileged modes -
Write Data Register Pipeline
are entered in order to service interrupts or exceptions, or
to access protected resources.
32-bit Data Bus
Each operating mode has dedicated banked registers for
fast exception handling. The FIQ mode has five additional
The ARM7TDMI processor is built around a bank of 37 32- banked working registers, r8_fiq to r12_fiq, to enhance
bit registers and six status registers. It features an integral interrupt processing speed.
32 x 8 multiplier and 32-bit barrel shifter. Five independent
internal buses (the PC Bus, the Increment Bus, the ALU
Bus and the A- and B-Buses) allow a high degree of paral-
lelism in instruction execution.

4 ARM7TDMI
 ARM7TDMI

Registers The ARM State Register Set

ARM7TDMI has a total of 37 registers – 31 general-pur- In ARM state, 16 general registers and one or two status
pose 32-bit registers and six status registers – but these registers are visible at any one time. In privileged (non-
cannot all be seen at once. The processor state and oper- User) modes, mode-specific banked registers are switched
ating mode dictate which registers are available to the pro- in. Figure 4 shows which registers are available in each
grammer. mode: the banked registers are marked with a shaded tri-
angle.
The ARM state register set contains 16 directly accessible
registers: R0 to R15. All of these except R15 are general-
purpose, and may be used to hold either data or address
values. In addition to these, there is a seventeenth register
used to store status information.

Figure 4. Register Organization in ARM State

ARM State General Registers and Program Counter

System & User FIQ Supervisor Abort IRQ Undefined
R0 R0 R0 R0 R0 R0

R1 R1 R1 R1 R1 R1

R2 R2 R2 R2 R2 R2

R3 R3 R3 R3 R3 R3

R4 R4 R4 R4 R4 R4

R5 R5 R5 R5 R5 R5

R6 R6 R6 R6 R6 R6

R7 R7 R7 R7 R7 R7

R8 R8_fiq R8 R8 R8 R8

R9 R9_fiq R9 R9 R9 R9

R10 R10_fiq R10 R10 R10 R10

R11 R11_fiq R11 R11 R11 R11

R12 R12_fiq R12 R12 R12 R12

R13 R13_fiq R13_svc R13_abt R13_irq R13_und

R14 R14_fiq R14_svc R14_abt R14_irq R14_und

R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC)

ARM State Program Status Registers

CPSR CPSR CPSR CPSR CPSR CPSR

SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und

= banked register

5
The THUMB State Register Set
The THUMB state register set is a subset of the ARM state CPSR. There are banked Stack Pointers, Link Registers
set. The programmer has direct access to eight general and Saved Process Status Registers (SPSRs) for each
registers, R0-R7, as well as the Program Counter (PC), a privileged mode.
stack pointer register (SP), a link register (LR), and the

Figure 5. Register Organization in Thumb State

THUMB State General Registers and Program Counter

System & User FIQ Supervisor Abort IRQ Undefined

R0 R0 R0 R0 R0 R0

R1 R1 R1 R1 R1 R1

R2 R2 R2 R2 R2 R2

R3 R3 R3 R3 R3 R3

R4 R4 R4 R4 R4 R4

R5 R5 R5 R5 R5 R5

R6 R6 R6 R6 R6 R6

R7 R7 R7 R7 R7 R7

SP SP_fiq SP_svc SP_abt SP_irq SP_und

LR LR_fiq LR_svc LR_abt LR_irq LR_und

PC PC PC PC PC PC

THUMB State Program Status Registers

CPSR CPSR CPSR CPSR CPSR CPSR

SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und

= banked register

6 ARM7TDMI
 ARM7TDMI

ARM7TDMI Architecture instruction has a corresponding 32-bit ARM instruction with

the same effect on the processor model.
The ARM7TDMI is a 3-stage pipeline, 32-bit RISC proces-
The major advantage of a 32-bit (ARM) architecture over a
sor. The processor architecture is Von Neumann load/store
16-bit architecture is its ability to manipulate 32-bit integers
architecture, which is characterized by a single data and
with single instructions, and to address a large address
address bus for instructions and data. The CPU has two
space efficiently. When processing 32-bit data, a 16-bit
instruction sets, the ARM and the Thumb instruction set.
architecture will take at least two instructions to perform the
The ARM instruction set has 32-bit wide instructions and
same task as a single ARM instruction.
provides maximum performance. Thumb instructions are
16-bits wide and give maximum code-density. Instructions However, not all the code in a program will process 32-bit
operate on 8-, 16-, and 32-bit data types. data (for example, code that performs character string han-
dling), and some instructions, like Branches, do not
process any data at all.
The THUMB Concept
If a 16-bit architecture only has 16-bit instructions, and a
The ARM7TDMI processor employs a unique architectural
32-bit architecture only has 32-bit instructions, then overall
strategy known as THUMB, which makes it ideally suited to
the 16-bit architecture will have better code density, and
high-volume applications with memory restrictions, or appli-
better than one half the performance of the 32-bit architec-
cations where code density is an issue.
ture. Clearly 32-bit performance comes at the cost of code
The key idea behind THUMB is that of a super-reduced density.
instruction set. Essentially, the ARM7TDMI processor has
THUMB breaks this constraint by implementing a 16-bit
two instruction sets:
instruction length on a 32-bit architecture, making the pro-
• the standard 32-bit ARM set
cessing of 32-bit data efficient with a compact instruction
• a 16-bit THUMB set coding. This provides far better performance than a 16-bit
The THUMB set’s 16-bit instruction length allows it to architecture, with better code density than a 32-bit
approach twice the density of standard ARM code while architecture.
retaining most of the ARM’s performance advantage over a THUMB also has a major advantage over other 32-bit
traditional 16-bit processor using 16-bit registers. This is architectures with 16-bit instructions. This is the ability to
possible because THUMB code operates on the same 32- switch back to full ARM code and execute at full speed.
bit register set as ARM code. Thus critical loops for applications such as
THUMB code is able to provide up to 65% of the code size • fast interrupts
of ARM, and 160% of the performance of an equivalent • DSP algorithms
ARM processor connected to a 16-bit memory system.
can be coded using the full ARM instruction set, and linked
with THUMB code. The overhead of switching from
The Advantages of THUMB THUMB code to ARM code is folded into sub-routine entry
THUMB instructions operate with the standard ARM regis- time. Various portions of a system can be optimized for
ter configuration, allowing excellent interoperability speed or for code density by switching between THUMB
between ARM and THUMB states. Each 16-bit THUMB and ARM execution as appropriate.

Figure 6. Flexible Selection of ARM or Thumb Instruction Set

Fetch Decode Execute

Phase 1 Phase 2

Mux

32-Bit Data
Mux
16
16 Thumb
Instruction
16 Decom- Mux
pressor
ARM
Instruction
A[1]
Decoder

Thumb State

7
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© Atmel Corporation 1999.

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ARM, Thumb and ARM Powered are registered trademarks of ARM Limited. Printed on recycled paper.
ARM7TDMI is a trademark of ARM Ltd.
Other marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation. 0673CS–11/99/0M
Terms and product names in this document may be trademarks of others.