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Lab 08 Layout: "Design and Implementation of Full Adder at Layout Level in Microwind" 1. Objective

The document describes a lab experiment on designing and implementing a CMOS full adder at the layout level using Microwind. The objectives are to design a full adder layout, implement it using layout design tools, and analyze the gate delay, area, power and current. Students will first design the schematic of a full adder using XOR and NAND gates, then draw the layout in Microwind following design rules. They will simulate the design and observe performance metrics like delay and power for different transistor dimensions and supply voltages. The lab report will include the design diagrams, layout, analysis of design parameters and results.

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Sheikh Abdullah Al Salman
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501 views4 pages

Lab 08 Layout: "Design and Implementation of Full Adder at Layout Level in Microwind" 1. Objective

The document describes a lab experiment on designing and implementing a CMOS full adder at the layout level using Microwind. The objectives are to design a full adder layout, implement it using layout design tools, and analyze the gate delay, area, power and current. Students will first design the schematic of a full adder using XOR and NAND gates, then draw the layout in Microwind following design rules. They will simulate the design and observe performance metrics like delay and power for different transistor dimensions and supply voltages. The lab report will include the design diagrams, layout, analysis of design parameters and results.

Uploaded by

Sheikh Abdullah Al Salman
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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VLSI Design 53

Lab 08 Layout

“Design and Implementation of Full Adder at Layout Level in


Microwind”

1. Objective

In this lab students will design and implement the layout of a CMOS Full Adder.
Delay, area, power and currents of Full Adder will be observed. This lab assumed that
students are familiar with Microwind and Lambda based design rules. The tool used
in this lab is Microwind. The goals for this Lab are:
 Design of CMOS Full Adder Layout.
 Layout Design using the tool.
 Gate delay, area, power and current analysis

2. Theory

CMOS Full Adder

A Full Adder is an important building bock of arithmetic circuits in a system. Full


adder accepts three inputs and produces the outputs sum and carry by adding the
binary bits with the help of logic gates. The Full Adder can be optimized using XOR
and NAND Gates only in the following way.

3. Design Diagram / Circuit

Figure 8.1: Full Adder Gate Level Diagram


VLSI Design 54

Schematic and Layout of the NAND Gate has been done in one or more of the
previous labs. There are many ways to construct the XOR schematic e.g. using
expression, using Transmission gate. We will construct the schematic in the following
way. From the table of XOR Gate.

Table 6.1: Truth Table for XOR

The XOR can be read from the Table as follows: IF B=0, OUT=A, IF B=1, OUT=Inv
(A). The principle of the circuit presented below is to enable the A signal to flow to
node W1 if B=1 and to enable Inv (A) the signal to flow to node W1 if B=0. The
output inverts the node W1 so that we can get the XOR operator.

Figure: Schematic of XOR Gate


Figure 8.2: Schematic of XOR Gate
VLSI Design 55

Figure 8.3 : Layout of XOR Gate


4. Lab Instructions

1. Open Microwind and select the foundry cmos025


2. Save the design as “Save as” as “Lab05”, and save the design frequently
during the lab session.
3. Draw the layout of nMOS using MOS Generator
4. Draw the layout of pMOS using MOS Generator by setting the appropriate
width of pMOS
5. Connect the transistors using Metal 1 as per design.
6. Draw the rails of VDD and ground rails above and below.
7. Connect the nWell to V DD
8. Check the design using DRC for any design rule violation and correct the
design in case of error, again run the DRC and check for errors. Or run the
DRC after each change in the layout.
9. Check for Electrical connections to be valid.
10. Add inputs and outputs to the design; also add virtual capacitance at the output
in your design.
11. Simulate the Design. Observe the values of configuration delay, gate delay,
power, current, VTC, and area.
12. Repeat the design using for different values of transistor’s dimensions, supply
voltages. And observe the changes in configuration delay, gate delay, power,
current, VTC, and area carefully. Make a conclusion of your observations.
VLSI Design 56

Figure 8.4: Simulating Full Adder

5. Lab Report
 Give a short description of the contents of the lab
 Include block diagram/diagrams of your design in the lab report
 Describe your layout design approach
parameters and explain the
effects of each the parameter
 Include layout of your design also add your
name on the design for
evaluation purpose.
 Include the results in timing
waveform format in your report 
Only follow the provided cover page
format.

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