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This document describes a 1Gb GDDR5 SGRAM memory. It provides specifications for features like clocking, initialization, addressing, training modes, mode registers, operations, and timings. The memory uses 32Mx32 banks and supports features such as address training, write training, read training, and refresh operations.

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Datasheet PDF

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H5GQ1H24AFR

1Gb (32Mx32) GDDR5 SGRAM

H5GQ1H24AFR

Revision History
Revision No. History Draft Date Remark

0.1 Defined target spec. Dec. 2008 Preliminary

0.2 Updated tRTPS / tRTW / tFAW / t32AW / Thermal Characteristics Mar. 2009 Preliminary

0.3 Updated tCKE / Pin Cap / CRCWL / CRCRL/ IDD / PLL Value April. 2009 Preliminary

0.4 Updated tRRDL / Revision ID/ Density ID May. 2009 Preliminary

Removed tFLK / tSTDBYLK

0.5 Updated tCKE / tCKSRE / tCKSRX (@ 6Gbps only) May. 2009 Preliminary

0.6 Updated CRCWL / VREFD Selection Coding July. 2009 Preliminary

Updated Auto VREFD Training
Updated tCKE & tPD
Updated Leakage Current
Updated x16 Mode IDD Value & 1.35V Timing Parameters
Updated Ordering Information

0.7 VREFD Options Figure31 change Sep. 2009 Preliminary

1.0 Revision 1.0 Release Nov. 2009

Rev. 1.0/Nov. 2009 2

H5GQ1H24AFR

TABLE OF CONTENTS

FEATURES........................................................................................................................................................5
FEATURES..............................................................................................................................................5
FUNCTIONAL DESCRIPTION....................................................................................................................5
DEFINITION OF SINGLE STATE TERMINOLOGY....................................................................................................7
CLOCKING..........................................................................................................................................................8
INITIALIZATION................................................................................................................................................10
POWER UP SEQUENCE...........................................................................................................................10
INITIALIZATION WITH STABLE POWER..................................................................................................11
VENDOR ID...........................................................................................................................................13
ADDRESS.........................................................................................................................................................15
ADDRESSING.........................................................................................................................................15
ADDRESS BUS INVERSION(ABI)..............................................................................................................16
BAND GROUP........................................................................................................................................18
TRAINING........................................................................................................................................................21
INTERFACE TRAINING SEQUENCE..........................................................................................................21
ADDRESS TRAINING..............................................................................................................................22
WCK2CK TRAINING...............................................................................................................................25
READ TRAINING...................................................................................................................................32
WRITE TRAINING.................................................................................................................................38
MODE REGISTER..............................................................................................................................................41
Mode REGISTER 0(MR0).......................................................................................................................42
Mode REGISTER 1(MR1).......................................................................................................................45
Mode REGISTER 2(MR2).......................................................................................................................48
Mode REGISTER 3(MR3).......................................................................................................................50
Mode REGISTER 4(MR4).......................................................................................................................52
Mode REGISTER 5(MR5).......................................................................................................................55
Mode REGISTER 6(MR6).......................................................................................................................57
Mode REGISTER 7(MR7).......................................................................................................................60
Mode REGISTER 15(MR15)....................................................................................................................62
OPERATION......................................................................................................................................................63
COMMAND.............................................................................................................................................63
DESELECT.............................................................................................................................................65
NO OPERATION.....................................................................................................................................65
MODE REGISTER SET.............................................................................................................................65
ACTIVATION..........................................................................................................................................66
BANK RESTRITIONS...............................................................................................................................68
WRITE (WOM).......................................................................................................................................70
WRITE DATA MAS(DM)...........................................................................................................................89

Rev. 1.0/Nov. 2009 3

H5GQ1H24AFR

READ....................................................................................................................................................86
DQ PREAMBLE .....................................................................................................................................95
READ AND WRITE DATA BUS INVERSION (DBI).......................................................................................97
ERROR DETECTION CODE.....................................................................................................................99
PRECHARGE........................................................................................................................................103
AUTO PRECHARGE...............................................................................................................................104
REFRESH.............................................................................................................................................104
SELF REFRESH....................................................................................................................................106
POWER-DOWN....................................................................................................................................109
COMMAND TRUTH TABLE.....................................................................................................................110
RDQS MODE........................................................................................................................................114
CLOCK FREQUENCY CHANGE SEQUENCE..............................................................................................116
DYNAMIC VOLTAGE SWITCHING(DVS).................................................................................................117
TEMPERATURE SENSOR.......................................................................................................................119
DUTY CYCLE CORRECTOR....................................................................................................................120
OPERATING CONDITIONS................................................................................................................................122
Absolute Maximum Ratings...................................................................................................................122
AC & DC Characteristics........................................................................................................................124
CLOCK TO DATA TIMING SENSITIVITY..................................................................................................148
PACKAGE SPECIFICATION................................................................................................................................151
BALL-OUT...............................................................................................................................................151
SIGNALS.................................................................................................................................................153
ON DIE TERMINATION(ODT)....................................................................................................................156
PACKAGE DIMENSIONS...........................................................................................................................157
MIRROR FUNCTION(MF) ENABLE AND X16 MODE ENABLE.................................................................................158
BOUNDARY SCAN............................................................................................................................................163

FEATURES FUNCTIONAL DESCRIPTION

• Single ended interface for data, address and command The GDDR5 SGRAM is a high speed dynamic

• Quarter data‐rate differential clock inputs CK/CK# for random‐access memory designed for applications
ADR/CMD
• Two half data‐rate differential clock inputs WCK/
requiring high bandwidth. GDDR5 devices contain
WCK#, each associated with two data bytes (DQ, DBI#, the following number of bits:
EDC)
• Double Data Rate (DDR) data (WCK) 1 Gb has 1,073,741,824 bits and sixteen banks
• Single Data Rate (SDR) command (CK)
• Double Data Rate (DDR) addressing (CK)
• 16 internal banks
• 4 bank groups for tCCDL = 3 tCK The GDDR5 SGRAM uses a 8n prefetch
• 8n prefetch architecture: 256 bit per array read or write architecture and DDR interface to achieve high‐
access speed operation. The device can be configured to
• Burst length: 8 only
• Programmable CAS latency: 5 to 20 tCK operate in x32 mode or x16 (clamshell) mode. The
• Programmable WRITE latency: 1 to 7 tCK mode is detected during device initialization. The
• WRITE Data mask function via address bus (single/ GDDR5 interface transfers two 32 bit wide data
double byte mask) words per WCK clock cycle to/from the I/O pins.
• Data bus inversion (DBI) & address bus inversion Corresponding to the 8n‐prefetch a single write or
(ABI)
• Input/output PLL on/off mode read access consists of a 256 bit wide, two CK clock
• Address training: address input monitoring by DQ cycle data transfer at the internal memory core and
pins eight corresponding 32 bit wide one‐half WCK clock
• WCK2CK clock training with phase information by cycle data transfers at the I/O pins.
EDC pins
• Data read and write training via READ FIFO The GDDR5 SGRAM operates from a differential
• READ FIFO pattern preload by LDFF command clock CK and CK#. Commands are registered at
• Direct write data load to READ FIFO by WRTR every rising edge of CK. Addresses are registered at
command every rising edge of CK and every rising edge of
• Consecutive read of READ FIFO by RDTR command CK#.
• Read/Write data transmission integrity secured by
cyclic redundancy check (CRC‐8) GDDR5 replaces the pulsed strobes (WDQS &
• READ/WRITE EDC on/off mode RDQS) used in previous DRAMs such as GDDR4
• Programmable EDC hold pattern for CDR with a free running differential forwarded clock
• Programmable CRC READ latency = 0 to 3 tCK (WCK/WCK#) with both input and output data
• Programmable CRC WRITE latency = 7 to 14 tCK
• Low Power modes registered and driven respectively at both edges of
• RDQS mode on EDC pin the forwarded WCK.
• Optional on‐chip temperature sensor with read‐out Read and write accesses to the GDDR5 SGRAM are
• Auto & self refresh modes burst oriented; an access starts at a selected location
• Auto precharge option for each burst access
• 32ms, auto refresh (8k cycles) and consists of a total of eight data words. Accesses
• Temperature sensor controlled self refresh rate begin with the registration of an ACTIVE command,
• On‐die termination (ODT); nominal values of 60 ohm which is then followed by a READ or WRITE
and 120 ohm command. The address bits registered coincident
• Pseudo open drain (POD‐15) compatible outputs (40 with the ACTIVE command and the next rising CK#
ohm pulldown, 60 ohm pullup)
• ODT and output drive strength auto‐calibration with edge are used to select the bank and the row to be
external resistor ZQ pin (120 ohm) accessed. The address bits registered coincident
• Programmable termination and driver strength offsets with the READ or WRITE command and the next
• Selectable external or internal VREF for data inputs; rising CK# edge are used to select the bank and the
programmable offsets for internal VREF column location for the burst access.
• Separate external VREF for address / command inputs
• Vendor ID, FIFO depth and Density info fields for
identification
• x32/x16 mode configuration set at power‐up with EDC
pin
• Mirror function with MF pin
• Boundary scan function with SEN pin
• 1.6V / 1.5V +/‐ 0.045V supply for device operation
(VDD)
• 1.6V / 1.5V +/‐ 0.045V supply for I/O interface (VDDQ)
• 170 ball BGA package

Rev. 1.0/Nov. 2009 5

H5GQ1H24AFR

ORDERING INFORMATION
Part No Power Supply CK Frequency WCK Frequency Max Data Rate Interface
H5GQ1H24AFR-R0C VDD/VDDQ = 1.6V 1.50GHz 3.00GHz 6.0Gbps/pin
H5GQ1H24AFR-T3C 1.375GHz 2.75GHz 5.5Gbps/pin
H5GQ1H24AFR-T2L (Note1) 1.25GHz 2.50GHz 5.0Gbps/pin POD_15
VDD/VDDQ = 1.5V
H5GQ1H24AFR-T2C 1.25GHz 2.50GHz 5.0Gbps/pin
H5GQ1H24AFR-T1C 1.125GHz 2.25GHz 4.5Gbps/pin
H5GQ1H24AFR-T0C 1.00GHz 2.00GHz 4.0Gbps/pin

Above Hynix P/N’s are Leead-free, RoHS Compliant and Halogen-free.

Note.1)It supports not only 5Gbps @ 1.5V, but also 3.2Gbps @ 1.35V.

Rev. 1.0 /Nov. 2009 6

H5GQ1H24AFR

0.1. DEFINITION OF SIGNAL STATE TERMINOLOGY
GDDR5 SGRAM will be operated in both ODT Enable (terminated) and ODT Disable (unterminated)
modes. For highest data rates it is recommended to operate in the ODT Enable mode. ODT Disable mode
is designed to reduce power and may operate at reduced data rates. There exist situations where ODT
Enable mode can not be guaranteed for a short period of time, i.e. during power up.

Following are four terminologies defined for the state of a device (GDDR5 SGRAM or controller) pin dur‐
ing operation. The state of the bus will be determined by the combination of the device pins connected to
the bus in the system. For example in GDDR5 it is possible for the SGRAM pin to be tristated while the
controller pin is High or ODT. In both cases the bus would be High if the ODT is enabled. For details on
the GDDR5 SGRAM pins and their function see “PACKAGE SPECIFICATION” on page 156 and “SIG‐
NALS” on page 158 in the section entitled “PACKAGE SPECIFICATION” on page 156.

Device pin signal level:
• High: A device pin is driving the Logic “1” state.
• Low: A device pin is driving the Logic “0” state.
• Hi‐Z: A device pin is tristate.
• ODT: A device pin terminates with ODT setting, which could be terminating or tristate depending on Mode
Register setting.

Bus signal level:
• High: One device on bus is High and all other devices on bus are either ODT or Hi‐Z. The voltage level on the bus
would be nominally VDDQ
• Low: One device on bus is Low and all other devices on bus are either ODT or Hi‐Z. The voltage level on the bus
would be nominally VOL(DC) if ODT was enabled, or VSSQ if Hi‐Z.
• Hi‐Z: All devices on bus are Hi‐Z. The voltage level on bus is undefined as the bus is floating.
• ODT: At least one device on bus is ODT and all others are Hi‐Z. The voltage level on the bus would be nominally
VDDQ.

Rev. 1.0/Nov. 2009 7

H5GQ1H24AFR
0.2. CLOCKING
The GDDR5 SGRAM operates from a differential clock CK and CK#. Commands are registered at every
rising edge of CK. Addresses are registered at every rising edge of CK and every rising edge of CK#.

GDDR5 uses a DDR data interface and an 8n‐prefetch architecture. The data interface uses two differen‐
tial forwarded clocks (WCK/WCK#). DDR means that the data is registered at every rising edge of WCK
and rising edge of WCK#. WCK and WCK# are continuously running and operate at twice the frequency
of the command/address clock (CK/CK#).

CK#
CK

COMMAND

ADDRESS

WCK#
WCK

DQ*1

Figure 1: GDDR5 Clocking and Interface Relationship
Note : Figure.1 shows the relationship between the data rate of the buses and the clocks and is not a timing diagram.

Controller GDDR5 SGRAM

CMD sampled by CK/CK# as SDR
ADD/CMD centered with CK/CK# ADD sampled by CK/CK# as DDR

CMD/ADD D Q D Q DRAM
QB core
CMD/ADD

CK/CK#
(1GHz) WCK2CK
Alignment
Oscillator

PLL
Data Tx/Rx Q
D

PLL

WCK/WCK#
(2GHz)
To EDC pin
WCKint
(1GHz)
Clock Phase
early/late Controller

Phase detector/
Phase accumulator Q D
DQ [0]‐[7]
corelogic early/late from (4Gbps)
Q D
calibration data

Receiver
clock DRAM
D Q
DQ core
D Q

Clock Phase
Controller

For 8 data bits

Figure 2: Block Diagram of an example clock system

1. INITIALIZATION
1.1. POWER‐UP SEQUENCE
GDDR5 SGRAMs must be powered up and initialized in a predefined manner as shown in <Link>Figure . Operational
procedures other than those specified may result in undefined operation. The Mode Registers do not have RESET
default values, except for ABI#, ADR/CMD termination, and the EDC hold pattern. If the mode registers are not set dur-
ing the initialization sequence, it may lead to unspecified operation.

Step

1 Apply power to VDD

2 Apply power to VDDQ at same time or after power is applied to VDD

3 Apply VREFC and VREFD at same time or after power is applied to VDDQ

4 After power is stable, provide stable clock signals CK/CK#

5 Assert and hold RESET# low to ensure all drivers are in Hi‐Z and all active terminations are off. Assert and hold NOP command.

6 Wait a minimum of 200μs.

If boundary scan mode is necessary, SEN can be asserted HIGH to enter boundary scan mode. Boundary scan mode must be
7
entered directly after power‐up while RESET# is low. Once boundary scan is executed, power‐up sequence should be followed.

Set CKE# for the desired ADR/CMD ODT settings, then bring RESET# High to latch in the logic state of CKE#, tATS and tATH must
be met during this procedure. See <Link>Table 1 for the values and logic states for CKE#. The rising edge of RESET# will determine
8
x32 mode or x16 mode depending on the state of EDC1(EDC2 when MF=1). In normal x32 mode, EDC1 has to be sustained HIGH
until RESET# is HIGH. See <Link>Table for the values and logic states for EDC1(EDC2 when MF=1).

9 Bring CKE# Low after tATH is satisfied

10 Wait at least 200μs referenced from the beginning of tATS

11 Issue at least 2 NOP commands

12 Issue a PRECHARGE ALL command followed by NOP commands until tRP is satisfied

13 Issue MRS command to MR15. Set GDDR5 SGRAM into address training mode (optional)

14 Complete address training (optional)

15 Issue MRS command to read the Vendor ID

16 Issue MRS command to set WCK01/WCK01# and WCK23/WCK23# termination values

17 Provide stable clock signals WCK01/WCK01# and WCK23/WCK23#

Issue MRS commands to use PLL or not and select the position of a WCK/CK phase detector. The use of PLL and the position of a
phase detector should be issued before WCK2CK training. Issue MRS commands including PLL reset to the mode registers in any
18
order. tMRD must be met during this procedure. WLmrs, CLmrs, CRCWL and CRCRL must be programmed before WCK2CK
training.

19 Issue two REFRESH commands followed by NOP until tRFC is satisfied

After any necessary GDDR5 training sequences such as WCK2CK training, READ training (LDFF, RDTR) and WRITE training
20 (WRTR, RDTR), the device is ready for operation.

Table 1 Address and Command Termination

VALUE (OHMS) CKE# at RESET# high transition

ZQ/2 Low

ZQ High

(( (( ((
)) )) ))
VDD
(( (( ((
)) )) ))
VDDQ

(( (( ((
VREFD/C )) )) ))
tATS tATH

((
))
RESET# (( ((
)) ))

(( (( ((
)) )) ))
CKE# (( (( (( ((
)) )) )) ))
(( (( (( (( (( (( (( (( (( (( ((
CK# )) )) )) )) )) )) )) )) )) )) ))
(( (( (( (( (( (( (( (( (( (( ((
CK )) )) )) )) )) )) )) )) )) )) ))

(( (( (( (( (( (( (( (( (( (( ((
)) )) )) )) )) )) )) )) )) )) ))
CMD (( NOP ((
NOP( ( NOP NOP (( PRE ((
NOP ((
TRAIN / MRS
(( ((
A.C. ((
A.C. ((
((
)) )) )) )) )) )) )) )) )) )) ))

(( (( (( (( (( (( (( (( (( (( ((
)) )) )) )) )) )) )) )) )) )) ))
ADR (( (( (( (( (( (( (( TRAIN / MRS
(( (( ADR ADR
((
ADR ADR
((
)) )) )) )) )) )) )) )) )) )) ))

(( (( (( (( (( (( (( (( (( (( ((
DQ<31:0>, )) )) )) )) )) )) )) )) )) )) ))
(( (( (( (( (( (( ((
TRAIN / MRS
(( (( (( ((
DBI#<3:0> )) )) )) )) )) )) )) )) )) )) ))
(( (( (( (( (( (( (( (( (( ((
)) )) ((
)) )) )) )) )) )) )) ))
))
EDC<3,0> (( (( ((
TRAIN / MRS
(( (( (( ((
)) )) )) )) )) )) ))

(( (( (( (( (( (( (( (( (( (( ((
)) )) )) x32 )) )) )) )) )) )) )) ))
EDC<2,1> (( (( TRAIN / MRS
((
(( (( (( x16 )) ))
(( ((
))
(( (( ((
)) )) )) )) )) )) )) ))

(( (( (( (( (( (( (( (( (( (( ((
WCK# )) )) )) )) )) )) )) )) )) )) ))
(( (( (( (( (( (( (( (( (( (( ((
WCK )) )) )) )) )) )) )) )) )) )) ))

Execution of steps
All Banks 13‐21 in Power‐up
Precharge sequence
min. 200 μs min. 200 μs tRP

Voltages and
CK stable

Note: A.C. = Any Command

Figure 3: GDDR5 SGRAM Power‐up Initialization

1.2. Initialization with Stable Power

The following sequence is required for reset subsequent to power‐up initialization. This requires that the
power has been stable within the specified VDD and VDDQ ranges since power‐up initialization (See
Figure 4)

2) Hold RESET# Low for minimum 100ns. Assert and hold NOP command.

3) Set CKE# for the desired ADR/CMD ODT settings, then bring RESET# High to latch in the logic state of
CKE#; tATS and tATH must be met during this procedure. Keep EDC1 (MF=0) / EDC2 (MF=1) at the same
logic level as during power‐up initialization as device functionality is not guaranteed if the I/O width has
changed.

4) Continue with step 9 of the power‐up initialization sequence.

(( (( ((
)) )) ))
VDD, VDDQ

(( (( ((
VREFD/C )) )) ))
tATS tATH

((
))
RESET# (( ((
)) ))

(( (( ((
)) )) ))
CKE# (( (( (( ((
)) )) )) ))
(( (( (( (( (( (( (( (( (( (( ((
CK# )) )) )) )) )) )) )) )) )) )) ))
(( (( (( (( (( (( (( (( (( (( ((
CK )) )) )) )) )) )) )) )) )) )) ))

(( (( (( (( (( (( (( (( (( (( ((
)) )) )) )) )) )) )) )) )) )) ))
CMD (( NOP ((
NOP( ( NOP NOP (( PRE ((
NOP ((
TRAIN / MRS
(( ((
A.C. (( A.C. ((
((
)) )) )) )) )) )) )) )) )) )) ))

(( (( (( (( (( (( (( (( (( (( ((
)) )) )) )) )) )) )) )) )) )) ))
ADR (( (( (( (( (( (( (( TRAIN / MRS
(( (( ADR ADR
((
ADR ADR
((
)) )) )) )) )) )) )) )) )) )) ))

(( (( (( (( (( (( (( (( (( (( ((
DQ<31:0>, )) )) )) )) )) )) )) )) )) )) ))
(( (( (( (( (( (( ((
TRAIN / MRS
(( (( (( ((
DBI#<3:0> )) )) )) )) )) )) )) )) )) )) ))

(( (( (( (( (( (( (( (( (( (( ((
)) ((
)) )) )) )) )) )) )) )) )) )) ))
EDC<3:0> (( (( (( (( (( (( ((
TRAIN / MRS
(( (( (( ((
)) )) )) )) )) )) )) )) )) )) ))
(( (( (( (( (( (( (( (( (( (( ((
WCK# )) )) )) )) )) )) )) )) )) )) ))
(( (( (( (( (( (( (( (( (( (( ((
WCK )) )) )) )) )) )) )) )) )) )) ))

Execution of steps
All Banks 13‐21 in Power‐up
Precharge sequence
min. 100 ns min. 200 μs tRP

Notes: 1. A.C. = Any Command
2. Device functionality is not guaranteed if x32/x16 mode is not the same as during power‐up initialization.

Figure 4: Initialization with Stable Power

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 12
H5GQ1H24AFR
1.2. VENDOR ID
GDDR5 SGRAMs are required to include a Vendor ID feature that allows the controller to receive informa‐
tion from the GDDR5 SGRAM to differentiate between different vendors and different devices using a
software algorithm.

When the Vendor ID function is enabled the GDDR5 SGRAM will provide its Manufacturers Vendor Code
on bits [3:0] as shown in Table 2; Revision Identification on bits [7:4]; Density on bits [9:8] ; FIFO Depth on
bits [11:10] as shown in Table 3 & Table4. Bits [15:12] are RFU.

Vendor ID is part of the INFO field of Mode Register 3 (MR3) and is selected by issuing a MODE REGIS‐
TER SET command with MR3 bit A6 set to 1, and bit A7 set to 0. MR3 bits A0‐A5 and A8‐A11 are set to the
desired values.

The Vendor ID will be driven onto the DQ bus after the MRS command that sets bits A6 to 1 and A7 to 0.
The DQ bus will be continuously driven until an MRS command sets MR3 A6 and A7 back to 0 to disable
the INFO field or to another valid state for the INFO field if the INFO field includes support for additional
vendor specific information. The DQ bus will be in ODT state after tWRIDOFF (max). The code can be sam‐
pled by the controller after waiting tWRIDON (max) and before tWRIDOFF (min). DBI is not enabled or
ignored during all Vendor ID operations. Table 4 shows the mapping of the Vendor ID info to the physical
DQs. The 16 bits of Vendor ID are sent on Byte 0 and 2 when MF=0. When MF=1 the 16 bits are sent on
Byte 1 and 3. Optionally the vendor may replicate the data on the other 2 bytes when in x32 mode. Byte 0
would be replicated on Byte 1 and Byte 2 would be replicated on Byte 3 when MF=0. When MF=1, Byte 1
would be replicated on Byte 0 and Byte 3 would be replicated on Byte 2.

TABLE 2. Manufacturers Vendor Code
Manufacturers ID Bit 3 Bit 2 Bit 1 Bit 0 Name of Company
0 0 0 0 0 Reserved
1 0 0 0 1 Samsung
2 0 0 1 0 Qimonda
3 0 0 1 1 Elpida
4 0 1 0 0 Etron
5 0 1 0 1 Nanya
6 0 1 1 0 Hynix
7 0 1 1 1 ProMOS
8 1 0 0 0 Winbond
9 1 0 0 1 ESMT
A 1 0 1 0 Reserved
B 1 0 1 1 Reserved
C 1 1 0 0 Reserved
D 1 1 0 1 Reserved
E 1 1 1 0 Reserved
F 1 1 1 1 Micron

Table 3 Revision ID & Density & FIFO Depth
Revision ID Density FIFO
Bit 7 Bit 6 Bit 6 Bit 4 Bit 9 Bit 8 Bit 11 Bit 10
0 0 0 1 0 1 1 0

Table 4 Vendor ID to DQ mapping
Bit 7 6 5 4 3 2 1 0
MF=0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
MF=1 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24
Feature Revision Identification Manufacturers Vendor Code

Bit 15 14 13 12 11 10 9 8
MF=0 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16
MF=1 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8
Feature RFU FIFO Depth Density

CK#
CK

CMD NOP MRS NOP NOP NOP NOP MRS NOP NOP NOP NOP

BA0‐BA3 MRA Code MRA Code

A2‐A5

A8
A7 Code Code

A11
A6 Code Code

A9,A10
A0,A1 Code Code Code Code

tWRIDON(max) tWRIDOFF(min)

DQ Vendor ID + Rev Code

MRA = Mode Register Address; Code = Opcode to be loaded Donʹt Care

Figure 5: Vendor ID Timing Diagram

2. ADDRESS
2.1. ADDRESSING
GDDR5 SGRAMs use a double data rate address scheme to reduce pins required on the GDDR5 SGRAM
as shown in Table 5. The addresses should be provided to the GDDR5 SGRAM in two parts; the first half is
latched on the rising edge of CK along with the command pins such as RAS#, CAS# and WE#; the second
half is latched on the next rising edge of CK#.

The use of DDR addressing allows all address values to be latched in at the same rate as the SDR com‐
mands. All addresses related to command access have been positioned for latching on the initial rising
edge for faster decoding.
Table 5 Address Pairs
Clock

Rising CK BA3 BA2 BA1 BA0 (A12) A11 A10 A9 A8

Rising CK# A3 A4 A5 A2 (RFU) A6 A0 A1 A7

Note: Address pin A12 is required only for 2G density.

GDDR5 addressing includes support for 1G density. For all densities two modes are supported (x32 mode
or x16 mode). x32 and x16 modes differ only in the number of valid column addresses, as shown in Table6.

Table 6 Addressing Scheme
1G

x32 mode x16 mode

Row address A0~A11 A0~A11

Column address A0~A5 A0~A6

Bank address BA0~BA3 BA0~BA3

Autoprecharge A8 A8

Page Size 2K 2K

Refresh 8K/32ms 8K/32ms

Refresh period 3.9us 3.9us

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 15
H5GQ1H24AFR
2.2. ADDRESS BUS INVERSION (ABI)
Address Bus Inversion (ABI) reduces the power requirements on address pins, as the no. of address lines
driving a low level can be limited to 4 (in case A12/RFU is not wired) or 5 (in case A12/RFU is wired).

The Address Bus Inversion function is associated with the electrical signalling on the address lines
between a controller and the GDDR5 SGRAM, regardless of whether the information conveyed on the
address lines is a row or column address, a mode register op‐code, a data mask, or any other pattern.

The ABI# input is an active Low double data rate (DDR) signal and sampled by the GDDR5 SGRAM at the
rising edge of CK and the rising edge of CK# along with the address inputs.

Once enabled by the corresponding ABI Mode Register bit, the GDDR5 SGRAM will invert the pattern
received on the address inputs in case ABI# was sampled Low, or leave the pattern non‐inverted in case
ABI# was sampled High, as shown in Figure 6.
8 (9)
Address 8 (9) to
Pins DRAM
core
ABI#

from Mode Register:
0 = enabled
1 = disabled

Note: bus width is 8 when A12/RFU pin is not present, and 9 when A12/RFU pin is present

Figure 6: Example of Address Bus Inversion Logic

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 16
H5GQ1H24AFR
The flow diagram in Figure 7 illustrates the ABI operation. The controller decides whether to invert or not
invert the data conveyed on the address lines. The GDDR5 SGRAM has to perform the reverse operation
based on the level of the ABI# pin. Address input timing parameters are only valid with ABI being enabled
and a maximum of 4 address inputs driven Low.

Data to be sent
Controller on address lines

Determine ’0’
count

No ’0’ count Yes
> 4 ?

ABI# = ’H’ ABI# = ’L’
Don’t invert Invert

GDDR5 Data received
SGRAM on address lines

Figure 7: Address Bus Inversion (ABI) Flow Diagram

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 17
H5GQ1H24AFR
2.3. BANK GROUPS
For GDDR5 SGRAM devices operating at frequencies above a certain threshold, the activity within a bank
group must be restricted to ensure proper operation of the device. The 8 or 16 banks in GDDR5 SGRAMs
are divided into four bank groups. The bank groups feature is controlled by bits A10 and A11 in Mode
Register 3 (MR3). The assignment of the banks to the bank groups is shown in Table 7.

Table 7 Bank Groups
Addressing 1G
Bank
BA3 BA2 BA1 BA0 16 banks
0 0 0 0 0
1 0 0 0 1
Group A
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
Group B
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
Group C
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
Group D
14 1 1 1 0
15 1 1 1 1

These bank groups allow the specification of different command delay parameters depending on whether
back‐to‐back accesses are to banks within one bank group or across bank groups as shown in Table 8.

Table 8 Command Sequences Affected by Bank Groups
Corresponding AC Timing Parameter
Bank Groups Enabled
Command Sequence Bank Groups Notes
Disabled Accesses to different bank Accesses within the same
groups bank group
ACTIVE to ACTIVE tRRDS tRRDS tRRDL
WRITE to WRITE tCCDS tCCDS tCCDL
READ to READ tCCDS tCCDS tCCDL
Internal WRITE to READ tWTRS tWTRS tWTRL
READ to PRECHARGE tRTPS 1 tck tRTPL 1

Note.1 : Parameters tRTPS and tRTPL apply only when READ and PRECHARGE go to the same bank; use tRTPS when BG are
disabled, and tRTPL when BG are enabled.

Back-to-back column accesses based on tCCDL and tCCDS parameters.

Example 1 (Bank Groups disabled): tCCDS = 2 * tCK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
CLK

CAS A0 A1 B0 B1 C0 C1 D0

DQ A0 A1 B0 B1 C0 C1 D0

Example 2: (Bank Groups enabled): tCCDL = 4 * tCK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
CLK

CAS A0 A1 A2 A3

DQ A0 A1 A2 A3

Example 3: (Bank Groups enabled): tCCDS = 2 * tCK
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
CLK

CAS A0 B0 A1 B1 C0 D0 C1

DQ A0 B0 A1 B1 C0 D0 C1
Notes:
1) Column accesses are to open banks, and tRCD has been met.
2) CL = 0 assumed
3) Ax, Bx, Cx, Dx: accesses to bank groups A, B, C or D, respectively
4) With bank groups enabled, tCCDL is 3tCK, as programmed in MR3.

Rev. 1.0 /Nov. 2009 20

H5GQ1H24AFR

3. TRAINING
3.1. INTERFACE TRAINING SEQUENCE
Due to the high data rates of GDDR5, it is recommended that the interfaces be trained to operate with the
optimal timings. GDDR5 SGRAM has features defined which allow for complete and efficient training of
the I/O interface without the use of the GDDR5 SGRAM array. The interface trainings are required for nor‐
mal DRAM functionality unless running in lower frequency modes as described in the low frequency sec‐
tion. Interface timings will only be guaranteed after all required trainings have been executed.

A recommended order of training sequences has been chosen based on the following criteria:

The address training must be done first to allow full access to the Mode Registers. (MRS for address train‐
ing is a special single data rate mode register set guaranteed to work without training). Address input tim‐
ing shall function without training as long as tAS/H are met at the GDDR5 SGRAM.

WCK2CK training should be done before read training because a shift in WCK relative CK will cause a
shift in all READ timings relative to CK.

READ training should be done before WRITE training because optimal WRITE training depends on cor‐
rect READ data.

Initialization

Address Training (optional)

WCK2CK Alignment Training

READ Training

WRITE Training

Start Normal Operation

Figure 8: Interface Training Sequence

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 21
H5GQ1H24AFR
3.2. ADDRESS TRAINING
The GDDR5 SGRAM provides means for address bus interface training. The controller may use the
address training mode to improve the timing margins on the address bus.

Address training mode is entered and exited via the ADT bit in Mode Register 15 (MR15). Mode Register
15 supports the same setup and hold times on the address pins as for commands to allow a safe entry into
address training mode.

Address training mode uses an internal bridge between the GDDR5 SGRAM’s address inputs and DQ/
DBI# outputs. It also uses a special READ command for address capture that is encoded using the SDR
command pins only (CS#,RAS#,CAS#,WE# = L,H,L,H). The address values normally used to encode the
commands will not be interpreted. Once the address training mode has been entered, the address values
registered coincident with this special READ command will be transmitted to the controller on the DQ/
DBI# pins. The controller is then expected to compare the address pattern received to the expected value
and to adjust the address transmit timing accordingly. The procedure may be repeated using different
address pattern and interface timings.

No WCK clock is required for this special READ command operation during address training mode. The
latched addresses are driven out asynchronously.

The only commands allowed during address training mode are this special READ, MRS (e.g. to exit
address training mode) and NOP / DESELECT.

When enabled by the ABI bit in Mode Register 1, address bus inversion (ABI) is effective during address
training mode. It is suggested to train the ABI# pin’s interface timing together with the other address lines.

The timing diagram in Figure 9 illustrates the typical command sequence in address training mode. The
DQ/DBI# output drivers are enabled as long as the ADT bit is set. The minimum spacing between consec‐
utive special READ commands is 2 tCK.

CK#
CK

CMD MRS NOP READ (*) NOP READ (*) NOP READ (*) NOP MRS NOP NOP NOP NOP

ADDR MR15 ADRx ADRx ADRy ADRy ADRz ADRz MR15

A10=1 R R# R R# R R# A10=0

tMRD tADR tADZ

tADR tADR

Even ADRx ADRy ADRz

DQ R R R

Odd ADRx ADRy ADRz

DQ R# R# R#

Donʹt Care
Notes:
1) READ command encoding: CS# = L, RAS# = H, CAS# = L, WE# = H
2) ADRxR   = 1st half of address x, sampled on rising edge of CK;
    ADRxR# = 2nd half of address x, sampled on rising edge of CK#
3) Addresses sampled on rising edge of CK are returned on even DQ after tADR;
    addresses sampled on rising edge of CK# are returned on odd DQ simultaneously with even DQ
4) DQs are enabled when ADT bit in Mode Register 15 set to 1 (Enter Address Training Mode)
    DQs are disabled after tADZ when ADT bit in Mode Register 15 set to 0 (Exit Address Training Mode)

Figure 9: Address Training Timing

Table 9 AC timings in Address Training Mode
Parameter Symbol Min Max Unit
READ command to data out delay tADR 0.5*tCK+0 0.5*tCK+10 ns
ADT off to DQ/DBI# in ODT state delay tADZ ‐‐ 0.5*tCK+10 ns

Table 10 defines the correspondence between address bits and DQ/DBI#. Devices configured to x16 mode
reflect the address on the two bytes being enabled in that mode, which are bytes 0 and 2 for MF=0 and
bytes 1 and 3 for MF=1 configurations. Devices configured to x32 mode reflect the address on the same DQ
as in x16 mode; in addition they are allowed but not required to reflect the address on those bytes that are
disabled in x16 mode, thus reflecting each address twice.

Devices not supporting an A12/RFU pin shall drive a logic High on the DBI# pins.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 23
H5GQ1H24AFR
Table 10 Address to DQ Mapping in Address Training Mode
Address bits registered at rising edge of CK
Output
A12 A8 A11 BA1 BA2 BA3 BA0 A9 A10
DBI0# DQ22 DQ20 DQ18 DQ16 DQ6 DQ4 DQ2 DQ0
DQ
DBI1# DQ30 DQ28 DQ26 DQ24 DQ14 DQ12 DQ10 DQ8

Address bits registered at rising edge of CK#
Output
RFU A7 A6 A5 A4 A3 A2 A1 A0
DBI2# DQ23 DQ21 DQ19 DQ17 DQ7 DQ5 DQ3 DQ1
DQ
DBI3# DQ31 DQ29 DQ27 DQ25 DQ15 DQ13 DQ11 DQ9

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 24
H5GQ1H24AFR
3.3. WCK2CK TRAINING
The purpose of WCK2CK training is to align the data WCK clock with the command CK clock to aid in the
GDDR5 SGRAM’s internal data synchronization between the logic clocked by CK/CK# and WCK/WCK#.
This will help to define both Read and Write latencies between the GDDR5 SGRAM and memory control‐
ler. WCK2CK training mode is controlled via MRS.

Before starting WCK2CK training, the following conditions must be met:
• CK/CK# clock is stable and toggling
• The timing of all address and command pins must be guaranteed
• PLL on/off(MR1 bit A7) and PLL delay compensation enable(MR7 bit A2) are set to desired mode before WCK to
CK training is started
• The desired WCK2CK alignment point (MR6, bit A0) is selected
• The EDC hold pattern (MR4, bits A0‐A3) must be programmed to ‘1111’
• 2 Mode Register bits for internal WCK01 and WCK23 inversion (MR3, bits A2‐A3) must be set to a known state
• All banks are idle and no other command execution is in progress

WCK2CK training must be done after any of the following conditions:
• Device initialization
• Any CLmrs, WLmrs, CRCRL or CRCWL latency change
• CK and WCK frequency changes
• PLL on/off(MR1 bit A7) and PLL delay compensation mode(MR7 bit A2) changes
• Change of the WCK2CK alignment point (MR6, bit A0)
• WCK state change from off to toggling, including self refresh exit or exit from power‐down when bit A1 (LP2) in
MR5 is set

Figure 10 and Figure 11 show example WCK2CK training sequences. WCK2CK training is entered via
MRS by setting bit A4 in MR3. This will initiate the WCK divide‐by‐2 circuits associated with WCK01 and
WCK23 clocks in the GDDR5 SGRAM. In case the divide‐by‐2 circuits are at opposite output phases,
which is indicated by opposite “early/late” phases on the EDC pins associated with WCK01 and WCK23
(see below), they may be put in phase by using the WCK01 and WCK23 inversion bits. Alternatively, the
WCK clocks may be put into a stable inactive state for this initialization event to aid in resetting all divid‐
ers to the same output phase as shown in <Link>Figure 11. The challenge of this method is to restart the
WCK clocks in a way that even their first clock edges meet the WCK clock input specification. Otherwise,
divide‐by‐2 circuits for both WCK01 and WCK23 might again have opposite phase alignment.

Figure 12 illustrates how the WCK phase information is derived. The phase detectors (PD) sample the
internally divided‐by‐2 WCK clocks. Only one sample point is shown in the figure for clarity. In reality,
when WCK2CK training mode is enabled, a sample will occur every tCK and will be translated to the EDC
pins accordingly. If the divided‐by‐2 WCK clock arrives early, then the EDC pin outputs the EDC hold
pattern during the time interval specified in Figure 12. If the divided‐by‐2 WCK clock arrives late, then the
EDC pin outputs the inverted EDC hold pattern during the time interval specified in Figure 12. This is
shown in Table 11.

CK
CK#

CMD NOP NOP MRS NOP NOP NOP NOP MRS MRS A.C.

WCK
WCK#

tLK tMRD

Enter WCK2CK Training Start WCK2CK PLL Reset Exit WCK2CK Training

Phase Search (PLL on only) (sets data synchronizers,
rests FIFO pointers)

Figure 10: Example WCK2CK Training Sequence

CK#

CMD NOP MRS NOP NOP NOP NOP NOP NOP MRS MRS Valid

WCK

WCK#

tWCK2MRS tMRSTWCK tWCK2TR tLK tMRD

Enter WCK2CK WCK Start WCK2CK PLL Reset Exit WCK2CK

Training by MRS Restart Phase Search (PLL on only) Training by MRS
(resets WCK divide‐ (Set data synchronizers,
by‐2 circuits) resets FIFO pointers)

Figure 11: Example WCK2CK Training Sequence with WCK Stopping

CK
1

WCK01/2
WCK23/2
(internal)
‐ tWCK2CK
WCK Early
1 Early EDC0 x x x x x x x x x x x x x x x
1 1 1 1
EDC2
~
~ tWCKTPH

WCK01/2 0
WCK23/2
(internal)
+ tWCK2CK WCK Late
EDC0 x x x x x x x x x x x x x x x
2 Late 0 0 0 0
EDC2
~
~

tWCKTPH

WCK01/2
WCK23/2
(internal)

EDC0
3 Aligned x x x x x x x x x x x x x x x x x x x
EDC2
~
~

tWCKTPH

Figure 12: EDC pin Behaviour for WCK2CK Training (assumes ‘1111’ as EDC Hold Pattern)

Table 11 Phase Detector and EDC Pin behavior
WCK/2 value sampled by CK WCK2CK Phase Data on EDC Pin Action

‘1’ ‘Early’ EDC hold (‘1111’) Increase Delay on WCK

‘0’ ‘Late’ Inverted EDC Hold (‘0000’) Decrease Delay on WCK

The ideal alignment is indicated by the phase detector output transitioning from “early” to “late” when
the delay of the WCK phase is continuously increased. The WCK phase range for ideal alignment is speci‐
fied by the parameter tWCK2CKPIN ; the value(s) vary with the PLL mode (on or off) and the selected align‐
ment point.

If enabled, the PLL shall not interfere in the behavior of the WCK2CK training. Significantly moving the
phase and/or stopping the WCK during training may disturb the PLL. It is required to perform a PLL reset
after the WCK2CK training has determined and selected the proper alignment between WCK and CK
clocks. The PLL lock time tLK must be met before exiting WCK2CK training to guarantee that the PLL is in
lock such that the GDDR5 SGRAM data synchronizers are set upon WCK2CK training exit.

WCK2CK training is exited via MRS by resetting bit A4 in MR3. For proper reset of the data synchronizers
it is required that the WCK and CK clocks are aligned within tWCK2CKSYNC at the time of the WCK2CK
training exit.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 27
H5GQ1H24AFR
After exiting WCK2CK training mode, the WCK phase is allowed to further drift from the ideal alignment
point by a maximum of tWCK2CK (e.g. due to voltage and temperature variation). Once this WCK phase
drift exceeds tWCK2CK(min) or tWCK2CK(max), it is required to repeat the WCK2CK training and realign
the clocks.

WCK2CK alignment at PIN Mode
The WCK and CK phase alignment point can be changed via MRS by setting bit A0 in MR6. In normal
mode, when MR6 A0 is set to ‘0’, the phases of CK and WCK are aligned at CK pins and the end of WCK
tree as shown in Figure 13. On the other hand, when MR6 A0 is set to ‘1’, the phases of CK and WCK are
aligned at the pin as shown in Figure 14. PIN mode is supported up to the max CK clock frequency of
fCKPIN, and is an option to reduce the time of WCK2CK training at low frequency.

D Q
WCK CK
WCK# Internal WCK/2
Phase
Detector
CK
CK# Internal CK

EDC

Figure 13: Normal Mode

D Q
WCK
CK
WCK# Internal WCK/2
Phase
Detector
CK
CK# Internal CK

EDC

Figure 14: Pin Mode

WCK2CK Auto Synchronization
GDDR5 SGRAMs support a WCK2CK automatic synchronization mode that eliminates the need for
WCK2CK training upon power‐down exit. This mode is controlled by the autosync bit (MR7, bit A4), and
is effective when the LP2 bit (MR5, bit A1) is set and the WCK clocks are stopped during power‐down.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 28
H5GQ1H24AFR
Also, this mode works for both normal and PIN mode. When WCK2CK automatic synchronization mode
is enabled, a full WCK2CK training including Phase search is not required after power‐down exit,
although WCK2CK MRS must be issued momentarily for setting the data synchronizers. However, WCK
and CK clocks must meet the tWCK2CKSYNC specification upon power‐down exit. Any allowed command
may be issued after tXPN or after tLK in case the PLL had been enabled upon power‐down entry. The PLL
sequence is not affected by this mode. The use of WCK2CK automatic synchronization mode is restricted
to lower operating frequencies up to fCKAUTOSYNC as described in the datasheets.

Table 12 describes WCK2CK training methods for different frequency ranges. Each Frequency range is
vendor specific. Normal and PIN mode of WCK2CK training are described in Table 12. Each frequency
range is DRAM vendor specific. Divider initialization can be done by training with WCK2CK inversion,
WCK2CK stopping, or WCK2CK auto‐sync. If the user wants to use WCK2CK stop for divider initializa‐
tion instead of WCK2CK auto‐sync, the user must not set the WCK2CK auto‐sync. Low frequency, the
combined use of PIN and WCK2CK auto‐sync modes can minimize WCK2CK training time.

Table 12 WCK2CK training simplified for Normal mode and PIN mode
High Frequency Low Frequency

Frequency ≥ 2Gbps ＜ 2Gbps

WCK2CK alignment mode Normal PIN Normal PIN

Phase Search Required Required No* No*

* Note: The divided WCK/WCK# should be aligned CK/CK# by WCK2CK Auto Synchronization or WCK stop mode

The following examples describe the WCK2CK training in more detail.

Example 1: outline of a basic WCK2CK training sequence without WCK clock stop:

1) Enable training mode via MRS and wait tMRD
2) Sweep and observe the phase independently for WCK01 on EDC0 and WCK23 on EDC2; in case
                the internal divide‐by‐2 circuits are at opposite phase use either the WCK01 or WCK23 inversion
bit
                to flip one of the WCK divide‐by‐2 circuits
3) Adjust the WCK phase independently for WCK01 and WCK23 to the optimal point (“ideal
                alignment”)
4) Issue a PLL reset and wait for tLK (PLL on mode only)
5) While all WCK and CK are aligned, exit WCK2CK training mode via MRS
6) Wait tMRD for the reset of data synchronizers

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 29
H5GQ1H24AFR
Example 2: outline of a basic WCK2CK training sequence with optional WCK clock stop:

1) Stop WCK clocks with WCK01/WCK23 LOW and WCK01#/WCK23# HIGH
2) Wait tWCK2MRS for internal WCK clocks to settle
3) Enable training mode via MRS and wait tMRD for divide‐by‐2 circuits to reset
4) Start WCK clocks without glitches (both divide‐by‐2 circuits remain in sync)
5) Wait tWCK2TR for internal WCK clocks to stabilize
6) Sweep and observe the phase independently for WCK01 on EDC0 and WCK23 on EDC2; adjust
the
WCK phase to the optimal point (“ideal alignment”)
7) Issue a PLL reset and wait tLK (PLL on mode only)
8) While all WCK and CK are aligned, exit WCK2CK training mode via MRS
9) Wait tMRD for the reset of data synchronizers

READ and WRITE latency timings are defined relative to CK. Any offset in WCK and CK at the pins and/
or the phase detector will be reflected in the latency timings. The parameters used to define the relation‐
ship between WCK and CK are shown in Figure 6. For more details on the impact on READ and WRITE
timings see the OPERATIONS section.

tCK tCH tCL

CK#
CK

Case 1: Negative tWCK2CKPIN; tWCK2CK = 0 (ideal WCK2CK alignment)
tWCKH tWCKL tWCK
tWCK2CKPIN
WCK#
WCK

Case 2: Negative tWCK2CKPIN; negative tWCK2CK
tWCK2CKPIN + tWCK2CK
WCK#
WCK

Case 3: Positive tWCK2CKPIN; tWCK2CK = 0 (ideal WCK2CK alignment)
tWCK2CKPIN
WCK#
WCK

Case 4: Positive tWCK2CKPIN; positive tWCK2CK
tWCK2CKPIN + tWCK2CK
WCK
WCK#

Note: tWCK2CKPIN and tWCK2CK parameter values could be negative or positive numbers, depending on the selected
WCK2CK alignment point, PLL‐on‐or PLL‐off mode operation and design implementation. They also vary across
PVT. WCK2CK training is required to determine the correct WCK‐to‐CK phase for stable device operation.

Figure 15: WCK2CK Timings

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 30
H5GQ1H24AFR
GDDR5 WCK2CK Training in x16 mode
For configurations with WCK clocks not shared between two GDDR5 SGRAMs it is suggested to set the
WCK phase to the ideal alignment point. However, for configurations where two GDDR5 SGRAMs (x16)
share their WCK clocks as in a x16 clamshell, an offset given by the midpoint of both DRAM’s ideal WCK
positions may be required. The maximum allowed offset in this case is specified by parameter
tWCK2CKSYNC: it defines the WCK offset range from the ideal alignment which still guarantees a GDDR5
SGRAM device to internally synchronize its WCK and CK clocks upon training exit.

Example: outline of training sequence for x32 and x16 configurations with 2 GDDR5 SGRAMs sharing
their WCK clocks (e.g. clamshell):

1) Enable training mode for both DRAMs via MRS and wait tMRD
2) For both DRAMs sweep and observe the phase independently for WCK01 on EDC0 and WCK23
on
               EDC2; in case the internal divide‐by‐2 circuits are at opposite phases use either the WCK01 or
               WCK23 inversion bit to flip one of the WCK divide‐by‐2 circuits; in case of shared CS# signals use
               MREMF0 and MREMF1 bits in MR15 to explicitly direct the MRS command for this phase flipping
                 to either DRAM1 or DRAM2 (“soft chip select”);
3) Sweep and observe the phase on DRAM1 independently for WCK01 on EDC0 and WCK23 on
                EDC2; store the setting for the optimal WCK phase
4) Sweep and observe the phase on DRAM2 independently for WCK01 on EDC0 and WCK23 on
                EDC2; store the setting for the optimal WCK phase
5) Sweep WCK01 and WCK23 phase to midpoint of DRAM1 and DRAM2 optimal settings
6) Issue a PLL reset and wait for tLK (PLL on mode only)
7) While all WCK and CK are aligned, exit WCK2CK training mode via MRS
8) Wait tMRD for the reset of data synchronizers

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 31
H5GQ1H24AFR
3.4. READ TRAINING
Read training allows the memory controller to find the data‐eye center (symbol training) and burst frame
location (frame training) for each high‐speed output of the GDDR5 SGRAM. Each pin (DQ0‐DQ31, DBI0#‐
DBI3#, EDC0‐EDC3) can be individually trained during this sequence.

For Read Training the following conditions must be true:
• at least one bank is active, or an auto refresh must be in progress and bit A2 in Mode Register 5 (MR5) is set to 0 to
allow training during auto refresh (to disable this special REF enabling of the WCK clock tree an ACT command
must be issued, or the device must be set into power‐down or self refresh mode)
• WCK2CK training must be complete
• the PLL must be locked, if enabled
• RDBI and WDBI must be enabled prior to and during Read Training if the training shall include the DBI# pins.
RDCRC and WRCRC must be enabled prior to and during Read Training if the training shall include the EDC
pins.
The following commands are associated with Read Training:
• LDFF to preload the Read FIFO;
• RDTR to read a burst of data directly out of the Read FIFO.
Neither LDFF nor RDTR access the memory core. No MRS is required to enter Read Training.

Figure 16 shows an example of the internal data paths used with LDFF and RDTR. Table 13 lists AC timing
parameters associated with Read Training.

Table 13 LDFF and RDTR TIMINGS
VALUES
PARAMETER SYMBOL UNIT NOTES
MIN MAX

ACTIVE to LDFF command delay tRCDLTR 10 – ns

ACTIVE to RDTR command delay tRCDRTR 10 – ns

REFRESH to RDTR or WRTR command delay tREFTR 10 – ns

RDTR to RDTR command delay tCCDS 2 – tCK

LDFF to LDFF command cycle time tLTLTR 4 – tCK

LDFF(111) to LDFF command cycle time tLTL7TR 4 – tCK a

LDFF(111) to RDTR command delay tLTRTR 4 – tCK

READ or RDTR to LDFF command delay tRDTLT 4 – tCK

a. The min. value does not exceed 8 tCK.

Serial to Parallel
Converter e.g. 500Mbps
RX 9 8:1 72 DQ Reverse 64
72
DBI

WRTR strobe
(CK domain) WRTR

FIFO 6 × 72=432 bits per byte M DRAM

U CRC8
DQ0‐DQ7
e.g. 4Gbps X Core
DBI0#

0 1 2 3 4 5 6 7 72
8 9 10 11 12 13 14 15
M
16 17 18 19 20 21 22 23 72 U DBI 64
Parallel to Serial X
Converter 24 25 26 27 28 29 30 31
TX 9 8:1 72 32 33 34 35 36 37 38 39 72
e.g. 40 41 42 43 44 45 46 47
500Mbps WRTR
48 49 50 51 52 53 54 55 LDFF

56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71

0 1 2 3 4 0 1 2 3 4 5 M
input WRTR strobe
RDTR strobe output U
(WCK) pointer pointer LDFF strobe (burst 7)
X
CRC FIFO 6 × 8 =48 bits per byte
M 8
8 U
Parallel to Serial X 8
Converter
EDC0 TX 8:1 8 0 1 2 3 4 5 6 7 DEMUX
LDFF BA0‐BA2
0 1 2 3 4 0 1 2 3 4 5
M CRC strobe 10
output input
RDTR strobe pointer U
(WCK) pointer Address
X LDFF strobe (burst 7)
Path

ADDR RX 8

Notes: Data path used with LDFF
1) FIFO depth of 5 shown; supported FIFO depths: 4, 5 or 6
Data path used with WRTR
2) data paths shown for 1 of 4 bytes (byte 0)
Data path used with LDFF/WRTR
Data path used with RDTR

Figure 16: Data Paths used for Read and Write Training
LDFF Command
The LDFF command (Figure 17) is used to securely load data to the GDDR5 SGRAM Read FIFOs via the
address bus. Depending on the GDDR5 SGRAM READ FIFO depth nFIFO 6, any bit pattern of length 32‐
48 can be loaded uniquely to every DQ, DBI# and EDC pin within a byte. The FIFO depth is fixed by
design and can be read via the Vendor ID function.

Eight LDFF commands are required to fill one FIFO stage; each LDFF command loads one burst position,
and the bank addresses BA0‐BA2 select the burst position from 0 to 7.

The data pattern is conveyed on address pins A0‐A7 for DQ0‐DQ7, A9 for DBI0#, and BA3 for EDC0; the
data are internally replicated to all 4 bytes, as shown in Figure 18.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 33
H5GQ1H24AFR
LDFF loads the DBI FIFO regardless of the WDBI and RDBI Mode Register bits. It also loads the EDC FIFO
regardless of the WRCRC and RDCRC Mode Register bits, and no CRC is calculated; however, RDBI and
RDCRC must be enabled to read the DBI and EDC bits, respectively, with the RDTR command.

LDFF
CK#

CKE# LOW

CS#

RAS#

CAS#

WE#

A9, BA3
DATA DATA
A1, A3

A8,A10,A11
0,0,1 DATA
A0,A7,A6

BA0‐BA2 DATA
BP
A2, A4,A5

BP = Burst Position
DATA = FIFO data

Figure 17: LDFF Command

LDFF Command Address‐to‐DQ Mapping 1 FIFO STAGE = 1 BURST

CK# Byte 0 Byte 1 Byte 2 Byte 3 0 1 2 3 4 5 6 7

CK A0 DQ0 DQ8 DQ16 DQ24
L A10 A0
A1 DQ1 DQ9 DQ17 DQ25
A9 A1
BA0 A2
A2 DQ2 DQ10 DQ18 DQ26
BA3 A3
BA2 A4
A3 DQ3 DQ11 DQ19 DQ27
BA1 A5
H A11 A6
A4 DQ4 DQ12 DQ20 DQ28
L A8 A7
A5 DQ5 DQ13 DQ21 DQ29

A6 DQ6 DQ14 DQ22 DQ30

A7 DQ7 DQ15 DQ23 DQ31

A9 DBI0# DBI1# DBI2# DBI3#

BA3 EDC0 EDC1 EDC2 EDC3

Burst Position
0 1 2 3 4 5 6 7
BA2 0 0 0 0 1 1 1 1
BA1 0 0 1 1 0 0 1 1
BA0 0 1 0 1 0 1 0 1

LDFF FIFO Load Pulse

Figure 18: LDFF Command Address to DQ/DBI#/EDC Mapping
All burst addresses 0 to 7 must be loaded; LDFF commands to burst address 0 to 6 may be issued in ran‐
dom order; the LDFF command to burst address 7 (LDFF7) must be the last of 8 consecutive LDFF com‐
mands, as it effectively loads the data into the FIFO and results in a FIFO pointer increment. Consecutive
LDFF commands have to be spaced by at least tLTLTR, and at least tLTL7TR cycles are required after each
LDFF command to burst address 7.

LDFF pattern may efficiently be replicated to the next FIFO stages by issuing consecutive LDFF commands
to burst address 7 (with identical data pattern). The data pattern in the scratch memory for LDFF will be
available until the first RDTR command.

The DQ/DBI# output buffers remain in ODT state during LDFF.

An amount of LDFF commands to burst address 7 greater than the FIFO depth is allowed and shall result
in a looping of the FIFO’s data input.

The total number of LDFF commands to burst address 7 modulo FIFO depth must equal the total number
of RDTR commands modulo FIFO depth when used in conjunction with RDTR. No READ or WRITE com‐
mands are allowed between LDFF and RDTR.

The EDC hold pattern is driven on the EDC pins during LDFF (provided RDQS mode is not enabled).

RDTR Command
A RDTR burst is initiated with a RDTR command as shown in Figure 19. No bank or column addresses are
used as the data is read from the internal READ FIFO, not the array. The length of the burst initiated with
a RDTR command is eight. There is no interruption nor truncation of RDTR bursts.

RDTR
CK#

CKE# LOW

CS#

RAS#

CAS#

WE#

A9 (A12)
A1

A8,A10,A11
0,1,1
A7,A0,A6

BA0‐BA3
A2‐A5

Figure 19: RDTR Command

A RDTR command may only be issued when a bank is open or a refresh is in progress and bit A2 in MR5
is set to 0 to allow training during refresh.

RDBI and RDCRC must be enabled to read the DBI and EDC bits, respectively, with the RDTR command.
If not set, the DBI# pins will remain in ODT state, and the EDC pins will drive the EDC hold pattern.

In case of the RDQS mode, the EDC pin functions like with a normal READ in this mode. The DBI# pin
behaves like a DQ, and no encoding with DBI is performed.

An amount of RDTR commands greater than the FIFO depth is allowed and shall result in a looping of the
FIFO’s data output. The FIFO depth from which the RDTR data is read must be a number between 4‐6 and
must be specified by the DRAM vendor. The FIFO depth is read via the Vendor ID function.

During RDTR bursts, the first valid data‐out element will be available after the CAS latency (CL). The
latency is the same as for READ. The data on the EDC pins comes with additional CRC latency (tCRCRD)
after the CL.

Upon completion of a burst, assuming no other RDTR command has been initiated, all DQ and DBI# pins
will drive a value of ʹ1ʹ and the ODT will be enabled at a maximum of 1 tCK later. The drive value and ter‐
mination value may be different due to separately defined calibration offsets. If the ODT is disabled, the
pins will drive Hi‐Z.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 36
H5GQ1H24AFR
Data from any RDTR burst may be concatenated with data from a subsequent RDTR command. A contin‐
uous flow of data can be maintained. The first data element from the new burst follows the last element of
a completed burst. The new RDTR command should be issued after the first RDTR command according to
the tCCDS timing.

A WRTR can be issued any time after a RDTR command as long as the bus turn around time tRTW is met.

The total number of RDTR commands modulo FIFO depth must be equal to total number of WRTR com‐
mands modulo FIFO depth when used in conjunction with WRTR. No READ or WRITE commands are
allowed between WRTR and RDTR.

The total number of RDTR commands modulo FIFO depth must be equal to the total number of LDFF
commands to burst position 7 modulo FIFO depth when used in conjunction with LDFF. No READ or
WRITE commands are allowed between LDFF and RDTR.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 37
H5GQ1H24AFR
3.5. WRITE TRAINING
Write training allows the memory controller to find the data‐eye center (symbol training) and burst frame
location (frame training) for each high‐speed input of the GDDR5 SGRAM. Each pin (DQ0‐DQ31, DBI0#‐
DBI3#) can be individually trained during this sequence.

For Write Training the following conditions must be true:
• at least one bank is active, or an auto refresh must be in progress and bit A2 in Mode Register 5 (MR5) is set to 0 to
allow training during auto refresh (to disable this special REF enabling of the WCK clock tree an ACT command
must be issued, or the device must be set into power‐down or self refresh mode)
• the PLL must be locked, if enabled.
• WCK2CK training should be complete
• Read training should be complete
• RDBI and WDBI must be enabled prior to and during Write Training if the training shall include the DBI# pins.
RDCRC and WRCRC must be enabled prior to and during Write Training if the training shall include the EDC
pins.
The following commands are associated with Write Training:
• WRTR to write a burst of data directly into the Read FIFO;
• RDTR to read a burst of data directly out of the Read FIFO.
Neither WRTR nor RDTR access the memory core. No MRS is required to enter Write Training.

Figure 16 shows an example of the internal data paths used with WRTR and RDTR. Figure 21 shows a typ‐
ical Write training command sequence using WRTR and RDTR. Table 14 lists AC timing parameters asso‐
ciated with WRITE Training.

Table 14 WRTR and RDTR Timings
VALUES
PARAMETER SYMBOL UNIT NOTES
MIN MAX

ACTIVE to WRTR command delay tRCDWTR 10 – ns

ACTIVE to RDTR command delay tRCDRTR 10 – ns

REFRESH to RDTR or WRTR command delay tREFTR 10 – ns

RD/WR bank A to RD/WR bank B command delay a
different bank groups tCCDS 2 – tCK

WRTR to RDTR command delay tWTRTR WL‐tWLmin – tCK

WRITE to WRTR command delay tWRWTR WL+CRCWL+2 – tCK

READ or RDTR to WRITE or WRTR command delay tRTW 1 – ns b

a. tCCDS is either for gapless consecutive READ or RDTR (any combination), gapless consecutive WRITE, or gapless consecutive
WRTR commands.
b. tRTW is not a device limit but determined by the system bus turnaround time. The difference between tWCK2DQO and tWCK2DQI
shall be considered in the calculation of the bus turnaround time.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 38
H5GQ1H24AFR
WRTR Command
A WRTR burst is initiated with a WRTR command as shown in Figure 20. No bank or column addresses
are used as the data is written to the internal READ FIFO, not the array. The length of the burst initiated
with a WRTR command is eight. There is no interruption nor truncation of WRTR bursts.

WRTR
CK#

CKE# LOW

CS#

RAS#

CAS#

WE#

A9 (A12)
A1

A8,A10,A11
0,1,1
A7,A0,A6

BA0‐BA3
A2‐A5

Figure 20: WRTR Command

A WRTR command may only be issued when a bank is open or a refresh is in progress and bit A2 in MR5
is set to 0 to allow training during refresh.

WDBI and WRCRC must be enabled to write the DBI and EDC bits, respectively, with the WRTR com‐
mand. If WDBI is not set, a ‘1’ will be written to the DBI FIFO, and a ‘1’ will be assumed for the DBI# input
in the CRC calculation. In contrast to a normal WRITE, no CRC is returned by the WRTR command and
the EDC pins will drive the EDC hold pattern.

In case of the RDQS mode, the EDC pin functions like with a normal READ in this mode. Please note that
RDCRC must be enabled to read the calculated CRC data with the RDTR command.

An amount of WRTR commands equal to the FIFO depth is required to fully load the FIFO; any number of
WRTR commands greater than the FIFO depth is allowed and shall result in a looping of the FIFO’s data
input. The FIFO depth to which the WRTR data is written must be 6. The FIFO depth is read via the Ven‐
dor ID function.

During WRTR bursts, the first valid data‐in element must be available at the input latch after the Write
Latency (WL). The Write Latency is the same as for WRITE.

Upon completion of a burst, assuming no other WRTR data is expected on the bus the GDDR5 SGRAM
DQ and DBI# pins will be driven according to the ODT state. Any additional input data will be ignored.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 39
H5GQ1H24AFR
Data from any WRTR burst may be concatenated with data from a subsequent WRTR command. A contin‐
uous flow of data can be maintained. The first data element from the new burst follows the last element of
a completed burst. The new WRTR command should be issued after the previous WRTR command
according to the tCCDS timing.

A RDTR can be issued any time after a WRTR command as long as the internal bus turn around time
tRTWTR is met.

The total number of WRTR commands modulo FIFO depth must equal the total number of RDTR com‐
mands modulo FIFO depth when used in conjunction with RDTR. No READ or WRITE commands are
allowed between WRTR and RDTR.

T0 T1 T2 T3 T4 T5 Ta Ta+1 Ta+2 Ta+3 Ta+4

CK#
CK

CMD WRTR NOP WRTR NOP NOP NOP RDTR NOP RDTR NOP NOP

ADDR

WLmrs WLmrs tWTRTR CLmrs CRCRL CLmrs CRCRL

WCK
WCK#
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7

D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
DQ
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
EDC EDC Hold EDC Hold EDC Hold EDC Hold EDC Hold EDC Hold EDC Hold EDC Hold

Donʹt Care
1. WLmrs, CLmrs and CRCRL set to 1 for ease of illustration; check Mode Register definition for supported settings
2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

Figure 21: Write Training using WRTR and RDTR Commands

4. MODE REGISTERS
GDDR5 specifies 10 Mode Registers to define the specific mode of operation. MR0 to MR7 and MR15 are defined as shown in
the overview in Figure 22. MR8 to MR13 are not defined and may be used by DRAM vendors for vendor specific features. Repro-
gramming the Mode Registers will not alter the contents of the memory array.
All Mode Registers are programmed via the MODE REGISTER SET (MRS) command and will retain the stored information until
they are reprogrammed or the device loses power. Mode Registers must be loaded when all banks are idle and no bursts are in
progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these
requirements will result in unspecified operation.
No default states are defined for Mode Registers except when otherwise noted. Users therefore must fully initialize all Mode Reg-
isters to the desired values e.g. upon power-up.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result. RFU bits are
reserved for future use and must be programmed to 0. Bit A12 is not used for any mode register programming as this address input
is not defined for 1G density.

BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Write Latency
MR0 0 0 0 0 0 Write Recovery (WR) TM CAS Latency (CLmrs)
(WLmrs)

PLL Cal ADR/CMD Data Driver

MR1 0 0 0 1 0 Reset ABI
WDBI RDBI PLL
Upd Termination Termination Strength

ADR/CMD Data and WCK OCD Pullup OCD Pulldown

MR2 0 0 1 0 0
Termination Offset Termination Offset Driver Offset Driver Offset

Bank WCK RDQS WCK WCK WCK

MR3 0 0 1 1 0 Groups Termination Info Mode 2CK 23Inv 01Inv Self Refresh

CRC Read
EDC WR RD CRC Write Latency
MR4 0 1 0 0 0 13Inv CRC CRC Latency

(CRCWL) EDC Hold Pattern
(CRCRL)

PLL Bandwidth
MR5 0 1 0 1 0 RFU (PLLBW) LP3 LP2 RFU

VREFD Offset VREFD Offset Auto VREFD WCK

MR6 0 1 1 0 0
Upper 2 bytes Lower 2 bytes
VREFD
VREFD Merge PIN

Half Temp DQ Auto LF

MR7 0 1 1 1 0 DCC RFU
VREFD Sense PreA Sync Mode
RFU

MR14 RFU

MRE MRE
MR15 1 1 1 1 0 RFU ADT MF1 MF0 X X X X X X X X

Figure 22. Mode Registers Overview

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 41
H5GQ1H24AFR
4.1. MODE REGISTER 0 (MR0)
Mode Register 0 controls operating modes such as Write Latency, CAS latency, Write Recovery and Test
Mode as shown in Figure 23.
The register is programmed via the MODE REGISTER SET (MRS) command with BA0=0, BA1=0, BA2=0
and BA3=0.

BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 Write Recovery (WR) TM CAS Latency (CLmrs) Write Latency

(WLmrs)

Write Recovery A7 Test Mode Write Latency

A11 A10 A9 A8 A2 A1 A0
(WR) (WLmrs)
0 Normal
0 0 0 0 4 0 0 0 RFU
1 Test Mode
0 0 0 1 5 0 0 1 1
0 0 1 0 6 0 1 0 2
0 0 1 1 7 0 1 1 3
0 1 0 0 8 1 0 0 4
0 1 0 1 9 1 0 1 5
0 1 1 0 10 1 1 0 6
0 1 1 1 11 1 1 1 7
1 0 0 0 12
1 0 0 1 13 A6 A5 A4 A3 CAS Latency (CLmrs)
1 0 1 0 14
0 0 0 0 5
1 0 1 1 15
0 0 0 1 6
1 1 0 0 16
0 0 1 0 7
1 1 0 1 17
0 0 1 1 8
1 1 1 0 18
0 1 0 0 9
1 1 1 1 19
0 1 0 1 10
0 1 1 0 11
0 1 1 1 12
1 0 0 0 13
1 0 0 1 14
1 0 1 0 15
1 0 1 1 16
1 1 0 0 17
1 1 0 1 18
1 1 1 0 19
1 1 1 1 20

Figure 23. Mode Register 0 (MR0) Definition

WRITE Latency (WLmrs)
The WRITE latency (WLmrs) is the delay in clock cycles used in the calculation of the total WRITE latency
(WL) between the registration of a WRITE command and the availability of the first piece of input data.
DRAM vendor specifications should be checked for value(s) of WLmrs supported. The full WRITE latency
definition can be found in the section entitled OPERATION.
When the WRITE latencies are set to small values (i.e. 1,2,... clocks), the input receivers never turn off, in
turn, raising the operating power. When the WRITE latency is set to higher values (i.e. .. 6, 7 clocks) the input
receivers turn on when the WRITE command is registered. Refer to vendor datasheets for value(s) of
WLmrs where the input receivers are always on or only turn on when the WRITE command is registered

Allowable Operating Frequency (Gbps)
Speed
WL7 WL6 WL5 WL4 WL3 WL2 WL1
6.0Gbps
5.5Gbps
5.0Gbps
4.5Gbps
4.0Gbps

CAS Latency (CLmrs)
The CAS latency (CLmrs) is the delay in clock cycles used in the calculation of the total READ latency
(CL) between the registration of a READ command and the availability of the first piece of output data.

By default CLmrs is specified by bits A3‐A6, defining a CLmrs range of 5 to 20 tCK.
DRAM vendor specifications should be checked for value(s) of CLmrs supported. The full READ latency
definition can be found in the section entitled OPERATION

RDBI Allowable Operating Frequency (Gbps)
Speed
ON/OFF CL20 CL19 CL18 CL17 CL16 CL15 CL14 CL13 CL12
OFF
6.0Gbps
ON
OFF
5.5Gbps
ON
OFF
5.0Gbps
ON
OFF
4.5Gbps
ON
OFF
4.0Gbps
ON

Rev. 1.0 /Nov. 2009 43

H5GQ1H24AFR

WRITE Recovery (WR)
The programmed WR value is used for the auto precharge feature along with tRP to determine tDAL. The
WR register bits are not a required function and may be implemented at the discretion of the DRAM
manufacturer.
WR must be programmed with a value greater than or equal to RU{tWR/tCK}, where RU stands for round
up, tWR is the analog value from the vendor datasheet and tCK is the operating clock cycle time.
By default WR is specified by bits A8‐A11, defining a WR range of 4 to 19 tCK.
Test Mode
The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A7 set to
’0’, and bits A0‐A6 and A8‐A11 set to the desired values. Programming bit A7 to ‘1’ places the device into a
test mode that is only to be used by the DRAM manufacturer. No functional operation is specified with test
mode enabled.

Rev. 1.0 /Nov. 2009 44

H5GQ1H24AFR
4.2. MODE REGISTER 1 (MR1)
Mode Register 1 controls functions like drive strength, data termination, address/command termination,
Read DBI, Write DBI, ABI, control of calibration updates and PLL as shown in Figure 24.
The register is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=0, BA2=0
and BA3=0. Bits A0‐A1, A4‐A6 and A10 of this register are initialized with’0’s.

BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 1 0 PLL ABI WDBI RDBI PLL Cal ADR/CMD Data Driver

Reset Upd Termination Termination Strength

A1 A0 Driver Strength

0 0 Auto Calibration On
A11 PLL Reset A7 PLL 0 1 RFU
0 No 0 Off 1 0 Nominal (60/40)
1 Yes 1 On 1 1 RFU

A10 ABI A6 Calibration Update A3 A2 Data Termination

0 On 0 On 0 0 Disabled
1 Off 1 Off 0 1 ZQ/2
1 0 ZQ
1 1 RFU

A9 Write DBI A8 Read DBI

0 On 0 On
A5 A4 ADD/CMD Termination
1 Off 1 Off
0 0 CKE# value at Reset
0 1 ZQ/2
1 0 ZQ
1 1 Disabled

Figure 24. Mode Register 1 (MR1) Definition

Impedance Autocalibration of Output Buffer and Active Terminator
GDDR5 SGRAMs offer autocalibrating impedance output buffers and on‐die terminations. This enables a
user to match the driver impedance and terminations to the system within a given range. To adjust the
impedance, an external precision resistor is connected between the ZQ pin and VSSQ. A nominal resistor

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 45
H5GQ1H24AFR
value of 120 Ohms is equivalent to the 40 Ohms Pulldown and 60 Ohms Pullup nominal impedances of
GDDR5 SGRAMs. RESET#, CK and CK# are not internally terminated. CK and CK# shall be terminated on
the system using external 1% resistors to VDDQ.
The output driver and on‐die termination impedances are updated during all REFRESH commands to
compensate for variations in supply voltage and temperature. The impedance updates are transparent to
the system.
Driver Strength
Bits A0 and A1 define the driver strength. The Auto Calibration setting enables the Auto‐Calibration
functionality for the Pulldown, Pullup and Termination over process, temperature and voltage changes.
The design target for the factory setting is 40 Ohm Pulldown, 60 Ohm Pullup driver strength with nominal
process, voltage and temperature conditions.
The nominal option enables the factory setting for the Pulldown, Pullup driver strength and termination.
With this option enabled, driver strength and termination are expected to change with process, voltage
and temperature. AC timings are only guaranteed with Auto Calibration.
Data Termination
Bits A2 and A3 define the data termination value for the on‐die termination (ODT) for the DQ and DBI#
pins in combination with the driver strength setting.
The termination can be set to a value of ZQ/2 which is intended for a single loaded system, or ZQ which
is intended for a weaker termination used in a lower power or frequency applications. The data
termination may also be turned off.
ADR/CMD Termination
Bits A4 and A5 define the address/command termination. The default setting (’00’) provides that the
address/command termination is determined by latching CKE# on the rising edge of RESET#.
The address/command termination can also be set to a value of ZQ/2 which is intended for a single
loaded system, or ZQ which is intended for double loaded configurations with two devices sharing a
common address/command bus. The address/command termination may also be turned off.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 46
H5GQ1H24AFR
Calibration Update
The Calibration Update setting enables the calibration value to be updated automatically by the auto
calibration engine. The function is enabled upon power‐up to reduce update induced jitter. The user may
decide to suppress updates from the auto calibration engine by disabling Calibration Update (A6=1).
The calibration updates can occur with any REFRESH command. The update is not complete for a time
tKO after the latching of the REFRESH command. During this tKO time, only NOP or DESELECT
commands may be issued
PLL and PLL Reset
If a PLL is to be used, it must be enabled for normal operation by setting bit A7 to ’1’.
A PLL reset is done by turning the PLL off then on, or by use of the PLL Reset bit A11. The PLL Reset bit
is self clearing meaning that it returns back to the value ‘0’ after the PLL reset function has been issued.
RDBI and WDBI
Bit A8 controls Data Bus Inversion (DBI) for READs (RDBI), and bit A9 controls Data Bus Inversion for
WRITEs (WDBI). For more details on DBI see READ and WRITE Data Bus Inversion (DBI) in the section
entitled OPERATION.
ABI
Address Bus Inversion (ABI) is selected independently from DBI using bit A10. When enabled any data
sent over the address bus (whether opcode, addresses, LDFF data or DM) is inverted or not inverted based
on the state of ABI# signal. For more details on ABI see Address Bus Inversion (ABI) in the section entitled
OPERATION.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 47
H5GQ1H24AFR
4.3. MODE REGISTER 2 (MR2)
Mode Register 2 defines the output driver (OCD) and termination offsets as shown in Figure 25.
Mode Register 2 is programmed via the MODE REGISTER SET (MRS) command with BA0=0, BA1=1,
BA2=0 and BA3=0.

BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

ADR/CMD Data and WCK OCD Pullup OCD Pulldown

0 0 1 0 0 Termination Offset Termination Offset Driver Offset Driver Offset

A8 A7 A6 Data and WCK A2 A1 A0 OCD Pulldown
Termination Offset Driver Offset

0 0 0 0 0 0 0 0
0 0 1 +1 0 0 1 +1
0 1 0 +2 0 1 0 +2
0 1 1 +3 0 1 1 +3
1 0 0 ‐4 1 0 0 ‐4
1 0 1 ‐3 1 0 1 ‐3
1 1 0 ‐2 1 1 0 ‐2
1 1 1 ‐1 1 1 1 ‐1

A11 A10 A9 ADR/CMD A5 A4 A3 OCD Pullup

Termination Offset Driver Offset

0 0 0 0 0 0 0 0
0 0 1 +1 0 0 1 +1
0 1 0 +2 0 1 0 +2
0 1 1 +3 0 1 1 +3
1 0 0 ‐4 1 0 0 ‐4
1 0 1 ‐3 1 0 1 ‐3
1 1 0 ‐2 1 1 0 ‐2
1 1 1 ‐1 1 1 1 ‐1

Figure 25. Mode Register 2 (MR2) Definition

Impedance Offsets
The driver and termination impedances may be offset individually for PD driver, PU driver, DQ/DBI#/
WCK termination and address/command termination. The offset impedance step values may be non‐
linear and will vary across PVT. With negative offset steps the drive strengths will be decreased and Ron

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 48
H5GQ1H24AFR
will be increased. With positive offset steps the drive strengths will be increased and Ron will be
decreased. With negative offset steps the termin‐ation value will be increased. With positive offset steps
the termination value will be decreased.
IV curves and AC timings are only guaranteed with zero offset.

Offset
PU Driver
Pullup
Impedance
Autocalibrated
ZQ Impedance
Calibration
Engine
120 Offset
Ohms PD Driver
Pulldown
Impedance
Auto/Fixed
VSSQ
nominal (60/40) Offset
ADD/CMD Termination ADD/CMD
Fixed Impedance Termination
Impedance

Offset
Note: sum of offset + auto‐ DQ/DBI#/WCK Termination DQ/DBI#/WCK
calibrated impedance cannot Termination
exceed maximum / minimum Impedance
available impedance steps

Figure 26. Impedance Offsets

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 49
H5GQ1H24AFR
4.4. MODE REGISTER 3 (MR3)
Mode Register 3 controls functions including Bank Groups, WCK termination, self refresh, RDQS mode,
DRAM Info and WCK2CK training as shown in Figure 27.
Mode Register 3 is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=1,
BA2=0 and BA3=0.

BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Bank WCK RDQS WCK WCK WCK

0 0 1 1 0 Groups Termination Info Mode 2CK 23Inv 01Inv Self Refresh

A11 A10 Bank Groups A1 A0 Self Refresh

0 X off / tCCDL = 2 tCK 0 0 32 ms

1 X on / tCCDL = 3 tCK 0 1 16ms
1 0 8ms
1 1 RFU

A9 A8 WCK Termination
RDQS A2 WCK01 Invert
A5 Mode
0 0 Disabled
0 Off
0 1 ZQ/2 0 Off
1 On
1 0 ZQ 1 On
1 1 RFU
A3 WCK23 Invert

0 Off
A7 A6 DRAM Info 1 On

0 0 off
0 1 Vendor ID A4 WCK2CK Training
1 0 Temperature Readout 0 Off
1 1 RFU 1 On

Figure 27. Mode Register 3 (MR3) Definition

Self Refresh
The refresh interval in self refresh mode may be set to 32ms, 16ms and 8ms.

WCK2CK

Bit A4 (WCK2CK) enables and disables the WCK2CK alignment training. For details on this training
sequence, see the section on TRAINING.

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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 50
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WCK01 / WCK23 Inversion
Bits A2 and A3 control whether the internal phase of the WCK01 and WCK23 clock inputs after internal
divide‐by‐2 shall be inverted, corresponding to a 2 U.I. phase shift. The bits are used in conjunction with
WCK2CK training mode.
RDQS Mode
Bit A5 enables the RDQS mode of the GDDR5 SGRAM. In this mode the EDC pins will act as a READ
strobe (RDQS). No CRC is supported in RDQS mode, and all related bits in MR4 will be ignored. A
detailed description of the RDQS mode can be found in the section entitled OPERATION.
DRAM Info
Bits A6 and A7 enable the DRAM Info mode which is provided to output the Vendor ID, or the current
junction temperature.
The Vendor ID identifies the manufacturer of the GDDR5 SGRAM, and provides the die revision,
memory density and FIFO depth.
The Temperature Readout provides the SGRAM’s junction temperature. The on‐chip temperature sensor
is enabled in advance by bit A6 in MR7.
WCK Termination
Bits A8 and A9 define the termination value for the on‐die termination (ODT) for the WCK01, WCK01#,
WCK23 and WCK23# pins in combination with the driver strength setting.
The termination can be set to a value of ZQ/2 which is intended for a single loaded system, or ZQ which
is intended for double load configurations with two devices sharing the WCK clocks. The WCK
termination may also be turned off.
Bank Groups
Bit A11 enables the bank groups feature. With A11 set to ‘1’, the bank groups feature is enabled and
tCCDL is 3tCK.

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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 51
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4.5. MODE REGISTER 4 (MR4)
Mode Register 4 defines the Error Detection Code (EDC) features of GDDR5 SGRAMs as shown in
Figure 28.
The register is programmed via the MODE REGISTER SET (MRS) command with BA0=0, BA1=0, BA2=1
and BA3=0. Bits A0‐A3 (EDC Hold Pattern) of this register are initialized with ’1111’.

BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

CRC Read
0 1 0 0 0 EDC WR RD Latency CRC Write Latency EDC Hold Pattern
13Inv CRC CRC

(CRCWL)
(CRCRL)

EDC Hold Pattern Invert A3 A2 A1 A0 EDC Hold Pattern
A11
for EDC1 + EDC3
0 0 0 0 Pattern
EDC hold pattern not
0 ...
inverted
1 1 1 1 Pattern
1 EDC hold pattern inverted
Burst Burst Burst Burst
Pos 3 Pos 2 Pos 1 Pos 0

A10 WR CRC A9 RD CRC

0 On 0 On
A6 A5 A4 CRC Write Latency (CRCWL)
1 Off 1 Off
0 0 0 N/A
0 0 1 8
0 1 0 9
A8 A7 CRC Read Latency (CRCRL) 0 1 1 10
0 0 0 1 0 0 11
0 1 1 1 0 1 12
1 0 2 1 1 0 13
1 1 3 1 1 1 14

Figure 28. Mode Register 4 (MR4) Definition

EDC Hold pattern / EDC13 Invert
The 4‐bit EDC hold pattern is considered a background pattern transmitted on the EDC pins. The register
is initialized with all ’1’s. The pattern is shifted from right to left and repeated with every clock cycle. The
output timing is the same as of a READ burst.
CRC bursts calculated from WRITEs or READs will replace the EDC hold pattern for the duration of
those bursts, provided CRC is enabled for those bursts.
With each MRS command to MR4 that changes bits A0‐A3 or A9‐A11, the EDC hold pattern will be
undefined for tMRD.

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responsability for use of circuits described. No patent licenses are implied.
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The EDC hold pattern will not be transmitted when the device is in address training mode, in WCK2CK
training mode, in RDQS mode, in self refresh mode, in reset state, in power‐down state with the LP2 bit
set, or in scan mode.
With register bit A11 set High, EDC1 and EDC3 will transmit the inverted EDC hold pattern, resulting in
a pseudo‐differential pattern. Please note that this function is not available in x16 configuration. Bit A11 is
ignored for READ, WRITE and RDTR CRC bursts and the clock phase information in WCK2CK training
mode.

CRC Write Latency (CRCWL)
The value of the CRC write latency is loaded into register bits A4‐A6. If the DRAM vendor does not
support the Mode Register definition of CRCWL, the Mode Register settings will be ignored. In that case
the valid fixed latency is given with the DRAM vendor’s specification. The user must set the CRCWL
Mode Register bits.

Allowable Operating Frequency (Gbps)
Speed
CRCWL14 CRCWL13 CRCWL12 CRCWL11 CRCWL10 CRCWL9 CRCWL8
6.0Gbps
5.5Gbps
5.0Gbps
4.5Gbps
4.0Gbps

CRC Read Latency (CRCRL)
The value of the CRC read latency is loaded into register bits A7‐A8. If the DRAM vendor does not support
the Mode Register definition of CRCRL, the Mode Register settings will be ignored. In that case the valid
fixed latency is given with the DRAM vendor’s specification. The user must set the CRCRL Mode Register
bits.

RDBI Allowable Operating Frequency (Gbps)
Speed
ON/OFF CRCRL3 CRCRL2 CRCRL1 CRCRL0
OFF
6.0Gbps
ON
OFF
5.5Gbps
ON
OFF
5.0Gbps
ON
OFF
4.5Gbps
ON
OFF
4.0Gbps
ON

Read CRC
Bit A9 controls the CRC calculation for READ bursts. When enabled, the calculated CRC pattern will be
transmitted on the EDC pins with the latency as programmed in the CRCRL field of this register. With
Read CRC being off, no CRC will be calculated for READ bursts, and the EDC hold pattern will be
transmitted instead.
Write CRC
Bit A10 controls the CRC calculation for WRITE bursts. When enabled, the calculated CRC pattern will be
transmitted on the EDC pins with the latency as programmed in the CRCWL field of this register. With
Write CRC being off, no CRC will be calculated for WRITE bursts, and the EDC hold pattern will be trans‐
mitted instead.

Rev. 1.0 /Nov. 2009 54

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4.6. MODE REGISTER 5 (MR5)
Mode Register 5 defines digital RAS, PLL band‐width and low power modes as shown in Figure 29.
The register is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=0, BA2=1
and BA3=0.

BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 1 0 1 0 RFU PLL Bandwidth LP3 LP2 RFU

A1 LP2
‐3dB [MHz] Peak [MHz] Peak [dB] 0 Off
A5 A4 A3 BW3dBLL BWPKLL PKLL
1 On
0 0 0 13 2 ＜ 1.2
0 0 1 18 4 ＜ 1.1
0 1 0 22 5 ＜ 1.1
0 1 1 28 7 ＜ 1.2
1 0 0 36 10 ＜ 1.2
1 0 1 44 13 ＜ 1.2 A2 LP3
1 1 0 54 15 ＜ 1.7 0 Off
1 1 1 69 20 ＜ 1.5 1 On
Note 1) PLL BW characteristics is extracted at 4Gbps
Note 2) PLL BW is linearly proportional to the data rate

Figure 29. Mode Register 5 (MR5) Definition

Low Power Modes (LP2, LP3)
Bits A1‐A2 control several low power modes of the GDDR5 SGRAM. The modes are independent of each
other.
When bit A1 (LP2) is set, the WCK receivers may be turned off during power‐down.
When bit A2 (LP3) is set, RDTR, WRTR and LDFF commands are not allowed while a REF command is
being executed.

PLL Bandwidth

The PLL bandwidth may optionally be configured to match system characteristics. Each setting defines a
unique combination of ‐3dB corner frequency, peaking frequency and peaking magnitude.

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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 56
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4.7. MODE REGISTER 6 (MR6)
Mode Register 6 controls the WCK2CK alignment point and defines VREFD related features such as
source, level, offsets, VREFD Merge and VREFD Auto Calibration mode, as shown in Figure 30.
The register is programmed via the MODE REGISTER SET (MRS) command with BA0=0, BA1=1, BA2=1
and BA3=0.

BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

VREFD Offset VREFD Offset Auto VREFD WCK

0 1 1 0 0 Bytes in rows A‐F Bytes in rows M‐U VREFD VREFD Merge PIN

VREFD VREFD WCK2CK

A11 A10 A9 A8 A7 A6 A5 A4 A0 Alignment Pt.
Offset Offset

0 / 0 / PD inside

0 0 0 0 0 0 0 0 0 DRAM
default default
0 0 0 1 +1 0 0 0 1 +1 1 PD at pins
0 0 1 0 +2 0 0 1 0 +2
0 0 1 1 +3 0 0 1 1 +3
0 1 0 0 +4 0 1 0 0 +4
0 1 0 1 +5 0 1 0 1 +5 A1 VREFD Merge
0 1 1 0 +6 0 1 1 0 +6 0 Off
0 1 1 1 +7 0 1 1 1 +7 1 On
0 / Auto 1 0 0 0 0 / Auto
1 0 0 0 (opt.)
(opt.)
1 0 0 1 ‐7 1 0 0 1 ‐7
1 0 1 0 ‐6 1 0 1 0 ‐6
1 0 1 1 ‐5 1 0 1 1 ‐5
A3 VREFD
1 1 0 0 ‐4 1 1 0 0 ‐4
1 1 0 1 ‐3 1 1 0 1 ‐3 0 external VREFD pins

1 1 1 0 ‐2 1 1 1 0 ‐2 1 internally generated

1 1 1 1 ‐1 1 1 1 1 ‐1

Figure 30. Mode Register 6 (MR6) Definition

WCK2CK Alignment Point (WCKPIN)
Bit A0 defines the position of the alignment point between CK and WCK. When set to ‘0‘, the alignment
point will be at the phase detector inside the GDDR5 SGRAM. When set to ‘1‘, the alignment point will be
at the CK and WCK pins.
Input Reference Voltage for DQ and DBI# Pins
GDDR5 SGRAMs offer multiple options for the input reference voltage (Vref) for the DQ and DBI# pins,
as shown in Figure 31.

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responsability for use of circuits described. No patent licenses are implied.
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Separate Vref circuits are associated with the bytes in rows A to F and the bytes in rows M to U, with
separate VREFD pins for the required external Vref.
The only mandatory mode is that Vref will be supplied externally at the VREFD pins. This mode is
configured with bits A1‐A3 and bit A7 in MR7 all set to ’0’.

VREFD Offsets

0.7*VDDQ (opt.)

0.5*VDDQ (opt.) + +
VREFD
Merge
VREFD (opt.)
‐
Receiver

DQ/DBI# +

Figure 31. VREFD Options

VREFD Merge
The VREFD Merge mode is enabled when bit A1 is set to’1’. The externally supplied VFRED and the
internally generated Vref will be merged, resulting in the average value of both. DRAM vendor
specifications should be checked for values of external resistors that may be connected to VREFD pins in
this VREF Merge mode.
Auto VREFD Training
When Auto is set for VREFD offsets, the internal Vref generator must be trained. Bit A2 enables this
training; the bit is self‐clearing, meaning that it returns back to the value ‘0’ after the training has
completed.
Once the training mode is enabled, the GDDR5 SGRAM drives the EDC pins Low to indicate to the
controller that the training has started. The controller is now expected to send the specified PRBS pattern
to the GDDR5 SGRAM. Upon completion of the training, the GDDR5 SGRAM stops driving the EDC pins
Low, and the EDC pins will resume transmitting the EDC hold pattern.
But, it is not supported.
VREFD
Bit A3 selects between external and internal Vref. The bit is “Don’t Care” when VREF Merge mode is
selected.
VREFD Offsets and VREFD Auto Mode
It supports the capability to offset Vref independently for the upper 2 bytes and the lower 2 bytes. The
offset step values may be non‐linear and will vary across PVT.

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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 58
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The vendors may optionally support the offset capability to be applied to the external Vref (not shown in
Figure 31).
The optional Auto setting for VREFD enables the GDDR5 SGRAM to search for its own optimal internal
Vref. There is no offset from this internally determined value (see also Auto VREFD Training).

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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 59
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4.8. MODE REGISTER 7 (MR7)
Mode Register 7 controls features like PLL Standby, PLL Fast‐Lock, PLL Delay Compensation, Low
Frequency mode, Auto Synchronization, Data Preamble, Temperature Sensor operation, Half VREFD,
VDD Range and DCC as shown in Figure 32.
The register is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=1, BA2=1
and BA3=0.

BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 1 1 1 0 DCC RFU Half Temp DQ Auto LF RFU

VREFD Sense PreA Sync Mode

A11 A10 DCC

0 0 no DCC /
DCC off or hold / opt.
0 1 DCC start
1 0 DCC reset l
A4 WCK2CK Auto Sync
1 1 RFU
0 Off
1 On

A5 Data Preamble A3 Low Frequency Mode
0 Off 0 Off
1 On 1 On

A7 Half VFRED A6 Temperature Sensor

0 0.7 * VDDQ 0 Off
1 0.5 * VDDQ 1 On

Figure 32. Mode Register 7 (MR7) Definition

Low Frequency Mode
When Low Frequency Mode is enabled by bit A3, the power consumption of input receivers and clock
trees is reduced. The maximum operating frequency for this low frequency mode is given in the vendor‘s
datasheet.
WCK2CK Auto Synchronization
GDDR5 SGRAMs support a WCK2CK automatic synchronization mode that eliminates the need for
WCK2CK training upon power‐down exit or for reducing WCK2CK training time at low frequency. This
mode is controlled by bit A4. For a detailed description see WCK2CK Auto Synchronization in the section
entitled WCK2CK Training.

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responsability for use of circuits described. No patent licenses are implied.
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Data Preamble
When enabled by bit A5, non‐gapless READ bursts will be preceded by a fixed data preamble on the DQ
and DBI# pins of 4 U.I. duration. The programmed READ latency does not change when the Data
Preamble is enabled. The pattern is not encoded with RDBI, however, if RDBI is disabled, the DBI# pins
will not toggle and drive a HIGH.
Temperature Sensor
The on‐chip temperature sensor is enabled by bit A6.
A detailed description of the Temperature Sensor can be found in the VENDOR ID, TEMP SENSOR and
SCAN section.
Half VREFD
This mode allows users to adjust the Vref level in case the GDDR5 SGRAM is operated without
termination: when bit A7 is set to’1’, a Vref level of nominally 0.5 * VDDQ is expected at the VREFD pin or
being generated internally (see Figure 31).
Duty Cycle Correction (DCC)
Bits A10 and A11 control the operation of the duty cycle corrector (DCC). The DCC can be used to cancel
out a static duty cycle error on the WCK clocks. For more details see Duty Cycle Correction (DCC) in the
section entitled OPERATION.

VREFD Selection Options Summary
The following table summarizes the complete set of VREFD selection options.
Table 15 VREFD Selection Options
MR6 MR7
A3 A7 Description

Internal VREFD Half VREFD
0 0 External
0 1 External
1 0 Internal 0.7 * VDDQ
1 1 Internal 0.5 * VDDQ

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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 61
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4.9. MODE REGISTER 15 (MR15)
Mode Register 15 controls address training mode (ADT) and access to Mode Registers 0 to 14 (MRE) as
shown in Figure 33.
The register is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=1, BA2=1
and BA3=1.
Mode Register 15 is a special register that operates in SDR addressing mode. Increased setup and hold
times as for command inputs are assumed to ensure the MRS command to this register is successful while
address training (ADT) has not taken place and the integrity of DDR addresses may not be guaranteed.
This is indicated by setting bits A0‐A7 to Don’t Care (“X”) which are paired with the usable bits (A8‐A11)
and the Mode Register address (BA0‐BA3).

BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

MRE MRE
1 1 1 1 0 RFU ADT X X X X X X X X
MF1 MF0

A10 Address Training (ADT) A9 MR0‐14 Enable MF=1 A8 MR0‐14 Enable MF=0

0 Off 0 Enabled 0 Enabled
1 On 1 Disabled 1 Disabled

Figure 33. Mode Register 15 (MR15) Definition

Address Training (ADT)
Address training mode is enabled and disabled with bit A10.
Mode Register 0‐14 Enable
When disabled by bit A8 (for SGRAMs configured to MF=0) or bit A9 (for SGRAMs configured to MF=1),
the GDDR5 SGRAM will ignore any MODE REGISTER SET command to Mode Registers 0 to 14. If
enabled, MODE REGISTER SET commands function as normal. MODE REGISTER SET commands to
Mode Register 15 (this register) are not affected and will always be executed.
This functional allows for individual configuration of two GDDR5 SGRAMS on a common address bus
without the use of a CS# pin.

5. OPERATION
5.1. COMMANDS
Table 16 Truth Table ‐ Commands
Operation CKE# A6,
Symbol A7, A0‐
Previous Current A9, A5
cycle cycle CS# RAS# CAS# WE# BA A11 A10 A8 (A12) (A6) Notes
DESELECT (NOP) DES L X H X X X X X X X X X 1, 2, 8
NO OPERATION (NOP) NOP L X L H H H X X X X X X 1, 2, 8
MODE REGISTER SET MRS L L L L L L MRA Opcode 1, 2, 3
ACTIVE (Select bank & ACT L L L L H H BA RA 1, 2, 4
activate row)
READ (Select bank and RD L L L H L H BA L L L X CA 1, 2, 5,
column, & start burst) 9
READ with Autoprecharge RDA L L L H L H BA L L H X CA 1, 2, 5
Load FIFO LDFF L L L H L H X H L L X X 1, 2, 7
READ Training RDTR L L L H L H X H H L X X 1, 2
WRITE without Mask WOM L L L H L L BA L L L X CA 1, 2, 5
(Select bank and column, &
start burst)
WRITE without Mask with WOMA L L L H L L BA L L H X CA 1, 2, 5
Autoprecharge
WRITE with single‐byte WSM L L L H L L BA L H L X CA 1, 2, 5
mask
WRITE with single‐byte WSMA L L L H L L BA L H H X CA 1, 2, 5
mask with Autoprecharge
WRITE with double‐byte WDM L L L H L L BA H L L X CA 1, 2, 5
mask (WDM)
WRITE with double‐byte WDMA L L L H L L BA H L H X CA 1, 2, 5
mask with Autoprecharge
WRITE Training WRTR L L L H L L X H H L X X 1, 2
PRECHARGE (Deactivate PRE L L L L H L BA X X L X X 1, 2
row in bank or banks)
PRECHARGE ALL PREALL L L L L H L X X X H X X 1, 2
REFRESH REF L L L L L H X X X X X X 1, 6
H X X X X X X X X X 1
POWER DOWN ENTRY PDE L H
L H H H X X X X X X 1
H X X X X X X X X X 1
POWER DOWN EXIT PDX H L
L H H H
SELF REFRESH ENTRY SRE L H L L L H X X X X X X 1, 6
H X X X X X X X X X 1
SELF REFRESH EXIT SRX H L
L H H H

Notes:
1) H = Logic High Level; L = Logic Low Level; X = Don’t care: signal may be H or L, but not floating
2) Addresses shown are logical addresses; physical addresses are inverted when address bus inversion (ABI) is activated and ABI#=L
3) BA0‐BA3 provide the Mode Register address (MRA), A0‐A11 the opcode to be loaded
4) BA0‐BA3 provide the bank address (BA), A0‐A11 (A12) provide the row address (RA).
5) BA0‐BA3 provide the bank address, A0‐A5 (A6) provide the column address (CA); no sub‐word addressing within a burst of 8.
6) The command is Refresh when CKE#(n) = L and Self Refresh Entry when CKE#(n) = H.
7) BA0‐BA3 and CA are used to select burst location and data respectively
8) DESELECT and NOP are functionally interchangeable
9) In address training mode READ is decoded from the commands pins only with RAS# = H, CAS# = L, WE# = H

Figure 34 and Figure 35 illustrate the timings associated with the Command and Address input as well as
Data input.

tCK tCH tCL

CK#
CK
tCMDPW tCMDS tCMDH

COMMAND
tAPW tAPW tAS tAH tAS tAH

ADDRESS

Donʹt Care

Figure 34. Command and Address Input Timings

WCK#
WCK
tWCK2DQI
tWCK2DQI

tDIPW tDIPW
tDIVW tDIVW
DQ/DBI#
(1 Pin)

Figure 35. Data Input Timings

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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 64
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5.2. DESELECT (NOP)
The DESELECT function (CS# HIGH) prevents new commands from being executed by the GDDR5
SGRAM. The GDDR5 SGRAM is effectively deselected. Operations already in progress are not affected.

5.3. NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected GDDR5 SGRAM to perform a NOP
(CS# LOW). This prevents unwanted commands from being registered during idle or wait states. Opera‐
tions already in progress are not affected.

5.4. MODE REGISTER SET
The MODE REGISTER SET command is used to load the Mode Registers of the GDDR5 SGRAM. The bank
address inputs BA0‐BA3 select the Mode Register, and address puts A0‐A11(A12) determine the op‐code
to be loaded. See MODE REGISTER for a register definition. The MODE REGISTER SET command can
only be issued when all banks are idle and no bursts are in progress, and a subsequent executable com‐
mand cannot be issued until tMRD is met.

Mode Register Set
CK#

CKE#
LOW

CS#

RAS#

CAS#

WE#

A8‐A11 (A12) CO CO
A0,A1,A6,A7
A8,9,10,11, (12) A0,1,6,7

BA0‐BA3
BA CO
A2‐A5
BA0,1,2,3 A2,3,4,5

RA = Row Address
DONʹT CARE
CO = Op‐code
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Aut o Precharge

Figure 36. MRS Command

CK#
CK

CMD NOP PRE NOP MRS NOP A.C. NOP

ALL
tRP tMRD

Old Setting Updating Setting New Setting

A.C. = any command allowed in bank idle state

Figure 37. Mode Register Set Timings

5.5. ACTIVATION
Before any READ or WRITE commands can be issued to a bank in the GDDR5 SGRAM, a row in that bank
must be “opened”. This is accomplished by the ACTIVE command (see Figure 38): BA0 ‐BA3 select the
bank, and A0‐A11 (A12) select the row to be activated. Once a row is open, a READ or WRITE command
could be issued to that row, subject to the tRCD specification.

A subsequent ACTIVE command to another row in the same bank can only be issued after the previous
row has been closed (precharged). The minimum time interval between two successive ACTIVE com‐
mands on the same bank is defined by tRC. A minimum time, tRAS, must have elapsed between opening
and closing a row.

A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed,
which results in a reduction of total row‐access overhead. The minimum time interval between two suc‐
cessive ACTIVE commands on different banks to different bank groups is defined by tRRDS. With bank
groups enabled, the minimum time interval between two successive ACTIVE commands to different
banks in the same bank group is defined by tRRDL. In all other cases the interval is defined by tRRDS.
<Link>Figure shows the tRCD and tRRD definition.

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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 66
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The row remains active until a PRECHARGE command (or READ or WRITE command with Auto Pre‐
charge) is issued to the bank.
Row Activation
CK#

CK
CKE#
LOW

CS#

RAS#

CAS#

WE#

A8‐A11 (A12) RA RA
A0, A1,A6,A7
A8,9,10,11, (12) A0,1,6,7

BA0‐BA3
BA RA
A2‐A5
BA0,1,2,3 A2,3,4,5

RA = Row Address
CA = Column Address DONʹT CARE
BA = Bank Address

Figure 38. Active Command

T0 T1 T2 Ta0 Ta1 Tb0 Tb1 Tc0 Tc1

CK#
CK

CMD NOP ACT NOP RD/WR NOP PRE* NOP ACT NOP

ADDR BA BA CA BA
RA RA BA RA RA
tRCD tRP
tRAS
tRC
(*) = could also be PREALL

BA = bank address; RA = row address; CA = column address
tRCD = tRCDRD, tRCDWR, tRCDRTR, tRCDWTR or tRCDLTR, depending on command Donʹt Care

Figure 39. Bank Activation Command Cycle

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 67
H5GQ1H24AFR
5.6. BANK RESTRICTIONS
There may be a need to limit the number of activates in a rolling window to ensure that the instantaneous
current supplying capability of the devices is not exceeded. To reflect the short term capability of the
GDDR5 SGRAM current supply, the parameter tFAW (four activate window) is defined. No more than 4
banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW (ns) by
tCK (ns) and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds
up to 10 clocks, and an activate command is issued at clock N, no more than three further activate com‐
mands may be issued at clocks N+1 through N+9 as illustrated in Figure 40.

To reflect a longer term GDDR5 SGRAM current supply capability, the parameter t32AW (thirty‐two acti‐
vate window) is defined. No more than 32 banks may be activated in a rolling t32AW window. Converting
to clocks is done by dividing t32AW (ns) by tCK (ns) and rounding up to next integer value. The use of a
shorter and longer rolling activation window allows the GDDR5 SGRAM design to be optimized to handle
higher instantaneous currents within a shorter window while still limiting the current strain over a longer
period of time. This means that in general t32AW will be greater than or equal to 8* tFAW as shown in
Figure41.

It is preferable that GDDR5 SGRAMs have no rolling activation window restrictions (tFAW = 4 * tRRD).

CK#

CMD ACT ACT ACT ACT ACT ACT ACT ACT

tRRD tRRD tRRD tRRD tRRD tRRD

tFAW
tFAW + 3 * t RRD

tRRD = tRRDL or tRRDS depending on Bank Groups on/off setting and accessed banks

Figure 40. tRRD and tFAW

A.) t32AW > 8 * tFAW

tFAW tFAW tFAW tFAW tFAW tFAW tFAW tFAW tFAW

t32AW

B.) t32AW = 8 * tFAW

tFAW tFAW tFAW tFAW tFAW tFAW tFAW tFAW tFAW

t32AW

Figure 41. t32AW

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 69
H5GQ1H24AFR
5.7. WRITE (WOM)
WRITE bursts are initiated with a WRITE command as shown in Figure 42. The bank and column
addresses are provided with the WRITE command and auto precharge is either enabled or disabled for
that access with the A8 pin. If auto precharge is enabled, the row being accessed is precharged at the com‐
pletion of the burst after tRAS(min) has been met. The length of the burst initiated with a WRITE command
is eight and the column address is unique for this burst of eight. There is no interruption nor truncation of
WRITE bursts.

WRITE
CK#

CKE# LOW

CS#

RAS#

CAS#

WE#

A10,A11
A0,A6 0,0 CA

A9 (A12)
A1 CA

A8 EN AP
A7 DIS AP

BA0‐BA3 BA CA
A2‐A5

BA = Bank Address; CA = Column Address
EN AP = Enable Auto‐Precharge; DIS AP = Disable Auto‐Precharge

Figure 42. WRITE Command

During WRITE bursts, the first valid data‐in element must be available at the input latch after the Write
Latency (WL). The Write Latency is defined as WLmrs * tCK + tWCK2CKPIN + tWCK2CK + tWCK2DQI, where
WLmrs is the number of clock cycles programed in MR0, tWCK2CKPIN is the phase offset between WCK
and CK at the pins when phase aligned at phase detector, tWCK2CK is the alignment error between WCK
and CK at the GDDR5 SGRAM phase detector, and tWCK2DQI is the WCK to DQ/DBI# offset as measured
at the DRAM pins to ensure concurrent arrival at the latch. The total delay is relative to the data eye center
averaged over one double‐byte. The maximum skew within a double‐byte is defined by tDQDQI.

The data input valid window, tDIVW, defines the time region when input data must be valid for reliable
data capture at the receiver for any one worst‐case channel. It accounts for jitter between data and clock at
the latching point introduced in the path between the DRAM pads and the latching point. Any additional
jitter introduced into the source signals (i.e. within the system before the DRAM pad) must be accounted
for in the final timing budget together with the chosen PLL mode and bandwidth. tDIVW is measured at
the pins. tDIVW is defined for the PLL off and on mode separately. In the case of PLL on, tDIVW must be
specified for each supported bandwidth. In general tDIVW is smaller than tDIPW.

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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 70
H5GQ1H24AFR
The data input pulse width, tDIPW, defines the minimum positive or negative input pulse width for any
one worst‐case channel required for proper propagation of an external signal to the receiver. tDIPW is mea‐
sured at the pins. tDIPW is independent of the PLL mode. In general tDIPW is larger than tDIVW.

Upon completion of a burst, assuming no other WRITE data is expected on the bus the GDDR5 SGRAM
DQ and DBI# pins will be driven according to the ODT state. Any additional input data will be ignored.
Data for any WRITE burst may not be truncated with a subsequent WRITE command.

Data from any WRITE burst may be concatenated with data from a subsequent WRITE command. A con‐
tinuous flow of data can be maintained. The first data element from the new burst follows the last element
of a completed burst. The new WRITE command should be issued after the previous WRITE command
according to the tCCD timing. If that WRITE command is to another bank then an ACTIVE command must
precede the WRITE command and tRCDWR also must be met.

A READ can be issued any time after a WRITE command as long as the internal turn around time tWTR is
met. If that READ command is to another bank, then an ACTIVE command must precede the READ com‐
mand and tRCDRD also must be met.

A PRECHARGE can also be issued to the GDDR5 SGRAM with the same timing restriction as the new
WRITE command if tRAS is met. After the PRECHARGE command, a subsequent command to the same
bank cannot be issued until tRP is met.

The data inversion flag is received on the DBI# pin to identify whether to store the true or inverted data. If
DBI# is LOW, the data will be stored after inversion inside the GDDR5 SGRAM and not inverted if DBI# is
HIGH. WRITE Data Inversion can be enabled (A9=0) or disabled (A9=1) using WDBI in MR1.

When enabled by the WRCRC flag in MR4, EDC data are returned to the controller with a latency of
(WLmrs + CRCWL) * tCK + tWCK2CKPIN + tWCK2CK + tWCK2DQO, where CRCWL is the CRC Write latency
programmed in MR4 and tWCK2DQO is the WCK to DQ/DBI#/EDC phase offset at the DRAM pins.

WLmrs tCH tCL tCK

CK#
CK
tWCK2CKPIN + tWCK2CK
WCK
WCK#

Case 1: Negative tWCK2DQI
tWCK2DQI
DQ/DBI#
D0 D1 D2 D3 D4 D5 D6 D7
(mean)
tDQDQI(min)
DQ/DBI#
D0 D1 D2 D3 D4 D5 D6 D7
(first bit)
tDQDQI(max)
DQ/DBI#
D0 D1 D2 D3 D4 D5 D6 D7
(last bit)

Case 2: Positive tWCK2DQI
tWCK2DQI
DQ/DBI#
D0 D1 D2 D3 D4 D5 D6 D7
(mean)
tDQDQI(min)
DQ/DBI#
D0 D1 D2 D3 D4 D5 D6 D7
(first bit)
tDQDQI(max)
DQ/DBI#
D0 D1 D2 D3 D4 D5 D6 D7
(last bit)
Donʹt Care
1) WLmrs is the WRITE latency programmed in Mode Register MR0.
2) Timings are shown with positive tWCK2CKPIN and tWCK2CK values. See WCK2CK timings for
tWCK2CKPIN and tWCK2CK ranges.
3) tWCK2DQI parameter values could be negative or positive numbers, depending on PLL‐on or PLL‐off mode
operation and design implementation. They also vary across PVT. Data training is required to determine
the actual tWCK2DQI value for stable WRITE operation.
4) tDQDQI defines the minimum to maximum variation of tWCK2DQI within a double byte (x32 mode) or
a single byte (x16 mode).
5) Data Read timings are used for CRC return timing from WRITE commands with CRC enabled.

Figure 43. WRITE Timings

T0 T1 T2 T3 T3n T4 T4n T5 T6 T7 T8
CK#
CK

COMMAND WRITE NOP NOP NOP NOP NOP NOP NOP NOP

ADDRESS Bank a, Col n

Col n

WL = WLmrs = 3

WCK
WCK#

DQ DO DO
n n+7

DBI# DBI DBI

n n+7

EDC EDC Hold Pattern

DONʹT CARE TRANSITIONING DATA

3.  For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.
4.  Before the WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDWR must be met.
5.  tWCK2DQI = 0 is shown for illustration purposes.

Figure 44. Single WRITE without EDC

T0 T1 T2 T3 T3n T4 T4n T5 (( T11 T12 T13

CK# ))
((
CK ))

((
))
COMMAND WRITE NOP NOP NOP NOP NOP ( ( NOP NOP NOP
))

((
))
ADDRESS Bank a, Col n
Col n ((
))
WL = WLmrs = 3

WCK ((
))
((
WCK# ))
((
DQ DO DO
))
n n+7

((
DBI# DBI DBI ))
n n+7

((
EDC Hold Pattern )) EDC EDC EDC Hold
EDC (( n n+7 Pattern
))

CRCWL = 8

DONʹT CARE TRANSITIONING DATA

Notes: 1. WLmrs = 3 and CRCWL = 8 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

Figure 45. Single WRITE with EDC

T0 T1 T2 T5 T5n T6 T6n T7 T10 T10n T11 T11n T12

((
CK# )) ((
))
((
CK )) ((
))
((
)) ((
WRITE NOP ACT WRITE NOP NOP )) NOP NOP NOP
COMMAND ((
)) ((
))

((
((
Bank a, Bank b, ) ) Bank b,
ADDRESS Col m Row Col n ))
Col m Row ( ( Col n
((
tRCDWR )
)
))
WL = WLmrs = 5 WL = WLmrs = 5

WCK ((
)) ((
(( ))
WCK# )) ((
))
((
DQ )) ((
DO DO )) DO DO
m m+7 n n+7

((
)) ((
DBI# DBI DBI )) DBI DBI
m m+7 n n+7

DONʹT CARE TRANSITIONING DATA

Notes: 1. WLmrs = 5 and tRCDWR = 3 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

3.  EDC may be on or off.  See Figure 4 for EDC Timing.
4.  For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.
5.  Before the WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDWR must be met.
6.  tWCK2DQI = 0 is shown for illustration purposes.

Figure 46. Non-Gapless WRITEs

T0 T1 T2 T2n T3 T3n T4 T4n T5 T5n T6 T7 T8

CK#
CK

COMMAND WRITE NOP WRITE NOP NOP NOP NOP NOP NOP

tCCD

Bank a, Bank a,
ADDRESS Col m Col m Col n
Col n

WL = WLmrs = 2 WL = WLmrs = 2

WCK
WCK#

DQ DO DO DO DO
m m+7 n n+7

DBI# DBI DBI DBI DBI

m m+7 n n+7

DONʹT CARE TRANSITIONING DATA

Notes: 1. WLmrs = 2 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

3. EDC may be on or off. See Figure 4 for EDC Timing.
4. tCCD = tCCDS when bank groups is disabled or the second WRITE is to a different bank group, otherwise tCCD=tCCDL.

5.  For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.
6.  Before the WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDWR must be met.
7.  tWCK2DQI = 0 is shown for illustration purposes.

Figure 47. Gapless WRITEs

T0 T1 T3 T3n T4 T4n T5 Ta0 Ta6 Ta6n Ta7 Ta8

(( (( ((
CK# )) )) ))
(( (( ((
CK )) )) ))

(( (( ((
)) )) ))
COMMAND WRITE NOP NOP NOP NOP READ NOP NOP NOP
(( (( ((
)) )) ))

(( (( ((
Bank a, )) )) Bank b, ))
ADDRESS Col m Col m (( Col n Col n
((
((
)) )) ))
tWTR
WL = WLmrs = 3
CL = CLmrs = 6
WCK (( (( ((
)) )) ))
(( (( ((
WCK# )) )) ))
(( (( ((
DQ )) DO DO )) )) DO DO
m m+7 n n+7

(( (( ((
)) )) ))
DBI# DBI DBI DBI DBI
m m+7 n n+7

DONʹT CARE TRANSITIONING DATA

Notes: 1. WLmrs = 3 and CLmrs = 6 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

3. EDC may be on or off. See Figure 4 for EDC Timing.
4. tWTR = tWTRL when bank groups is enabled and both WRITE and READ access banks in the same bank group, otherwise tWTR=tWTRS.

5.  For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.
6.  Before the READ and WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD or tRCDWR
respectively must be met.
7.  tWCK2DQI, tWCKDQO = 0 is shown for illustration purposes.

Figure 48. WRITE to READ

T0 T1 T2 T3 T3n T4 T4n T5 T6 Ta0 Ta1

CK# ((
))
CK ((
))

((
WRITE NOP NOP NOP NOP NOP NOP )) PRE NOP
COMMAND
((
tWR )) tRP
((
Bank a, )) Bank a,
ADDRESS Col n Col n
or all
((
))
WL = WLmrs = 3

WCK ((
))
WCK# ((
))

DQ ((
DO DO ))
n n+7

((
DBI# DBI DBI ))
n n+7

DONʹT CARE TRANSITIONING DATA

Notes: 1.  WLmrs = 3 is shown as an example.  Actual supported values will be found in the MR and AC timings sections.
2.  WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes.  WCK2CK training determines the needed offset between WCK and CK.
3.  EDC may be on or off.  See Figure 4 for EDC Timing.
4.  For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.
5.  Before the WRITE command, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDWR must be met.
6.  tWCK2DQI = 0 is shown for illustration purposes.

Figure 49. WRITE to PRECHARGE

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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 78
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5.8. WRITE DATA MASK (DM)
The traditional method of using a DM pin for WRITE data mask must be abandoned for a new method.
Due to the high data rate of GDDR5 SGRAMs, bit errors are expected on the interface and are not recover‐
able when they occur on the traditional DM pin.

In GDDR5 the DM is sent to the SGRAM over the address following the bank/column address cycle associ‐
ated with the command, during the NOP/DESELECT commands between the WRITE command and the
next command. The DM is used to mask the corresponding data according to the following table.

Table 17: DM State
DM
FUNCTION DQ
Value

Write Enable 0 Valid

Write Inhibit 1 X

Two additional WRITE commands that augment the traditional WRITE Without Mask (WOM) are
required for proper DM support:

• WDM: WRITE‐With‐Doublebyte‐Mask:
2 cycle command where the 1st cycle carries address information and the 2nd cycle carries data mask
information (2 byte granularity);

WDM
CK#

CKE# LOW

CS#

RAS#

CAS#

WE#

A9 (A12) CA DM DM
A1

A10,A11 CA DM
0,1 DM
A0,A6

A8 EN AP
DM
DIS AP DM
A7

BA0‐BA3
BA CA DM DM
A2‐A5

BA = Bank Address; CA = Column Address; DM = Data Mask
EN AP = Enable Auto‐Precharge; DIS AP = Disable Auto‐Precharge

Note: NOP shown as an example only

Figure 50. WRITE-With-Doublebyte-Mask Command

T0 T1 T2 T2n T3 T3n T4 T4n T5 T5n T6 T7 T8

CK#
CK

COMMAND WDM NOP WDM NOP NOP NOP NOP NOP NOP

tCCD

Bank a, Bank a,
ADDRESS Col m Col m DM m DM m Col n
Col n DM n DM n

WL = WLmrs = 2 WL = WLmrs = 2

WCK
WCK#

DQ DO DO DO DO
m m+7 n n+7

DBI# DBI DBI DBI DBI

m m+7 n n+7

DONʹT CARE TRANSITIONING DATA

3. EDC may be on or off. See Figure 4 for EDC Timing.
4. tCCD = tCCDS when bank groups is disabled or the second WRITE is to a different bank group, otherwise tCCD=tCCDL.

Figure 51. WDM Timing

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 81
H5GQ1H24AFR
• WSM: WRITE‐With‐Singlebyte‐Mask:
3 cycle command where the 1st cycle carries address information, the 2nd and 3rd cycle carry data mask
information

WSM
CK#

CKE# LOW

CS#

RAS#

CAS#

WE#

A9 (A12) CA DM DM DM DM
A1

A10,A11 CA DM DM
0,1 DM DM
A0,A6

A8 EN AP
DM DM
DIS AP DM DM
A7

BA0‐BA3
BA CA DM DM DM DM
A2‐A5

BA = Bank Address; CA = Column Address; DM = Data Mask
EN AP = Enable Auto‐Precharge; DIS AP = Disable Auto‐Precharge
Note: NOP shown as an example only

Figure 52. WRITE-With-Singlebyte-Mask Command

T0 T1 T2 T5 T5n T6 T6n T7 T10 T10n T11 T11n T12

(( ((
CK# )) ))
(( ((
CK )) ))
(( ((
)) ))
COMMAND WSM NOP NOP WSM NOP NOP NOP NOP NOP
(( ((
)) ))

(( ((
Bank a, ) ) Bank b,
ADDRESS Col m DM m DM m DM m DM m Col n DM n DM n DM n DM n ) )
Col m ( ( Col n ((
)) ))
WL = WLmrs = 5 WL = WLmrs = 5

WCK (( ((
)) ))
(( ((
WCK# )) ))
(( ((
DQ )) DO DO ) ) DO DO
m m+7 n n+7

(( ((
))
DBI# DBI DBI ) ) DBI DBI
m m+7 n n+7

DONʹT CARE TRANSITIONING DATA

Figure 53. WSM Timing

Byte and Burst Position Masked during WDM
ADR ADR CK Rising Edge ADR ADR CK# Rising Edge
Byte Burst Byte Burst
A10 DQ[15:0] 0 A0 DQ[15:0] 4
A9 DQ[15:0] 1 A1 DQ[15:0] 5
BA0 DQ[15:0] 2 A2 DQ[15:0] 6
BA3 DQ[15:0] 3 A3 DQ[15:0] 7
BA2 DQ[31:16] 0 A4 DQ[31:16] 4
BA1 DQ[31:16] 1 A5 DQ[31:16] 5
A11 DQ[31:16] 2 A6 DQ[31:16] 6
A8 DQ[31:16] 3 A7 DQ[31:16] 7

Table 19 WDM Mapping for non‐mirrored x16 Mode

Byte and Burst Position Masked during WDM
ADR CK Rising Edge ADR ADR CK# Rising Edge
ADR Byte Burst Byte Burst
A10 DQ[7:0] 0 A0 DQ[7:0] 4
A9 DQ[7:0] 1 A1 DQ[7:0] 5
BA0 DQ[7:0] 2 A2 DQ[7:0] 6
BA3 DQ[7:0] 3 A3 DQ[7:0] 7
BA2 DQ[23:16] 0 A4 DQ[23:16] 4
BA1 DQ[23:16] 1 A5 DQ[23:16] 5
A11 DQ[23:16] 2 A6 DQ[23:16] 6
A8 DQ[23:16] 3 A7 DQ[23:16] 7

Table 20 WDM Mapping for mirrored x16 Mode

Byte and Burst Position Masked during WDM
ADR CK Rising Edge ADR ADR CK# Rising Edge
ADR Byte Burst Byte Burst
A10 DQ[15:8] 0 A0 DQ[15:8] 4
A9 DQ[15:8] 1 A1 DQ[15:8] 5
BA0 DQ[15:8] 2 A2 DQ[15:8] 6
BA3 DQ[15:8] 3 A3 DQ[15:8] 7
BA2 DQ[31:24] 0 A4 DQ[31:24] 4
BA1 DQ[31:24] 1 A5 DQ[31:24] 5
A11 DQ[31:24] 2 A6 DQ[31:24] 6
A8 DQ[31:24] 3 A7 DQ[31:24] 7

Byte and Burst Position Masked During WSM
ADR CK 1st rising Edge ADR CK# 1st rising Edge ADR CK 2nd rising Edge ADR CK# 2nd rising Edge
ADR Byte Burst ADR Byte Burst ADR Byte Burst ADR Byte Burst
A10 DQ[7:0] 0 A0 DQ[7:0] 4 A10 DQ[15:8] 0 A0 DQ[15:8] 4

A9 DQ[7:0] 1 A1 DQ[7:0] 5 A9 DQ[15:8] 1 A1 DQ[15:8] 5

BA0 DQ[7:0] 2 A2 DQ[7:0] 6 BA0 DQ[15:8] 2 A2 DQ[15:8] 6

BA3 DQ[7:0] 3 A3 DQ[7:0] 7 BA3 DQ[15:8] 3 A3 DQ[15:8] 7

BA2 DQ[23:16] 0 A4 DQ[23:16] 4 BA2 DQ[31:24] 0 A4 DQ[31:24] 4

BA1 DQ[23:16] 1 A5 DQ[23:16] 5 BA1 DQ[31:24] 1 A5 DQ[31:24] 5

A11 DQ[23:16] 2 A6 DQ[23:16] 6 A11 DQ[31:24] 2 A6 DQ[31:24] 6

A8 DQ[23:16] 3 A7 DQ[23:16] 7 A8 DQ[31:24] 3 A7 DQ[31:24] 7

Table 22 WSM Mapping for non‐mirrored x16 Mode

Byte and Burst Position Masked During WSM
ADR CK 1st rising Edge ADR CK# 1st rising Edge ADR CK 2nd rising Edge ADR CK# 2nd rising Edge
ADR Byte Burst ADR Byte Burst Byte Burst Byte Burst
A10 DQ[7:0] 0 A0 DQ[7:0] 4 ‐ 0 ‐ 4

A9 DQ[7:0] 1 A1 DQ[7:0] 5 ‐ 1 ‐ 5

BA0 DQ[7:0] 2 A2 DQ[7:0] 6 ‐ 2 ‐ 6

BA3 DQ[7:0] 3 A3 DQ[7:0] 7 ‐ 3 ‐ 7

BA2 DQ[23:16] 0 A4 DQ[23:16] 4 ‐ 0 ‐ 4

BA1 DQ[23:16] 1 A5 DQ[23:16] 5 ‐ 1 ‐ 5

A11 DQ[23:16] 2 A6 DQ[23:16] 6 ‐ 2 ‐ 6

A8 DQ[23:16] 3 A7 DQ[23:16] 7 ‐ 3 ‐ 7

Table 23 WSM Mapping for mirrored x16 Mode

Byte and Burst Position Masked During WSM
ADR CK 1st rising Edge ADR CK# 1st rising Edge ADR CK 2nd rising Edge ADR CK# 2nd rising Edge
Byte Burst Byte Burst ADR Byte Burst ADR Byte Burst
‐ 0 ‐ 4 A10 DQ[15:8] 0 A0 DQ[15:8] 4
‐ 1 ‐ 5 A9 DQ[15:8] 1 A1 DQ[15:8] 5
‐ 2 ‐ 6 BA0 DQ[15:8] 2 A2 DQ[15:8] 6
‐ 3 ‐ 7 BA3 DQ[15:8] 3 A3 DQ[15:8] 7
‐ 0 ‐ 4 BA2 DQ[31:24] 0 A4 DQ[31:24] 4
‐ 1 ‐ 5 BA1 DQ[31:24] 1 A5 DQ[31:24] 5
‐ 2 ‐ 6 A11 DQ[31:24] 2 A6 DQ[31:24] 6
‐ 3 ‐ 7 A8 DQ[31:24] 3 A7 DQ[31:24] 7

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 85
H5GQ1H24AFR
5.9. READ
A READ burst is initiated with a READ command as shown in Figure 54. The bank and column addresses
are provided with the READ command and auto precharge is either enabled or disabled for that access
with the A8 address. If auto precharge is enabled, the row being accessed is precharged at the completion
of the burst after tRAS(min) has been met. The length of the burst initiated with a READ command is eight
and the column address is unique for this burst of eight. There is no interruption nor truncation of READ
bursts.

READ
CK#

CKE# LOW

CS#

RAS#

CAS#

WE#

A10,A11
A0,A6 0,0 CA

A9 (A12)
A1 CA

A8 EN AP
A7 DIS AP

BA0‐BA3 BA CA
A2‐A5

BA = Bank Address; CA = Column Address
EN AP = Enable Auto‐Precharge; DIS AP = Disable Auto‐Precharge

Figure 54. READ Command

During READ bursts, the first valid data‐out element will be available after the CAS latency (CL). The CAS
Latency is defined as CLmrs * tCK + tWCK2CKPIN + tWCK2CK + tWCK2DQO, where CLmrs is the number of
clock cycles programed in MR0, tWCK2CKPIN is the phase offset between WCK and CK at the pins when
phase aligned at phase detector, tWCK2CK is the alignment error between WCK and CK at the GDDR5
SGRAM phase detector, and tWCK2DQO is the WCK to DQ/DBI#/EDC offset as measured at the DRAM
pins. The total delay is relative to the data eye initial edge averaged over one double‐byte. The maximum
skew within a double‐byte is defined by tDQDQO.

Upon completion of a burst, assuming no other READ command has been initiated, all DQ and DBI# pins
will drive a value of ʹ1ʹ and the ODT will be enabled at a maximum of 1 tCK later. The drive value and ter‐
mination value may be different due to separately defined calibration offsets. If the ODT is disabled, the
pins will drive Hi‐Z.

Data from any READ burst may be concatenated with data from a subsequent READ command. A contin‐
uous flow of data can be maintained. The first data element from the new burst follows the last element of
a completed burst. The new READ command should be issued after the previous READ command accord‐
ing to the tCCD timing. If that READ command is to another bank then an ACTIVE command must pre‐
cede the READ command and tRCDRD also must be met.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 86
H5GQ1H24AFR
A WRITE can be issued any time after a READ command as long as the bus turn around time tRTW is met.
If that WRITE command is to another bank, then an ACTIVE command must precede the second WRITE
command and tRCDWR also must be met.

A PRECHARGE can also be issued to the GDDR5 SGRAM with the same timing restriction as the new
READ command if tRAS is met. After the PRECHARGE command, a subsequent command to the same
bank cannot be issued until tRP is met.

The data inversion flag is driven on the DBI# pin to identify whether the data is true or inverted data. If
DBI# is HIGH, the data is not inverted, and if LOW it is inverted. READ Data Inversion can be enabled
(A8=0) or disabled (A8=1) using RDBI in MR1.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 87
H5GQ1H24AFR
When enabled by the RDCRC flag in MR4, EDC data is returned to the controller with a latency of (CLmrs
+ CRCRL) * tCK + tWCK2CKPIN + tWCK2CK + tWCK2DQO, where CRCRL is the CRC Read latency pro‐
grammed in MR4.
CLmrs tCH tCL tCK

CK#
CK
tWCK2CKPIN + tWCK2CK
WCK
WCK#
Case 1: Negative tWCK2DQO
tWCK2DQO
DQ/DBI#/EDC
D0 D1 D2 D3 D4 D5 D6 D7
(mean)
tDQDQO(min)
DQ/DBI#/EDC
D0 D1 D2 D3 D4 D5 D6 D7
(first bit)
tDQDQO(max)
DQ/DBI#/EDC
D0 D1 D2 D3 D4 D5 D6 D7
(last bit)

Case 2: Positive tWCK2DQO
tWCK2DQO
DQ/DBI#/EDC
D0 D1 D2 D3 D4 D5 D6 D7
(mean)
tDQDQO(min)
DQ/DBI#/EDC
D0 D1 D2 D3 D4 D5 D6 D7
(first bit)
tDQDQO(max)
DQ/DBI#/EDC
D0 D1 D2 D3 D4 D5 D6 D7
(last bit)

Donʹt Care
1) CLmrs is the CAS latency programmed in Mode Register MR0.
2) Timings are shown with positive tWCK2CKPIN and tWCK2CK values. See WCK2CK timings for
tWCK2CKPIN and tWCK2CK ranges.
3) tWCK2DQO parameter values could be negative or positive numbers, depending on PLL‐on or PLL‐off mode
operation and design implementation. They also vary across PVT. Data training is required to determine
the actual tWCK2DQO value for stable READ operation.
4) tDQDQO defines the minimum to maximum variation of tWCK2DQO within a double byte (x32 mode) or
a single byte (x16 mode).
5) tDQDQO also applies for CRC data from WRITE and READ commands with CRC enabled, the EDC hold
pattern, and the data strobe in RDQS mode.

Figure 55. READ Word Lane Timing

T0 T1 T2 T5 T6 T6n T7 T7n T8 T9 T10

((
CK# ))
((
CK ))
((
READ NOP NOP )) NOP NOP NOP NOP NOP NOP
COMMAND
((
))
((
Bank a, ))
ADDRESS Col n Col n
((
))
CL = CLmrs = 6

WCK ((
))
((
WCK# ))
((
DQ )) DO DO
n n+7

((
DBI# )) DBI DBI
n n+7

((
ODT ODT Enabled )) ODT Enabled
(( ODT Disabled
))

((
EDC EDC Hold Pattern ))
((
))

DONʹT CARE TRANSITIONING DATA

Notes: 1. CLmrs = 6 is shown as an example. Actual supported values will be found in the MR and AC timings sections.
2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

3. Before the READ command, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
4. tWCK2DQO = 0 is shown for illustration purposes.

Figure 56. Single READ without EDC

T0 T1 (( T6 T6n T7 T7n T8 T9 T10 T10n T11 T11n T12

CK# ))
((
CK ))

((
))
COMMAND READ NOP (( NOP NOP NOP NOP NOP NOP NOP
))

((
))
ADDRESS Bank a,
Col n ((
Col n
))
CL = CLmrs = 6

WCK ((
))
((
WCK# ))
((
DQ )) DO DO
n n+7

((
DBI# )) DBI DBI
n n+7

((
)) EDC EDC EDC Hold
EDC (( EDC Hold Pattern n n+7 Pattern
))

CRCRL = 4

DONʹT CARE TRANSITIONING DATA

Notes: 1. CLmrs = 6 and CRCRL = 4 are shown as examples. Actual supported values will be found in the MR and AC timings sections.
2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

3. Before the READ command, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
4. tWCK2DQO = 0 is shown for illustration purposes.

Figure 57. Single READ with EDC

T0 T1 T3 T6 T6n T7 T7n T8 T9 T9n T10 T10n T11

(( ((
CK# )) ))
CK (( ((
)) ))

(( ((
READ NOP )) READ ) )NOP NOP NOP NOP NOP NOP
COMMAND
(( ((
)) ))
tCCD
(( ((
Bank a, Col m )) Bank b, ))
ADDRESS Col n Col n
Col m
(( ((
)) ))
CL = CLmrs = 6
CL = CLmrs = 6
WCK (( ((
)) ))
(( ((
WCK# )) ))
(( ((
DQ )) )) DO DO DO DO
m m+7 n n+7

(( ((
DBI# )) )) DBI DBI DBI DBI
m m+7 n n+7

DONʹT CARE TRANSITIONING DATA

3.  EDC may be on or off.  See Figure 4 for EDC Timing.
4.  tCCD = tCCDL when bank groups are enabled and both READs access banks in the same bank group; otherwise tCCD=tCCDS.
5.  Before the READ commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
6.  tWCK2DQI = 0 is shown for illustration purposes.

Figure 58. Non-Gapless READs

T0 T1 T2 T3 T6 T6n T7 T7n T8 T8n T9 T9n T10

CK# ((
))
CK ((
))

((
READ NOP READ NOP )) NOP NOP NOP NOP NOP
COMMAND
((
))
tCCD
((
Bank a, Bank b, ))
ADDRESS Col m Col m Col n Col n
((
))
CL = CLmrs = 6

WCK ((
))
WCK# ((
))
((
DQ )) DO DO DO DO
m m+7 n n+7

((
DBI# )) DBI DBI DBI DBI
m m+7 n n+7

DONʹT CARE TRANSITIONING DATA

3.  EDC may be on or off.  See Figure 4 for EDC Timing.
4.  tCCD = tCCDS when bank groups are disabled or the second READ is to a different bank group; otherwise tCCD=tCCDL.
5.  Before the READ commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
6.  tWCK2DQI = 0 is shown for illustration purposes.

Figure 59. Gapless READs

T0 T1 T6 T6n T7 T7n T8 T9 T10 T10n T11 T11n T12

((
CK# ))
CK ((
))

((
))
COMMAND READ NOP NOP WRITE NOP NOP NOP NOP NOP
((
tRTW ))

((
Bank a, )) Bank b,
ADDRESS Col m Col m Col n Col n
((
))
CL = CLmrs = 6
WL = WLmrs = 3
WCK ((
))
((
WCK# ))
((
DQ )) DO DO DO DO
m m+7 n n+7

((
DBI# )) DBI DBI DBI DBI
m m+7 n n+7

DONʹT CARE TRANSITIONING DATA

3. EDC may be on or off. See Figure 4 for EDC Timing.
4. tWTR = tWTRL when bank groups is enabled and both WRITE and READ access banks in the same bank group, otherwise tWTR=tWTRS.

Figure 60. READ to WRITE

T0 T1 T2 T3 T4 T5 T6 T6n T7 T7n T8
CK#
CK

COMMAND READ NOP PRE NOP NOP NOP NOP NOP NOP

tRTP tRP

Bank a, Bank a,
ADDRESS Col n Col n
or all

CL = CLmrs = 6

WCK
WCK#

DQ DO DO
n n+7

DBI# DBI DBI

n n+7

DONʹT CARE TRANSITIONING DATA

3.  EDC may be on or off.  See Figure 4 for EDC Timing.
4.  tRTP = tRTPL when bank groups are enabled and the PRECHARGE command accesses the same bank; otherwise tRTP = tRTPS.
5.  Before the READ commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
6.  tWCK2DQO = 0 is shown for illustration purposes.

Figure 61. READ to PRECHARGE

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 94
H5GQ1H24AFR
5.10. DQ PREAMBLE
DQ preamble is a feature for GDDR5 SGRAMs that is used for READ data. DQ preamble conditions the
DQs for better signal integrity on the initial data of a burst.

Once enabled by bit 5 in MR7, the DQ preamble will precede all READ bursts, including non‐consecutive
READ bursts with a minimum gap of 1 tCK, as shown in Figure 58. When enabled, the DQ preamble pat‐
tern applies to all DQ and DBI# pins in a byte, and the same pattern is used for all bytes as shown in
Figure62. DQ preamble is enabled or disabled for all bytes. The EDC pin in each byte is not included in the
DQ preamble. If ODT is enabled, the ODT is disabled 1 tCK before the start of the preamble pattern as
shown in Figure 63.

The preamble pattern on the DBI# pin is only enabled if the MR for RDBI is enabled (MR1 A8 bit). During
the preamble the DBI# pin is treated as another DQ pin and the preamble pattern on the DQs is not
encoded with RDBI. If RDBI is disabled, then the DBI# pin drives ODT.

Byte 0 Byte 1 Byte 2 Byte 3 Idle Preamble Burst

DQ7 DQ15 DQ23 DQ31 1 1 1 1 0 1 0 1 x x x x x x x x

DQ6 DQ14 DQ22 DQ30 1 1 1 1 1 0 1 0 x x x x x x x x

DQ5 DQ13 DQ21 DQ29 1 1 1 1 0 1 0 1 x x x x x x x x

DQ4 DQ12 DQ20 DQ28 1 1 1 1 1 0 1 0 x x x x x x x x

DQ3 DQ11 DQ19 DQ27 1 1 1 1 0 1 0 1 x x x x x x x x

DQ2 DQ10 DQ18 DQ26 1 1 1 1 1 0 1 0 x x x x x x x x

DQ1 DQ9 DQ17 DQ25 1 1 1 1 0 1 0 1 x x x x x x x x

DQ0 DQ8 DQ16 DQ24 1 1 1 1 1 0 1 0 x x x x x x x x

DBI0# DBI1# DBI2# DBI3# 1 1 1 1 0 1 0 1 x x x x x x x x

Max 0’s 0 0 0 0 5 4 5 4 4 4 4 4 4 4 4 4

Time

Notes:
1) The number of Max 0’s in the burst is 4 only if RDBI is enabled. Max 0‘s is on a per byte basis and does not include the EDC pin.
2) x = Valid Data

Figure 62. DQ Preamble Pattern

T0 T1 T4 T5 T5n T6 T6n T7 T7n T8 T9 T10

((
CK# ))
((
CK ))
((
READ NOP )) NOP NOP NOP NOP NOP NOP NOP
COMMAND
((
))
((
Bank a, ))
ADDRESS Col n
Col n
((
))
CL = CLmrs = 6

WCK ((
))
((
WCK# ))

DQ6 ((
)) DO DO
n n+7

DQ7 ((
)) DO DO
n n+7

((
DBI# )) DBI DBI
n n+7

((
ODT ODT Enabled )) ODT Disabled
(( ODT Enabled
))

DONʹT CARE TRANSITIONING DATA

3.  EDC may be on or off.  See Figure 4 for EDC Timing.
4.  DQ6, DQ7 and the DBI# pin are shown to illustrate the DQ preamble pattern. RDBI is Enabled (MR1 A8=0).
5.  Before the READ commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
6.  tWCK2DQO = 0 is shown for illustration purposes.

Figure 63. Preamble Timing Diagram

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 96
H5GQ1H24AFR
5.11. READ and WRITE DATA BUS INVERSION (DBI)
The GDDR5 SGRAM Data Bus Inversion (DBIdc) reduces the DC power consumption on data pins, as the
number of DQ lines driving a low level can be limited to 4 within a byte. DBIdc is evaluated per byte.

There is one DBI# pin per byte: DBI0# is associated with DQ0‐DQ7, DBI1# with DQ8‐DQ15, DBI2# with
DQ16‐DQ23 and DBI3# with DQ24‐DQ31.

The DBI# pins are bidirectional active Low double data rate (DDR) signals. For Writes, they are sampled
by the GDDR5 SGRAM along with the DQ of the same byte. For Reads, they are driven by the GDDR5
SGRAM along with the DQ of the same byte.

Once enabled by the corresponding RDBI Mode Register bit, the GDDR5 SGRAM inverts read data and
sets DBI# Low, when the number of ’0’ data bits within a byte is greater than 4; otherwise the GDDR5
SGRAM does not invert the read data and sets DBI# High, as shown in Figure 64.

Once enabled by the corresponding WDBI Mode Register bit, the GDDR5 SGRAM inverts write data
received on the DQ inputs in case DBI# was sampled Low, or leaves the data non‐inverted in case DBI#
was sampled High, as shown in Figure 65.

from 8
8
DRAM
DQ
core
’0’
count
>4 DBI#

from Mode Register:
0 = enabled
1 = disabled

Figure 64. Example of Data Bus Inversion Logic for READs

8
8 to
DQ
DRAM
core
DBI#

from Mode Register:
0 = enabled
1 = disabled

Figure 65. Example of Data Bus Inversion Logic for WRITEs

The flow diagram in Figure 66 illustrates the DBIdc operation. In any case, the transmitter (the controller
for WRITEs, the GDDR5 SGRAM for READs) decides whether to invert or not invert the data conveyed on
the DQs. The receiver (the GDDR5 SGRAM for WRITEs, the controller for READs) has to perform the
reverse operation based on the level on the DBI# pin. Data input and output timing parameters are only
valid with DBI being enabled and a maximum of 4 data lines per byte driven Low.

Logical
Transmitter output data

Determine ’0’ count
in data byte

’0’ count
No Yes
> 4 ?

DBI# = ’H’ DBI# = ’L’
Don’t invert Invert
data byte data byte

Logical
Receiver input data

Figure 66. DBI Flow Diagram

DBI# Pin Special Function Overview
The DBI# pin has special behavior compared to DQ pins because of the ability to enable and disable it via
MRS. For either WRITE or READ DBI# pin training, both DBI READ and DBI WRITE in MRS must be
enabled. The behavior of the DBI# pin in various mode register settings is summarized below:

If both DBI READ and DBI WRITE are enabled:
• Pin drives DBI FIFO data with RDTR command
• DBI# pin FIFO accepts WRTR data with the WRTR command
If only DBI READ is enabled:
• DBI# pin drives ODT when not READ or RDTR
If only DBI WRITE is enabled:
• Pin always drives ODT (unless RESET)
If both DBI READ and DBI WRITE are disabled:
• DBI# pin drives ODT (unless RESET)

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 98
H5GQ1H24AFR
5.12. ERROR DETECTION CODE (EDC)
The GDDR5 SGRAM provides error detection on the data bus to improve system reliability. The device
generates a checksum per byte lane for both READ and WRITE data and returns the checksum to the con‐
troller. Based on the checksum, the controller can decide if the data (or the returned CRC) was transmitted
in error and retry the READ or WRITE command. The GDDR5 SGRAM itself does not perform any error
correction. The features of the EDC are:
• 8 bit checksum on 72 bits (9 channels x 8 bit burst)
• dedicated EDC transfer pin per 9 channels (4x per GDDR5 SGRAM)
• asymmetrical latencies on EDC transfer for Reads and Writes
The CRC polynomial used by the GDDR5 SGRAM is an ATM‐8 HEC, X^8+X^2+X^1+1. The starting seed
value is set in hardware at “zero”. Table 24 shows the error types that are detectable and the detection rate.

Table 24 Error Correction Details
Error Type Detection Rate
Random Single Bit 100%
Random Double Bit 100%
Random Odd Count 100%
Burst <= 8 100%

The bit ordering calculation for the CRC error detection is optimized for errors in the time burst direction.
Figure 67 shows the bit orientation on a byte lane basis.

T0 Burst 8 Ordering (2 tCK) T0 + 8 U.I.
CRC Data Input
DQ/DBI# bit ordering
0 1 2 3 4 5 6 7

DQ0 0 1 2 3 4 5 6 7

DQ1 8 9 10 11 12 13 14 15

DQ2 16 17 18 19 20 21 22 23

DQ3 24 25 26 27 28 29 30 31

DQ4 32 33 34 35 36 37 38 39

DQ5 40 41 42 43 44 45 46 47

DQ6 48 49 50 51 52 53 54 55

DQ7 56 57 58 59 60 61 62 63

DBI0# 64 65 66 67 68 69 70 71

CRC Polynomial X8 + X2 + X + 1 = 0 x 83 = ( X + 1) (X7 + X6 + X5 + X4 + X3 + X2 + 1)

CRC Data Output T0 Burst 8 Ordering (2 tCK) T0 + 8 U.I.

EDC bit ordering
X0 X1 X2 X3 X4 X5 X6 X7

Figure 67. EDC Calculation matrix

The CRC calculation is embedded into the WRITE and READ data stream as shown in Figure 16:
• for WRITEs, the CRC checksum is calculated on the DQ and DBI# input data before decoding with DBI
• for READs, the CRC checksum is calculated on the DQ and DBI# output data after encoding with DBI

The bit ordering is optimized for errors in the time burst direction. Figure 67 shows the bit orientation on a
byte lane basis. All ʹ1sʹ are assumed in the calculation for the DBI# in burst in case DBI is disabled for
WRITEs or READs in the Mode Register.

The CRC calculation is also not affected by any data mask sent along with WDM, WDMA, WSM or WSMA
commands.

The EDC latency is based on the CAS latency for READ data and the WRITE latency for WRITE data.
Table 25 shows the 2 timing parameters associated with the EDC scheme.

Mode Register 4 is used to determine the functionality of the EDC pin. Register bits A9 and A10 control the
GDDR5 SGRAM’s CRC calculation independently for READs and WRITEs. With EDC off, the calculated
CRC pattern will be replaced by the EDC hold pattern defined in Mode Register bits A0 ‐ A3. See “Mode
Registers on page 39” section for more details.

Table 25 EDC Timing
Description Parameter Value Units
EDC READ Latency tEDCRL CL + CRCRL tCK
EDC WRITE Latency tEDCWL WL + CRCWL tCK

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 101
H5GQ1H24AFR
EDC Pin Special Function Overview
The EDC pin is used for many different functions. The behavior of the EDC pin in various modes is sum‐
marized in Table 26.

Table 26 EDC Pin Behavior
Device Status Condition EDC0‐EDC3 Pin Status
RESET# = LOW Hi‐Z
Device Power‐up RESET# = HIGH; no WCK clocks High
RESET# = HIGH; stable WCK clocks EDC hold pattern (default = ’1111’)
WCK is sampled High EDC hold pattern (’1111’)
WCK2CK Training
WCK is sampled Low Inverted EDC hold pattern (’0000’)
EDC13inv MR4 A11=0 EDC hold pattern
Idle EDC0, EDC2: EDC hold pattern
EDC13inv MR4 A11=1
EDC1, EDC3: inverted EDC hold pattern
WRCRC on CRC data
WRITE Burst
WRCRC off EDC hold pattern
RDCRC on CRC data
READ or RDTR burst
RDCRC off EDC hold pattern
LDFF WRCRC + RDCRC both on or both off EDC hold pattern
WRTR burst ‐ EDC hold pattern
WCK enabled (MR5 A1=0) EDC hold pattern
Power‐Down WCK disabled during Power‐Down
using MR5 A1=1 High

Self Refresh ‐ High

Read Burst in RDQS Mode MR3 A5=1 Fixed ’1010’ strobe pattern with 4 U.I.

preamble
EDC0, EDC2: Fixed ’1010’ strobe pattern
READ burst in RDQS Mode with with 4 U.I. preamble
MR3 A5=1; EDC13inv MR4 A11=1
RDQS pseudo‐differential EDC1, EDC3: Fixed ’0101’ strobe pattern
with 4 U.I. preamble

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 102
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5.13. PRECHARGE
The PRECHARGE command (see Figure 68) is used to deactivate the open row in a particular bank (PRE)
or the open row in all banks (PREALL). The bank(s) will be available for a subsequent row access a speci‐
fied time (tRP) after the PRECHARGE command is issued as illustrated in Figure 39.

Input A8 determines whether one or all banks are to be precharged. In case where only one bank is to be
precharged, inputs BA0‐BA3 select the bank. Otherwise BA0‐BA3 are treated as “Don’t Care”.

Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE
command being issued. A PRECHARGE command will be treated as a NOP if there is no open row in that
bank, or if the previously open row is already in the process of precharging. Sequences of PRECHARGE
commands must be spaced by at least tPPD as shown in Figure 69.

Precharge
CK#

CKE# LOW

CS#

RAS#

CAS#

WE#

A9‐A11(A12)
A0,A1,A6,A7

PREALL
A8
A7
PRE

BA0‐BA3 BA
A2‐A5

BA = Bank Address (if A8 is LOW;
otherwise Donʹt Care)

Figure 68. PRECHARGE command

T0 T1 T2 T3 T4
CK#
CK

CMD NOP PRE NOP PRE NOP

ADDR BAx BAy

tRAS tPPD tRP

BAx,y = bank address x,y Donʹt Care

Figure 69. Precharge to Precharge Timings

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 103
H5GQ1H24AFR
5.14. AUTO PRECHARGE
Auto Precharge is a feature which performs the same individual bank precharge function as described
above, but without requiring an explicit command. This is accomplished by using A8 (A8 = High), to
enable Auto Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank
/ row that is addressed with the READ or WRITE command is automatically performed upon completion
of the read or write burst. Auto Precharge is non persistent in that it is either enabled or disabled for each
individual READ or WRITE command.

Auto Precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The user
must not issue another command to the same bank until the precharge time (tRP) is completed. This is
determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described
for each burst type in the OPERATION section of this specification.

5.15. REFRESH
The REFRESH command is used during normal operation of the GDDR5 SGRAM. The command is non
persistent, so it must be issued each time a refresh is required. A minimum time tRFC is required between
two REFRESH commands. The same rule applies to any access command after the refresh operation. All
banks must be precharged prior to the REFRESH command.

The refresh addressing is generated by the internal refresh controller. This makes the address bits ʺDonʹt
Careʺ during a REFRESH command. The GDDR5 SGRAM requires REFRESH cycles at an average peri‐
odic interval of tREFI(max). The values of tREFI for different densities are listed in Table 6. To allow for
improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of eight REFRESH commands can be posted to the GDDR5 SGRAM, and
the maximum absolute interval between any REFRESH command and the next REFRESH command is 9 *
tREFI.

During REFRESH, and when bit A2 in MR5 is set to 0, WRTR, RDTR, and LDFF commands are allowed at
time tREFTR after the REFRESH command, which enable (incremental) data training to occur in parallel
with the internal refresh operation and thus without loss of performance on the interface. See READ Train‐
ing and WRITE Training for details.

As impedance updates from the auto‐calibration engine may occur with any REFRESH command, it is safe
to only issue NOP commands during tKO period to prevent false command, address or data latching
resulting from impedance updates.

Refresh
CK#

CKE# LOW

CS#

RAS#

CAS#

WE#

A9‐A11 (A12)
A0,A1,A6

A8
A7

BA0‐BA3
A2‐A5

Figure 70. REFRESH command

T0 T1 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tc0

CK#
CK

CMD PRE NOP REF NOP WRTR NOP NOP NOP NOP NOP ACT
ALL
tREFTR
tRP tRFC

ADDR BA
RA
tKO WL = 3
WCK
WCK#
D0
D1
D2
D3
D4
D5
D6
D7

BA = bank address; RA = row address
Donʹt Care
WRTR and RDTR commands are allowed during refresh unless disabled in the Mode Register
WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines
the needed offset between WCK and CK.

Figure 71. Refresh Timings

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 105
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5.16. SELF‐REFRESH
Self‐Refresh can be used to retain data in the GDDR5 SGRAM, even if the rest of the system is powered
down. When in the Self‐Refresh mode, the GDDR5 SGRAM retains data without external clocking. The
SELF REFRESH ENTRY command (see Figure 72) is initiated like a REFRESH command except that CKE#
is pulled HIGH. SELF REFRESH ENTRY is only allowed when all banks are precharged with tRP satisfied,
and when the last data element or CRC data element from a preceding READ or WRITE command have
been pushed out (tRDSRE). NOP commands are required until tCKSRE is met after the entering Self‐Refresh.
The PLL is automatically disabled upon entering Self‐Refresh and is automatically enabled and reset upon
exiting Self‐Refresh. If the GDDR5 SGRAM enters Self‐Refresh with the PLL disabled, it will exit Self‐
Refresh with the PLL disabled.

Once the SELF REFRESH ENTRY command is registered, CKE# must be held HIGH to keep the device in
Self‐Refresh mode. When the device has entered the Self‐Refresh mode, all external control signals, except
CKE# and RESET# are “Don’t care”. For proper Self‐Refresh operation, all power supply and reference
pins (VDD, VDDQ, VSS, VSSQ, VREFC, VREFD) must be at valid levels. The GDDR5 SGRAM initiates a
minimum of one internal refresh within tCKE period once it enters Self‐Refresh mode. The address, com‐
mand, data and WCK pins are in ODT state, and the EDC pins drive a HIGH.

The clock is internally disabled during Self‐Refresh operation to save power. The minimum time that the
GDDR5 SGRAM must remain in Self‐Refresh mode is tCKE. The user may change the external clock fre‐
quency or halt the external CK and WCK clocks tCKSRE after Self‐Refresh entry is registered. However, the
clocks must be restarted and stable tCKSRX before the device can exit Self‐Refresh operation.

The procedure for exiting Self‐Refresh requires a sequence of events. First, the CK and WCK clocks must
be stable prior to CKE# going back LOW. A delay of at least tXSNRW must be satisfied before a valid com‐
mand not requiring a locked PLL can be issued to the device to allow for completion of any internal
refresh in progress. Before a command requiring a locked PLL can be applied, a delay of at least tXSRW
must be satisfied.

During Self‐Refresh the on‐die termination (ODT) and driver will not be auto‐calibrated. Therefore, it is
recommended that the ODT and driver be recalibrated by the controller upon exiting Self‐Refresh. Alter‐
natively, if changes in voltage and temperature are tracked or known to be bounded then the provided
Voltage and Temperature Variation tables may be consulted to determine if recalibration is necessary.

Upon exit from Self‐Refresh, the GDDR5 SGRAM can be put back into Self‐Refresh mode after waiting at
least tXSNRW period and issuing one extra REFRESH command.

Self‐Refresh
CK#

CK
HIGH
CKE#

CS#

RAS#

CAS#

WE#

A9‐A11 (A12)
A0,A1,A6

A8
A7

BA0‐BA3
A2‐A5

Figure 72. SELF REFRESH Entry Command

T0 T1 T2 Ta0 Tb0 Tb1 Tb2 Tc0 Td0

CK#
CK
tCKSRE tCKSRX
tCMDS
CKE#
tRDSRE or tWRSRE tXSRW
tCPDED tXSNRW
tRP
CMD NOP SRE NOP NOP NOP SRX PREA Valid

ADDR

Enter Self Refresh Mode Exit Self Refresh Mode Donʹt Care

Self refresh exit requires WCK2CK training prior to any WRITE or READ operation
At least one REFRESH command shall be issued after tXSNRW for output driver and termination impedance updates.

Figure 73. Self Refresh Entry and Exit

Note:
1.   Clock(CK and CK#) must be stable before exiting self refresh mode.
2.   Device must be in the all banks idle state prior to entering self refresh mode.
3.   tXSNRW is required before any non‐READ or WRITE command can be applied, and tXSRW is required before a READ or WRITE command can be
applied.
4.   REF = REFRESH command.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 107
H5GQ1H24AFR
Table 27 Pin States During Self Refresh
Pin State
EDC High
DQ/DBI# ODT
ADR/CMD ODT
CKE# ODT (Driven High by Controller)
WCK/WCK# ODT

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 108
H5GQ1H24AFR
5.17. POWER‐DOWN
GDDR5 SGRAMs requires CKE# to be LOW at all times an access is in progress: from the issuing of a
READ or WRITE command until completion of the burst. For READs, a burst completion is defined as
when the last data element including CRC has been transmitted on the DQ outputs, for WRITEs, a burst
completion is defined as when the last data element has been written to the memory array and CRC data
has been returned to the controller.

POWER‐DOWN is entered when CKE# is registered HIGH. If POWER‐DOWN occurs when all banks are
idle, this mode is referred to as precharge POWER‐DOWN; if POWER‐DOWN occurs when there is a row
active in any bank, this mode is referred to as active POWER‐DOWN. Entering POWER‐DOWN deacti‐
vates the input and output buffers, excluding CK, CK#, WCK, WCK#, EDC pins and CKE#.

For maximum power savings, the user has the option of disabling the PLL prior to entering POWER‐
DOWN. In that case, on exiting POWER‐DOWN, WCK2CK training is required to set the internal synchro‐
nizers which will include the enabling of the PLL, PLL reset, and tLK clock cycles must occur before any
READ or WRITE command can be issued.

While in power‐down, CKE# HIGH and stable CK and WCK signals must be maintained at the device
inputs. The EDC pins continuously drive the EDC hold pattern; if the controller does not require CDR,
users may program the EDC hold pattern to ’1111’ prior to entering power‐down mode. POWER‐DOWN
duration is limited by the refresh requirements of the device.

The POWER‐DOWN state is synchronously exited when CKE# is registered LOW (in conjunction with a
NOP or DESELECT command). A valid executable command may be applied tXPN cycles later. The min.
power‐down duration is specified by tPD.

T0 T1 T2 T3 T4 Ta0 Ta1 Ta2 Tb0

CK#
CK

CKE#
tCPDED
tRDSRE or tWRSRE tPD tXPN

CMD NOP PDE NOP NOP NOP PDX Valid

WCK
WCK#

Enter Power‐Down Mode Exit Power‐Down Mode Donʹt Care

Figure 74. Power-Down Entry and Exit

Note:
1. Minimum CKE# pulse width must satisfy tCKE.
2. After issuing Power‐Down command, two more NOPs should be issued.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 109
H5GQ1H24AFR
Table 28 Pin States During Power Down
Pin LP2 State
WCK ‘Hold’
EDC
no WCK High
DQ/DBI# x ODT
ADR/CMD x ODT
CKE# x ODT (Driven High by Controller)
WCK/WCK# x ODT

5.18. COMMAND TRUTH TABLES

Table 29 Truth Table – CKE#
CURRENT
CKE#n‐1 CKE#n COMMANDn ACTIONn NOTES
STATE

H H Power‐Down X Maintain Power‐Down

H H Self Refresh X Maintain Self Refresh

H L Power‐Down DESELECT or NOP Exit Power‐Down

H L Self Refresh DESELECT or NOP Exit Self Refresh 5

L H All Banks Idle DESELECT or NOP Precharge Power‐Down Entry

L H Bank(s) Active DESELECT or NOP Active Power‐Down Entry

L H All Banks Idle REFRESH Self Refresh Entry

L L See <Link>Table 30 and 1, 2, 3
<Link>Table 31

Notes:
1.  CKE#n is the logic state of CKE# at clock edge n; CKE#n‐1 was the state of CKE# at the previous clock edge.
2.  Current state is the state of the GDDR5 SGRAM immediately prior to clock edge n.
3.  COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4.  All states and sequences not shown are illegal or reserved.
5.  DESELECT or NOP commands should be issued on any clock edges occurring during the tXSRW period. A minimum of tLK is
needed for the PLL to lock before applying a READ or WRITE command if the PLL was disabled.

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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 110
H5GQ1H24AFR
Table 30 Truth Table – Current State Bank n – Command To Bank n
CURRENT
CS# RAS# CAS# WE# COMMAND/ACTION NOTES
STATE
H X X X DESELECT (NOP/continue previous operation)
Any
L H H H NO OPERATION (NOP/continue previous operation)
L L H H ACTIVE (select and activate row)
Idle L L L H REFRESH 4
L L L L MODE REGISTER SET 4
L H L H READ (select column and start READ burst) 6
WRITE (select column and start WRITE burst)
Row Active L H L L 6
(WOM, WSM or WDM)
L L H L PRECHARGE (deactivate row in bank or banks) 5
L H L H READ (select column and start new READ burst) 6
Read
(Auto WRITE (select column and start WRITE burst)
L H L L 6, 8
Precharge (WOM, WSM or WDM)
Disabled)
L L H L PRECHARGE (only after the READ burst is complete 5
Write L H L H READ (select column and start READ burst) 6, 7
(Auto
Precharge WRITE (select column and start new WRITE burst)
L H L L 6
Disabled) (WOM, WSM or WDM)
(WOM, WSM
or WDM) L L H L PRECHARGE (only after the WRITE burst is complete) 5, 7

Notes
1.  This table applies when CKE#n‐1 was LOW and CKE#n is LOW (see <Link>Table 29) and after tXSNR has been met (if the previous
state was self refresh).
2.  This table is bank‐specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those
allowed to be issued to that bank when in that state). Exceptions are covered in the notes below.
3.  Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are
in progress.
Read: A READ burst has been initiated, with auto precharge disabled.
Write: A WRITE burst has been initiated, with auto precharge disabled.
4.  The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or allowable
commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and <Link>Table 30, and according to <Link>Table 31.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in
the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be
in the “row active” state.
Read w/Auto‐Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto‐Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
5.  The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each
positive clock edge during these states.
Refreshing: Starts with registration of a REFRESH command and ends when tRC is met. Once tRC is met, the GDDR5 SGRAM will
be in the all banks idle state.
Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once
tMRD is met, the GDDR5 SGRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks
will be in the idle state.
READ or WRITE: Starts with the registration of the ACTIVE command and ends the last valid data nibble.
6.  All states and sequences not shown are illegal or reserved.
7.  Not bank‐specific; requires that all banks are idle, and bursts are not in progress.
8.  May or may not be bank‐specific; if multiple banks are to be precharged, each must be in a valid state for precharging.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 111
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9. Reads or Writes listed in the Command/Action column include Reads or Writes with auto precharge enabled and Reads or Writes
with auto precharge disabled.
10. A WRITE command may be applied after the completion of the READ burst

Table 31 Truth Table – Current State Bank n – Command To Bank m
CURRENT
CS# RAS# CAS# WE# COMMAND/ACTION NOTES
STATE
Any H X X X DESELECT (NOP/continue previous operation)
L H H H NO OPERATION (NOP/continue previous operation)
Idle X X X X Any Command Otherwise Allowed to Bank m
Row Activating, L L H H ACTIVE (select and activate row)
Active, or L H L H READ (select column and start READ burst) 6
Precharging
L H L L WRITE (select column and start WRITE burst) 6
(WOM, WSM or WDM)
L L H L PRECHARGE
Read L L H H ACTIVE (select and activate row)
(Auto Precharge L H L H READ (select column and start new READ burst) 6
Disabled)
L H L L WRITE (select column and start WRITE burst) 6
(WOM, WSM or WDM)
L L H L PRECHARGE
Write L L H H ACTIVE (select and activate row)
(Auto Precharge L H L H READ (select column and start READ burst) 6, 7
Disabled)
L H L L WRITE (select column and start new WRITE burst) 6
(WOM, WSM or WDM)
L L H L PRECHARGE
Read L L H H ACTIVE (select and activate row)
(With Auto L H L H READ (select column and start new READ burst) 6
Precharge)
L H L L WRITE (select column and start WRITE burst) 6
(WOM, WSM or WDM)
L L H L PRECHARGE
Write L L H H ACTIVE (select and activate row)
(With Auto L H L H READ (select column and start READ burst) 6
Precharge)
L H L L WRITE (select column and start new WRITE burst) 6
(WOM, WSM or WDM)
L L H L PRECHARGE

Notes
1.  This table applies when CKE#n‐1 was LOW and CKE#n is LOW (see <Link>Table 30) and after tXSNR has been met (if the previous
state was self refresh).
2.  WRITE in this table refers to both WOM/WOMA, WSM/WSMA and WDM/WDMA commands
3.  This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are
those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable). Exceptions
are covered in the notes below.
4.  Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are
in progress.
Read: A READ burst has been initiated, with auto precharge disabled.
Write: A WRITE burst has been initiated, with auto precharge disabled.
Read with Auto Precharge Enabled: See following text
Write with Auto Precharge Enabled: See following text

4a. The read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access
period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was

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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 112
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executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses
all of the data in the burst. For write with auto precharge, the precharge period begins when tWR ends, with tWR measured as if
auto precharge was disabled. The access period starts with registration of the command and ends where the precharge period
(or tRP) begins. During the precharge period of the read with auto precharge enabled or write with auto precharge enabled
states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied. In either case, all other related
limitations apply (e.g., contention between read data and write data must be avoided).

4b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different bank is
summarized below.
5.  REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.
6.  All states and sequences not shown are illegal or reserved.
7.  READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or
WRITEs with auto precharge disabled.

Table 32  Minimum Delay Between Commands to Different Banks with Auto Precharge Enabled
From Command To Command Minimum delay
(with concurrent auto precharge)
READ or READ with AUTO PRECHARGE [WLmrs + (BL/4)] tCK + tWTRL ***
WRITE WRITE or WRITE with AUTO PRECHARGE 2 * tCK
with AUTO (WOM/WOMA, WSM/WSMA or WDM/WDMA)
PRECHARGE
(WOMA) PRECHARGE 1 tCK
ACTIVE 1 tCK
READ or READ with AUTO PRECHARGE [WL + (BL/4)] tCK + tWTR ***
WRITE WRITE or WRITE with AUTO PRECHARGE 2 * tCK
with AUTO (WOM/WOMA, WSM/WSMA or WDM/WDMA)
PRECHARGE
(WDMA) PRECHARGE 2 tCK
ACTIVE 2 tCK
READ or READ with AUTO PRECHARGE [WL + (BL/4)] tCK + tWTR  ***
WRITE WRITE or WRITE with AUTO PRECHARGE 3 * tCK
with AUTO (WOM/WOMA, WSM/WSMA or WDM/WDMA)
PRECHARGE
(WSMA) PRECHARGE 3 tCK
ACTIVE 3 tCK
READ or READ with AUTO PRECHARGE 2 * tCK
READ WRITE or WRITE with AUTO PRECHARGE [CLmrs + (BL/4) + 2 ‐ WL] * tCK  ***
with AUTO (WOM/WOMA, WSM/WSMA or WDM/ WDMA)
PRECHARGE PRECHARGE 1 tCK
ACTIVE 1 tCK

*** CL = CAS latency (CL)
BL = Burst length
WL = WRITE latency
tWTR = tWTRL if Bank Groups enabled and access to the same bank otherwise tWTR=tWTRS

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 113
H5GQ1H24AFR
5.19. RDQS MODE
For device operation at lower clock frequencies the GDDR5 SGRAM may be set into RDQS mode in which
a READ DATA STROBE (RDQS) in the style of GDDR4 will be sent on the EDC pins along with the READ
data. The controller will use the RDQS to latch the READ data.

RDQS mode is entered by setting the RDQS Mode bit A5 in Mode Register 3 (MR3). When the bit is set, the
GDDR5 SGRAM will asynchronously terminate any EDC hold pattern and drive a logic HIGH after tMRD
at the latest. All features controlled by MR4 are ignored by RDQS mode.

READ commands are executed as in normal mode regarding command to data out delay and pro‐
grammed READ latencies. A fixed clock‐like pattern as shown in Figure 75 is driven on EDC pins in phase
(edge aligned) with the DQ. Prior to the first valid data element, this fixed clock‐like pattern or READ pre‐
amble is driven for 2 tWCK.

No CRC is calculated in RDQS mode, neither for READs nor for WRITEs. The CRC engine is effectively
disabled, and the corresponding WRCRC and RDCRC Mode Register bits are ignored. The PLL may be on
or off with RDQS mode, depending on system considerations and the PLL’s minimum clock frequency.

There is no equivalent WDQS mode; WRITE commands to the GDDR5 SGRAM are not affected by RDQS
mode.

RDQS mode is exited by resetting the RDQS Mode bit. In this case the GDDR5 SGRAM will asynchro‐
nously start driving the EDC hold pattern after tMRD.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 114
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The WCK2CK training should be performed prior to entering RDQS mode. No WCK2CK training can be
done when the RDQS mode is active.

T0 T1 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tc0

CK#
CK

CMD MRS NOP READ NOP NOP NOP NOP NOP MRS NOP NOP

ADDR MRA MRA BA CA MRA MRA

tMRD CLmrs tMRD

WCK
WCK# D0
D1
D2
D3
D4
D5
D6
D7
DQ

EDC EDC
Hold
EDC
Hold

Enter RDQS Mode Exit RDQS Mode Donʹt Care

1. MRA = Mode Register address and opcode; BA = bank address; CA = column address

2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

3. Before the READ command, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.
4. tWCK2DQO = 0 is shown for illustration purposes.

Figure 75. RDQS Mode Timings

EDC1 and EDC3 can be treated as pseudo‐differential to EDC0 and EDC2 respectively, by setting the
EDC13Inv field, bit A11 in MR4, as shown in Table 34.

Table 33 EDC pin behavior in RDQS mode including pseudo‐differential RDQS
NOP
POWER‐
(except
MRS Set READ/RDTR DOWN/SELF
RD/RDTR/
REFRESH
PDN/SRF)

WCK2CK EDC02 EDC13 EDC0123 EDC0123

RDQS Mode EDC13 Invert
Training Output Output Output Output

Off RDQS RDQS 1111 High

On Off
On RDQS Inverted 1111 High
RDQS

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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 115
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5.20. CLOCK FREQUENCY CHANGE SEQUENCE
Step 1) Wait until all commands have finished, all banks are idle.

Step 2) Send NOP or DESELECT (must meet setup/hold relative to clock while clock is changing) to
GDDR5 SGRAM for the entire sequence unless stated to do otherwise. The user must take care of refresh
requirements.

Step 3) If the new desired clock frequency is below the min frequency supported by PLL‐on mode, turn the
PLL off via an MRS command.

Step 4) Change the clock frequency and wait until clock is stabilized.

Step 5) If the new clock frequency is within the PLL on range and the PLL on state is desired, enable the
PLL via an MRS Command if it is not already enabled.

Step 6) Perform address training if required.

Step 7) Perform WCK2CK training. As defined in the WCK2CK training process, if the PLL is enabled,
then complete steps 7a and 7b:

7a) Reset the PLL by writing to the MRS register.

7b) Wait tLK clock cycles before issuing any commands to the GDDR5 SGRAM.

Step 8) Exit WCK2CK training.

Step 9) Perform READ and WRITE training, if required.

Step 10) GDDR5 SGRAM is ready for normal operation after any necessary interface training.

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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 116
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5.21. DYNAMIC VOLTAGE SWITCHING (DVS)
GDDR5 SGRAM’s allow the supply voltage to be changed during the course of normal operation using the
GDDR5 Dynamic Voltage Switching (DVS) feature. By using DVS the GDDR5 SGRAM’s power consump‐
tion can be reduced whenever only a fraction of the maximum available bandwidth is required by the cur‐
rent work load.

DVS requires the GDDR5 SGRAM to be properly placed into self refresh before the voltage is changed
from the exising stable voltage, Voriginal to the new desired voltage Vnew . The DVS procedure may also
require changes to the VDD Range mode register using MR7 bits A8 and A9, depending on whether the
feature is supported. The datasheet shall be consulted regarding the supported supply voltages for DVS,
and any dependencies of AC timing parameters on the selected supply voltage.

Clock frequency changes can also take place before or after entering self refresh mode using the standard
Clock Frequency Change procedure. A clock frequency change in conjunction with DVS is required if tCK
is less than tCKmin supported by Vnew . In this case normal device operation including self refresh exit is
not guaranteed without a frequency change. Changing the frequency while in self refresh is the most safe
procedure.

Once self refresh is entered, tCKSRE must be met before the supply voltage is allowed to transition from
Voriginal to Vnew. After VDD and VDDQ are stable at Vnew, tVS must be met to allow for internal voltages
in the GDDR5 SGRAM to stabilize before self refresh mode may be exited. During the voltage transition
the voltage must not go below Vmin of the lower voltage of either Voriginal or Vnew in order to prevent false
chip reset. Vmin is the minimum voltage allowed by VDD or VDDQ in the DC operating conditions table.
VREF shall continue to track VDDQ.

DVS Procedure
Step 1) Complete all operations and precharge all banks.
Step 2) Issue an MRS command to set VDD Range to proper values for Vnew. This step is only required when the VDD
Range mode register field is supported by the GDDR5 SGRAM.
Step 3) Enter self refresh mode. Self refresh entry procedure must be met.
Step 4) Wait required time tCKSRE before changing voltage to Vnew.
Step 5) Change VDD and VDDQ to Vnew.
Step 6) Wait required time tVS for voltage stabilization.
Step 7) Exit self refresh. The self refresh exit procedure must be met.
Step 8) Issue MRS commands to adjust mode register settings as desired (e.g. latencies, PLL on/off, CRC on/off, RDQS
mode on/off).
Step 9) Perform any interface training as required.
Step 10) Continue normal operation.

T0 T1 T2 Ta0 Tb0 Tb1 Tb2 Tc0 Td0

Voriginal
VDD, Vnew
VDDQ VSS, VSSQ

Voltage ramp tVS
CK#
CK
tCKSRE tCKSRX

CKE#
tRDSRE or tWRSRE tXSRW
tCPDED tXSNRW
tRP
CMD NOP SRE NOP NOP NOP SRX PREA Valid

Enter Self‐Refresh Mode Exit Self‐ Refresh Mode Donʹt Care

Self refresh exit requires WCK2CK training prior to any WRITE or READ operation
At least one REFRESH command shall be issued after tXSNRW for output driver and termination impedance updates
Voriginal > Vnew shown as an example of a voltage change

Figure 76. DVS Sequence

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 118
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5.22. TEMPERATURE SENSOR
GDDR5 SGRAMs incorporate a temperature sensor with digital temperature readout function. This func‐
tion allows the controller to monitor the GDDR5 SGRAM die’s junction temperature and use this informa‐
tion to make sure the device is operated within the specified temperature range or to adjust interface
timings relative to temperature changes over time.

The temperature sensor is enabled by bit A6 in Mode Register 7 (MR7). In this case the temperature read‐
out is valid after tTSEN. Hynix applies 10us to tTSEN.

The temperature readout uses the DRAM Info mode feature. The digital value is driven asynchronously
on the DQ bus following the MRS command to Mode Register 3 (MR3) that sets bit A7 to 1 and bit A6 to 0.
The temperature readout will be continuously driven until an MRS command sets both bits to 0.

The GDDR5 SGRAM’s junction temperature is linearly encoded as shown in Table 35. Hynix has the read‐
out to a subset of six digital codes out of Table 35, corresponding to six temperature thresholds.

Table 34 Temperature Sensor Readout Pattern
Binary Temperature Readout
Temperature [°C] MF=0: DQ[5:0]
MF=1: DQ[31:26]
＜ 45 000000
55 000001
65 000011
75 000111
85 001111
95 011111
＞ 95 111111

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 119
H5GQ1H24AFR
5.23. DUTY CYCLE CORRECTOR (DCC)
As GDDR5 SGRAMs can operate with the PLL off during normal operation, the use of a Duty Cycle Cor‐
rector (DCC) can correct for the duty cycle of the WCK. DCC can be used at any time, however, rising and
falling edges of WCK can be shifted according to the DCC type. The DCC should be enabled before WCK
training and should be run for tDCC in order to effectively correct any error.
Table 35 DCC Timings
Parameter Symbol Min Max Unit
Required time for duty cycle corrector tDCC 150 ‐ tCK

DCC can correct the duty cycle error within the range of ± 100ps.

WCK#

WCK

CK#

CMD NOP NOP MRS NOP NOP NOP NOP MRS MRS A.C.

tWCKTMRS tMRD tLK tMRD

tWCKTTR tDCC

Start WCK2CK Phase
Enter WCK2CK PLL Reset Enter WCK2CK
Training
Training (reset WCK Training (sets data
divide by circuits) synchronizers, resets
DCC reset FIFO pointers)
DCC start
DCC stop or not

Figure 77. Timing Diagram of DCC Control Signals

DCC control signals
• DCC reset : The DCC reset is used to initialize the DCC code and should be issued anytime before the WCK
enables (MRS7 A11:1, A10:0)
• DCC start : The DCC start is used to update the DCC code and should be issued anytime after the WCK is stable
(MRS7 A11:0, A10:1)
• DCC stop : The DCC stop is used to make it stop to update the DCC code while the DCC code is held. This should
be issued after enough time from DCC start if needs (MRS7 A11:0, A10:0)

Table 36 DCC Control Signals
A11 A10 DCC
0 0 no DCC & DCC stop
0 1 DCC start
1 0 DCC reset
1 1 RFU

6. OPERATING CONDITIONS
6.1. ABSOLUTE MAXIMUM RATINGS
Voltage on Vdd Supply
    Relative to Vss...................................................  ‐0.5V to +2.0V
Voltage on VddQ Supply
    Relative to Vss ..................................................  ‐0.5V to +2.0V
Voltage on Vref and Inputs
    Relative to Vss ..................................................  ‐0.5V to +2.0V
Voltage on I/O Pins
    Relative to Vss ..................................................  ‐0.5V to VddQ +0.5V
Storage Temperature (plastic) ............................  ‐55°C to +150°C
Short Circuit Output Current .............................  50mA

*Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Table 37 Capacitance
PARAMETER SYMBOL MIN MAX UNITS NOTES

Delta Input/Output Capacitance: DQs, DBI#, EDC,
WCK, WCK# DCio 0 0.5 pF

Delta Input Capacitance: Command and Address DCi1 0 0.5 pF

Delta Input Capacitance: CK, CK# DCi2 0 0.3 pF

Input/Output Capacitance: DQs, DBI#, EDC, WCK,
WCK# Cio 1.2 1.9 pF

Input Capacitance: Command and Address Ci1 0.9 1.6 pF

Input Capacitance: CK, CK#, WCK, WCK# Ci2 0.9 1.6 pF

Input Capacitance: CKE# Ci3 0.9 1.6 pF

Table 38 Thermal Characteristics

Parameter Description Value Units Notes

o
45 C/W 1,2,4,5
1s
33 oC/W 1,4,5 (at Tc 115oC)
Theta_JA Thermal resistance junction to ambient

2s2p 30 oC/W 1,2,4,5

o
Theta_JB Thermal resistance junction to board 12 C/W 1,3

Theta_JC Thermal resistance junction to case 3 oC/W 1,6

Notes:
1. Measurement procedures for each parameter must follow standard procedures defined in the current JEDEC JESD‐51 standard.
2. Theta_JA measured with the low and high thermal conductivity test board defined in JESD51‐9

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 122
H5GQ1H24AFR
3.  Theta_JB measured with the special boundary condition defined in JESD51‐8
4.  Theta_JA  should only be used for comparing the thermal performance of single package and not for system related junction.
5.  Theta_JA is  the  natural convection junction‐to‐ambient  air thermal  resistance measured in one cubic  foot sealed enclosure
     as decribed in JESD  51‐2.
     The environment is sometimes refered to  as “still‐air” although  natural convection causes  the  air to move.
6.  Theta_JC case surface is defined as the “outside surface of the package (case) closest to  the  chip  mounting area when  that
     same  surface is properly hear sunk” so as to minimize temperature variation across that surface.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 123
H5GQ1H24AFR
6.2. AC & DC CHARACTERISTICS
All GDDR5 SGRAMs are designed for 1.5V typical voltage supplies. The interface of GDDR5 with 1.5V
VDDQ will follow the POD15 specification. All AC and DC values are measured at the ball.
Table 39 DC Operating Conditions
Parameter Symbol Min Typ Max Unit Note
Device Supply Voltage VDD 1.452 1.6 1.648 V 1
Output Supply Voltage VDDQ 1.452 1.6 1.648 V 1
Device Supply Voltage VDD 1.455 1.5 1.545 V 2
Output Supply Voltage VDDQ 1.455 1.5 1.545 V 2
Reference Voltage for DQ and DBI# pins VREFD 0.69 * VDDQ 0.71 * VDDQ V 3, 4
Reference Voltage for DQ and DBI# pins VREFD2 0.49 * VDDQ 0.51 * VDDQ V 3, 4, 5
External Reference Voltage for address and VREFC 0.69 * VDDQ 0.71 * VDDQ V 6
command
DC Input Logic HIGH Voltage for address and
VIHA (DC) VREFC + 0.15 V
command
DC Input Logic LOW Voltage for address and
command VILA (DC) VREFC ‐ 0.15 V

DC Input Logic HIGH Voltage for DQ and DBI# VIHD (DC) VREFD + 0.10 V

pins with VREFD
DC Input Logic LOW Voltage for DQ and DBI#
VILD (DC) VREFD ‐ 0.10 V
pins with VREFD
DC Input Logic HIGH Voltage for DQ and DBI# VIHD2
pins with VREFD2 (DC) VREFD2 + 0.30 V

DC Input Logic LOW Voltage for DQ and DBI# VILD2 (DC) VREFD2 ‐ 0.30 V

pins with VREFD2
Input Logic HIGH Voltage for RESET#, SEN, MF VIHR VDDQ ‐ 0.50 V
Input Logic LOW Voltage for RESET#, SEN, MF VILR 0.30 V
Input logic HIGH voltage for
VIHX VDDQ ‐ 0.3 V 9
EDC1/2 (x16 mode detect)
Input logic LOW voltage for
VILX 0.30 V 9
EDC1/2 (x16 mode detect)
Input Leakage Current
Any Input 0V <= VIN <= VDDQ Il 10 μA
(All other pins not under test = 0V)
Output Leakage Current
Ioz 10 μA
(DQs are disabled; 0V <= Vout <= VDDQ)
Output Logic LOW Voltage VOL (DC) 0.62 V

Notes:
1.  VDD/VDDQ 1.6V is for 6Gbps
2.  GDDR5 SGRAMs are designed to tolerate PCB designs with separate VDD and VDDQ power regulators.
3.  AC noise in the system is estimated at 50mV pk‐pk for the purpose of DRAM design.
4.  Source of Reference Voltage and control of Reference Voltage for DQ and DBI# pins is determined by VREFD, Half VREFD, Auto
VREFD, VREFD MERGE and VREFD Offsets mode registers.
5.  VREFD Offsets are not supported with VREFD2.
6.  External VREFC is to be provided by the controller as there is no other alternative supply.
7.  DQ/DBI# input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFD crossing and VIHD(AC)
or VILD(AC) or VREFD2 crossing and VIHD2(AC) or VILD2(AC).
8.  ADR/CMD input slew rate must be greater than or equal to 3V/ns.  The slew rate is measured between VREFC crossing and
VIHA(AC) or VILA(AC).
9.  VIHX and VILX define the voltage levels for the receiver that detects x32 or x16 mode with RESET# going High.

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 124
H5GQ1H24AFR
Table 40 AC Operating Conditions
POD15
Parameter Symbol Min Typ Max Unit Note
AC Input Logic HIGH Voltage for VIHA (AC) VREFC + 0.20 V
address and command
AC Input Logic LOW Voltage for
VILA (AC) VREFC ‐ 0.20 V
address and command
AC Input Logic HIGH Voltage for
VIHD (AC) VREFD + 0.15 V
DQ and DBI# pins with VREFD
AC Input Logic LOW Voltage for
DQ and DBI# pins with VREFD VILD (AC) VREFD ‐ 0.15 V

AC Input Logic HIGH Voltage for VIHD2 (AC) VREFD2 + 0.40 V

DQ and DBI# pins with VREFD2
AC Input Logic LOW Voltage for
VILD2 (AC) VREFD2 ‐ 0.40 V
DQ and DBI# pins with VREFD2

VDDQ

VOH
System Noise Margin (Power/Ground,
Crosstalk, Signal Integrity Attenuation)

VIH (AC)

VIH (DC)

VREF + AC Noise
VREF + DC Noise
VREF ‐ DC Noise
VREF ‐ AC Noise

VIL (DC)

VIL (AC)
VIN (AC) ‐ Provides margin
between VOL (MAX) and
VIL (AC)
VOL (MAX)

Note: VREF, VIH, VIL refer to
whichever VREFxx (VREFD,
VREFD2, or VREFC) is being used.

Output Input

Figure 78. Voltage Waveform

Table 41 Clock Input Operating Conditions
POD15
Parameter Symbol Min Max Unit Note
Clock Input Mid‐Point Voltage; CK and CK# VMP (DC) VREFC ‐ 0.10 VREFC + 0.10 V 1, 6
Clock Input Differential Voltage; CK and CK# VIDCK (DC) 0.22 V 4, 6
Clock Input Differential Voltage; CK and CK# VIDCK (AC) 0.40 V 2, 4, 6
Clock Input Differential Voltage; WCK and WCK# VIDWCK (DC) 0.20 V 5, 7
Clock Input Differential Voltage; WCK and WCK# VIDWCK (AC) 0.30 2, 5, 7
Clock Input Voltage Level; CK, CK#, WCK and WCK# VIN ‐0.30 VDDQ + 0.30
single ended
CK/CK# Single ended slew rate CKslew 3 V/ns 9
WCK/WCK# Single ended slew rate WCKslew 3 V/ns 10
Clock Input Crossing Point Voltage; CK and CK# VIXCK (AC) VREFC ‐ 0.12 VREFC + 0.12 V 2, 3, 6
2, 3, 7,
Clock Input Crossing Point Voltage; WCK and WCK# VIXWCK (AC) VREFD ‐ 0.10 VREFD + 0.10 V
8
Allowed time before ringback of CK/WCK below 11, 12,
VIDCK/WCK(AC) tDVAC ps 13

Notes:
1. This provides a minimum of 0.9V to a maximum of 1.2V, and is nominally 70% of VDDQ with POD15. DRAM timings relative to
CK cannot be guaranteed if these limits are exceeded.
2. For AC operations, all DC clock requirements must be satisfied as well.
3. The value of VIXCK and VIXWCK is expected to equal 70% VDDQ for the transmitting device and must track variations in the DC
level of the same.
4. VIDCK is the magnitude of the difference between the input level in CK and the input level on CK#. The input reference level for
signals other than CK and CK# is VREFC.
5. VIDWCK is the magnitude of the difference between the input level in WCK and the input level on WCK#. The input reference level
for signals other than WCK and WCK# is either VREFD, VREFD2 or the internal VREFD.
6. The CK and CK# input reference level (for timing referenced to CK and CK#) is the point at which CK and CK# cross. Please refer
to the applicable timings in the AC timings table (Table 44).
7. The WCK and WCK# input reference level (for timing referenced to WCK and WCK#) is the point at which WCK and WCK# cross.
Please refer to the applicable timings in the AC Timings table (Table 44).
8. VREFD is either VREFD, VREFD2 or the internal VREFD.
9. The slew rate is measured between VREFC crossing and VIXCK(AC).
10. The slew rate is measured between VREFD crossing and VIXWCK(AC).
11. Figure illustrates the exact relationship between (CK‐CK#) or (WCK‐WCK#) and VID(AC), VID(DC) and tDVAC
12. Ringback below VID(DC) is not allowed.
13. tDVAC is not measured in and of itself as a compliance specification, but is relied upon in measurement of clock operating
conditions and clock related parameters.

Maximum Clock Level

VMP (DC) VID (DC)
VIX(AC)
VID (AC)

CK#

Minimum Clock Level

Figure 79. Clock Waveform

tDVAC

VID (AC) MIN
Differential Input Voltage (i.e. WCK ‐ WCK#, CK ‐ CK#)

VID (DC) MIN

half cycle

‐(VID (DC) MIN)

‐(VID (AC) MIN)

tDVAC
time

Figure 80. Definition of differential ac-swing and “time above ac-level” tDVAC

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 128
H5GQ1H24AFR
Table 42 IDD Specifications and Test Conditions
PARAMETER/CONDITION SYMBOL NOTES

One Bank Activate Precharge Current: tCK = tCK(min); tWCK = tWCK(min); tRC = tRC(min); CKE# =
LOW; DQ, DBI# are HIGH; random bank and row addresses (4 address inputs set LOW) with ACT IDD0 1
command

One Bank Activate Read Precharge Current: tCK = tCK (min); tWCK = tWCK(min);
tRC = tRC(min); CKE# = LOW; one bank activated; single read burst with 50% data toggle on each data
IDD1 1
transfer, with 4 outputs per data byte driven LOW; otherwise DQ, DBI# are HIGH; random bank, row
and column addresses (4 address inputs set LOW) with ACT and READ commands; IOUT = 0mA

Precharge Power‐down Current: tCK = tCK (min); tWCK = tWCK(min); all banks idle;
IDD2P
CKE# = HIGH; all other inputs are HIGH; PLLs are off

Precharge Standby Current: tCK = tCK (min); tWCK = tWCK(min); all banks idle;
IDD2N
CKE# = LOW; all other inputs are HIGH

Active Power‐down Current: tCK = tCK (min); tWCK = tWCK(min); one bank active;
IDD3P
CKE# = HIGH; all other inputs are HIGH

Active Standby Current: tCK = tCK (min); tWCK = tWCK(min); one bank active;
IDD3N
CKE# = LOW; all other inputs are HIGH

Read Burst Current: tCK = tCK (min); tWCK = tWCK(min); CKE# = LOW; one bank in each of the 4 bank
groups activated; continuous read burst across bank groups with 50% data toggle on each data
IDD4R
transfer, with 4 outputs per data byte driven LOW; random bank and column addresses (4 address
inputs set LOW) with READ command; IOUT = 0mA

Write Burst Current: tCK = tCK (min); tWCK = tWCK(min); CKE# = LOW; one bank in each of the 4 bank
groups activated; continuous write burst across bank groups with 50% data toggle on each data
IDD4W
transfer, with 4 inputs per data byte set LOW; random bank and column addresses (4 address inputs
set LOW) with WRITE command; no data mask

Refresh Current: tCK = tCK (min); tWCK = tWCK(min); tRFC = tRFC(min); CKE# = LOW;
IDD5 1
DQ, DBI# are HIGH; address inputs are HIGH

Self Refresh Current: CKE# = HIGH; all other inputs are HIGH IDD6

Four Bank Interleave Read Current: tCK = tCK(min); tWCK = tWCK(min); CKE# = LOW;
one bank in each of the 4 bank groups activated and precharged at tRC(min); continuous read burst
across bank groups with 50% data toggle on each data transfer, with 4 outputs per data byte driven IDD7
LOW; random bank, row and column addresses (4 address inputs set LOW) with ACT and READ/
READA commands; IOUT = 0mA

NOTE: Min tRC or tRFC for IDD measurements is the smallest multiple of tCK that meets the minimum of the absolute value for the
respective parameter.

Common Test conditions:
1) Device is configured to x32 mode
2) ABI and DBI are enabled
3) All ODTs are enabled with ZQ/2
4) PLLs are enabled unless otherwise noted
5) CRC is enabled for READs and WRITEs, and the EDC hold pattern is programmed to’1010’
6) Bank groups are enabled if required for device operation at tCK(min)
7) Address inputs include ABI# pin
8) Each data byte consists of eight DQs and one DBI# pin
9) DESELECT condition during idle command cycles

Table 43. IDD SPECIFICATIONS AND CONDITIONS

1. × 32 Mode IDD
Symbol 4.0Gbps 4.5Gbps 5.0Gbps 5.5Gbps 6.0Gbps Units
IDD0 550 590 630 670 710 mA
IDD1 590 630 670 710 750 mA
IDD2P 240 260 280 300 320 mA
IDD2N 260 280 300 320 340 mA
IDD3P 385 405 425 445 465 mA
IDD3N 540 580 620 660 700 mA
IDD4W 1300 1430 1560 1690 1820 mA
IDD4R 1370 1500 1630 1760 1890 mA
IDD5 545 580 615 650 685 mA
IDD6 60 60 60 60 60 mA
IDD7 900 1000 1100 1200 1300 mA

2. × 16 Mode IDD

Symbol 4.0Gbps 4.5Gbps 5.0Gbps 5.5Gbps 6.0Gbps Units

IDD0 370 400 420 450 490 mA
IDD1 390 420 450 480 520 mA
IDD2P 170 175 185 195 210 mA
IDD2N 190 200 210 230 250 mA
IDD3P 250 260 275 290 310 mA
IDD3N 350 370 390 420 450 mA
IDD4W 830 910 990 1070 1160 mA
IDD4R 850 930 1010 1090 1080 mA
IDD5 350 370 390 420 450 mA
IDD6 60 60 60 60 60 mA
IDD7 660 710 770 840 910 mA

Rev. 1.0 /Nov. 2009 130

H5GQ1H24AFR

Table 44. AC Timings (@1.5V)

6.0Gbps 5.5Gbps
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

CK and WCK Timings

PLL on 0.667 2 0.727 2

CK Clock cycle time tCK ns
PLL off 0.667 20 0.727 20

CK Clock high-level width tCH 0.470 0.530 0.470 0.530 tCK C

CK Clock low-level width tCL 0.470 0.530 0.470 0.530 tCK C

Min CK Clock half period tHP 0.470 - 0.470 - tCK

Max CK Clock frequency with bank groups disabled fCKBG - 1500 - 1375 MHz d

Max CK Clock frequency with bank groups enabled

fCKBG4 - 1500 - 1375 MHz d
and tCCDL=3tCK

Max CK Clock frequency with WCK2CK alignment

fCKPIN - 1500 - 1375 MHz e
at pins

Max CK Clock frequency in RDQS Mode fCKRDQS - TBD - TBD MHz f

Max CK Clock frequency for device operation with

fCKVREFD2 - TBD - TBD MHz g
VREFD2

Max CK Clock frequency for WCK-to-CK

fCKAUTOSYNC - 1500 - 1375 MHz h
auto synchronization in WCK2CK training mode

Max CK Clock frequency for device operation with

fCKLF - 900 - 900 MHz i
Low Frequency Mode enabled

PLL on 0.333 1 0.364 1

WCK Clock cycle time tWCK ns j
PLL off 0.333 10 0.364 10

WCK Clock high-level width tWCKH 0.470 0.530 0.470 0.530 tWCK k,l

WCK Clock low-level width tWCKL 0.470 0.530 0.470 0.530 tWCK k,l

Min WCK Clock half period tWCKHP 0.470 - 0.470 - tWCK

Command and Address Input Timings

Command input setup time tCMDS 0.25 - 0.25 - ns m,n

Command input hold time tCMDH 0.25 - 0.25 - ns m,n

Command input pulse width tCMDPW 0.60 - 0.65 - ns m,n,o

Address input setup time tAS 0.1 - 0.1 - ns m,n,p

Address input hold time tAH 0.1 - 0.1 - ns m,n,p

Address input pulse width tAPW 0.3 - 0.32 - ns m,n,o,p

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H5GQ1H24AFR

Table 44. AC Timings (@1.5V)

6.0Gbps 5.5Gbps
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

WCK2CK Timings

WCK stop to MRS delay for entering WCK2CK

tWCK2MRS 3 - 3 - ns
training

MRS to WCK restart delay after entering WCK2CK

tMRSTWCK 10 - 10 - ns q
training

WCK start to WCK phase movement delay tWCK2TR 10 - 10 - tCK

WCK phase change to phase detector out delay tWCK2PH 5 - 5 - ns

WCK Clock high-level width during WCK2CK

tWCKHTR 0.42 0.58 0.42 0.58 tWCK k,l,r
training

WCK Clock low-level width during WCK2CK

tWCKLTR 0.42 0.58 0.42 0.58 tWCK k,l,r
training

PLL on;MR6A0=0
-0.2 0.2 -0.2 0.2
(at phase detector)

PLL on;MR6A0=1
-0.2 0.2 -0.2 0.2
WCK2CK offset when zero (at pins)
offset at phase detector or at tWCK2CKPIN ns s
pins PLL off;MR6A0=0
-0.2 0.2 -0.2 0.2
(at phase detector)

PLL off;MR6A0=1
-0.2 0.2 -0.2 0.2
(at pins)

MR6A0=0
-0.25 0.25 -0.25 0.25 tCK
(at phase detector)
WCK2CK phase offset upon
tWCK2CKSYNC t
WCK2CK training exit MR6A0=1
-0.25 0.25 -0.25 0.25 ns
(at pins)

MR6A0=0
-0.4 0.4 -0.4 0.4 tCK
(at phase detector)
WCK2CK phase offset tWCK2CK u
MR6A0=1
-0.4 0.4 -0.4 0.4 ns
(at pins)

PLL Input and Output Timings

PLL on 0.7 1.7 0.7 1.7

WCK to DQ/DBI# offset for
tWCK2DQI ns v
input data PLL off 0.7 1.7 0.7 1.7

PLL on 1.1 2.2 1.1 2.2

WCK to DQ/DBI#/EDC/
tWCK2DQO ns w,x
offset for output data PLL off 1.1 2.2 1.1 2.2

DQ/DBI# input pulse width tDIPW 0.15 - 0.164 - ns y,z,aa

Rev. 1.0 /Nov. 2009 132

H5GQ1H24AFR

Table 44. AC Timings (@1.5V)

6.0Gbps 5.5Gbps
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

PLL on 0.1 - 0.11 -

DQ/DBI# data input valid
tDIVW ns y,z,ab
window PLL off 0.1 - 0.11 -

DQ/DBI# input skew within double byte tDQDQI -0.1 0.1 -0.1 0.1 ns ac

DQ/DBI#/EDC output skew within double byte tDQDQO -0.125 0.125 -0.125 0.125 ns ad

Row Access Timings

Active to Active command period tRC 40 - 40 - ns

Active to PRECHARGE command period tRAS 28 9tREFI 28 9tREFI ns ae

Active to READ command delay tRCDRD 12 - 12 - ns

Active to WRITE command delay tRCDWR 10 - 10 - ns

Active to RDTR command delay tRCDRTR 10 - 10 - ns

Active to WRTR command delay tRCDWTR 10 - 10 - ns

Active to LDFF command delay tRCDLTR 10 - 10 - ns

REFRESH to RDTR or WRTR command delay tREFTR 10 - 10 - ns

Active bank A to Active bank B command delay same

tRRDL 5.5 - 5.5 - ns af
bank group

Active bank A to Active bank B command delay

tRRDS 5.5 - 5.5 - ns ag
different bank groups

Four bank activate window tFAW 23 - 23 - ns ah

Thirty two bank activate window t32AW 184 - 184 - ns ai

READ to PRECHARGE command delay same bank

tRTPL 2 - 2 - tCK aj
with bank groups enabled

READ to PRECHARGE command delay same bank

tRTPS 2 - 2 - tCK ak
with bank groups disabled

PRECHARGE to PRECHARGE command delay tPPD 1 - 1 - ns

PRECHARGE command period tRP 12 - 12 - ns

WRITE recovery time tWR 12 - 12 - ns

Auto precharge write recovery + precharge time tDAL 24 - 24 - tCK al

Column Access Timings

RD/WR bank A to RD/WR bank B command delay

tCCDL 3 - 3 - tCK af,am
same bank group

RD/WR bank A to RD/WR bank B command delay

tCCDS 2 - 2 - tCK ag,an
different bank groups

Rev. 1.0 /Nov. 2009 133

H5GQ1H24AFR

Table 44. AC Timings (@1.5V)

6.0Gbps 5.5Gbps
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

LDFF to LDFF command cycle time tLTLTR 4 - 4 - tCK

LDFF(111) to LDFF command cycle time tLTL7TR 4 - 4 - tCK ao

LDFF(111) to RDTR command cycle delay tLTRTR 4 - 4 - tCK

READ or RDTR to LDFF command delay tRDTLT 4 - 4 - tCK

WRITE to LDFF command delay tWRTLT WL+5 - WL+5 - tCK

WL- WL-
WRTR to RDTR command delay tWTRTR - - tCK
tWLmin tWLmin

WL+tCR WL+tCR
WRITE to WRTR command delay tWRWTR - - tCK
CWL+2 CWL+2

Internal WRITE to READ command delay same bank

tWTRL 5 - 5 - ns af
group

Internal WRITE to READ command delay different

tWTRS 5 - 5 - ns ag
bank groups

[CLmrs+(BL [CLmrs+(BL
READ or RDTR to WRITE or WRTR command /4)+2- /4)+2-
tRTW WLmrs]*tC
- - tCK ap
delay WLmrs]*tC
K K

Write Latency tWL 4 7 4 7 tCK aq

Power-Down and Refresh Timings

CKE# min high and low pulse width tCKE 16 - 14 - tCK

Valid CK Clock required after self refresh entry tCKSRE 16 - 14 - tCK

Valid CK Clock required before self refresh exit tCKSRX 16 - 14 - tCK

READ to SELF REFRESH ENTRY or POWER

tRDSRE CL+2tCK - CL+2tCK - tCK ar
DOWN ENTRY command delay

WRITE to SELF REFRESH ENTRY or POWER

tWRSRE TBD - TBD - tCK as
DOWN ENTRY command delay

REFRESH command period tRFC 65 - 65 - ns

Exit self refresh to non-READ/WRITE command

tXSNRW tRFC - tRFC - ns
delay

tRFC+ tRFC+
Exit self refresh to READ/WRITE command delay tXSRW - - tCK at
tRCD tRCD

Refresh period tREF - 32 - 32 ms

Average periodic refresh 8k rows - 3.9 - 3.9

tREFI us au
interval 16k rows - 1.9 - 1.9

Min Power down entry to exit time tPD 16 14 tCK

Rev. 1.0 /Nov. 2009 134

H5GQ1H24AFR

Table 44. AC Timings (@1.5V)

6.0Gbps 5.5Gbps
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

NOP/DESELECT commands required upon power-

tCPDED 4 - 3 - tCK
down and self refresh entry

Power down exit time tXPN 17 - 15 - tCK

Miscellaneous Timings

MODE REGISTER SET command period tMRD 4 - 4 - tCK

PLL enabled to PLL lock delay tLK - 5000 - 5000 tCK

PLL standby time tSTDBTY - TBD - TBD us ax

DVS voltage stabilization time tVS TBD - TBD - us

REFRESH to calibration update complete delay tKO - 40 - 40 ns

Active termination setup time tATS 10 - 10 - ns

Active termination hold time tATH 10 - 10 - ns

0.5tCK+ 0.5tCK+ 0.5tCK+ 0.5tCK+

READ to data out delay in address training mode tADR tCK q
0 10 0 10

0.5*tCK+ 0.5*tCK+
Address training exit to DQ in ODT state delay tADZ - - ns
10 10

Vendor ID on tWRIDON - 11 - 11 ns

Venodr ID off tWRIDOFF - 11 - 11 ns

Temperature sensor enable delay tTSEN 10 - 10 - us

Rev. 1.0 /Nov. 2009 135

H5GQ1H24AFR

Table 44. AC Timings (@1.5V)

5.0Gbps 4.5Gbps
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

CK and WCK Timings

PLL on 0.8 2 0.89 2

CK Clock cycle time tCK ns
PLL off 0.8 20 0.89 20

CK Clock high-level width tCH 0.470 0.530 0.470 0.530 tCK C

CK Clock low-level width tCL 0.470 0.530 0.470 0.530 tCK C

Min CK Clock half period tHP 0.470 - 0.470 - tCK

Max CK Clock frequency with bank groups disabled fCKBG - 1250 - 1125 MHz d

Max CK Clock frequency with bank groups enabled

fCKBG4 - 1250 - 1125 MHz d
and tCCDL=3tCK

Max CK Clock frequency with WCK2CK alignment

fCKPIN - 1250 - 1125 MHz e
at pins

Max CK Clock frequency in RDQS Mode fCKRDQS - TBD - TBD MHz f

Max CK Clock frequency for device operation with

fCKVREFD2 - TBD - TBD MHz g
VREFD2

Max CK Clock frequency for WCK-to-CK

fCKAUTOSYNC - 1250 - 1125 MHz h
auto synchronization in WCK2CK training mode

Max CK Clock frequency for device operation with

fCKLF - 900 - 900 MHz i
Low Frequency Mode enabled

PLL on 0.4 1 0.444 1

WCK Clock cycle time tWCK ns j
PLL off 0.4 10 0.444 10

WCK Clock high-level width tWCKH 0.470 0.530 0.470 0.530 tWCK k,l

WCK Clock low-level width tWCKL 0.470 0.530 0.470 0.530 tWCK k,l

Min WCK Clock half period tWCKHP 0.470 - 0.470 - tWCK

Command and Address Input Timings

Command input setup time tCMDS 0.25 - 0.25 - ns m,n

Command input hold time tCMDH 0.25 - 0.25 - ns m,n

Command input pulse width tCMDPW 0.7 - 0.7 - ns m,n,o

Address input setup time tAS 0.1 - 0.125 - ns m,n,p

Address input hold time tAH 0.1 - 0.125 - ns m,n,p

Address input pulse width tAPW 0.36 - 0.4 - ns m,n,o,p

Rev. 1.0 /Nov. 2009 136

H5GQ1H24AFR

Table 44. AC Timings (@1.5V)

5.0Gbps 4.5Gbps
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

WCK2CK Timings

WCK stop to MRS delay for entering WCK2CK

tWCK2MRS 3 - 3 - ns
training

MRS to WCK restart delay after entering WCK2CK

tMRSTWCK 10 - 10 - ns q
training

WCK start to WCK phase movement delay tWCK2TR 10 - 10 - tCK

WCK phase change to phase detector out delay tWCK2PH 5 - 5 - ns

WCK Clock high-level width during WCK2CK

tWCKHTR 0.42 0.58 0.42 0.58 tWCK k,l,r
training

WCK Clock low-level width during WCK2CK

tWCKLTR 0.42 0.58 0.42 0.58 tWCK k,l,r
training

PLL on;MR6A0=0
-0.2 0.2 -0.2 0.2
(at phase detector)

PLL on;MR6A0=1
-0.2 0.2 -0.2 0.2
WCK2CK offset when zero (at pins)
offset at phase detector or at tWCK2CKPIN ns s
pins PLL off;MR6A0=0
-0.2 0.2 -0.2 0.2
(at phase detector)

PLL off;MR6A0=1
-0.2 0.2 -0.2 0.2
(at pins)

MR6A0=0
-0.25 0.25 -0.25 0.25 tCK
(at phase detector)
WCK2CK phase offset upon
tWCK2CKSYNC t
WCK2CK training exit
MR6A0=1
-0.25 0.25 -0.25 0.25 ns
(at pins)

MR6A0=0
-0.4 0.4 -0.4 0.4 tCK
(at phase detector)
WCK2CK phase offset tWCK2CK u
MR6A0=1
-0.4 0.4 -0.4 0.4 ns
(at pins)

PLL Input and Output Timings

PLL on 0.7 1.7 0.7 1.7

WCK to DQ/DBI# offset for
tWCK2DQI ns v
input data
PLL off 0.7 1.7 0.7 1.7

PLL on 1.1 2.2 1.1 2.2

WCK to DQ/DBI#/EDC/
tWCK2DQO ns w,x
offset for output data
PLL off 1.1 2.2 1.1 2.2

DQ/DBI# input pulse width tDIPW 0.18 - 0.197 - ns y,z,aa

Rev. 1.0 /Nov. 2009 137

H5GQ1H24AFR

Table 44. AC Timings (@1.5V)

5.0Gbps 4.5Gbps
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

PLL on 0.12 - 0.13 -

DQ/DBI# data input valid
tDIVW ns y,z,ab
window PLL off 0.12 - 0.13 -

DQ/DBI# input skew within double byte tDQDQI -0.1 0.1 -0.1 0.1 ns ac

DQ/DBI#/EDC output skew within double byte tDQDQO -0.125 0.125 -0.125 0.125 ns ad

Row Access Timings

Active to Active command period tRC 40 - 40 - ns

Active to PRECHARGE command period tRAS 28 9tREFI 28 9tREFI ns ae

Active to READ command delay tRCDRD 12 - 12 - ns

Active to WRITE command delay tRCDWR 10 - 10 - ns

Active to RDTR command delay tRCDRTR 10 - 10 - ns

Active to WRTR command delay tRCDWTR 10 - 10 - ns

Active to LDFF command delay tRCDLTR 10 - 10 - ns

REFRESH to RDTR or WRTR command delay tREFTR 10 - 10 - ns

Active bank A to Active bank B command delay same

tRRDL 5.5 - 5.5 - ns af
bank group

Active bank A to Active bank B command delay

tRRDS 5.5 - 5.5 - ns ag
different bank groups

Four bank activate window tFAW 23 - 23 - ns ah

Thirty two bank activate window t32AW 184 - 184 - ns ai

READ to PRECHARGE command delay same bank

tRTPL 2 - 2 - tCK aj
with bank groups enabled

READ to PRECHARGE command delay same bank

tRTPS 2 - 2 - tCK ak
with bank groups disabled

PRECHARGE to PRECHARGE command delay tPPD 1 - 1 - ns

PRECHARGE command period tRP 12 - 12 - ns

WRITE recovery time tWR 12 - 12 - ns

Auto precharge write recovery + precharge time tDAL 24 - 24 - tCK al

Column Access Timings

RD/WR bank A to RD/WR bank B command delay

tCCDL 3 - 3 - tCK af,am
same bank group

RD/WR bank A to RD/WR bank B command delay

tCCDS 2 - 2 - tCK ag,an
different bank groups

Rev. 1.0 /Nov. 2009 138

H5GQ1H24AFR

Table 44. AC Timings (@1.5V)

5.0Gbps 4.5Gbps
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

LDFF to LDFF command cycle time tLTLTR 4 - 4 - tCK

LDFF(111) to LDFF command cycle time tLTL7TR 4 - 4 - tCK ao

LDFF(111) to RDTR command cycle delay tLTRTR 4 - 4 - tCK

READ or RDTR to LDFF command delay tRDTLT 4 - 4 - tCK

WRITE to LDFF command delay tWRTLT WL+5 - WL+5 - tCK

WL- WL-
WRTR to RDTR command delay tWTRTR - - tCK
tWLmin tWLmin

WL+tCR WL+tCR
WRITE to WRTR command delay tWRWTR - - tCK
CWL+2 CWL+2

Internal WRITE to READ command delay same bank

tWTRL 5 - 5 - ns af
group

Internal WRITE to READ command delay different

tWTRS 5 - 5 - ns ag
bank groups

[CLmrs+(BL [CLmrs+(BL
READ or RDTR to WRITE or WRTR command /4)+2- /4)+2-
tRTW WLmrs]*tC - WLmrs]*tC - tCK ap
delay
K K

Write Latency tWL 3 7 3 7 tCK aq

Power-Down and Refresh Timings

CKE# min high and low pulse width tCKE 12 - 11 - tCK

Valid CK Clock required after self refresh entry tCKSRE 12 - 11 - tCK

Valid CK Clock required before self refresh exit tCKSRX 12 - 11 - tCK

READ to SELF REFRESH ENTRY or POWER

tRDSRE CL+2tCK - CL+2tCK - tCK ar
DOWN ENTRY command delay

WRITE to SELF REFRESH ENTRY or POWER

tWRSRE TBD - TBD - tCK as
DOWN ENTRY command delay

REFRESH command period tRFC 65 - 65 - ns

Exit self refresh to non-READ/WRITE command

tXSNRW tRFC - tRFC - ns
delay

tRFC+ tRFC+
Exit self refresh to READ/WRITE command delay tXSRW - - tCK at
tRCD tRCD

Refresh period tREF - 32 - 32 ms

Average periodic refresh 8k rows - 3.9 - 3.9

tREFI us au
interval 16k rows - 1.9 - 1.9

Min Power down entry to exit time tPD 12 11 tCK

Rev. 1.0 /Nov. 2009 139

H5GQ1H24AFR

Table 44. AC Timings (@1.5V)

5.0Gbps 4.5Gbps
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

NOP/DESELECT commands required upon power-

tCPDED 3 - 3 - tCK
down and self refresh entry

Power down exit time tXPN 13 - 11 - tCK

Miscellaneous Timings

MODE REGISTER SET command period tMRD 4 - 4 - tCK

PLL enabled to PLL lock delay tLK - 5000 - 5000 tCK

PLL standby time tSTDBTY - TBD - TBD us ax

DVS voltage stabilization time tVS TBD - TBD - us

REFRESH to calibration update complete delay tKO - 40 - 40 ns

Active termination setup time tATS 10 - 10 - ns

Active termination hold time tATH 10 - 10 - ns

0.5tCK+ 0.5tCK+ 0.5tCK+ 0.5tCK+

READ to data out delay in address training mode tADR tCK q
0 10 0 10

0.5*tCK+ 0.5*tCK+
Address training exit to DQ in ODT state delay tADZ - - ns
10 10

Vendor ID on tWRIDON - 11 - 11 ns

Venodr ID off tWRIDOFF - 11 - 11 ns

Temperature sensor enable delay tTSEN 10 - 10 - us

Rev. 1.0 /Nov. 2009 140

H5GQ1H24AFR

Table 44. AC Timings (@1.5V)

4.0Gbps -
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

CK and WCK Timings

PLL on 1 2
CK Clock cycle time tCK ns
PLL off 1 20

CK Clock high-level width tCH 0.470 0.530 tCK C

CK Clock low-level width tCL 0.470 0.530 tCK C

Min CK Clock half period tHP 0.470 - tCK

Max CK Clock frequency with bank groups disabled fCKBG - 1000 MHz d

Max CK Clock frequency with bank groups enabled

fCKBG4 - 1000 MHz d
and tCCDL=3tCK

Max CK Clock frequency with WCK2CK alignment

fCKPIN - 1000 MHz e
at pins

Max CK Clock frequency in RDQS Mode fCKRDQS - TBD MHz f

Max CK Clock frequency for device operation with

fCKVREFD2 - TBD MHz g
VREFD2

Max CK Clock frequency for WCK-to-CK

fCKAUTOSYNC - 100 MHz h
auto synchronization in WCK2CK training mode

Max CK Clock frequency for device operation with

fCKLF - 800 MHz i
Low Frequency Mode enabled

PLL on 0.5 1
WCK Clock cycle time tWCK ns j
PLL off 0.5 10

WCK Clock high-level width tWCKH 0.470 0.530 tWCK k,l

WCK Clock low-level width tWCKL 0.470 0.530 tWCK k,l

Min WCK Clock half period tWCKHP 0.470 - tWCK

Command and Address Input Timings

Command input setup time tCMDS 0.25 - ns m,n

Command input hold time tCMDH 0.25 - ns m,n

Command input pulse width tCMDPW 0.7 - ns m,n,o

Address input setup time tAS 0.125 - ns m,n,p

Address input hold time tAH 0.125 - ns m,n,p

Address input pulse width tAPW 0.45 - ns m,n,o,p

Rev. 1.0 /Nov. 2009 141

H5GQ1H24AFR

Table 44. AC Timings (@1.5V)

4.0Gbps -
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

WCK2CK Timings

WCK stop to MRS delay for entering WCK2CK

tWCK2MRS 3 - ns
training

MRS to WCK restart delay after entering WCK2CK

tMRSTWCK 10 - ns q
training

WCK start to WCK phase movement delay tWCK2TR 10 - tCK

WCK phase change to phase detector out delay tWCK2PH 5 - ns

WCK Clock high-level width during WCK2CK

tWCKHTR 0.42 0.58 tWCK k,l,r
training

WCK Clock low-level width during WCK2CK

tWCKLTR 0.42 0.58 tWCK k,l,r
training

PLL on;MR6A0=0
-0.2 0.2
(at phase detector)

PLL on;MR6A0=1
WCK2CK offset when zero -0.2 0.2
(at pins)
offset at phase detector or at tWCK2CKPIN ns s
pins PLL off;MR6A0=0
-0.2 0.2
(at phase detector)

PLL off;MR6A0=1
-0.2 0.2
(at pins)

MR6A0=0
-0.25 0.25 tCK
(at phase detector)
WCK2CK phase offset upon
tWCK2CKSYNC t
WCK2CK training exit MR6A0=1
-0.25 0.25 ns
(at pins)

MR6A0=0
-0.4 0.4 tCK
(at phase detector)
WCK2CK phase offset tWCK2CK u
MR6A0=1
-0.4 0.4 ns
(at pins)

PLL Input and Output Timings

WCK to DQ/DBI# offset for PLL on 0.7 1.7

tWCK2DQI ns v
input data
PLL off 0.7 1.7

WCK to DQ/DBI#/EDC/ PLL on 1.1 2.2

tWCK2DQO ns w,x
offset for output data
PLL off 1.1 2.2

DQ/DBI# input pulse width tDIPW 0.225 - ns y,z,aa

Rev. 1.0 /Nov. 2009 142

H5GQ1H24AFR

Table 44. AC Timings (@1.5V)

4.0Gbps -
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

PLL on 0.15 -
DQ/DBI# data input valid
tDIVW ns y,z,ab
window PLL off 0.15 -

DQ/DBI# input skew within double byte tDQDQI -0.1 0.1 ns ac

DQ/DBI#/EDC output skew within double byte tDQDQO -0.125 0.125 ns ad

Row Access Timings

Active to Active command period tRC 40 - ns

Active to PRECHARGE command period tRAS 28 9*tREFI ns ae

Active to READ command delay tRCDRD 12 - ns

Active to WRITE command delay tRCDWR 10 - ns

Active to RDTR command delay tRCDRTR 10 - ns

Active to WRTR command delay tRCDWTR 10 - ns

Active to LDFF command delay tRCDLTR 10 - ns

REFRESH to RDTR or WRTR command delay tREFTR 10 - ns

Active bank A to Active bank B command delay same

tRRDL 5.5 - ns af
bank group

Active bank A to Active bank B command delay

tRRDS 5.5 - ns ag
different bank groups

Four bank activate window tFAW 23 - ns ah

Thirty two bank activate window t32AW 184 - ns ai

READ to PRECHARGE command delay same bank

tRTPL 2 - tCK aj
with bank groups enabled

READ to PRECHARGE command delay same bank

tRTPS 2 - tCK ak
with bank groups disabled

PRECHARGE to PRECHARGE command delay tPPD 1 - ns

PRECHARGE command period tRP 12 - ns

WRITE recovery time tWR 12 - ns

Auto precharge write recovery + precharge time tDAL 24 - tCK al

Column Access Timings

RD/WR bank A to RD/WR bank B command delay

tCCDL 3 - tCK af,am
same bank group

RD/WR bank A to RD/WR bank B command delay

tCCDS 2 - tCK ag,an
different bank groups

Rev. 1.0 /Nov. 2009 143

H5GQ1H24AFR

Table 44. AC Timings (@1.5V)

4.0Gbps -
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

LDFF to LDFF command cycle time tLTLTR 4 - tCK

LDFF(111) to LDFF command cycle time tLTL7TR 4 - tCK ao

LDFF(111) to RDTR command cycle delay tLTRTR 4 - tCK

READ or RDTR to LDFF command delay tRDTLT 4 - tCK

WRITE to LDFF command delay tWRTLT WL+5 - tCK

WL-
WRTR to RDTR command delay tWTRTR - tCK
tWLmin

WL+tCR
WRITE to WRTR command delay tWRWTR - tCK
CWL+2

Internal WRITE to READ command delay same bank

tWTRL 5 - ns af
group

Internal WRITE to READ command delay different

tWTRS 5 - ns ag
bank groups

[CLmrs+(BL
READ or RDTR to WRITE or WRTR command /4)+2-
tRTW WLmrs]*tC - tCK ap
delay
K

Write Latency tWL 3 7 tCK aq

Power-Down and Refresh Timings

CKE# min high and low pulse width tCKE 10 - tCK

Valid CK Clock required after self refresh entry tCKSRE 10 - tCK

Valid CK Clock required before self refresh exit tCKSRX 10 - tCK

READ to SELF REFRESH ENTRY or POWER

tRDSRE CL+2tCK - tCK ar
DOWN ENTRY command delay

WRITE to SELF REFRESH ENTRY or POWER

tWRSRE TBD - tCK as
DOWN ENTRY command delay

REFRESH command period tRFC 65 - ns

Exit self refresh to non-READ/WRITE command

tXSNRW tRFC - ns
delay

tRFC+
Exit self refresh to READ/WRITE command delay tXSRW - tCK at
tRCD

Refresh period tREF - 32 ms

Average periodic refresh 8k rows - 3.9

tREFI us au
interval 16k rows - 1.9

Min Power down entry to exit time tPD 10 tCK

Rev. 1.0 /Nov. 2009 144

H5GQ1H24AFR

Table 44. AC Timings (@1.5V)

4.0Gbps -
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

NOP/DESELECT commands required upon power-

tCPDED 2 - tCK
down and self refresh entry

Power down exit time tXPN 10 - tCK

Miscellaneous Timings

MODE REGISTER SET command period tMRD 4 - tCK

PLL enabled to PLL lock delay tLK - 5000 tCK

PLL standby time tSTDBTY - TBD us ax

DVS voltage stabilization time tVS TBD - us

REFRESH to calibration update complete delay tKO - 40 ns

Active termination setup time tATS 10 - ns

Active termination hold time tATH 10 - ns

0.5*tCK+ 0.5*tCK+
READ to data out delay in address training mode tADR tCK q
0 10

0.5*tCK+
Address training exit to DQ in ODT state delay tADZ - ns
10

Vendor ID on tWRIDON - 11 ns

Venodr ID off tWRIDOFF - 11 ns

Temperature sensor enable delay tTSEN 10 - us

Rev. 1.0 /Nov. 2009 145

H5GQ1H24AFR

Table 44. AC Timings (@1.35V)

3.2Gbps -
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

CK and WCK Timings

PLL on 1.25 2
CK Clock cycle time tCK ns
PLL off 1.25 20

CK Clock high-level width tCH 0.470 0.530 tCK C

CK Clock low-level width tCL 0.470 0.530 tCK C

Min CK Clock half period tHP 0.470 - tCK

Max CK Clock frequency with bank groups disabled fCKBG - 800 MHz d

Max CK Clock frequency with bank groups enabled

fCKBG4 - 800 MHz d
and tCCDL=3tCK

Max CK Clock frequency with WCK2CK alignment

fCKPIN - 800 MHz e
at pins

Max CK Clock frequency in RDQS Mode fCKRDQS - TBD MHz f

Max CK Clock frequency for device operation with

fCKVREFD2 - TBD MHz g
VREFD2

Max CK Clock frequency for WCK-to-CK

fCKAUTOSYNC - 800 MHz h
auto synchronization in WCK2CK training mode

Max CK Clock frequency for device operation with

fCKLF - 700 MHz i
Low Frequency Mode enabled

PLL on 0.625 1
WCK Clock cycle time tWCK ns j
PLL off 0.625 10

WCK Clock high-level width tWCKH 0.470 0.530 tWCK k,l

WCK Clock low-level width tWCKL 0.470 0.530 tWCK k,l

Min WCK Clock half period tWCKHP 0.470 - tWCK

Command and Address Input Timings

Command input setup time tCMDS 0.3 - ns m,n

Command input hold time tCMDH 0.3 - ns m,n

Command input pulse width tCMDPW 1.0 - ns m,n,o

Address input setup time tAS 0.15 - ns m,n,p

Address input hold time tAH 0.15 - ns m,n,p

Address input pulse width tAPW 0.55 - ns m,n,o,p

Rev. 1.0/Nov. 2009 146

H5GQ1H24AFR

Table 44. AC Timings (@1.35V)

3.2Gbps -
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

WCK2CK Timings

WCK stop to MRS delay for entering WCK2CK

tWCK2MRS 3 - ns
training

MRS to WCK restart delay after entering WCK2CK

tMRSTWCK 10 - ns q
training

WCK start to WCK phase movement delay tWCK2TR 10 - tCK

WCK phase change to phase detector out delay tWCK2PH 5 - ns

WCK Clock high-level width during WCK2CK

tWCKHTR 0.42 0.58 tWCK k,l,r
training

WCK Clock low-level width during WCK2CK

tWCKLTR 0.42 0.58 tWCK k,l,r
training

PLL on;MR6A0=0
-0.2 0.2
(at phase detector)

PLL on;MR6A0=1
WCK2CK offset when zero -0.2 0.2
(at pins)
offset at phase detector or at tWCK2CKPIN ns s
pins PLL off;MR6A0=0
-0.2 0.2
(at phase detector)

PLL off;MR6A0=1
-0.2 0.2
(at pins)

MR6A0=0
-0.25 0.25 tCK
(at phase detector)
WCK2CK phase offset upon
tWCK2CKSYNC t
WCK2CK training exit MR6A0=1
-0.25 0.25 ns
(at pins)

MR6A0=0
-0.4 0.4 tCK
(at phase detector)
WCK2CK phase offset tWCK2CK u
MR6A0=1
-0.4 0.4 ns
(at pins)

PLL Input and Output Timings

WCK to DQ/DBI# offset for PLL on 0.7 1.7

tWCK2DQI ns v
input data
PLL off 0.7 1.7

WCK to DQ/DBI#/EDC/ PLL on 1.1 2.2

tWCK2DQO ns w,x
offset for output data
PLL off 1.1 2.2

DQ/DBI# input pulse width tDIPW 0.295 - ns y,z,aa

Rev. 1.0/Nov. 2009 147

H5GQ1H24AFR

Table 44. AC Timings (@1.35V)

3.2Gbps -
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

PLL on 0.19 -
DQ/DBI# data input valid
tDIVW ns y,z,ab
window PLL off 0.19 -

DQ/DBI# input skew within double byte tDQDQI -0.1 0.1 ns ac

DQ/DBI#/EDC output skew within double byte tDQDQO -0.125 0.125 ns ad

Row Access Timings

Active to Active command period tRC 48 - ns

Active to PRECHARGE command period tRAS 32 9*tREFI ns ae

Active to READ command delay tRCDRD 16 - ns

Active to WRITE command delay tRCDWR 14 - ns

Active to RDTR command delay tRCDRTR 16 - ns

Active to WRTR command delay tRCDWTR 14 - ns

Active to LDFF command delay tRCDLTR 14 - ns

REFRESH to RDTR or WRTR command delay tREFTR 14 - ns

Active bank A to Active bank B command delay same

tRRDL 12 - ns af
bank group

Active bank A to Active bank B command delay

tRRDS 7 - ns ag
different bank groups

Four bank activate window tFAW 30 - ns ah

Thirty two bank activate window t32AW 245 - ns ai

READ to PRECHARGE command delay same bank

tRTPL 2 - tCK aj
with bank groups enabled

READ to PRECHARGE command delay same bank

tRTPS 2 - tCK ak
with bank groups disabled

PRECHARGE to PRECHARGE command delay tPPD 1 - ns

PRECHARGE command period tRP 16 - ns

WRITE recovery time tWR 16 - ns

Auto precharge write recovery + precharge time tDAL 32 - tCK al

Column Access Timings

RD/WR bank A to RD/WR bank B command delay

tCCDL 3 - tCK af,am
same bank group

RD/WR bank A to RD/WR bank B command delay

tCCDS 2 - tCK ag,an
different bank groups

Rev. 1.0/Nov. 2009 148

H5GQ1H24AFR

Table 44. AC Timings (@1.35V)

3.2Gbps -
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

LDFF to LDFF command cycle time tLTLTR 4 - tCK

LDFF(111) to LDFF command cycle time tLTL7TR 4 - tCK ao

LDFF(111) to RDTR command cycle delay tLTRTR 4 - tCK

READ or RDTR to LDFF command delay tRDTLT 4 - tCK

WRITE to LDFF command delay tWRTLT WL+5 - tCK

WL-
WRTR to RDTR command delay tWTRTR - tCK
tWLmin

WL+tCR
WRITE to WRTR command delay tWRWTR - tCK
CWL+2

Internal WRITE to READ command delay same bank

tWTRL 5 - ns af
group

Internal WRITE to READ command delay different

tWTRS 5 - ns ag
bank groups

[CLmrs+(BL
READ or RDTR to WRITE or WRTR command /4)+2-
tRTW WLmrs]*tC - tCK ap
delay
K

Write Latency tWL 3 7 tCK aq

Power-Down and Refresh Timings

CKE# min high and low pulse width tCKE 11 - tCK

Valid CK Clock required after self refresh entry tCKSRE 11 - tCK

Valid CK Clock required before self refresh exit tCKSRX 11 - tCK

READ to SELF REFRESH ENTRY or POWER

tRDSRE CL+2tCK - tCK ar
DOWN ENTRY command delay

WRITE to SELF REFRESH ENTRY or POWER

tWRSRE TBD - tCK as
DOWN ENTRY command delay

REFRESH command period tRFC 120 - ns

Exit self refresh to non-READ/WRITE command

tXSNRW tRFC - ns
delay

tRFC+
Exit self refresh to READ/WRITE command delay tXSRW - tCK at
tRCD

Refresh period tREF - 32 ms

Average periodic refresh 8k rows - 3.9

tREFI us au
interval 16k rows - 1.9

Min Power down entry to exit time tPD 11 tCK

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Table 44. AC Timings (@1.35V)

3.2Gbps -
PARAMETER a, b SYMBOL UNIT NOTES
MIN MAX MIN MAX

NOP/DESELECT commands required upon power-

tCPDED 2 - tCK
down and self refresh entry

Power down exit time tXPN 10 - tCK

Miscellaneous Timings

MODE REGISTER SET command period tMRD 4 - tCK

PLL enabled to PLL lock delay tLK - 5000 tCK

PLL standby time tSTDBTY - TBD us ax

DVS voltage stabilization time tVS TBD - us

REFRESH to calibration update complete delay tKO - 40 ns

Active termination setup time tATS 10 - ns

Active termination hold time tATH 10 - ns

0.5*tCK+ 0.5*tCK+
READ to data out delay in address training mode tADR tCK q
0 10

0.5*tCK+
Address training exit to DQ in ODT state delay tADZ - ns
10

Vendor ID on tWRIDON - 11 ns

Venodr ID off tWRIDOFF - 11 ns

Temperature sensor enable delay tTSEN 10 - us

a. All parameters assume proper device initialization.

b. Tests for AC timing may be considered at norminal supply voltage levels, but the related specification and device operation are guaranteed for the full
voltage and temperature range specified.
c. CK and CK# single-ended input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFC crossing and VIXCK(AC)
d. Parameter fCKBG4 is required for those devices supporting both 3*tCK and 4*tCK setting for bank groups. Devices supporting only 3*tCK or 4*tCK
need only to specify fCKBG.
e. Parameter fCKPIN applies when the alignment point in MR6, bit A0 is set to “at pins”, the phase difference between the WCK and CK clocks at the
DRAM pins is within tWCK2CKSYNC or tWCK2CK for pin mode and no phase search in WCK2CK training is performed.
f. Parameter fCKRDQS applies when RDQS mode is enabled in AR3, bit A5.
g. Parameter fCKBREFD2 applies when the data input reference voltage in MR7, bit A7 (Half VREFD) is set to VREFD2.
h. Parameter fCKAUTOSYNC applies when WCK2CK Auto Synchronization is enabled in MR7, bit A4.
i. Parameter fCKLF applies when Low Frequency Mode is enabled in MR7, bit A3.
j. By definition the norminal WCK clock cycle time always is 1/2 of the CK clock cycle time (not including jitter).
k. WCK and WCK# single-ended input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFD crossing and
VIXWCK(AC).

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l. The phase relationship between WCK/WCK# and CK/CK# clocks must meet the tWCK2CK specification.
m. Command and address input timings are referenced to VREFC.
n. Command and address input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFC crossing and VIHA(AC)
or VILA(AC).
o. Command and address input pulse widths are design targets. The value will be characterized but not tested on each device.
p. Address input timings are only valid with ABI beging enabled and a maximum of 4 address input driven LOW.
q. Parameter may be specified as a combination of tCK and ns.
r. Parameters tWCKHTR and tWCKLTR specify the max. allowed WCK clock-to-clock phase shift during WCK2CK training. For READ and WRITE
bursts use tWCKH and tWCKL.
s. Parameter tWCK2CKPIN defines the WCK2CK phase offset range at the CK and WCK pins for ideal (phase=0 °) clock alignment at the
GDDR5 SGRAM’s phase detector (when the alignment point in MR6, bit A0 is set to “at phase detector”), or at the WCK and CK pins (when the
alignment in MR6, bit A0 is set to “at pins”). The minimum and maximum values could be negative or positive numbers, depending on the selected
WCK2CK alignment point, PLL-on or PLL-off mode and design implementation.
t. Parameter tWCK2CKSYNC defines the max. phase offset from the ideal (phase = 0 °) clock alignment at the GDDR5 SGRAM’s phase
detector (when the alignment point in MR6, bit A0 is set to “at the phase detector”), or at the WCK and CK pins (when the alignment point
in MR6, bit A0 is set to “at pins”), where the internal logic synchronizes the CK and WCK clocks; it is expected to be a fraction of tWCK2CK.
u. Parameter tWCK2CK defines the max. phase offset from the ideal (phase = 0 °) clock alignment at the GDDR5 SGRAM’s phase detector
(when the alignment point in MR6, bit A0 is set to “at phase detector”) or at the WCK and CK pins (when the alignment point in MR6, bit A0 is set to
“at pins”), for stable device operation.
v. Parameter tWCK2DQI defines the WCK to DQ/DBI# time delay range for WRITEs for PLL-on and PLL-off mode. The minimum and maximum values
could be negative or positive numbers, depending on design implementation and PLL-on or PLL-off mode. They also vary across PVT.
Data training is required to determine the actual tWCK2DQI value for reliable WRITE operation.
w. Parameter tWCK2DQO defines the WCK to DQ/DBI# time delay range for READs for PLL-on and PLL-off mode. The minimum and maxium values
could be negative or positive numbers, depending on design implementation and PLL-on or PLL-off mode. They also vary across PVT.
Data training is required to determind the actual tWCK2DQO value for reliable READ operation.
x. Outputs measured with equivalent load terminated with 60 Ohms to VDDQ
y. DQ/DBI# input timings are valid only with DBI being enabled and a maximum of 4 data inputs per byte driven LOW.
z. Data input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFD crossing and VIHD(AC) or VILD(AC).
aa. The data input pulse width, tDIPW, defines the minimum positive or negative input pulse width for any worst-case channel required for proper
propagation of an external signal to the receiver. tDIPW is measured at the pins. tDIPW is independent of the PLL mode.
In general tDIPW is larger than tDIVW
ab. The data input valid width, tDIVW, defines the time region where input data must be valid for reliable data capture at the receiver for any one worst
case channel. It accounts for jitter between data and clock at the latching point introduced in the path between DARM pads and the latching point.
Any additional jitter introduced into the source signals (e.g. within the system before the DRAM pad) must be accounted for in the final timing
budget together with the chosen PLL mode and bandwidth. tDIVW is measured at the pins. tDIVW is defined for PLL off and on mode separately.
In the case of PLL on, tDIVW must be specified for each supported bandwidth. In general, tDIVW is smaller than tDIPW.
ac. tDQDQI defines the maximum skew among all DQ/DBI# inputs of a double byte (when configured to × 32 mode) or a single byte (when
configured to × 16 mode) under worst case conditions. Parameter tWCK2DQI defines the mean value of the earliest and latest DQ/DBI# pin,
tDQDQI(min) the negative offset to tWCK2DQI for the earliest DQ/DBI# pin and tDQDQI(max) the positive offset to tWCK2DQI for the latest
DQ/DBI# pin.
ad. tDQDQO defines the maximum skew among all DQ/DBI# outputs of a double byte (when configured to × 32mode) or a single byte (when
configured to × 16 mode) under worst case conditions. Parameter tWCK2DQO defines the mean value of of the earliest and latest DQ/DBI#
/EDC pin, tDQDQO(min) the negative offset to tWCK2DQO for earliest DQ/DBI#/EDC pin and tDQDQO(max) the positive offset to tWCK2DQO
for the latest DQ/DBI#/EDC pin.
ae. For READs and WRITEs with AUTO PRECHARGE enabled the device will hold off the internal PRECHARGE until tRAS(min) has been satisfied.
af. Parameter applies when bank groups are enabled and consecutive commands access the same bank group.
ag. Parameter applies when bank groups are disabled or consecutive commands access different bank group.
ah. Not more than 4 ACTIVE commands are allowed within period.
ai. Not more than 32 ACTIVE commands are allowed within t32AW period. The parameter need not to be specified in case t32AW(min) would not be
greater than 8*tFAW(min).
aj. Parameter applies when bank groups are enabled and READ and PRECHARGE commands access the same bank.
ak. Parameter applies when bank groups are disabled or READ and PRECHARGE commands access the same bank.
al. tDAL = (tWR/tCK) + ( tRP/tCK). For each of the terms, if not already an integer, round up to the next integer.
am. tCCDL is either for gapless consecutive READ or gapless consecutive WRITE commands
an. tCCDS is either for gapless consecutive READ or RDTR (any combination), gapless consecutive WRITE, or gapless consecutive WRTR commands.
ao. The min. value does not exceed 8 tCK
ap. tRTW is not a device limit but determined by the system bus turnaround time. The difference between tWCK2DQO and tWCK2DQI shall be considered
in the calculation of the bus turnaround time.

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aq. The WRITE latency WLmrs cna be set to 3 to 7 clocks. When the WRITE latency is set to small values (3 ~ 4 clocks), the input buffers are always on,
reducing the latency but adding power. When the WRITE latency is set to larger values (5 ~ 7 clocks), the input buffers are turned on with the WRITE
command, thus saving power.
ar. Read data including CRC data must have been clocked out before entering self refresh or power down mode.
as. Write data must have been written to the memory core and CRC data must have been clocked out before entering self refresh or power down mode.
at. Time for WCK2CK training and data training not included.
au. A maximum of 8 consecutive REFRESH commands can be posted to a GDDR5 SGRAM device, meaning that the maximum absolute interval
between any REFRESH command and the next REFRESH command is 9*tREFI.
av. Replaces parameter tLK when PLL Fast Lock has been neabled prior to the PLL enable or reset.
aw. Replaces parameter tLK when PLL Standby has been enabed and the WCK clock frequency has not charged while in standby mode.
ax. The PLL standby time tSTDBY ismeasured from self refresh entry until after self refresh exit a subsequent PLL reset is given (with PLL Standby
enabled)

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6.3 CLOCK-TO-DATA TIMING SENSITIVITY

The availability of clock‐to‐data (WCK2DQ) timing sensitivity information provides the controller the
opportunity to anticipate the impact to timings from variations in environmental conditions (such as
changes in voltage or temperature) allowing the controller to take corrective action if necessary (e.g.
realigning WCK and DQ).

Variations in relative timing between WCK and data are reported for READ and WRITE paths. This speci‐
fication calls out one zone each for VDDQ, VDD, and Tcase temperature over a specified range. Vendors
may choose to provide information for additional zones covering, in total, a wider range or a finer granu‐
larity or both.

However, within a given zone if an approximated value (i.e. the specified slope) deviates from the charac‐
terized slope to such a degree that the approximated WCK‐to‐DQ time delay would be in error by more
than 5% of one UI relative to the characterized delay then the splitting of this zone into more than one zone
is required.

All zones and their associated specified slopes must form a continuous piece‐wise‐linear curve such that,
after calibration during normal operation, traversing the approximated curve (i.e. the set of specified
slopes) does not lead to time delay errors in excess of the 5% of one UI.

Tables 45, 46, and 47 below describe the minimum set of defined zones.
Table 45. VDDQ Voltage Zone

VDDQ High VDDQ Low Notes

a
Zone_VQ1 VDDQmax VDDQmin

a. VDDQ(max) is the maximum specified operating voltage. VDDQ(min) is the minimum specified operating
voltage.

Table 46. VDD Voltage Zone

VDD High VDD Low Notes

Zone_VD1 VDDmax VDDmin a

a. VDD(max) is the maximum specified operating voltage. VDD(min) is the minimum specified operating
voltage.

Table 47. Tcase Temperature Zone

Tcase High Tcase Low Notes

a
Zone_T1 Tcasemax 10°C

a. Tcase(max) is the maximum specified operating temperature.

As noted, variations in relative timing are reported for READ and WRITE paths. Tables 48,49 and 50 below
provide information for READ timings while Tables 51,52 and 53 provide information for WRITE timings

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Table 48. WCK-to-Data READ Timing Sensitivity to VDDQ

Parameter Symbol Values Units Notes

WCK2DQO Sensitivity to variations in VDDQ for PLL on TBD

tO2VQSensZ1 ps/V ab
,
zone_VQ1 PLL off TBD

a. Calculation of tO2VQSensZ1 is performed as follows:
tO2VQSensZ1 equals the quantity (tWCK2DQO(Zone_VQ1(max)) ‐ tWCK2DQO(Zone_VQ1(min)))
divided by (VDDQ(Zone_VQ1(max)) ‐ VDDQ(Zone_VQ1(min)))
= (tWCK2DQO(VDDQ(max)) ‐ tWCK2DQO(VDDQ(min))) / (VDDQ(max) ‐ VDDQ(min)).
b. VDD(typ), Tcase = 85°C, worst‐case process corner.

Table 49. WCK-to-Data READ Timing Sensitivity to VDD

Parameter Symbol Values Units Notes

PLL on TBD
WCK2DQO Sensitivity to variations in VDD for zone_VD1 tO2VDSensZ1 ps/V a,b
PLL off TBD

a. Calculation of tO2VDSensZ1 is performed as follows:
tO2VDSensZ1 equals the quantity (tWCK2DQO(Zone_VD1(max)) ‐ tWCK2DQO(Zone_VD1(min)))
divided by (VDD(Zone_VD1(max)) ‐ VDD(Zone_VD1(min)))
= (tWCK2DQO(VDD(max)) ‐ tWCK2DQO(VDD(min))) / (VDD(max) ‐ VDD(min)).
b. VDDQ(typ), Tcase = 85°C, worst‐case process corner.

Table 50. WCK-to-Data READ Timing Sensitivity to Tcase

Parameter Symbol Values Units Notes

PLL on TBD
WCK2DQO Sensitivity to variations in Tcase for zone_T1 tO2TSensZ1 ps/°C ab
,
PLL off TBD

a. Calculation of tO2TSensZ1 is performed as follows:
tO2TSensZ1 equals the quantity (tWCK2DQO(Zone_T1(max)) ‐ tWCK2DQO(Zone_T1(min)))
divided by (Tcase(Zone_T1(max)) ‐ Tcase(Zone_T1(min)))
= (tWCK2DQO(Tcase(max)) ‐ tWCK2DQO(Tcase(min))) / (Tcase(max) ‐ Tcase(min)).
b. VDDQ(typ), VDD(typ), worst‐case process corner.

.
Table 51. WCK-to-Data WRITE Timing Sensitivity to VDDQ

Parameter Symbol Values Units Notes

PLL on TBD
WCK2DQI Sensitivity to variations in VDDQ for zone_VQ1 tI2VQSensZ1 ps/V a,b
PLL off TBD

a. Calculation of tI2VQSensZ1 is performed as follows:
tI2VQSensZ1 equals the quantity (tWCK2DQI(Zone_VQ1(max)) ‐ tWCK2DQI(Zone_VQ1(min)))
divided by (VDDQ(Zone_VQ1(max)) ‐ VDDQ(Zone_VQ1(min)))
= (tWCK2DQI(VDDQ(max)) ‐ tWCK2DQI(VDDQ(min))) / (VDDQ(max) ‐ VDDQ(min)).
b. VDD(typ), Tcase = 85°C, worst‐case process corner.

Table 52. WCK-to-Data WRITE Timing Sensitivity to VDD

Parameter Symbol Values Units Notes

PLL on TBD
WCK2DQI Sensitivity to variations in VDD for zone_VD1 tI2VDSensZ1 ps/V a,b
PLL off TBD

a. Calculation of tO2VDSensZ1 is performed as follows:
tI2VDSensZ1 equals the quantity (tWCK2DQI(Zone_VD1(max)) ‐ tWCK2DQI(Zone_VD1(min)))
divided by (VDD(Zone_VD1(max)) ‐ VDD(Zone_VD1(min)))
= (tWCK2DQI(VDD(max)) ‐ tWCK2DQI(VDD(min))) / (VDD(max) ‐ VDD(min)).
b. VDDQ(typ), Tcase = 85°C, worst‐case process corner.

Table 53. WCK-to-Data WRITE Timing Sensitivity to Tcase

Parameter Symbol Values Units Notes

PLL on TBD
WCK2DQI Sensitivity to variations in Tcase for zone_T1 tI2TSensZ1 ps/°C a,b
PLL off TBD

a. Calculation of tI2TSensZ1 is performed as follows:
tI2TSensZ1 equals the quantity (tWCK2DQI(Zone_T1(max)) ‐ tWCK2DQI(Zone_T1(min)))
divided by (Tcase(Zone_T1(max)) ‐ Tcase(Zone_T1(min)))
= (tWCK2DQI(Tcase(max)) ‐ tWCK2DQI(Tcase(min))) / (Tcase(max) ‐ Tcase(min)).
b. VDDQ(typ), VDD(typ), worst‐case process corner.

7. PACKAGE SPECIFICATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14
BYTE 0 BYTE 1
VSSQ VSSQ VPP, VSSQ
DQ1 DQ0 A VREFD DQ8 VSSQ DQ9
NC

VDDQ DQ3 VDDQ DQ2 VSS B VSS DQ10 VDDQ DQ11 VDDQ

VSSQ EDC0 VSSQ VSSQ VDD C VDD VSSQ VSSQ EDC1 VSSQ

VDDQ DBI0# VDDQ WCK01 WCK01# D VSS VDD VDDQ DBI1# VDDQ

VSSQ DQ5 VSSQ DQ4 VDDQ E VDDQ DQ12 VSSQ DQ13 VSSQ

VDDQ DQ7 VDDQ DQ6 VSSQ F VSSQ DQ14 VDDQ DQ15 VDDQ

VDD VDDQ RAS# VDD VSS G VSS VDD CS# VDDQ VDD

A10 A9 BA3 BA0

VSS VSSQ VDDQ A1 H VDDQ VSSQ VSS
A0 A3 A2
A12
MF RESET# CKE# ABI# RFU, J SEN CK# CK ZQ VREFC
NC

A8 A11 BA1 BA2

VSS VSSQ VDDQ VDDQ VSSQ VSS
A7 A6 K A5 A4

VDD VDDQ CAS# VDD VSS L VSS VDD WE# VDDQ VDD

VDDQ DQ31 VDDQ DQ30 VSSQ M VSSQ DQ22 VDDQ DQ23 VDDQ

VSSQ DQ29 VSSQ DQ28 VDDQ N VDDQ DQ20 VSSQ DQ21 VSSQ

VDDQ DBI3# VDDQ WCK23 WCK23# VSS VDD VDDQ DBI2# VDDQ
P

VSSQ EDC3 VSSQ VSSQ VDD R VDD VSSQ VSSQ EDC2 VSSQ

VDDQ DQ27 VDDQ DQ26 VSS VSS VDDQ DQ19 VDDQ

T DQ18

VPP,
VSSQ DQ25 VSSQ DQ24 VSSQ VSSQ
NC U VREFD DQ16 DQ17

BYTE 3 x32 mode: ON x32 mode: ON BYTE 2

x16 mode: ON x16 mode: OFF

Note) Top View (as seen thru package), MF = LOW (MF = 0)

Figure 81. GDDR5 SGRAM 170ball BGA Ball-out MF=0
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responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 156
H5GQ1H24AFR

1 2 3 4 5 6 7 8 9 10 11 12 13 14
BYTE 3 BYTE 2
VPP, VSSQ
VSSQ DQ25 VSSQ DQ24 A VREFD DQ16 VSSQ DQ17
NC

VDDQ DQ27 VDDQ DQ26 VSS B VSS DQ18 VDDQ DQ19 VDDQ

VSSQ EDC3 VSSQ VSSQ VDD C VDD VSSQ VSSQ EDC2 VSSQ

VDDQ DBI3# VDDQ WCK23 WCK23# D VSS VDD VDDQ DBI2# VDDQ

VSSQ DQ29 VSSQ DQ28 VDDQ E VDDQ DQ20 VSSQ DQ21 VSSQ

VDDQ DQ31 VDDQ DQ30 VSSQ F VSSQ DQ22 VDDQ DQ23 VDDQ

VDD VDDQ CAS# VDD VSS G VSS VDD WE# VDDQ VDD

A8 A11 H BA1 BA2

VSS VSSQ VDDQ VDDQ VSSQ VSS
A7 A6 A5 A4
A12
MF RESET# CKE# ABI# RFU, J SEN CK# CK ZQ VREFC
NC

A10 A9 BA3 BA0

VSS VSSQ VDDQ A1
K A3 A2
VDDQ VSSQ VSS
A0

VDD VDDQ RAS# VDD VSS L VSS VDD CS# VDDQ VDD

VDDQ DQ7 VDDQ DQ6 VSSQ M VSSQ DQ14 VDDQ DQ15 VDDQ

VSSQ DQ5 VSSQ DQ4 VDDQ N VDDQ DQ12 VSSQ DQ13 VSSQ

VDDQ DBI0# VDDQ WCK01 WCK01# P VSS VDD VDDQ DBI1# VDDQ

VSSQ EDC0 VSSQ VSSQ VDD R VDD VSSQ VSSQ EDC1 VSSQ

VDDQ DQ3 VDDQ DQ2 VSS T VSS DQ10 VDDQ DQ11 VDDQ

VPP,
VSSQ DQ1 VSSQ DQ0 U VREFD DQ8 VSSQ DQ9 VSSQ
NC

BYTE 0 x32 mode: ON x32 mode: ON BYTE 1

x16 mode: ON x16 mode: OFF
Note) Top View (as seen thru package), MF = HIGH (MF = 1)

Figure 82. GDDR5 SGRAM 170ball BGA Ball-out MF=1

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 157
H5GQ1H24AFR
7.1. SIGNALS
Table 54. Ball-out Description
SYMBOL TYPE DESCRIPTION
CK, CK# Input Clock: CK and CK# are differential clock inputs. Command inputs are latched on the rising
edge of CK. Address inputs are latched on the rising edge of CK and the rising edge of CK#.
All latencies are referenced to CK. CK and CK# are externally terminated.
WCK01, Input Write Clocks: WCK and WCK# are differential clocks used for WRITE data capture and READ
WCK01#, data output. WCK01/WCK01# is associated with DQ0‐DQ15, DBI0#, DBI1#, EDC0 and EDC1.
WCK23, WCK23/WCK23# is associated with DQ16‐DQ31, DBI2#, DBI3#, EDC2 and EDC3.
WCK23#
CKE# Input Clock Enable: CKE# LOW activates and CKE# HIGH deactivates the internal clock, device
input buffers, and output drivers. Taking CKE# HIGH provides PRECHARGE POWER‐
DOWN and SELF REFRESH operations (all banks idle), or ACTIVE POWER‐DOWN (row
ACTIVE in any bank). CKE# must be maintained LOW throughout read and write accesses.
The value of CKE# latched at power‐up with RESET# going High determines the termination
value of the address and command inputs.
CS# Input Chip Select: CS# LOW enables and CS# HIGH disables the command decoder. All commands
are masked when CS# is registered HIGH. CS# provides for external rank selection on systems
with multiple ranks. CS# is considered part of the command code.
RAS#, Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
CAS#,WE# entered.
BA0–BA3 Input Bank Address Inputs: BA0 ‐ BA3 define to which bank an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA0‐BA3 also determine which Mode Register is
accessed with an MODE REGISTER SET command. BA0‐BA3 are sampled with the rising
edge of CK.
A0–A11 Input Address Inputs: A0‐A11 (A12) provide the row address for ACTIVE commands, A0‐A5 (A6)
(A12) provide the column address and A8 defines the auto precharge function for READ/WRITE
commands, to select one location out of the memory array in the respective bank. A8 sampled
during a PRECHARGE command determines whether the PRECHARGE applies to one bank
(A8 LOW, bank selected by BA0‐BA3) or all banks (A8 HIGH). The address inputs also
provide the op‐code during a MODE REGISTER SET command and the data bits during a
LDFF command. A8‐A11(A12) are sampled with the rising edge of CK and A0‐A7 are
sampled with the rising edge of CK#.
DQ0–31 I/O Data Input/Output: 32‐bit data bus
DBI#0‐3 I/O Data Bus Inversion. DBI#0 is associated with DQ0‐DQ7, DBI#1 is associated with DQ8‐DQ15,
DBI#2 is associated with DQ16‐DQ23, DBI#3 is associated with DQ24‐DQ31.
EDC0‐3 Output Error Detection Code. The calculated CRC data is transmitted on these pins. In addition these
pins drive a ‘hold’ pattern when idle and can be used as an RDQS function. EDC0 is
associated with DQ0‐DQ7, EDC1 is associated with DQ8‐DQ15, EDC2 is associated with
DQ16‐DQ23, EDC3 is associated with DQ24‐DQ31.
ABI# Input Address Bus Inversion
VddQ Supply I/O Power Supply. Isolated on the die for improved noise immunity.
VssQ Supply I/O Ground: Isolated on the die for improved noise immunity.
Vdd Supply Power Supply
Vss Supply Ground
Vrefd Supply Reference Voltage for DQ, DBI#, and EDC pins.
Vrefc Supply Reference Voltage for address and command pins.
Vpp Supply Pump Voltage
MF Reference Mirror Function: VDDQ CMOS input. Must be tied to power or ground.
ZQ Reference External Reference Pin for autocalibration

Figure clarifies the use of the MF=0 and MF=1 ball‐outs in x16 mode and why the bytes are renumbered to
give the controller the view of the same bytes that a controller sees with a single x32 device. This is impor‐
tant for Address Training, DM and EDC functionality. For more details see the x16 enable and MF enable
section.

0 1 0 1

+ =

2 3 3 2

Top view thru package Top view thru PCB Controller view

(PCB below) (PCB above)

x16 MF=0 x16 MF=0

x16 MF=1 x16 MF=1

Legend:

DQ
ADDRESS/COMMAND (except CS#)
CS#

Figure 83. Byte Orientation in Clamshell Topology

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 160
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7.2. ON DIE TERMINATION (ODT)
GDDR5 SGRAMs support multiple termination modes for its high speed input signals. When the termina‐
tion is enabled for a receiver, an impedance defined for that termination mode is applied between that
input receiver and the VDDQ supply rail. This is commonly referred to as VDDQ termination. Registers
have been defined to control the termination modes. ADD/CMD Termination is controlled using MR1 bits
A4 and A5. Data termination is controlled using MR1 bits A2 and A3. WCK termination is controlled
using MR3 bits A8 and A9.

Table 55 includes all the high speed GDDR5 SGRAM signals whose receivers include on die termination to
VDDQ and whether their termination can be disabled by ADD/CMD Term, DQ Term, or WCK Term. A
“Yes” indicates whether the mode register field controls termination for the signal.
Table 55. Signals Affected by Termination Control Registers
ADD/CMD Term DQ Term WCK Term
MR1 (A4,A5) MR1 (A2,A3) MR3 (A8,A9)

Signal x32 x16 x32 x16 x32 x16

RAS#, CAS#, WE, CS#, CKE# Yes Yes No No No No

A10/A0, A9/A1, BA0/A2, BA3/A3,
BA2/A4, BA1/A5, A11/A6, A8/A7, Yes Yes No No No No
A12/RFU/(NC), ABI#

DQ[7:0], DBI0# No No Yes Yes No No

DQ[15:8], DBI1# No Disabled Yes Disabled No Disabled

DQ[23:16], DBI2# No No Yes Yes No No

DQ[31:24], DBI3# No Disabled Yes Disabled No Disabled

WCK01, WCK01#, WCK23, WCK23# No No No No Yes Yes

BOTTOM VIEW
TOP VIEW SIDE VIEW
(170 ball)
pkgheight

16 x 0.8 = 12.8
K
pkgY

14
H

0.8
B

pkgstandoff
5x0.8=4.0 0.8

13x0.8=10.4

pkgx 12

Figure 84. Package Dimensions

Table 56. Package Height Parameters

Nominal Variation

pkgstandoff 0.350 +/‐ 0.050

pkgheight 1.100 +/‐ 0.100

Notes:
1) GDDR5 package height specification is compliant to MO‐207 Rev L, variation DAA‐z

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 162
H5GQ1H24AFR
7.4. MIRROR FUNCTION (MF) ENABLE and x16 MODE ENABLE
The GDDR5 SGRAM provides a mirror function (MF) pin to change the physical location of the command,
address, data, and WCK pins assisting in routing devices back to back. The MF ball should be tied directly
to VSSQ or VDDQ depending on the control line orientation desired.

The GDDR5 SGRAM can operate in a x32 mode or a x16 mode to allow a clamshell configuration with a
point to point connection on the high speed data signal. The disabled pins in x16 mode should all be in a
Hi‐Z state, non‐terminating.

The x16 mode is detected at power up on the pin at location C‐13 which is EDC1 when configured to MF=0
and EDC2 when configured to MF=1. For x16 mode this pin is tied to VSSQ; the pin is part of the two bytes
that are disabled in this mode and therefore not needed for EDC functionality. For x32 mode this pin is
active and always terminated to VDDQ in the system or by the controller. The configuration is set with
RESET# going High. Once the configuration has been set, it cannot be changed during normal operation.
Usually the configuration is fixed in the system. Details of the x16 mode detection are depicted in Figure .
A comparison of x32 mode and x16 mode systems is shown in Figure .

VDDQ GDDR5
EDC data from in x16 mode
enable other DRAM
Termination MF=0

EDC1 EDC1 EDC Data

RX EDC TX
EN
x16
0 = x16
Controller VSSQ
RX D

RESET# RESET#
RESET#

VDDQ GDDR5
enable
EDC data from in x16 mode
other DRAM
Termination
MF=1

EDC2 EDC2 EDC Data

RX EDC TX
EN
x16
0 = x16
RX D
Controller VSSQ

RESET# RESET#
RESET#

VDDQ GDDR5
in x32 mode
enable
Termination MF=0 or 1

EDC1 EDC1 EDC Data

RX EDC TX
EN
x32
1 = x32
RX D
VSSQ
Controller
RESET# RESET#
RESET#

Figure 85. Enabling x16 mode

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009 164
H5GQ1H24AFR
Table 57. x16 mode and MF
MODE MF EDC1 (MF=0) or EDC2 (MF=1)
x16 non‐mirrored VSSQ VSSQ
x32 non‐mirrored VSSQ VDDQ (terminated by the system or controller)
x16 mirrored VDDQ VSSQ
x32 mirrored VDDQ VDDQ (terminated by the system or controller)

GDDR5 GDDR5 GDDR5

x32 x16 x16

DQ0‐DQ7,DBI0# Byte0 DQ0‐DQ7,DBI0# Byte0

EDC0 EDC0 EDC1 EDC2
WCK01,WCK01# WCK01,WCK01#
DQ8‐DQ15,DBI1# Byte1 DQ8‐DQ15,DBI1# Byte1
EDC1 EDC1
Controller
Controller

DQ16‐DQ23,DBI2# Byte2 DQ16‐DQ23,DBI2# Byte2

EDC2 EDC2
WCK23,WCK23# WCK23,WCK23#

DQ24‐DQ31,DBI3# Byte3 DQ24‐DQ31,DBI3# Byte3

EDC3 EDC3

Address Bus Address Bus
ADD/ ADD/
Command Bus CMD Command Bus CMD
CK,CK# CK,CK#
RESET# RESET
MF MF MF

VSSQ VSSQ VDDQ

Figure 86. System view for x32 mode vs. x16 mode

Figure 86 and Figure 87 show examples of the board channels and topologies that are supported in
GDDR5 in order to illustrate the expected usage of x16 mode and the MF pin.

32bit channel 64bit channel

16 DQ 32 DQ
(P2P) (P2P)
32 DQ
(P2P)
ADD/CMD ADD/CMD
(P22P) ADD/CMD (P22P)
(P2P)

16 DQ 32 DQ
(P2P) (P2P)

Figure 87. Example Channel Topologies

For flexibility of PCB routing GDDR5 SGRAM devices, the ball‐out includes definition of both MF=0 and
MF=1. The following simple block diagrams in Figure 88 demonstrate some of the flexibility of PCB rout‐
ing.

Single side configurations
1
x32 MF=0 x32 MF=0 x32 MF=0 x32 MF=0

1
x32 MF=0 x32 MF=1
x32 MF=0 x32 MF=1

1 x32 MF=1 x32 MF=1
x32 MF=1 x32 MF=1

x16 MF=0 x16 MF=1

Clamshell configurations
1
x32 MF=0

x16 MF=0

x32 MF=1
1
x32 MF=1
x16 MF=1
x16 MF=1

x32 MF=1
1
x32 MF=0 x16 MF=0

Legend:

DQ
x32 MF=0 ADDRESS/COMMAND (except CS#)
CS#
Note 1: 32bit channel is shown as an example.
Also applies with x16 on a 16bit channel.

Figure 88. Example GDDR5 PCB Layout Topologies

BOUNDARY SCAN

The GDDR5 SGRAM incorporates a modified boundary scan test mode. This mode does not operate in
accordance with IEEE Standard 1149.1‐1990. To save the current GDDR5 SGRAM’s ball‐out, this mode will
scan the parallel data input and output the scanned data on EDC0 located at C‐2 controlled by an add‐on
pin, SEN which is located at J‐10 of the 170 ball package.

Scan mode is entered directly after power‐up while the device is in reset state. This ensures that no
unwanted access commands are being executed prior to scan mode.

Boundary scan does not distinguish between x16 and x32 modes, and data is captured on all pins. The user
has to make sure to mask those bits in the test program which are not wired in the system.

For normal device operation, i.e. after scan mode operation, it is required that device re‐initialization
occurs through device power‐down and then power‐up.

It is possible to operate the GDDR5 SGRAM without using the boundary scan feature. SEN should be tied
Low to prevent the device from entering the boundary scan mode. The other pins which are used for scan
mode (RESET#, MF, EDC0 and CS#) will be operating as normal when SEN is deasserted.

Table 58. Boundary Scan Exit Order

BIT# BALL BIT# BALL BIT# BALL BIT# BALL BIT# BALL

1 D‐5 13 J‐3 25 T‐2 37 M‐11 49 E‐13

2 D‐4 14 K‐4 26 T‐4 38 M‐13 50 E‐11

3 D‐2 15 K‐5 27 U‐2 39 L‐12 51 D‐13

4 E‐4 16 L‐3 28 U‐4 40 K‐10 52 C‐13

5 E‐2 17 M‐2 29 U‐11 41 K‐11 53 B‐13

6 F‐4 18 M‐4 30 U‐13 42 J‐13 54 B‐11

7 F‐2 19 N‐2 31 T‐11 43 J‐12 55 A‐13

8 G‐3 20 N‐4 32 T‐13 44 J‐11 56 A‐11

9 H‐5 21 P‐2 33 R‐13 45 H‐11 57 A‐4

10 H‐4 22 P‐4 34 P‐13 46 H‐10 58 A‐2

11 J‐5 23 P‐5 35 N‐11 47 F‐13 59 B‐4

12 J‐4 24 R‐2 36 N‐13 48 F‐11 60 B‐2

Note: When the device is in scan mode, mirror function is disabled (MF=0) and none of the pins are remapped.

Scan Shift: capture the data input from the pad at logic LOW
J‐2 SSH RESET# Input
and shift the data on the chain at logic HIGH.

Scan Clock. Not a true clock, could be a single pulse or series of
G‐12 SCK CS# Input pulses. All scan inputs will be referenced to the rising edge of
the scan clock.

C‐2 SOUT EDC0 Output Scan Output.

Scan Enable: logic HIGH enables scan mode. Scan mode is
J‐10 SEN RFU Input
disabled at logic LOW. Must be tied to VSSQ when not in use.

Scan Output Enable: enables (registered LOW) and disables
(registered HIGH) SOUT data. This pin will be tied to VDDQ or
J‐1 SOE# MF Input GND through a resistor (typically 1K Ohm) for normal
operation. Tester needs to overdrive this pin to guarantee the
required input logic level in scan mode.

Notes:
1. When SEN is asserted, no commands are to be executed by the GDDR5 SGRAM. This applies to both user
commands and manufacturing commands which may exist while RESET# is deasserted.
2. All scan functionality is valid only after the appropriate power‐up (Steps 1‐4 of initialization sequence).
3. In scan mode, all ODT will be disabled.

Table 60. Scan AC Electrical Characteristics

UNIT
PARAMETER/CONDITION SYMBOL MIN MAX NOTES
S

Clock

Clock cycle time tSCK 40 ‐ ns 1

Scan Command Time

Scan enable setup time tSES 20 ‐ ns 1

Scan enable hold time tSEH 20 ‐ ns 1

Scan command setup time for SSH, SOE# and SOUT tSCS 14 ‐ ns 1

Scan command hold time for SSH, SOE# and SOUT tSCH 14 ‐ ns 1

Scan Capture Time

Scan capture setup time tSDS 10 ‐ ns 1

Scan capture hold time tSDH 10 ‐ ns 1

UNIT
PARAMETER/CONDITION SYMBOL MIN MAX NOTES
S

Scan Shift Time

Scan clock to valid scan output tSAC ‐ 6 ns 1

Scan clock to scan output hold tSOH 1.5 ‐ ns 1

Notes:
1. The parameter applies only when SEN is asserted.

Not a true clock, but a single pulse
SCK or a series of pulses
tSES

SEN

SSH (Low)
tSCS

SOE#
tSDS tSDH
Pins
under VALID
Test

Figure. 89 Scan Capture Timing

SCK
tSES

SEN
tSCS

SSH
tSCS
SOE#

tSOH

SOUT tSAC Scan Out Scan Out Scan Out Scan Out

bit 1 bit 2 bit 3 bit 4

Figure. 90 Scan Shift Timing

VDD

VDDQ

VREF
RESET#
(SSH in tSCS
Scan Mode)

SEN tSES
tSCK

SCK

tSCS
SOE# tSCS

SOUT Scan Out
tSAC bit 1
tSDS tSDH

Pins
under VALID
Test
200us
Power‐up RESET at power‐up Boundary Scan Mode
VDD stable Don’t Care

Figure 91. Scan Initialization Sequence

SET
D Q Dedicated Scan D FF per signal under test
DQ3

CLR Q

Signals in scan chain:
D
SET
Q
DQ[31:0], EDC[3:1], DBI#[3:0],
DQ2 WCK01, WCK01#, WCK23, WCK23#,
RAS#, CAS#, WE#, CKE#, ABI#,
CLR Q A[7:0]***, CK, CK#, ZQ

Pins under test Note: A[7:0]*** are multiplexed pins and
SET
D Q represent A[12:8] and BA[3:0]
DQ1
Signals not in the scan chain:
CLR Q
VDDQ, VSSQ, VDD, VSS, VREFx

SET
D Q SOUT, Scan Out Pin EDC0
WCK01#
SSH, Scan Shift Pin RESET#
CLR Q
SCK, Scan Clock Pin CS#
SEN, Scan Enable Pin SEN
SOE#, Scan Output Enable Pin MF

Figure. 92 Internal Block Diagram

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