Interface

COP87L84BC 8-Bit CMOS OTP Microcontrollers with 16k Memory, Comparators, and CAN
September 1999

COP87L84BC
8-Bit CMOS OTP Microcontrollers with 16k Memory,
Comparators, and CAN Interface
General Description Features include an 8-bit memory mapped architecture, 10
MHz CKI (-XE = crystal oscillator) with 1µs instruction cycle,
The COP87L84BC OTP (One Time Programmable) micro- one multi-function 16-bit timer/counter, 8-bit 39 kHz PWM
controllers are highly integrated COP8™ Feature core de- timer with 2 outputs, CAN 2.0B (passive) interface,
vices with 16k OTP EPROM memory and advanced features MICROWIRE/PLUS™ serial I/O, two Analog comparators,
including a CAN 2.0B (passive) interface and two Analog two power saving HALT/IDLE modes, idle timer, MIWU, soft-
comparators. These multi-chip CMOS devices are suited for ware selectable I/O options, low EMI 4.5V to 5.5V operation,
applications requiring a full featured controller with a CAN in- and 28 pin packages.
terface, and 8-bit 39 kHz PWM timer, and as pre-production
Note: The companion devices with CAN interface, more I/O
devices for a masked ROM design. Pin and software com-
and memory, A/D, and USART are the COP87L88EB/RB.
patible 2k ROM versions are available (COP884BC) with a
range of COP8 software and hardware development tools. Device included in this datasheet is:

Device Memory (bytes) RAM (bytes) I/O Pins Packages Temperature

COP87L84BC 16k OTP EPROM 64 18 28 SOIC -40 to +85˚C

Key Features CPU/Instruction Set Features

n CAN 2.0B (passive) Interface n 1 µs instruction cycle time
n One 16-bit timer, with two 16-bit registers supporting: n Eleven multi-source vectored interrupts servicing
— Processor Independent PWM mode — External Interrupt
— External Event counter mode — Idle Timer T0
— Input Capture mode — Timer T1 (with 2 Interrupts)
n High speed, constant resolution 8-bit PWM/frequency — MICROWIRE/PLUS
monitor timer with 2 output pins — Multi-Input Wake Up
n 16 kbytes on-board OTP EPROM with security feature — Software Trap
n 64 bytes on-board RAM — PWM Timer
— CAN Interface (with 3 interrupts)
n Versatile and easy to use instruction set
Additional Peripheral Features n 8-bit Stack Pointer (SP) — stack in RAM
n Idle Timer
n Two 8-bit Register Indirect Data Memory Pointers
n Multi-Input Wake Up (MIWU) with optional interrupts (7) (B and X)
n Two analog comparators
MICROWIRE/PLUS serial I/O
n
Fully Static CMOS
n Two power saving modes: HALT and IDLE
I/O Features n Single supply operation: 4.5V–5.5V
n Memory mapped I/O n Temperature ranges: −40˚C to +85˚C
n Software selectable I/O options (TRI-STATE ® Output,
Push-Pull Output, Weak Pull-Up Input, High Impedance
Input)
Development Support
n Schmitt trigger inputs on ports G and L n Emulation device for COP884BC/COP885BC
n Packages: 28 SO with 18 I/O pins n Real time emulation and full program debug offered by
MetaLink Development Systems

COP8™, and MICROWIRE/PLUS™ are trademarks of National Semiconductor Corporation.

TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
iceMASTER ® is a registered trademark of MetaLink Corporation.

© 1999 National Semiconductor Corporation DS101137 www.national.com

 Block Diagram

DS101137-1

FIGURE 1. Block Diagram

Connection Diagrams Pinouts for 28-Pin SO Package

Port Pin Type Alt. Function 28-Pin SO
G0 I/O INTR 25
G1 I/O 26
G2 I/O T1B 27
G3 I/O T1A 28
G4 I/O SO 1
G5 I/O SK 2
G6 I SI 3
G7 I CKO 4
L0 I/O CMP1IN+/MIWU 7
L1 I/O CMP1IN−/MIWU 8
L2 I/O CMP10UT/MIWU 9
L3 I/O CMP2IN−/MIWU 10
L4 I/O CMP2IN+/MIWU 11
L5 I/O CMP2IN−/PWM1/MIWU 12
L6 I/O CMP2OUT/PWM0/ 13
DS101137-2
CAPTIN/MIWU
Note:X = Crystal Oscillator
E = Halt Mode Enabled D0 O 19
Top View D1 O 20
Order Number COP87L84BCM-XE D2 O 21
See NS Package Number M28B
D3 O 22
FIGURE 2. Connection Diagrams
CAN VREF 18
CAN Tx0 O 15
CAN Tx1 O 14
CAN Rx0 I MIWU 17
CAN Rx1 I MIWU 16
VCC 6
GND 23
CKI I 5
RESET I 24

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 Absolute Maximum Ratings (Note 1) Total Current into VCC Pin (Source) 90 mA
If Military/Aerospace specified devices are required, Total Current out of GND Pin (Sink) 100 mA
please contact the National Semiconductor Sales Office/ Storage Temperature Range −65˚C to +150˚C
Distributors for availability and specifications. Note 1: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
Supply Voltage (VCC) 6V when operating the device at absolute maximum ratings.
Voltage at Any Pin −0.3V to VCC +0.3V

DC Electrical Characteristics
−40˚C ≤ TA ≤ +85˚C
Parameter Conditions Min Typ Max Units
Operating Voltage 4.5 5.5 V
Power Supply Ripple (Note 2) Peak-to-Peak 0.1 VCC V
Supply Current
CKI = 10 MHz (Note 3) VCC = 5.5V, tc = 1 µs 19 mA
HALT Current (Notes 4, 5) VCC = 5.5V, CKI = 0 MHz
Power-On Reset Enabled 480 µA
Power-On Reset Disabled 380 µA
IDLE Current (Note 5)
CKI = 10 MHz VCC = 5.5V, tc = 1 µs 5.5 mA
Input Levels (VIH, VIL)
Reset, CKI
Logic High 0.8 VCC V
Logic Low 0.2 VCC V
All Other Inputs
Logic High 0.7 VCC V
Logic Low 0.2 VCC V
Hi-Z Input Leakage VCC = 5.5V ±2 µA
Input Pull-up Current VCC = 5.5V, VIN = 0V −40 −250 µA
G and L Port Input Hysteresis 0.05 VCC V
Output Current Levels D Outputs
Source VCC = 4.5V, VOH = 3.3V −0.4 mA
Sink VCC = 4.5V, VOL = 1.0V 10 mA
Comparator Output (L2, L6)
Source (Push-Pull) VCC = 4.5V, VOH = 3.3V −1.6 mA
Sink (Push-Pull) VCC = 4.5V, VOL = 0.4V 1.6 mA
CAN Transmitter Outputs
Source (Tx1) VCC = 4.5V, VOH = VCC − 0.1V −1.5 mA
VCC = 4.5V, VOH = VCC − 0.6V −10 mA
Sink (Tx0) VCC = 4.5V, VOL = 0.1V 1.5 mA
VCC = 4.5V, VOL = 0.6V 10 mA
All Others
Source (Weak Pull-Up) VCC = 4.5V, VOH = 2.7V −10 −110 µA
Source (Push-Pull) VCC = 4.5V, VOH = 3.3V −0.4 mA
Sink (Push-Pull) VCC = 4.5V, VOL = 0.4V 1.6 mA
TRl-STATE Leakage VCC = 5.5V ± 2.0 µA
Allowable Sink/Source Current per
Pin
D Outputs (Sink) 15 mA
Tx0 (Sink) 30 mA
Tx1 (Source) 30 mA
All Other 3 mA

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 DC Electrical Characteristics (Continued)

−40˚C ≤ TA ≤ +85˚C
Parameter Conditions Min Typ Max Units
Maximum Input Current
without Latchup Room Temp ± 100 mA
RAM Retention Voltage, Vr 500 ns Rise and Fall Time 2.0 V
Input Capacitance 7 pF
Load Capacitance on D2 1000 pF
Note 2: Maximum rate of voltage change must be less than 0.5 V/ms
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at VCC or GND, and outputs open.
Note 4: The HALT mode will stop CKI from oscillating in the Crystal configurations. Halt test conditions: All inputs tied to VCC; L, and G port I/Os configured as outputs
and programmed low; D outputs programmed low. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during
HALT in crystal clock mode.
Note 5: HALT and IDLE current specifications assume CAN block and comparators are disabled.

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 Absolute Maximum Ratings (Note 1) Total Current into VCC Pin (Source) 90 mA
If Military/Aerospace specified devices are required, Total Current out of GND Pin (Sink) 100 mA
please contact the National Semiconductor Sales Office/ Storage Temperature Range −65˚C to +150˚C
Distributors for availability and specifications. Note 6: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
Supply Voltage (VCC) 6V when operating the device at absolute maximum ratings.
Voltage at Any Pin −0.3V to VCC +0.3V

AC Electrical Characteristics:
−40˚C ≤ TA ≤ +85˚C
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (tc)
Crystal/Resonator VCC ≥ 4.5V 1.0 DC µs
Inputs
tSETUP VCC ≥ 4.5V 200 ns
tHOLD VCC ≥ 4.5V 60 ns
PWM Capture Input
tSETUP VCC ≥ 4.5V 30 ns
tHOLD VCC ≥ 4.5V 70 ns
Output Propagation Delay
(tPD1, tPD0) CL = 100 pF, RL = 2.2 kΩ
SK, SO VCC ≥ 4.5V 0.7 µs
PWM Outputs VCC ≥ 4.5V 75 ns
All Others VCC ≥ 4.5V 1 µs
MICROWIRE
Setup Time (tUWS) 20 ns
Hold Time (tUWH) 56 ns
Output Prop Delay (tUPD) 220 ns
Input Pulse Width
Interrupt High Time 1 tc
Interrupt Low Time 1 tc
Timer 1,2 High Time 1 tc
Timer 1,2 Low Time 1 tc
Reset Pulse Width 1.0 µs
Power Supply Rise Time for Proper 50 µs 256*tc
Operation of On-Chip RESET
Note 7: For device testing purposes of all AC parameters, VOH will be tested at 0.5*VCC.
Note 8: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 9: Parameter not tested.
Note 10: tc = Instruction Cycle Time.

On-Chip Voltage Reference:

−40˚C ≤ TA ≤ +85˚C
Parameter Conditions Min Max Units
Reference Voltage IOUT < 80 µA, 0.5 VCC −0.12 0.5 VCC +0.12 V
VREF VCC = 5V
Reference Supply Current, IOUT = 0A, (No Load) 120 µA
IDD VCC = 5V (Note 11)
Note 11: Reference supply IDD is supplied for information purposes only, it is not tested.

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 Comparator DC/AC Characteristics:
4.5V ≤ VCC ≤ 5.5V, −55˚C ≤ TA ≤ +125˚C
Parameter Conditions Min Typ Max Units
Input Offset Voltage 0.4V < VIN < VCC −1.5V ± 10 ± 25 mV
Input Common Mode Voltage Range 0.4 VCC −1.5 V
Voltage Gain 300k V/V
Outputs Sink/Source See I/O-Port DC Specifications
DC Supply Current (when enabled) VCC = 6.0V 250 µA
Response Time TBD mV Step, TBD mV Overdrive, 1 µs
100 pF Load

CAN Comparator DC and AC Characteristics:

4.8V ≤ VCC ≤ 5.2V, −40˚C ≤ TA ≤ +125˚C
Parameters Conditions Min Typ Max Units
Differential Input Voltage ± 25 mV
Input Offset Voltage 1.5V < VIN < VCC − 1.5V ± 10 mV
Input Common Mode Voltage Range 1.5 VCC − 1.5 V
Input Hysteresis 8 mV

DS101137-3

FIGURE 3. MICROWIRE/PLUS Timing Diagram

DS101137-4

FIGURE 4. PWM/CAPTURE Timer

Input/Output Timing Diagram

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Typical Performance Characteristics −55˚C ≤ TA ≤ +125˚C

Port D Source Current Port D Sink Current

DS101137-39 DS101137-40

Ports G/L Source Current Port G/L Sink Current

DS101137-41 DS101137-42

Ports G/L Weak Pull-Up Source Current Dynamic IDD vs VCC

DS101137-43 DS101137-44

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 Typical Performance Characteristics −55˚C ≤ TA ≤ +125˚C (Continued)

Idle IDD vs VCC Halt Supply Current

DS101137-46
DS101137-45

CAN Tx0 Sink Current CAN Tx1 Source Current

DS101137-47 DS101137-48

Pin Descriptions Configuration Data

VCC and GND are the power supply pins. Port Set-Up
Register Register
CKI is the clock input. The clock can come from a crystal os- 0 0 Hi-Z Input (TRI-STATE
cillator (in conjunction with CKO). See Oscillator Description
Output)
section.
0 1 Input with Weak Pull-Up
RESET is the master reset input. See Reset Description sec-
tion. 1 0 Push-Pull Zero Output
The device contains one bidirectional 8-bit I/O port (G), and 1 1 Push-Pull One Output
one 7-bit bidirectional I/O port (L) where each individual bit PORT L is a 7-bit I/O port. All L-pins have Schmitt triggers on
may be independently configured as an input (Schmitt trig- the inputs.
ger inputs on ports G and L), output or TRI-STATE ® under Port L supports Multi-Input Wake Up (MIWU) on all seven
program control. Three data memory address locations are pins.
allocated for each of these I/O ports. Each I/O port has two
Port L has the following alternate features:
associated 8-bit memory mapped registers, the CONFIGU-
RATION register and the output DATA register. A memory L6 MIWU or CMP2OUT or PWM0 or CAPTIN
mapped address is also reserved for the input pins of each L5 MIWU or CMP2IN− or PWM1
I/O port. (See the memory map for the various addresses as- L4 MIWU or CMP2IN+
sociated with the I/O ports.) Figure 5 shows the I/O port con-
L3 MIWU or CMP2IN−
figurations for the device. The DATA and CONFIGURATION
registers allow for each port bit to be individually configured L2 MIWU or CMP1OUT
under software control as shown below: L1 MIWU or CMP1IN−
L0 MIWU or CMP1IN+
Port G is an 8-bit port with 5 I/O pins (G0–G5), an input pin
(G6), and one dedicated output pin (G7). Pins G0–G6 all
have Schmitt Triggers on their inputs. G7 serves as the dedi-
cated output pin for the CKO clock output. There are two reg-

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Pin Descriptions (Continued)

isters associated with the G Port, a data register and a con-

figuration register. Therefore, each of the 6 I/O bits (G0–G5)
can be individually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin the associated bits in the data and configu-
ration registers for G6 and G7 are used for special purpose
functions as outlined below. Reading the G6 and G7 data
bits will return zeroes.
Note that the chip will be placed in the HALT mode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register en-
ables the MICROWIRE/PLUS to operate with the alternate
DS101137-5
phase of the SK clock.
FIGURE 5. I/O Port Configurations
Config. Register Data Register
G7 HALT
G6 Alternate SK IDLE
Functional Description
The architecture of the device utilizes a modified Harvard ar-
CAN pins: For the on-chip CAN interface this device has five
chitecture. With the Harvard architecture, the control store
dedicated pins with the following features:
program memory (ROM) is separated from the data store
VREF On-chip reference voltage with the value of VCC/2 memory (RAM). Both ROM and RAM have their own sepa-
Rx0 CAN receive data input pin. rate addressing space with separate address buses. The ar-
Rx1 CAN receive data input pin. chitecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
Tx0 CAN transmit data output pin. This pin may be put in
the TRI-STATE mode with the TXEN0 bit in the CAN
CPU REGISTERS
Bus control register.
The CPU can do an 8-bit addition, subtraction, logical or shift
Tx1 CAN transmit data output pin. This pin may be put in
operation in one instruction (tc) cycle time.
the TRI-STATE mode with the TXEN1 bit in the CAN
Bus control register. There are five CPU registers:
Port G has the following alternate features: A is the 8-bit Accumulator Register
G6 SI (MICROWIRE Serial Data Input) PC is the 15-bit Program Counter Register
G5 SK (MICROWIRE Serial Clock) PU is the upper 7 bits of the program counter (PC)
G4 SO (MICROWIRE Serial Data Output) PL is the lower 8 bits of the program counter (PC)
G3 T1A (Timer T1 I/O) B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
G2 T1B (Timer T1 Capture Input)
X is an 8-bit alternate RAM address pointer, which can be
G0 INTR (External Interrupt Input)
optionally post auto incremented or decremented.
Port G has the following dedicated function:
SP is the 8-bit stack pointer, which points to the subroutine/
G7 CKO Oscillator dedicated output interrupt stack (in RAM). The SP is initialized to RAM ad-
Port D is a 4-bit output port that is preset high when RESET dress 02F with reset.
goes low. The user can tie two or more D port outputs (ex- All the CPU registers are memory mapped with the excep-
cept D2) together in order to get a higher drive. tion of the Accumulator (A) and the Program Counter (PC).
Note: Care must be exercised with the D2 pin operation. At RESET, the ex-
ternal loads on this pin must ensure that the output voltages stay PROGRAM MEMORY
above 0.8 VCC to prevent the chip from entering special modes. Also
keep the external loading on D2 to less than 1000 pF. Program memory for the device consists of 16 kbytes of OTP
EPROM. These bytes may hold program instructions or con-
stant data (data tables tor the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS in-
struction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the device vector to
program memory location 0FF Hex.
The device can be configured to inhibit external reads of the
program memory. This is done by programming the Security
Byte.

SECURITY FEATURE
The program memory array has an associate Security Byte
that is located outside of the program address range. This
byte can be addressed only from programming mode by a
programmer tool.

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 Functional Description (Continued) CAN:
The CAN Interface comes out of external reset in the
Security is an optional feature and can only be asserted after “error-active” state and waits until the user’s software
the memory array has been programmed and verified. A se- sets either one or both of the TXEN0, TXEN1 bits to “1”.
cured part will read all 00(hex) by a programmer. The part After that, the device will not start transmission or recep-
will fail Blank Check and will fail Verify operations. A Read tion of a frame until eleven consecutive “recessive” (un-
operation will fill the programmer’s memory with 00(hex). driven) bits have been received. This is done to ensure
The Security Byte itself is always readable with value of that the output drivers are not enabled during an active
00(hex) if unsecure and FF(hex) if secure. message on the bus.
CSCAL, CTlM, TCNTL, TEC, REC: CLEARED
DATA MEMORY
RTSTAT: CLEARED with the exception of the TBE bit
The data memory address space includes the on-chip RAM
which is set to 1
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift RID, RIDL, TID, TDLC: RANDOM
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data ON-CHIP POWER-ON RESET
memory is addressed directly by the instruction or indirectly The device is designed with an on-chip power-on reset cir-
by the B, X and SP pointers. cuit which will trigger a 256 tc delay as VCC rises above the
The device has 64 bytes of RAM. Sixteen bytes of RAM are minimum RAM retention voltage (Vr). This delay allows the
mapped as “registers” at addresses 0F0 to 0FF Hex. These oscillator to stabilize before the device exits the reset state.
registers can be loaded immediately, and also decremented The contents of data registers and RAM are unknown follow-
and tested with the DRSZ (decrement register and skip if ing an on-chip power-on reset. The external reset takes pri-
zero) instruction. The memory pointer registers X, SP, and B ority over the on-chip reset and will deactivate the 256 tc de-
are memory mapped into this space at address locations lay if in progress.
0FC to 0FE Hex respectively, with the other registers (other When using external reset, the external RC network shown
than reserved register 0FF) being available for general us- in Figure 6 should be used to ensure that the RESET pin is
age. held low until the power supply to the chip stabilizes.
The instruction set permits any bit in memory to be set, reset Under no circumstances should the RESET pin be allowed
or tested. All I/O and registers (except A and PC) are to float. If the on-chip power-on reset feature is being used,
memory mapped; therefore, I/O bits and register bits can be RESET should be connected directly to VCC. Be aware of
directly and individually set, reset and tested. The accumula- the Power Supply Rise Time requirements specified in the
tor (A) bits can also be directly and individually tested. DC Specifications Table. These requirements must be met
Note: RAM contents are undefined upon power-up. for the on-chip power-on reset to function properly.
The on-chip power-on reset circuit may reset the device if
RESET the operating voltage (VCC) goes below Vr.
The RESET input when pulled low initializes the microcon-
troller. lnitialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for Ports L and G, are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Port D is ini-
tialized high with RESET. The PC, PSW, CNTRL, and ICN-
TRL control registers are cleared. The Multi-Input Wake Up
registers WKEN, WKEDG, and WKPND are cleared. The
Stack Pointer, SP, is initialized to 02F Hex.
The following initializations occur with RESET: DS101137-6
Port L: TRI-STATE RC > 5 x Power Supply Rise Time
Port G: TRI-STATE FIGURE 6. Recommended Reset Circuit
Port D: HIGH
PC: CLEARED
PSW, CNTRL and ICNTRL registers: CLEARED
Oscillator Circuits
Accumulator and Timer 1: The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
RANDOM after RESET with power already applied
clock is on pin G7. The CKI input frequency is divided by 10
RANDOM after RESET at power-on to produce the instruction cycle clock (1/tc).
SP (Stack Pointer): Loaded with 2F Hex Figure 7 shows the Crystal diagram.
CMPSL (Comparator control register): CLEARED
PWMCON (PWM control register): CLEARED
B and X Pointers:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-up
RAM:
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-up

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Oscillator Circuits (Continued) T1ENA Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
EXPND External interrupt pending
BUSY MICROWIRE/PLUS busy shifting flag
EXEN Enable external interrupt
GIE Global interrupt enable (enables interrupts)
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.

DS101137-7 ICNTRL Register (Address X'00E8)

FIGURE 7. Crystal Oscillator Diagram Reserved LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB

CRYSTAL OSCILLATOR Bit 7 Bit 0

CKI and CKO can be connected to make a closed loop crys- The ICNTRL register contains the following bits:
tal (or resonator) controlled oscillator. Reserved This bit is reserved and must be zero.
Table 1 shows the component values required for various LPEN L Port Interrupt Enable (Multi-Input Wakeup/
standard crystal values. Interrupt)
T0PND Timer T0 Interrupt pending
TABLE 1. Crystal Oscillator Configuration, TA = 25˚C T0EN Timer T0 Interrupt Enable (Bit 12 toggle)
R1 R2 C1 C2 CKI Freq. µWPND MICROWIRE/PLUS interrupt pending
Conditions µWEN Enable MICROWIRE/PLUS interrupt
(kΩ) (MΩ) (pF) (pF) (MHz)
T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-
0 1 30 30–36 10 VCC = 5V
ture edge
0 1 30 30–36 4 VCC = 5V
T1ENB Timer T1 Interrupt Enable for T1B Input cap-
0 1 200 100–150 0.455 VCC = 5V ture edge

Control Registers Timers

The device contains a very versatile set of timers (T0, T1,
CNTRL Register (Address X'00EE) and an 8-bit PWM timer). All timers and associated
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0 autoreload/capture registers power up containing random
Bit 7 Bit 0 data.
The Timer1 (T1) and MICROWIRE/PLUS control register Figure 8 shows a block diagram for timers T1 and T0 on the
contains the following bits: device.
T1C3 Timer T1 mode control bit TIMER T0 (IDLE TIMER)
T1C2 Timer T1 mode control bit The device supports applications that require maintaining
T1C1 Timer T1 mode control bit real time and low power with the IDLE mode. This IDLE
T1C0 Timer T1 Start/Stop control in timer mode support is furnished by the IDLE timer T0, which is a
modes 1 and 2, T1 Underflow Interrupt 16-bit timer. The Timer T0 runs continuously at the fixed rate
Pending Flag in timer mode 3 of the instruction cycle clock, tc. The user cannot read or
write to the IDLE Timer T0, which is a count down timer.
MSEL Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively The Timer T0 supports the following functions:
IEDG External interrupt edge polarity select Exit out of the Idle Mode (See Idle Mode description)
(0 = Rising edge, 1 = Falling edge) Start up delay out of the HALT mode
SL1 & SL0 Select the MICROWIRE/PLUS clock divide The IDLE Timer T0 can generate an interrupt when the thir-
by (00 = 2, 01 = 4, 1x = 8) teenth bit toggles. This toggle is latched into the T0PND
pending flag, and will occur every 4.096 ms at the maximum
PSW Register (Address X'00EF) clock frequency (tc = 1 µs). A control flag T0EN allows the in-
terrupt from the thirteenth bit of Timer T0 to be enabled or
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE disabled. Setting T0EN will enable the interrupt, while reset-
Bit 7 Bit 0 ting it will disable the interrupt.
The PSW register contains the following select bits:
TIMER T1
HC Half Carry Flag
The device has a powerful timer/counter block, T1.
C Carry Flag
The timer block consists of a 16-bit timer, T1, and two sup-
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload porting 16-bit autoreload/capture registers, R1A and R1B.
RA in mode 1, T1 Underflow in Mode 2, T1A The timer block has two pins associated with it, T1A and
capture edge in mode 3) T1B. The pin T1A supports I/O required by the timer block,

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 Timers (Continued)

while the pin T1B is an input to the timer block. The powerful
and flexible timer block allows the device to easily perform all
timer functions with minimal software overhead. The timer
block has three operating modes: Processor Independent
PWM mode, External Event Counter mode, and Input Cap-
ture mode.
The control bits T1C3, T1C2, and T1C1 allow selection of the
different modes of operation.

Mode 1. Processor Independent PWM Mode

As the name suggests, this mode allows the device to gen-
erate a PWM signal with very minimal user intervention.
The user only has to define the parameters of the PWM sig-
nal (ON time and OFF time). Once begun, the timer block will DS101137-8
continuously generate the PWM signal completely indepen- FIGURE 8. Timers T1 and T0
dent of the microcontroller. The user software services the
timer block only when the PWM parameters require updat-
ing.
In this mode the timer T1 counts down at a fixed rate of tc.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, R1A and R1B. The very
first underflow of the timer causes the timer to reload from
the register R1A. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register R1B.
The T1 Timer control bits, T1C3, T1C2 and T1C1 set up the
timer for PWM mode operation.
Figure 9 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the T1A output
pin. The underflows can also be programmed to generate in-
terrupts.
DS101137-9
Underflows from the timer are alternately latched into two
pending flags, T1PNDA and T1PNDB. The user must reset FIGURE 9. Timer 1 in PWM MODE
these pending flags under software control. Two control en-
able flags, T1ENA and T1ENB, allow the interrupts from the Mode 2. External Event Counter Mode
timer underflow to be enabled or disabled. Setting the timer
This mode is quite similar to the processor independent
enable flag T1ENA will cause an interrupt when a timer un-
PWM mode described above. The main difference is that the
derflow causes the R1A register to be reloaded into the
timer, T1, is clocked by the input signal from the T1A pin. The
timer. Setting the timer enable flag T1ENB will cause an in-
T1 timer control bits, T1C3, T1C2 and T1C1 allow the timer
terrupt when a timer underflow causes the R1B register to be
to be clocked either on a positive or negative edge from the
reloaded into the timer. Resetting the timer enable flags will
T1A pin. Underflows from the timer are latched into the
disable the associated interrupts.
T1PNDA pending flag. Setting the T1ENA control flag will
Either or both of the timer underflow interrupts may be en- cause an interrupt when the timer underflows.
abled. This gives the user the flexibility of interrupting once
In this mode the input pin T1B can be used as an indepen-
per PWM period on either the rising or falling edge of the
dent positive edge sensitive interrupt input if the T1ENB con-
PWM output. Alternatively, the user may choose to interrupt
trol flag is set. The occurrence of a positive edge on the T1B
on both edges of the PWM output.
input pin is latched into the T1PNDB flag.
Figure 10 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the T1A pin is be-
ing used as the counter input clock.

Mode 3. Input Capture Mode

The device can precisely measure external frequencies or
time external events by placing the timer block, T1, in the in-
put capture mode.
In this mode, the timer T1 is constantly running at the fixed tc
rate. The two registers, R1A and R1B, act as capture regis-
ters. Each register acts in conjunction with a pin. The register
R1A acts in conjunction with the T1A pin and the register
R1B acts in conjunction with the T1B pin.

www.national.com 12
Timers (Continued) Underflows from the timer can also be programmed to gen-
erate interrupts. Underflows are latched into the timer T1C0
The timer value gets copied over into the register when a pending flag (the T1C0 control bit serves as the timer under-
trigger event occurs on its corresponding pin. Control bits, flow interrupt pending flag in the Input Capture mode). Con-
T1C3, T1C2 and T1C1, allow the trigger events to be speci- sequently, the T1C0 control bit should be reset when enter-
fied either as a positive or a negative edge. The trigger con- ing the Input Capture mode. The timer underflow interrupt is
dition for each input pin can be specified independently. enabled with the T1ENA control flag. When a T1A interrupt
The trigger conditions can also be programmed to generate occurs in the Input Capture mode, the user must check both
interrupts. The occurrence of the specified trigger condition the T1PNDA and T1C0 pending flags in order to determine
on the T1A and T1B pins will be respectively latched into the whether a T1A input capture or a timer underflow (or both)
pending flags, T1PNDA and T1PNDB. The control flag caused the interrupt.
T1ENA allows the interrupt on T1A to be either enabled or Figure 11 shows a block diagram of the timer in Input Cap-
disabled. Setting the T1ENA flag enables interrupts to be ture mode.
generated when the selected trigger condition occurs on the
T1A pin. Similarly, the flag T1ENB controls the interrupts
from the T1B pin.

DS101137-10

FIGURE 10. Timer 1 in External Event Counter Mode

DS101137-11

FIGURE 11. Timer 1 in Input Capture Mode

13 www.national.com
 Timers (Continued) T1PNDA Timer Interrupt Pending Flag
T1ENA Timer Interrupt Enable Flag
TIMER CONTROL FLAGS
1 = Timer Interrupt Enabled
The control bits and their functions are summarized below.
0 = Timer Interrupt Disabled
T1C3 Timer mode control
T1PNDB Timer Interrupt Pending Flag
T1C2 Timer mode control
T1ENB Timer Interrupt Enable Flag
T1C1 Timer mode control
1 = Timer Interrupt Enabled
T1C0 Timer Start/Stop control in Modes 1 and 2 (Pro-
0 = Timer Interrupt Disabled
cessor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)

The timer mode control bits (T1C3, T1C2 and T1C1) are detailed below:

Interrupt A Interrupt B Timer

Mode T1C3 T1C2 T1C1 Description
Source Source Counts On
1 0 1 PWM: T1A Toggle Autoreload RA Autoreload RB tC
1 1 0 0 PWM: No T1A Autoreload RA Autoreload RB
tC
Toggle
0 0 0 External Event Timer Pos. T1B Edge Pos. T1A
Counter Underflow Edge
2
0 0 1 External Event Timer Pos. T1B Edge Pos. T1A
Counter Underflow Edge
0 1 0 Captures: Pos. T1A Edge Pos. T1B Edge tC
T1A Pos. Edge or Timer
T1B Pos. Edge Underflow
1 1 0 Captures: Pos. T1A Neg. T1B tC
T1A Pos. Edge Edge or Timer Edge
T1B Neg. Edge Underflow
3
0 1 1 Captures: Neg. T1A Neg. T1B tC
T1A Neg. Edge Edge or Timer Edge
T1B Neg. Edge Underflow
1 1 1 Captures: Neg. T1A Neg. T1B tC
T1A Neg. Edge Edge or Timer Edge
T1B Neg. Edge Underflow

HIGH SPEED, CONSTANT RESOLUTION PSCAL + 1, so the maximum PWM clock frequency = CKI
PWM TIMER and the minimum PWM clock frequency = CKI/256. The pro-
The device has one processor independent PWM timer. The cessor is able to modify the PSCAL register regardless of
PWM timer operates in two modes: PWM mode and capture whether the counter is running or not and the change in fre-
mode. In PWM mode the timer outputs can be programmed quency occurs with the next underflow of the prescaler (CK-
to two pins PWM0 and PWM1. In capture mode, pin PWM0 PWM).
functions as the capture input. Figure 12 shows a block dia-
gram for this timer in capture mode and Figure 13 shows a PWM On-time Register (RLON)(Address X’00A1)
block diagram for the timer in PWM mode. RLON is a read/write register. In PWM mode the timer output
will be a “1” for RLON counts out of a total cycle of 255 PWM
PWM Timer Registers clocks. In capture mode it is used to program the threshold
The PWM Timer has three registers: PWMCON, the PWM frequency.
control register, RLON, the PWM on-time register and The PWM timer is specially designed to have a resolution of
PSCAL, the prescaler register. 255 PWM clocks. This allows the duty cycle of the PWM out-
put to be selected between 1/255 and 254/255. A value of 0
PWM Prescaler Register (PSCAL)(Address X’00A0) in the RLON register will result in the PWM output being con-
The prescaler is the clock source for the counter in both tinuously low and a value of 255 will result in the PWM output
PWM mode and in frequency monitor mode. being continuously high.
Note: The effect of changing the RLON register during active PWM mode op-
PSCAL is a read/write register that can be used to program
eration is delayed until the boundary of a PWM cycle. In capture mode
the prescaler. The clock source to the timer in both PWM and the effect takes place immediately.
capture modes can be programmed to CKI/N where N =

www.national.com 14
Timers (Continued)

DS101137-12

FIGURE 12. PWM Timer Capture Mode Block Diagram

DS101137-13

FIGURE 13. PWM Timer PWM Mode Block Diagram

PWM Control Register (PWMCON)(Address X’00A2) PWEN1 Enable PWM1 output function on I/O port.
Note: The associated bits in the configuration and data register of the I/O-
Reserved ESEL PWPND PWIE PWMD PWON PWEN1 PWEN0
port have to be setup as outputs and/or inputs in addition to setting the
Bit 7 Bit 0 PWEN bits.
The PWMCON Register Bits are: PWEN0 Enable PWM0 output/input function on I/O port.
Reserved This bit is reserved and should be zero.
PWM Mode
ESEL Edge select bit, “1” for falling edge, “0” for rising
edge. The PWM timer can generate PWM signals at frequencies
up to 39 kHz (@ tc = 1 µs) with a resolution of 255 parts.
PWPND PWM interrupt pending bit.
Lower PWM frequencies can be programmed via the pres-
PWIE PWM interrupt enable bit. caler.
PWMD PWM Mode bit, “1” for PWM mode, “0” for fre- If the PWM mode bit (PWMD) in the PWM configuration reg-
quency monitor mode. ister (PWMCON) is set to “1” the timer operates in PWM
PWON PWM start Bit, “1” to start timer, “0” to stop timer. mode. In this mode, the timer generates a PWM signal with

15 www.national.com
 Timers (Continued) When the timer overflows, the PWM pending flag (PWPND)
is set to “1”. If the PWM interrupt enable bit (PWIE) is also
a fixed, non-programmable repetition rate of 255 PWM clock set to “1”, timer overflow will generate an interrupt. The
cycles. The timer is clocked by the output of an 8-bit, pro- PWPND bit remains set until the user’s software writes a “0”
grammable prescaler, which is clocked with the chip’s CKI to it. If the software writes a “1” to the PWPND bit, this has no
frequency. Thus the PWM signal frequency can be calcu- effect. If the software writes a “0” to the PWPND bit at the
lated with the formula: same time as the hardware writes to the bit, the hardware
has precedence.
Note: The software controlling the duty cycle is able to change the PWM duty
cycle without having to wait for the timer overflow.

Selecting the PWM mode by setting PWMD to “1”, but not Figure 14 shows how the PWM output is implemented. The
yet starting the timer (PWON is “0”), will set the timer output PWM Timer output is set to “1” on an overflow of the timer
to “1”. and set to “0” when the timer is greater than RLON. The out-
put can be multiplexed to two pins.
The contents of an 8-bit register, RLON, multiplied by the
clock cycle of the prescaler output defines the time between Capture Mode
overflow (or starting) and the falling edge of the PWM output.
If the PWM mode bit (PWMD) is set to “0” the PWM Timer
Once the timer is started, the timer output goes low after operates in capture mode. Capture mode allows the pro-
RLON cycles and high after a total of 255 cycles. The proce- grammer to test whether the frequency of an external source
dure is continually repeated. In PWM mode the timer is avail- exceeds a certain threshold.
able at pins PWM0 and/or PWM1, provided the port configu-
If PWMD is “0” and PWON is “0”, the timer output is set to
ration bits for those pins are defined as outputs and the
“0”. In capture mode the timer output is available at pin
PWEN0 and/or PWEN1 bits in the PWMCON register are
PWM1, provided the port configuration register bit for that
set.
pin is set up as an output and the PWEN1 bit in the
The PWM timer is started by the software setting the PWON PWMCON register is set. Setting PWON to “1” will initialize
bit to “1”. Starting the timer initializes the timer register. From the timer register and start the counter. A rising edge, or if se-
this point, the timer will continually generate the PWM signal, lected, a falling edge, on the FMONIN input pin will initialize
independent of any processor activity, until the timer is the timer register and clear the timer output. The counter
stopped by software setting the PWON bit to “0”. The pro- continues to count up after being initialized. The ESEL bit de-
cessor is able to modify the RLON register regardless of termines whether the active edge is a rising or a falling edge.
whether the timer is running. If RLON is changed while the
timer is running, the previous value of RLON is used for com-
parison until the next overflow occurs, when the new value of
RLON is latched into the comparator inputs.

DS101137-14

FIGURE 14. PWM Mode Operation

If, in capture mode PWM0 is configured incorrectly as an than the value in RLON. However, if the frequency of the in-
output and is enabled via the PWEN0 bit, the timer output put edges is too low, the free-running counter value will
will feedback into the PWM block as the timer input. count up beyond the value in RLON.
The contents of the counter are continually compared with When the counter is greater than RLON, the PWM timer out-
the RLON register. If the frequency of the input edges is suf- put is set to “1”. It is set to “0” by a detected edge on the timer
ficiently high, the contents of the counter will always be less input or when the counter overflows. When the counter be-

www.national.com 16
Timers (Continued) comes less than the current timer value, PWPND will be
set.
comes greater than RLON, the PWPND bit in the PWM con- The PWPND bit remains set until the user’s software writes
trol register is set to “1”. If the PWIE bit is also set to “1”, the a “0” to it. If the software writes a “1” to the PWPND bit, this
PWPND bit is enabled to request an interrupt. has no effect. If the software writes a “0” to the PWPND bit at
It should be noted that two other conditions could also set the same time as the hardware writes to the bit, the hard-
the PWPND bit: ware has precedence. (See Figure 17 for Frequency Monitor
1. If the mode of operation is changed on the fly the timer Mode Operation.)
output will toggle. If frequency monitor mode is entered Note: If the clock to the device stops while PWM0 is high,
on the fly such that the timer output changes from 0 to 1, and a subsequent Reset occurs while the clock is stopped,
PWPND will be set. the PWM0/L6 output will be put in the weak pull-up mode un-
2. If the timer is operating in frequency monitor mode and til the clock resumes.
the RLON value is changed on the fly so that RLON be-

DS101137-15

FIGURE 15. Frequency Monitor Mode Operation

Power Save Modes running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full ampli-
The device offers the user two power save modes of opera- tude and frequency stability. The IDLE timer is used to gen-
tion: HALT and IDLE. In the HALT mode, all microcontroller erate a fixed delay to ensure that the oscillator has indeed
activities are stopped. In the IDLE mode, the on-board oscil- stabilized before allowing instruction execution. In this case,
lator circuitry and timer T0 are active but all other microcon- upon detecting a valid Wake Up signal, only the oscillator cir-
troller activities are stopped. In either mode, all on-board cuitry is enabled. The IDLE timer is loaded with a value of
RAM, registers, I/O states, and timers (with the exception of 256 and is clocked with the tc instruction cycle clock. The tc
T0) are unaltered. clock is derived by dividing the oscillator clock down by a fac-
tor of 10. The Schmitt trigger following the CKI inverter on
HALT MODE the chip ensures that the IDLE timer is clocked only when the
The contents of all PWM Timer registers are frozen during oscillator has a sufficiently large amplitude to meet the
HALT mode and are left unchanged when exiting HALT Schmitt trigger specifications. This Schmitt trigger is not part
mode. The PWM timer resumes its previous mode of opera- of the oscillator closed loop. The start-up time-out from the
tion when exiting HALT mode. IDLE timer enables the clock signals to be routed to the rest
The device is placed in the HALT mode by writing a “1” to the of the chip.
HALT flag (G7 data bit). All microcontroller activities, includ- The device has two mask options associated with the HALT
ing the clock, and timers, are stopped. In the HALT mode, mode. The first mask option enables the HALT mode feature,
the power requirements of the device are minimal and the while the second mask option disables the HALT mode. With
applied voltage (VCC) may be decreased to Vr (Vr = 2.0V) the HALT mode enable mask option, the device will enter
without altering the state of the machine. and exit the HALT mode as described above. With the HALT
The device supports two different ways of exiting the HALT disable mask option, the device cannot be placed in the
mode. The first method of exiting the HALT mode is with the HALT mode (writing a “1” to the HALT flag will have no ef-
Multi-Input Wake Up feature on the L port. The second fect).
method of exiting the HALT mode is by pulling the RESET
pin low. IDLE MODE
Since a crystal or ceramic resonator may be selected as the The device is placed in the IDLE mode by writing a “1” to the
oscillator, the Wake Up signal is not allowed to start the chip IDLE flag (G6 data bit). In this mode, all activities, except the
associated on-board oscillator circuitry, and the IDLE Timer

17 www.national.com
 Power Save Modes (Continued) high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an
T0, are stopped. The power supply requirements of the mi- 8-bit control register with a bit assigned to each L Port pin.
crocontroller in this mode of operation are typically around Setting the control bit will select the trigger condition to be a
30% of normal power requirement of the microcontroller. negative edge on that particular L Port pin. Resetting the bit
As with the HALT mode, the device can be returned to nor- selects the trigger condition to be a positive edge. Changing
mal operation with a reset, or with a Multi-Input Wake Up an edge select entails several steps in order to avoid a
from the L Port or CAN Interface. Alternately, the microcon- pseudo Wake Up condition as a result of the edge change.
troller resumes normal operation from the IDLE mode when First, the associated WKEN bit should be reset, followed by
the thirteenth bit (representing 4.096 ms at internal clock fre- the edge select change in WKEDG. Next, the associated
quency of 1 MHz, tc = 1 µs) of the IDLE Timer toggles. WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.
This toggle condition of the thirteenth bit of the IDLE Timer
T0 is latched into the T0PND pending flag. An example may serve to clarify this procedure. Suppose we
wish to change the edge select from positive (low going high)
The user has the option of being interrupted with a transition
to negative (high going low) for L Port bit 5, where bit 5 has
on the thirteenth bit of the IDLE Timer T0. The interrupt can
previously been enabled for an input interrupt. The program
be enabled or disabled via the T0EN control bit. Setting the
would be as follows:
T0EN flag enables the interrupt and vice versa.
RBIT 5, WKEN ; Disable MIWU
The user can enter the IDLE mode with the Timer T0 inter-
SBIT 5, WKEDG ; Change edge polarity
rupt enabled. In this case, when the T0PND bit gets set, the
RBIT 5, WKPND ; Reset pending flag
device will first execute the Timer T0 interrupt service routine
SBIT 5, WKEN ; Enable MIWU
and then return to the instruction following the “Enter Idle
Mode” instruction. If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wake Up/Interrupt, a
Alternatively, the user can enter the IDLE mode with the
safety procedure should also be followed to avoid inherited
IDLE Timer T0 interrupt disabled. In this case, the device will
pseudo wake up conditions. After the selected L port bits
resume normal operation with the instruction immediately
have been changed from output to input but before the asso-
following the “Enter IDLE Mode” instruction.
ciated WKEN bits are enabled, the associated edge select
Note: It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions. These NOP instructions
bits in WKEDG should be set or reset for the desired edge
are necessary to allow clock resynchronization following the HALT or selects, followed by the associated WKPND bits being
IDLE modes. cleared.
This same procedure should be used following reset, since
Multi-Input Wake Up the L port inputs are left floating as a result of reset. The oc-
The Multi-Input Wake Up feature is used to return (wake up) currence of the selected trigger condition for Multi-Input
the device from either the HALT or IDLE modes. Alternately, Wake Up is latched into a pending register called WKPND.
the Multi-Input Wake Up/Interrupt feature may also be used The respective bits of the WKPND register will be set on the
to generate up to 7 edge selectable external interrupts. occurrence of the selected trigger edge on the correspond-
ing Port L pin. The user has the responsibility of clearing
Figure 18 shows the Multi-Input Wake Up logic for the micro- these pending flags. Since WKPND is a pending register for
controller. The Multi-Input Wake Up feature utilizes the L the occurrence of selected wake up conditions, the device
Port. The user selects which particular L port bit (or combina- will not enter the HALT mode if any Wake Up bit is both en-
tion of L Port bits) will cause the device to exit the HALT or abled and pending. Consequently, the user has the respon-
IDLE modes. The selection is done through the Reg: WKEN. sibility of clearing the pending flags before attempting to en-
The Reg: WKEN is an 8-bit read/write register, which con- ter the HALT mode.
tains a control bit for every L port bit. Setting a particular
WKEN bit enables a Wake Up from the associated port pin. The WKEN, WKPND and WKEDG are all read/write regis-
ters, and are cleared at reset.
The user can select whether the trigger condition on the se-
lected L Port pin is going to be either a positive edge (low to

www.national.com 18
Multi-Input Wake Up (Continued)

DS101137-16

FIGURE 16. Multi-Input Wake Up Logic

CAN RECEIVE WAKE UP nite start up time. The IDLE Timer (T0) generates a fixed de-
The CAN Receive Wake Up source is always enabled and is lay to ensure that the oscillator has indeed stabilized before
always active on a falling edge of the CAN comparator out- allowing the device to execute instructions. In this case,
put. There is no specific enable bit for the CAN Wake Up fea- upon detecting a valid Wake Up signal, only the oscillator cir-
ture. Although the wake up feature on pins L0..L6 can be cuitry and the IDLE Timer T0 are enabled. The IDLE Timer is
programmed to generate an interrupt (L-port interrupt), no in- loaded with a value of 256 and is clocked from the tc instruc-
terrupt is generated upon a CAN receive wake up condition. tion cycle clock. The tc clock is derived by dividing down the
The CAN block has its own, dedicated receiver interrupt oscillator clock by a factor of 10. A Schmitt trigger following
upon receive buffer full. the CKI on-chip inverter ensures that the IDLE timer is
clocked only when the oscillator has a sufficiently large am-
PORT L INTERRUPTS plitude to meet the Schmitt trigger specifications. This
Schmitt trigger is not part of the oscillator closed loop. The
Port L provides the user with an additional seven fully select-
start-up time-out from the IDLE timer enables the clock sig-
able, edge sensitive interrupts which are all vectored into the
nals to be routed to the rest of the chip.
same service subroutine.
The interrupt from Port L shares logic with the wake up cir-
cuitry. The register WKEN allows interrupts from Port L to be CAN Block Description *
individually enabled or disabled. The register WKEDG speci- This device contains a CAN serial bus interface as described
fies the trigger condition to be either a positive or a negative in the CAN Specification Rev. 2.0 part B.
edge. Finally, the register WKPND latches in the pending *Patents Pending.
trigger conditions.
The GIE (global interrupt enable) bit enables the interrupt CAN Interface Block
function. A control flag, LPEN, functions as a global interrupt
enable for Port L interrupts. Setting the LPEN flag will enable This device supports applications which require a low speed
interrupts and vice versa. A separate global pending flag is CAN interface. It is designed to be programmed with two
not needed since the register WKPND is adequate. transmit and two receive registers. The user’s program may
check the status bytes in order to get information of the bus
Since Port L is also used for waking the device out of the state and the received or transmitted messages. The device
HALT or IDLE modes, the user can elect to exit the HALT or has the capability to generate an interrupt as soon as one
IDLE modes either with or without the interrupt enabled. If he byte has been transmitted or received. Care must be taken if
elects to disable the interrupt, then the device will restart ex- more than two bytes in a message frame are to be
ecution from the instruction immediately following the in- transmitted/received. In this case the user’s program must
struction that placed the microcontroller in the HALT or IDLE poll the transmit buffer empty (TBE)/receive buffer full (RBF)
modes. In the other case, the device will first execute the in- bits or enable their respective interrupts and perform a data
terrupt service routine and then revert to normal operation. exchange between the user data and the Tx/Rx registers.
The Wake Up signal will not start the chip running immedi-
ately since crystal oscillators or ceramic resonators have a fi-

19 www.national.com
 CAN Interface Block (Continued) ware overhead. The device can support a bus speed of up to
1 Mbit/s with a 10 MHz oscillator and 2 byte messages. The
Fully automatic transmission on error is supported for mes- 1 Mbit/s bus speed refers to the rate at which protocol and
sages not longer than two bytes. Messages which are longer data bits are transferred on the bus. Longer messages re-
than two bytes have to be processed by software. quire slower bus speeds due to the time required for soft-
The interface is compatible with CAN Specification 2.0 part ware intervention between data bytes. The device will sup-
B, without the capability to receive/transmit extended port a maximum of 125k bit/s with eight byte messages and
frames. Extended frames on the bus are checked and ac- a 10 MHz oscillator.
knowledged according to the CAN specification.
The maximum bus speed achievable with the CAN interface
is a function of crystal frequency, message length and soft-

DS101137-49

FIGURE 17. CAN Interface Block Diagram

Functional Block Description of Bit Stream Processor (BSP)

The BSP is a sequencer controlling the data stream between
the CAN Interface The Interface Management Logic (parallel data) and the bus
line (serial data). It controls the transceive logic with regard
Interface Management Logic (IML) to reception and arbitration, and creates error signals ac-
The IML executes the CPU’s transmission and reception cording to the bus specification
commands and controls the data transfer between CPU,
Rx/Tx and CAN registers. It provides the CAN Interface with
Rx/Tx data from the memory mapped Register Block. It also
sets and resets the CAN status information and generates
interrupts to the CPU.

www.national.com 20
Functional Block Description of Where divider is the value of the clock prescaler, PS is the
programmable value of phase segment 1 and 2 (1..8) and
the CAN Interface (Continued) PPS the programmed value of the propagation segment
(1..8) (located in CTIM).
Transceive Logic (TCL)
The TCL is a state machine which incorporates the bit stuff Bus Timing Considerations
logic and controls the output drivers, CRC logic and the
The internal architecture of the CAN interface has been op-
Rx/Tx shift registers. It also controls the synchronization to
timized to allow fast software response times within mes-
the bus with the CAN clock signal generated by the BTL.
sages of more than two data bytes. The TBE (Transmit
Buffer Empty) bit is set on the last bit of odd data bytes when
Error Management Logic (EML)
CAN internal sample points are high.
The EML is responsible for the fault confinement of the CAN
It is the user’s responsibility to ensure that the time between
protocol. It is also responsible for changing the error
setting TBE and a reload of TxD2 is longer than the length of
counters, setting the appropriate error flag bits and interrupts
phase segment 2 as indicated in the following equation:
and changing the error status (passive, active and bus off).

Cyclic Redundancy Check (CRC) Generator and

Register
The CRC Generator consists of a 15-bit shift register and the Table 2 shows examples of the minimum required tLOAD for
logic required to generate the checksum of the destuffed bit- different CSCAL settings based on a clock frequency of
stream. It informs the EML about the result of a receiver 10 MHz. Lower clock speeds require recalculation of the
checksum. CAN bit rate and the mimimum tLOAD.
The checksum is generated by the polynomial:
χ15 + χ14 + χ10 + χ8 + χ7 + χ4 + χ3 + 1 TABLE 2. CAN Timing (CKI = 10 MHz tc = 1 µs)
Minimum
Receive/Transmit (Rx/Tx) Registers PS CSCAL CAN Bit Rate (kbit/s)
tLOAD (µs)
The Rx/Tx registers are 8-bit shift registers controlled by the
TCL and the BSP. They are loaded or read by the Interface 4 3 250 2.0
Management Logic, which holds the data to be transmitted 4 9 100 5.0
or the data that was received. 4 15 62 8.0
Bit Time Logic (BTL) 4 24 40 12.5
The bit time logic divider divides the CKI input clock by the 4 39 25 20
value defined in the CAN prescaler (CSCAL) and bus timing 4 99 10 50
register (CTIM). The resultig bit time (tcan) can be computed 4 199 5 100
by the formula:

DS101137-50

FIGURE 18. Bit Rate Generation

Figure 19 illustrates the minimum time required for tLOAD.

DS101137-51

FIGURE 19. TBE Timing

21 www.national.com
 Functional Block Description of the CAN Interface (Continued)

In the case of an interrupt driven CAN interface, the calculation of the actual tLOAD time would be done as follows:
INT: ; Interrupt latency = 7t<inf>c<reset> = 7 µs
PUSH A ; 3t<inf>c<reset> = 3 µs
LD A,AB ; 2t<inf>c<reset> = 2 µs
PUSH A ; 3t<inf>c<reset> = 3 µs
VIS ; 5t<inf>c<reset> = 5 µs
CANTX: ; 20t<inf>c<reset> = µs to this point
. ; additional time for instructions which check
. ; status prior to reloading the transmit data
. ; registers with subsequent data bytes.
LD TXD2,DATA
.
.
.
Interrupt driven programs use more time than programs TDLC3..TDLC0 Transmit Data Length Code
which poll the TBE flag, however programs which operate at These bits determine the number of data bytes to be trans-
lower baud rates (which are more likely to be sensitive to this mitted within a frame. The CAN specification allows a maxi-
issue) have more time for interrupt response. mum of eight data bytes in any message.

Output Drivers/Input Comparators TRANSMIT IDENTIFIER HIGH (TID) (Address X’00B3)

The output drivers/input comparators are the physical inter-
TRTR TID10 TID9 TID8 TID7 TID6 TID5 TID4
face to the bus. Control bits are provided to TRI-STATE the
output drivers. Bit 7 Bit 0

A dominant bit on the bus is represented as a “0” in the data This register is read/write.
registers and a recessive bit on the bus is represented as a TRTR Transmit Remote Frame Request
“1” in the data registers. This bit is set if the frame to be transmitted is a remote frame
request.
TABLE 3. Bus Level Definition TID10..TID4 Transmit Identifier Bits 10 .. 4 (higher 7 bits)
Bus Level Pin Tx0 Pin Tx1 Data Bits TID10..TID4 are the upper 7 bits of the 11 bit transmit
identifier.
drive low drive high
“dominant” 0
(GND) (VCC) RECEIVER DATA REGISTER 1 (RXD1) (Address
“recessive” TRI-STATE TRI-STATE 1 X’00B4)
The Receive Data Register 1 (RXD1) contains the first data
Register Block byte received in a frame and then successive odd byte num-
The register block consists of fifteen 8-bit registers which are bers (i.e., bytes 1, 3,..7). This register is read-only.
described in more detail in the following paragraphs.
RECEIVE DATA REGISTER 2 (RXD2) (Address X’00B5)
Note: The contents of the receiver related registers RxD1, RxD2, RDLC,
RIDH and RTSTAT are only changed if a received frame passes the The Receive Data Register 2 (RXD2) contains the second
acceptance filter or the Receive Identifier Acceptance Filter bit (RIAF) data byte received in a frame and then successive even byte
is set to accept all received messages.
numbers (i.e., bytes 2,4,..,8). This register is read-only.
TRANSMIT DATA REGISTER 1 (TXD1) (Address REGISTER DATA LENGTH CODE AND IDENTIFIERLOW
X’00B0) REGISTER (RIDL) (Address X’00B6)
The Transmit Data Register 1 contains the first data byte to
be transmitted within a frame and then the successive odd RID3 RID2 RID1 RID0 RDLC3 RDLC2 RDLC1 RDLC0
byte numbers (i.e., bytes number 1,3,..,7). Bit 7 Bit 0
This register is read only.
TRANSMIT DATA REGISTER 2 (TXD2)(Address X’00B1)
RID3..RID0 Receive Identifier bits (lower four bits)
The Transit Data Register 2 contains the second data byte to
The RID3..RID0 bits are the lower four bits of the eleven bit
be transmitted within a frame and then the successive even
long Receive Identifier. Any received message that matches
byte numbers (i.e., bytes number 2,4,..,8).
the upper 7 bits of the Receive Identifier (RID10..RID4) is ac-
cepted if the Receive Identifier Acceptance Filter (RIAF) bit is
TRANSMIT DATA LENGTH CODE AND IDENTIFIER
set to zero.
LOW REGISTER (TDLC) (Address X’00B2)
RDLC3..RDLC0 Receive Data Length Code bits
TID3 TID2 TID1 TID0 TDLC3 TDLC2 TDLC1 TDLC0
The RDLC3..RDLC0 bits determine the number of data
Bit 7 Bit 0 bytes within a received frame.
This register is read/write.
TID3..TIDO Transmit Identifier Bits 3..0 (lower 4 bits) RECEIVE IDENTIFIER HIGH (RID) (Address X’00B7)
The transmit identifier is composed of eleven bits in total, bits Reserved RID10 RID9 RID8 RID7 RID6 RID5 RID4
3 to 0 of the TID are stored in bits 7 to 4 of this register. Bit 7 Bit 0

www.national.com 22
Functional Block Description of Note: (BTL settings at high speed; PSC = 0) Due to the on-chip delay from
the rx-pins through the receive comparator (worst case assumption: 3
the CAN Interface (Continued) clocks delay * 2 (devices on the bus) + 1 tx delay) the user needs to set
the sample point to (2*3 + 1) i.e., 7 CKI clocks to ensure correct com-
This register is read/write. munication on the bus under all circumstances. With prescaler settings
of 0 this is a given (i.e., no caution has to be applied).
Reserved Bit 7 is reserved and must be zero. Example: for 1 Mbit CTIM = b’10000100 (PSS = 5; PS1 = 2). Example
RID10..RID4 Receive Identifier bits (upper bits) for 500 kbit CTIM = b’01011100 (PPS = 3; PS1 = 8). − all at 10 MHz
CKI and CSCAL = 0.
The RID10...RID4 bits are the upper 7 bits of the eleven bit
long Receive Identifier. If the Receive Identifier Acceptance
CAN BUS CONTROL REGISTER (CBUS) (00BA)
Filter (RIAF) bit (see CBUS register) is set to zero, bits 4 to
10 of the received identifier are compared with the mask bits Re- RIAF TxEN1 TxEN0 RxREF1 RxREF0 Re- FMOD
of RID4..RID10. If the corresponding bits match, the mes- served served
sage is accepted. If the RIAF bit is set to a one, the filter Bit 7 Bit 0
function is disabled and all messages, independent of iden- Reserved This bit is reserved and must be zero.
tifier, will be accepted.
RIAF Receive identifier acceptance filter bit
CAN PRESCALER REGISTER (CSCAL) (Address If the RIAF bit is set to zero, bits 4 to 10 of the received iden-
X’00B8) tifier are compared with the mask bits of RID4..RID10 and if
the corresponding bits match, the message is accepted. If
CKS7 CKS6 CKS5 CKS4 CKS3 CKS2 CKS1 CKS0
the RIAF bit is set to a one, the filter function is disabled and
Bit 7 Bit 0
all messages independent of the identifier will be accepted.
This register is read/write. TxEN0, TxEN1 TxD Output Driver Enable
CKS7..0 Prescaler divider select.
The resulting clock value is the CAN Prescaler clock. TABLE 5. Output Drivers
CAN BUS TIMING REGISTER (CTIM) (00B9) TxEN1 TxEN0 Output
PPS2 PPS1 PPS0 PS2 PS1 PS0 Reserved Reserved 0 0 Tx0, Tx1 TRI-STATE, CAN
Bit 7 Bit 0 input comparator disabled
This register is read/write. 0 1 Tx0 enabled
PPS2..PPS0 Propagation Segment, bits 2..0 1 0 Tx1 enabled
The PPS2..PPS0 bits determine the length of the propaga- 1 1 Tx0 and Tx1 enabled
tion delay in Prescaler clock cycles (PSC) per bit time. (For Bus synchronization of the device is done in the following
a more detailed discussion of propagation delay and phase way:
segments, see SYNCHRONIZATION.)
If the output was disabled (TxEN1, TxEN0 = “0”) and either
PS2..PS0 Phase Segment 1, bits 2..0 TxEN1 or TxEN0, or both are set to 1, the device will not start
The PS2..PS0 bits fix the number of Prescaler clock cycles transmission or reception of a frame until eleven consecutive
per bit time for phase segment 1 and phase segment 2. The “recessive” bits have been received. Resetting the TxEN1
PS2..PS0 bits also set the synchronization Jump Width to a and TxEN0 bits will disable the output drivers and the CAN
value equal to the lesser of: 4 PSC, or the length of PS1/2 input comparator. All other CAN related registers and flags
(Min: 4 l length of PS1/2). will be unaffected. It is recommended that the user reset the
TxEN1 and TxEN0 bits before switching the device into the
TABLE 4. Synchronization Jump Width HALT mode (the CAN receive wakeup will still work) in order
to reduce current consumption and to assure a proper resy-
Length of Synchronization chronization to the bus after exiting the HALT mode.
PS2 PS1 PS0 Phase Jump Width Note: A “bus off” condition will also cause Tx0 and Tx1 to be at TRI-STATE
(independent of the values of the TxEN1 and TxEN0 bits).
Segment 1⁄2
RXREF1 Reference voltage applied to Rx1 if bit is set
0 0 0 1 tcan 1 tcan
RXREF0 Reference voltage applied to Rx0 if bit is set
0 0 1 2 tcan 2 tcan
FMOD Fault Confinement Mode select
0 1 0 3 tcan 3 tcan Setting the FMOD bit to “0” (default after power on reset) will
0 1 1 4 tcan 4 tcan select the Standard Fault Confinement mode. In this mode
1 0 0 5 tcan 4 tcan the device goes from “bus off” to “error active” after monitor-
ing 128*11 recessive bits (including bus idle) on the bus. This
1 0 1 6 tcan 4 tcan
mode has been implemented for compatibility with existing
1 1 0 7 tcan 4 tcan solutions. Setting the FMOD bit to “1” will select the En-
1 1 1 8 tcan 4 tcan hanced Fault Confinement mode. In this mode the device
LENGTH OF TIME SEGMENTS (See Figure 31) goes from “bus off” to “error active” after monitoring 128
“good” messages, as indicated by the reception of 11 con-
• The Synchronization Segment is 1 CAN Prescaler clock secutive “recessive” bits including the End of Frame,
(PSC)
whereas the standard mode may time out after 128 x 11 re-
• The Propagation Segment can be programmed (PPS) to cessive bits (e.g., bus idle).
be 1,2...,8 PSC in length.
• Phase Segment 1 and Phase Segment 2 are program-
mable (PS) to be 1,2,..,8 PSC long.

23 www.national.com
 Functional Block Description of sion. If the device has already started transmission (won ar-
bitration) the TXPND and TXSS flags will stay set until the
the CAN Interface (Continued) transmission is completed, even if the user’s software has
written zero to the TXSS bit. If one or more data bytes are to
TRANSMIT CONTROL/STATUS (TCNTL) (00BB)
be transmitted, care must be taken by the user, that the
NS1 NS0 TERR RERR CEIE TIE RIE TXSS Transmit Data Register(s) have been loaded before the
Bit 7 Bit 0 TXSS bit is set. TXSS will be cleared on three conditions
only: Successful completion of a transmitted message; suc-
NS1..NS0 Node Status, i.e., Error Status.
cessful cancellation of a pending transmision; Transition of
the CAN interface to the bus-off state.
TABLE 6. Node Status
NS1 NS0 Output
0 0 Error active
0 1 Error passive
1 0 Bus off
1 1 Bus off
The Node Status bits are read only.
TERR Transmit Error
DS101137-52
This bit is automatically set when an error occurs during the
transmission of a frame. TERR can be programmed to gen- FIGURE 20. Acceptance Filter Block-Diagram
erate an interrupt by setting the Can Error Interrupt Enable
bit (CEIE). This bit must be cleared by the user’s software. Writing a zero to the TXSS bit will request cancellation of a
Note: This is used for messages for more than two bytes. If an error occurs
pending transmission but TXSS will not be cleared until
during the transmission of a frame with more than 2 data bytes, the us- completion of the operation. If an error occurs during trans-
er’s software has to handle the correct reloading of the data bytes to mission of a frame, the logic will check for cancellation re-
the TxD registers for retransmission of the frame. For frames with 2 or quests prior to restarting transmission. If zero has been writ-
fewer data bytes the interface logic of this chip does an automatic re- ten to TXSS, retransmission will be canceled.
transmission. Regardless of the number of data bytes, the user’s soft-
ware must reset this bit if CEIE is enabled. Otherwise a new interrupt
will be generated immediately after return from the interrupt service RECEIVE/TRANSMIT STATUS (RTSTAT) (Address
routine. X’00BC)
RERR Receiver Error TBE TXPND RRTR ROLD RORN RFV RCV RBF
This bit is automatically set when an error occurred during 1 0 0 0 0 0 0 0
the reception of a frame. RERR can be programmed to gen-
Bit 7 Bit 0
erate an interrupt by setting the Can Error Interrupt Enable
bit (CEIE). This bit has to be cleared by the user’s software. This register is read only.
CEIE CAN Error Interrupt Enable TBE Transmit Buffer Empty
If set by the user’s software, this bit enables the transmit and This bit is set as soon as the TxD2 register is copied into the
receive error interrupts. The interrupt pending flags are Rx/Tx shift register, i.e., the 1st data byte of each pair has
TERR and RERR. Resetting this bit with a pending error in- been transmitted. The TBE bit is automatically reset if the
terrupt will inhibit the interrupt, but will not clear the cause of TxD2 register is written (the user should write a dummy byte
the interrupt (RERR or TERR). If the bit is then set without to the TxD2 register when transmitting an odd number of
clearing the cause of the interrupt, the interrupt will reoccur. bytes of zero bytes). TBE can be programmed to generate
an interrupt by setting the Transmit Interrupt Enable bit (TIE).
TIE Transmit Interrupt Enable
When servicing the interrupt the user has to make sure that
If set by the user’s software, this bit enables the transmit in- TBE gets cleared by executing a WRITE instruction on the
terrupt. (See TBE and TXPND.) Resetting this bit with a TxD2 register, otherwise a new interrupt will be generated
pending transmit interrupt will inhibit the interrupt, but will not immediately after return from the interrupt service routine.
clear the cause of the interrupt. If the bit is then set without The TBE bit is read only. It is set to 1 upon reset. TBE is also
clearing the cause of the interrupt, the interrupt will reoccur. set upon completion of transmission of a valid message.
RIE Receive Interrupt Enable TXPND Transmission Pending
If set by the user’s software, this bit enables the receive in- This bit is set as soon as the Transmit Start/Stop (TXSS) bit
terrupt or a remote transmission request interrupt (see RBF, is set by the user. It will stay set until the frame was success-
RFV and RRTR). Resetting this bit with a pending receive in- fully transmitted, until the transmission was successfully can-
terrupt will inhibit the interrupt, but will not clear the cause of celed by writing zero to the Transmission Start/Stop bit
the interrupt. If the bit is then set without clearing the cause (TXSS), or the device enters the bus-off state. Resetting the
of the interrupt, the interrupt will reoccur. TXSS bit will only cancel a transmission if the transmission
TXSS Transmission Start/Stop of a frame hasn’t been started yet (bus idle) or if arbitration
This bit is set by the user’s software to initiate the transmis- has been lost (receiving). If the device has already started
sion of a frame. Once this bit is set, a transmission is pend- transmission (won arbitration) the TXPND flag will stay set
ing, as indicated by the TXPND flag being set. It can be reset until the transmission is completed, even if the user’s soft-
by software to cancel a pending transmission. Resetting the ware has requested cancellation of the message. If an error
TXSS bit will only cancel a transmission, if the transmission occurs during transmission, a requested cancellation may
of a frame hasn’t been started yet (bus idle), if arbitration has occur prior to the begining of retransmission.
been lost (receiving) or if an error occurs during transmis- RRTR Received Remote Transmission Request

www.national.com 24
Functional Block Description of For test purposes and to identify the node status, the trans-
mit error counter, an 8-bit error counter, is mapped into the
the CAN Interface (Continued) data memory. If the lower seven bits of the counter overflow,
i.e., TEC7 is set, the device is error passive.
This bit is set when the remote transmission request (RTR)
bit in a received frame was set. It is automatically reset CAUTION
through a read of the RXD1 register. To prevent interference with the CAN fault confinement, the
To detect RRTR the user can either poll this flag or enable user must not write to the REC/TEC registers. Both counters
the receive interrupt (the reception of a remote transmission are automatically updated following the CAN specification.
request will also cause an interrupt if the receive interrupt is
enabled). If the receive interrupt is enabled, the user should RECEIVE ERROR COUNTER (REC) (00BE)
check the RRTR flag in the service routine in order to distin- ROVL REC6 REC5 REC4 REC3 REC2 REC1 REC0
guish between a RRTR interrupt and a RBF interrupt. It is the
Bit 7 Bit 0
responsibility of the user to clear this bit by reading the RXD1
register, before the next frame is received. This register is read/write.
ROLD Received Overload Frame ROVL receive error counter overflow
This bit is automatically set when an Overload Frame was For test purposes and to identify the node status the receive
received on the bus. It is automatically reset through a read error counter, a 7-bit error counter, is mapped into the data
of the Receive/Transmit Status register. It is the responsibil- memory. If the counter overflows the ROVL bit is set to indi-
ity of the user to clear this bit by reading the Receive/ cate that the device is error passive and won’t transmit any
Transmit Status register, before the next frame is received. active error frames. If ROVL is set then the counter is frozen.
RORN Receiver Overrun
MESSAGE IDENTIFICATION
This bit is automatically set on an overrun of the receive data
a. Transmitted Message
register, i.e., if the user’s program does not maintain the
RxDn registers when receiving a frame. It it automatically re- The user can select all 11 Transmit Identifier Bits to transmit
set through a read of the Receive/Transmit Status register. It any message whigh fulfills the CAN2.0, part B spec without
is the responsibility of the user to clear this bit by reading the an extended identifier (see note below). Fully automatic re-
Receive/Transmit Status register before the next frame is re- transmission is supported for messages no longer than 2
ceived. bytes.
RFV Received Frame Valid b. Received Messages
This bit is set if the received frame is valid, i.e., after the pen- The lower four bits of the Receive Identifier are don’t care,
ultimate bit of the End of Frame is received. It is automati- i.e., the controller will receive all messages that fit in that win-
cally reset through a read of the Receive/Transmit Status dow (16 messages). The upper 7 bits can be defined by the
register. It is the responsibility of the user to clear this bit by user in the Receive Identifier High Register to mask out
reading the receive/transmit status register (RTSTAT), be- groups of messages. If the RIAF bit is set, all messages will
fore the next frame is received. RFV will cause a Receive In- be received.
terrupt if enabled by RIE. The user should be careful to read Note: The CAN interface tolerates the extended CAN frame format of 29
identifier bits and gives an acknowledgment. If an error occurs the re-
the last data byte (RxD1) of odd length messages (1, 3, 5 or ceive error counter will be increased, and decreased if the frame is
7 data bytes) on receipt of RFV. RFV is the only indication valid.
that the last byte of the message has been received.
RCV Receive Mode BUS SYNCHRONIZATION DURING OPERATION
This bit is set after the data length code of a message that Resetting the TxEN1 and TxEN0 bits in Bus Control Register
passes the device’s acceptance filter has been received. It is will disable the output drivers and do a resynchronization to
automatically reset after the CRC-delimiter of the same the bus. All other CAN related registers and flags will be un-
frame has been received. It indicates to the user’s software affected.
that arbitration is lost and that data is coming in for that node. Bus synchronization of the device is this case is done in the
RBF Receive Buffer Full following way:
This bit is set if the second Rx data byte was received. It is If the output was disabled (TxEN1, TxEN0 = “0”) and either
reset automatically, after the RxD1-Register has been read TxEN1 or TxEN0, or both are set to 1, the device will not start
by the software. RBF can be programmed to generate an in- transmission or reception of a frame until eleven consecutive
terrupt by setting the Receive Interrupt Enable bit (RIE). “recessive” bits have been received.
When servicing the interrupt, the user has to make sure that A “bus off” condition will also cause the output drivers Tx1
RBF gets cleared by executing a LD instruction from the and Tx0 to be at TRI-STATE (independent of the status of
RxD1 register, otherwise a new interrupt will be generated TxEN1 and TxEN0). The device will switch from “bus off” to
immediately after return from the interrupt service routine. “error active” mode as described under the FMOD-bit de-
The RBF bit is read only. scription (see Can Bus Control register). This will ensure that
the device is synchronized to the bus, before starting to
TRANSMIT ERROR COUNTER (TEC) (Address X’00BD) transmit or receive.
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 For information on bus synchronization and status of the
Bit 7 Bit 0 CAN related registers after external reset refer to the RESET
section.
This register is read/write.

25 www.national.com
 Functional Block Description of SYSTEM WIDE DATA CONSISTENCY
As the CAN network is message oriented, a message can be
the CAN Interface (Continued) used like a variable which is automatically updated by the
ON-CHIP VOLTAGE REFERENCE controlling processor. If any module cannot process informa-
tion it can send an overload frame. The device is incapable
The on-chip voltage reference is a ratiometric reference. For
of initiating an overload frame, but will join a overload frame
electrical characteristics of the voltage reference refer to the
initiated by another device as required by CAN specifica-
electrical specifications section.
tions.
ANALOG SWITCHES
NON-DESTRUCTIVE CONTENTION-BASED
Analog switches are used for selecting between Rx0 and ARBITRATION
VREF and between Rx1 and VREF.
The CAN protocol allows several transmitting modules to
start a transmission at the same time as soon as they moni-
Basic CAN Concepts tor the bus to be idle. During the start of transmission every
The following paragraphs provide a generic overview of the node monitors the bus line to detect whether its message is
basic concepts of the Controller Area Network (CAN) as de- overwritten by a message with a higher priority. As soon as a
scribed in Chapter 4 of ISO/DIS11519-1. Implementation re- transmitting module detects another module with a higher
lated issues of the National Semiconductor device will be priority accessing the bus, it stops transmitting its own frame
discussed as well. and switches to receive mode. For illustration see Figure 21.
This device will process standard frame format only. Ex-
tended frame formats will be acknowledged, however the AUTOMATIC RETRANSMISSION OF FRAMES
data will be discarded. For this reason the description of If a data or remote frame is overwritten by either a higher-
frame formats in the following section will cover only the prioritized data frame, remote frame or an error frame, the
standard frame format. transmitting module will automatically retransmit it. This de-
The following section provides some more detail on how the vice will handle the automatic retransmission of up to two
device will handle received extended frames: data bytes automatically. Messages with more than 2 data
bytes require the user’s software to update the transmit reg-
If the device’s remote identifier acceptance filter bit (RIAF) is isters.
set to “1”, extended frame messages will be acknowledged.
However, the data will be discarded and the device will not ERROR DETECTION AND ERROR SIGNALING
reply to a remote transmission request received in extended
All messages on the bus are checked by each CAN node
frame format. If the device’s RIAF bit is set to “0”, the upper
and acknowledge if they are correct. If any node detects an
7 received ID bits of an extended frame that match the de-
error it starts the transmission of an error frame.
vice’s receive identifier (RID) acceptance filtler bits, are
stroed in the device’s RID register. However, the device does
Switching Off Defective Nodes
not reply to an RTR and any data is discarded. The device
will only acknowledge the message. There are two error counters, one for transmitted data and
one for received data, which are incremented, depending on
MULTI-MASTER PRIORITY BASED BUS ACCESS the error type, as soon as an error occurs. If either counter
goes beyond a specific value the node goes to an error state.
The CAN protocol is message based protocol that allows a
A valid frame causes the error counters to decrease.
total of 2032 (= 211 −16) different messages in the standard
format and 512 million (= 229 −16) different messages in the The device can be in one of three states with respect to error
extended frame format. handling:
• Error active
MULTICAST FRAME TRANSFER BY An error active unit can participate in bus communication
ACCEPTANCE FILTERING and sends an active (“dominant”) error flag.
Every CAN Frame is put on the common bus. Each module • Error passive
receives every frame and filters out the frames which are not
An error passive unit can participate in bus communica-
required for the module’s task.
tion. However, if the unit detects an error it is not allowed
REMOTE DATA REQUEST to send an active error flag. The unit sends only a passive
(“recessive”) error flag.
A CAN master module has the ability to set a specific bit
called the “remote transmission request bit” (RTR) in a • Bus off
frame. This causes another module, either another master or A unit that is “bus off” has the output drivers disabled, i.e., it
a slave, to transmit a data frame after the current frame has does not participate in any bus activity.
been completed. (See ERROR MANAGEMENT AND DETECTION for more
detailed information.)
SYSTEM FLEXIBILITY
Additional modules can be added to an existing network
without a configuration change. These modules can either
perform completely new functions requiring new data or pro-
cess existing data to perform a new function.

www.national.com 26
Frame Formats 6. ACK field
7. End of Frame (EOF)
INTRODUCTION A remote frame has no data field and is used for requesting
There are basically two different types of frames used in the data from other (remote) CAN nodes. Figure 24 shows the
CAN protocol. format of a CAN data frame.
The data transmission frames are: data/remote frame
FRAME CODING
The control frames are: error/overload frame
Remote and Data Frames are NRZ codes with bit-stuffing in
Note: This device cannot send an overload frame as a result of not being
able to process all information. However, the device is able to recog-
every bit field which holds computable information for the in-
nize an overload condition and join overload frames initiated by other terface, i.e., Start of Frame arbitration field, control field, data
devices. field (if present) and CRC field.
If no message is being transmitted, i.e., the bus is idle, the Error and overload frames are NRZ coded without bit stuff-
bus is kept at the “recessive” level. Figure 22 and Figure 23 ing.
give an overview of the various CAN frame formats.
BIT STUFFING
DATA AND REMOTE FRAME After five consecutive bits of the same value, a stuff bit of the
Data frames consist of seven bit fields and remote frames inverted value is inserted by the transmitter and deleted by
consist of six different bit fields: the receiver.
1. Start of Frame (SOF)
Destuffed Bit Stream 100000x 011111x
2. Arbitration field
Stuffed Bit Stream 1000001x 0111110x
3. Control field (IDE bit, R0 bit, and DLC field)
Note: x = {0,1}
4. Data field (not in remote frame)
5. CRC field

DS101137-53

FIGURE 21. CAN Message Arbitration

27 www.national.com
 Frame Formats (Continued)

DS101137-54

DS101137-55

A remote frame is identical to a data frame, except that the RTR bit is “recessive”, and there is no data field.
IDE = Identifier Extension Bit
The IDE bit in the standard format is transmitted “dominant”, whereas in the extended format the IDE bit is “recessive” and the id is expanded to 29 bits.
r = recessive
d = dominant
FIGURE 22. CAN Data Transmission Frames

DS101137-56

An error frame can start anywhere in the middle of a frame.

DS101137-57

INT = Intermission
Suspend Transmission is only for error passive nodes.

DS101137-58

An overload frame can only start at the end of a frame.

FIGURE 23. CAN Control Frames

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Frame Formats (Continued)

DS101137-59

FIGURE 24. CAN Frame Format

START OF FRAME (SOF) ACK FIELD
The Start of Frame indicates the beginning of data and re- The ACK field is two bits long and contains the ACK slot and
mote frames. It consists of a single “dominant” bit. A node is the ACK delimiter. The ACK slot is filled with a “recessive” bit
only allowed to start transmission when the bus is idle. All by the transmitter. This bit is overwritten with a “dominant” bit
nodes have to synchronize to the leading edge (first edge af- by every receiver that has received a correct CRC se-
ter the bus was idle) caused by SOF of the node which starts quence. The second bit of the ACK field is a “recessive” bit
transmission first. called the acknowledge delimiter. As a consequence the ac-
knowledge flag of a valid frame is surrounded by two “reces-
ARBITRATION FIELD sive” bits, the CRC-delimiter and the ACK delimiter.
The arbitration field is composed of the identifier field and the
RTR (Remote Transmission Request) bit. The value of the EOF FIELD
RTR bit is “dominant” in a data frame and “recessive” in a re- The End of Frame Field closes a data and a remote frame. It
mote frame. consists of seven “recessive” bits.

CONTROL FIELD INTERFRAME SPACE

The control field consists of six bits. It starts with two bits re- Data and remote frames are separate from every preceding
served for future expansion followed by the four-bit Data frame (data, remote, error and overload frames) by the inter-
Length Code. Receivers must accept all possible combina- frame space see Figure 25 and Figure 26 for details. Error
tions of the two reserved bits. Until the function of these re- and overload frames are not preceded by an interframe
served bits is defined, the transmitter only sends “0” (domi- space. They can be transmitted as soon as the condition oc-
nant) bits. The first reserved bit (IDE) is actually defined to curs. The interframe space consists of a minimum of three
indicate an extended frame with 29 Identifier bits if set to “1”. bit fields depending on the error state of the node.
CAN chips must tolerate extended frames, even if they can These bit fields are coded as follows:
only understand standard frames, to prevent the destruction
The intermission has the fixed form of three “recessive” bits.
of an extended frames on an existing network.
While this bit field is active, no node is allowed to start a
The Data Length Code indicates the number of bytes in the transmission of a data or a remote frame. The only action to
data field. This Data Length Code consists of four bits. The be taken is signaling an overload condition. This means that
data field can be of length zero. The permissible number of an error in this bit field would be interpreted as an overload
data bytes for a data frame ranges from 0 to 8. condition. Suspend transmission has to be inserted by error-
passive nodes that were transmitter for the last message.
DATA FIELD This bit field has the form of eight “recessive” bits. However,
The Data field consists of the data to be transferred within a it may be overwritten by a “dominant” start-bit from another
data frame. It can contain 0 to 8 bytes and each byte con- non error passive node which starts transmission. The bus
tains 8 bits. A remote frame has no data field. idle field consists of “recessive” bits. Its length is not speci-
fied and depends on the bus load.
CRC FIELD
The CRC field consists of the CRC sequence followed by the ERROR FRAME
CRC delimiter. The CRC sequence is derived by the trans- The Error Frame consists of two bit fields: the error flag and
mitter from the modulo 2 division of the preceding bit fields, the error delimiter. The error field is built up from the various
starting with the SOF up to the end of the data field, exclud- error flags of the different nodes. Therefore, its length may
ing stuff-bits, by the generator polynomial: vary from a minimum of six bits up to a maximum of twelve
χ15 + χ14 + χ10 + χ8 + χ7 + χ4 + χ3 + 1 bits depending on when a module detects the error. When-
ever a bit error, stuff error, form error, or acknowledgment er-
The remainder of this division is the CRC sequence transmit-
ror is detected by a node, this node starts transmission of the
ted over the bus. On the receiver side the module divides all
error flag at the next bit. If a CRC error is detected, transmis-
bit fields up to the CRC delimiter, excluding stuff-bits, and
sion of the error flag starts at the bit following the acknowl-
checks if the result is zero. This will then be interpreted as a
edge delimiter, unless an error flag for a previous error con-
valid CRC. After the CRC sequence a single “recessive” bit
dition has already been started. Figure 27 shows how a local
is transmitted as the CRC delimiter.
fault at one module (module 2) leads to a 12-bit error frame
on the bus.
The bus level may either be “dominant” for an error-active
node or “recessive” for an error-passive node. An error ac-

29 www.national.com
 Frame Formats (Continued) sive” bits on the bus. This sequence does not destroy a mes-
sage sent by another node and is not detected by other
tive node detecting an error, starts transmitting an active er- nodes. However, if the node detecting an error was the
ror flag consisting of six “dominant” bits. This causes the de- transmitter of the frame the other modules will get an error
struction of the actual frame on the bus. The other nodes condition by a violation of the fixed bit or stuff rule. Figure 26
detect the error flag as either a violation of the rule of bit- shows how an error passive transmitter transmits a passive
stuffing or the value of a fixed bit field is destroyed. As a con- error frame and when it is detected by the receivers.
sequence all other nodes start transmission of their own er- After any module has transmitted its active or passive error
ror flag. This means, that the error sequence which can be flag it waits for the error delimiter which consists of eight “re-
monitored on the bus as a maximum length of twelve bits. If cessive” bits before continuing.
an error passive node detects an error it transmits six “reces-

DS101137-60

FIGURE 25. Interframe Space for Nodes Which Are Not

Error Passive or Have Been Receiver for the Last Frame

DS101137-61

FIGURE 26. Interframe Space for Nodes Which Are Error Passive
and Have Been Transmitter for the Last Frame

OVERLOAD FRAME FRAME ARBITRATION AND PRIORITY

Like an error frame, an overload frame consists of two bit Except for an error passive node which transmitted the last
fields: the overload flag and the overload delimiter. The bit frame, all nodes are allowed to start transmission of a frame
fields have the same length as the error frame field: six bits after the intermission, which can lead to two or more nodes
for the overload flag and eight bits for the delimiter. The over- starting transmission at the same time. To prevent a node
load frame can only be sent after the end of frame (EOF) from destroying another node’s frame, it monitors the bus
field and in they way destroys the fixed form of the intermis- during transmission of the identifier field and the RTR-bit. As
sion field. soon as it detects a “dominant” bit while transmitting a “re-
cessive” bit it releases the bus, immediately stops transmis-
ORDER OF BIT TRANSMISSION sion and starts receiving the frame. This causes no data or
A frame is transmitted starting with the Start of Frame, se- remote frame to be destroyed by another. Therefore the
quentially followed by the remaining bit fields. In every bit highest priority message with the identifier 0x000 out of
field the MSB is transmitted first. 0x7EF (including the remote data request (RTR) bit) always
gets the bus. This is only valid for standard CAN frame for-
FRAME VALIDATION mat. Note that while the CAN specification allows valid stan-
Frames have a different validation point for transmitters and dard identifiers only in the range 0x000 to 0x7EF, the device
receivers. A frame is valid for the transmitter of a message, if will allow identifiers to 0x7FF.
there is no error until the end of the last bit of the End of There are three more items that should be taken into consid-
Frame field. A frame is valid for a receiver, if there is no error eration to avoid unrecoverable collisions on the bus:
until and including the end of the penultimate bit of the End
of Frame.

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Frame Formats (Continued)

DS101137-62

module 1 = error active transmitter detects bit error at t2

module 2 = error active receiver with a local fault at t1
module 3 = error active receiver detects stuff error at t2
FIGURE 27. Error Frame — Error Active Transmitter
• Within one system each message must be assigned a ACCEPTANCE FILTERING
unique identifier. This is to prevent bit errors, as one mod- Every node may perform acceptance filtering on the identi-
ule may transmit a “dominant” data bit while the other is fier of a data or a remote frame to filter out the messages
transmitting a “recessive” data bit. This could happen if which are not required by the node. In they way only the data
two or more modules start transmission of a frame at the of frames which match the acceptance filter is stored in the
same time and all win arbitration. corresponding data buffers. However, every node which is
• Data frames with a given identifier and a non-zero data not in the bus-off state and has received a correct CRC-
length code may be initiated by one node only. Other- sequence acknowledges each frame.
wise, in worst case, two nodes would count up to the bus-
off state, due to bit errors, if they always start transmitting ERROR MANAGEMENT AND DETECTION
the same ID with different data. There are multiple mechanisms in the CAN protocol, to de-
• Every remote frame should have a system-wide data tect errors and to inhibit erroneous modules from disabling
length code (DLC). Otherwise two modules starting all bus activities.
transmission of a remote frame at the same time will
overwrite each other’s DLC which result in bit errors.

31 www.national.com
 Frame Formats (Continued)

DS101137-63

module 1 = error active receiver with a local fault at t1

module 2 = error passive transmitter detects bit error at t2
module 3 = error passive receiver detects stuff error at t2
FIGURE 28. Error Frame — Error Passive Transmitter

DS101137-64

FIGURE 29. Order of Bit Transmission within a CAN Frame

The following errors can be detected: A CRC error is detected if the remainder of the CRC calcula-
• Bit Error tion of a received CRC polynomial is non-zero.
A CAN device that is sending also monitors the bus. If the • Acknowledgment Error
monitored bit value is different from the bit value that is sent, An acknowledgment error is detected whenever a transmit-
a bit error is detected. The reception of a “dominant” bit in- ting node does not get an acknowledgment from any other
stead of a “recessive” bit during the transmission of a pas- node (i.e., when the transmitter does not receive a “domi-
sive error flag, during the stuffed bit stream of the arbitration nant” bit during the ACK frame).
field or during the acknowledge slot, is not interpreted as a The device can be in one of three states with respect to error
bit error. handling:
• Stuff error • Error active
A stuff error is detected, if the bit level after 6 consecutive bit An error active unit can participate in bus communication
times has not changed in a message field that has to be and sends an active (“dominant”) error flag.
coded according to the bit stuffing method.
• Error passive
• Form Error
A form error is detected, if a fixed frame bit (e.g., CRC delim-
iter, ACK delimiter) does not have the specified value. For a
receiver a “dominant” bit during the last bit of End of Frame
does NOT constitute a form error.
• Bit CRC Error

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Frame Formats (Continued) The counters are modified by the device’s hardware accord-
ing to the following rules:
An error passive unit can participate in bus communication.
However, if the unit detects an error it is not allowed to send
TABLE 7. Receive Error Counter Handling
an active error flag. The unit sends only a passive (“reces-
sive”) error flag. A device is error passive when the transmit Receive Error
error counter is greater than 127 or when the receive error Condition
Counter
counter is greater than 127. A device becoming error passive
sends an active error flag. An error passive device becomes A receiver detects a Bit Error Increment by 8
error active again when both transmit and receive error during sending an active error
counter are less than 128. flag.
• Bus off A receiver detects a Increment by 8
A unit that is “bus off” has the output drivers disabled, i.e., it “dominant” bit as the first bit
does not participate in any bus activity. A device is bus off after sending an error flag.
when the transmit error counter is greater than 255. A bus off After detecting the 14th Increment by 8
device will become error active again in one of two ways de- consecutive “dominant” bit
pending on which mode is selected by the user through the following an active error flag
Fault Confinement Mode select bit (FMOD) in the CAN Bus
or overload flag or after
Control Register (CBUS). Setting the FMOD bit to “0” (de-
detecting the 8th consecutive
fault after power on reset) will select the Standard Fault Con-
finement mode. In this mode the device goes from “bus off” “dominant” bit following a
to “error active” after monitoring 128*11 recessive bits (in- passive error flag. After each
cluding bus idle) on the bus. This mode has been imple- sequence of additional 8
mented for compatibility reasons with existing solutions. Set- consecutive “dominant” bits.
ting the FMOD bit to “1” will select the Enhanced Fault Any other error condition Increment by 1
Confinement mode. In this mode the device goes from “bus (stuff, frame, CRC, ACK).
off” to “error active” after monitoring 128 “good” messages,
as indicated by the reception of 11 consecutive “recessive” A valid reception or Decrement by 1 if
bits including the End of Frame. The enhanced mode offers transmission. Counter is not 0
the advantage that a “bus off” device (i.e., a device with a se-
rious fault) is not allowed to destroy any messages on the TABLE 8. Transmit Error Counter Handling
bus until other devices can transmit at least 128 messages.
This is not guaranteed in the standard mode, where a defec- Transmit Error
Condition
tive device could seriously impact bus communication. When Counter
the device goes from “bus off” to “error active”, both error
A transmitter detects a Bit Increment by 8
counters will have the value “0”.
Error during sending an active
In each CAN module there are two error counters to perform error flag.
a sophisticated error management. The receive error
counter (REC) is 7 bits wide and switches the device to the After detecting the 14th Increment by 8
error passive state if it overflows. The transmit error counter consecutive “dominant” bit
(TEC) is 8 bits wide. If it is greater than 127, the device is following an active error flag
switched to the error passive state. As soon as the TEC or overload flag or after
overflows, the device is switched bus-off, i.e., it does not par- detecting the 8th consecutive
ticipate in any bus activity. “dominant” bit following a
passive error flag. After each
sequence of additional 8
consecutive “dominant” bits.
Any other error condition Increment by 8
(stuff, frame, CRC, ACK).
A valid reception or Decrement by
transmission. 1 if Counter is not 0
Special error handling for the TEC counter is performed in
the following situations:
• A stuff error occurs during arbitration, when a transmitted
“recessive” stuff bit is received as a “dorminant” bit. This
does not lead to an incrementation of the TEC.

33 www.national.com
 Frame Formats (Continued) SYNCHRONIZATION
Every receiver starts with a “hard synchronization” on the
• An ACK-error occurs in an error passive device and no falling edge of the SOF bit. One bit time consists of four bit
“dominant” bits are detected while sending the passive segments: Synchronization segment, propagation segment,
error flag. This does not lead to an incrementation of the phase segment 1 and phase segment 2.
TEC.
A falling edge of the data signal should be in the synchroni-
• If only one device is on the bus and this device transmits zation segment. This segment has the fixed length of one
a message, it will get no acknowledgment. This will be time quanta. To compensate for the various delays within a
detected as an error and message will be repeated. network, the propagation segment is used. Its length is pro-
When the device goes “error passive” and detects an ac- grammable from 1 to 8 time quanta. Phase segment 1 and
knowledge error, the TEC counter is not incremented. phase segment 2 are used to resynchronize during an active
Therefore the device will not go from “error passive” to frame. The length of these segments is from 1 to 8 time
the “bus off” state due to such a condition. quanta long.
Two types of synchronization are supported:
Hard synchronization is done with the falling edge on the
bus while the bus is idle, which is then interpreted as the
SOF. It restarts the internal logic.
Soft synchronization is used to lengthen or shorten the bit
time while a data or remote frame is received. Whenever a
falling edge is detected in the propagation segment or in
phase segment 1, the segment is lengthened by a specific
value, the resynchronization jump width (see Figure 32).
If a falling edge lies in the phase segment 2 (as shown in Fig-
ure 32) it is shortened by the resynchronization jump width.
Only one resynchronization is allowed during one bit time.
The sample point lies between the two phase segments and
DS101137-65
is the point where the received data is supposed to be valid.
FIGURE 30. CAN Bus States The transmission point lies at the end of phase segment 2 to
start a new bit time with the synchronization segment.
Figure 30 shows the connection of different bus states ac- Note 12: The resynchronization jump width (RJW) is automatically deter-
cording to the error counters. mined from the programmed value of PS. If a soft resynchronization is done
during phase segment 1 or the propagation segment, then RJW will either be
equal to 4 internal CAN clocks (CKI/(1 + divider)) or the programmed value of
PS, whichever is less. PS2 will never be shorter than 1 internal CAN clock.
Note 13: (PS1 — BTL settings any PSC setting) The PS1 of the BTL should
always be programmed to values greater than 1. To allow device resynchro-
nization for positive and negative phase errors on the bus. (if PS1 is pro-
grammed to one, a bit time could only be lengthened and never shortened
which basically disables half of the synchronization).

DS101137-66

A) Synchronization segment
B) Propagation segment
FIGURE 31. Bit Timing

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Frame Formats (Continued)

DS101137-67

FIGURE 32. Resynchronization 1

DS101137-68

FIGURE 33. Resynchronization 2

Comparators COMPARATOR CONTROL REGISTER (CMPSL) (00D3)

These bits reside in the Comparator Register
The device has two differential comparators. Port L is used
for the comparators. The output of the comparators is multi- CMP2 CMP2 CMP2 CMP2 CMP1 CMP1 CMP1 Re-
plexed out to two pins. The following are the Port L assign- SEL OE RD EN OE RD EN served
ments:
Bit 7 Bit 0
L6 Comparator 2 output
The register contains the following bits:
L5 Comparator 2 negative input
CMP2SEL Selects which L port pin to use for comparator2
L4 Comparator 2 positive input negative input. (CMP2SEL = 0 selects L5;
L3 Comparator 2 negative input CMP2SEL = 1 selects pin L3).
L2 Comparator 1 output CMP2OE Enables comparator 2 output (“1”=enable),
L1 Comparator 1 negative input CMP2EN bit must be set to enable this function.
L0 Comparator 1 positive input CMP2RD Reads comparator 2 output internally
(CMP2EN=1) Read-only, reads as a “0” if com-
Additionally the comparator output can be connected inter-
parator not enabled.
nally to the L-Port pin of the respective positive input and
thereby generate an interrupt using the L-Port interrupt CMP2EN Enables comparator 2 (“1”=enable). If compara-
structure (neg/pos. edge, enable/disable). tor 2 is disabled the associated L-pins can be
used as standard I/O.
Note that in Figure 34, pin L6 has a second alternate function
of supporting the PWM0 output. The comparator 2 output CMP1OE Enables comparator 1 output (“1”=enable),
MUST be disabled in order to use PWM0 output on L6. CMP1EN bit must be set to enable this function.
Figure 34 shows the Comparator Block Diagram. CMP1RD Reads comparator 1 output internally
(CMP1EN=1) Read-only, reads as a “0” if com-
parator not enabled.

35 www.national.com
 Comparators (Continued) The Comparator rise and fall times are symmetrical. The
user program must set up the Configuration and Data regis-
CMP1EN Enables comparator 1 (“1”=enable). If compara- ters of the L port correctly for comparator Inputs/Output.
tor 1 is disabled the associated L-pins can be
used as standard I/O.
Reserved This bit is reserved and should be zero.
The Comparator Select/Control bits are cleared on RESET
(the comparator is disabled). To save power, the program
should also disable the comparator before the device enters
the HALT mode.

DS101137-36

The BOXED area shows logic from PWM Timer. Comparator 2 output (CMP2OE) must be disabled in order to use PWM0 output.
FIGURE 34. Comparator Block

Interrupts The Software trap has the highest priority while the default
VIS has the lowest priority.
INTRODUCTION Each of the 11 maskable inputs has a fixed arbitration rank-
ing and vector.
Each device supports eleven vectored interrupts. Interrupt
sources include Timer 0, Timer 1, Port L Wakeup, Software Figure 35 shows the Interrupt Block Diagram.
Trap, MICROWIRE/PLUS, and External Input.
All interrupts force a branch to location 00FF Hex in program
memory. The VIS instruction may be used to vector to the
appropriate service routine from location 00FF Hex.

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Interrupts (Continued)

DS101137-17

FIGURE 35. Interrupt Block Diagram

MASKABLE INTERRUPTS is to be skipped, the skip is performed before the pending in-
All interrupts other than the Software Trap are maskable. terrupt is acknowledged.
Each maskable interrupt has an associated enable bit and At the start of interrupt acknowledgment, the following ac-
pending flag bit. The pending bit is set to 1 when the interrupt tions occur:
condition occurs. The state of the interrupt enable bit, com- 1. The GIE bit is automatically reset to zero, preventing any
bined with the GIE bit determines whether an active pending subsequent maskable interrupt from interrupting the cur-
flag actually triggers an interrupt. All of the maskable inter- rent service routine. This feature prevents one maskable
rupt pending and enable bits are contained in mapped con- interrupt from interrupting another one being serviced.
trol registers, and thus can be controlled by the software.
2. The address of the instruction about to be executed is
A maskable interrupt condition triggers an interrupt under the pushed onto the stack.
following conditions:
3. The program counter (PC) is loaded with 00FF Hex,
1. The enable bit associated with that interrupt is set. causing a jump to that program memory location.
2. The GIE bit is set. The device requires seven instruction cycles to perform the
3. The device is not processing a non-maskable interrupt. actions listed above.
(If a non-maskable interrupt is being serviced, a If the user wishes to allow nested interrupts, the interrupts
maskable interrupt must wait until that service routine is service routine may set the GIE bit to 1 by writing to the PSW
completed.) register, and thus allow other maskable interrupts to interrupt
An interrupt is triggered only when all of these conditions are the current service routine. If nested interrupts are allowed,
met at the beginning of an instruction. If different maskable caution must be exercised. The user must write the program
interrupts meet these conditions simultaneously, the highest in such a way as to prevent stack overflow, loss of saved
priority interrupt will be serviced first, and the other pending context information, and other unwanted conditions.
interrupts must wait. The interrupt service routine stored at location 00FF Hex
Upon Reset, all pending bits, individual enable bits, and the should use the VIS instruction to determine the cause of the
GIE bit are reset to zero. Thus, a maskable interrupt condi- interrupt, and jump to the interrupt handling routine corre-
tion cannot trigger an interrupt until the program enables it by sponding to the highest priority enabled and active interrupt.
setting both the GIE bit and the individual enable bit. When Alternately, the user may choose to poll all interrupt pending
enabling an interrupt, the user should consider whether or and enable bits to determine the source(s) of the interrupt. If
not a previously activated (set) pending bit should be ac- more than one interrupt is active, the user’s program must
knowledged. If, at the time an interrupt is enabled, any pre- decide which interrupt to service.
vious occurrences of the interrupt should be ignored, the as- Within a specific interrupt service routine, the associated
sociated pending bit must be reset to zero prior to enabling pending bit should be cleared. This is typically done as early
the interrupt. Otherwise, the interrupt may be simply en- as possible in the service routine in order to avoid missing
abled; if the pending bit is already set, it will immediately trig- the next occurrence of the same type of interrupt event.
ger an interrupt. A maskable interrupt is active if its associ- Thus, if the same event occurs a second time, even while the
ated enable and pending bits are set. first occurrence is still being serviced, the second occur-
An interrupt is an asychronous event which may occur be- rence will be serviced immediately upon return from the cur-
fore, during, or after an instruction cycle. Any interrupt which rent interrupt routine.
occurs during the execution of an instruction is not acknowl-
edged until the start of the next normally executed instruction

37 www.national.com
 Interrupts (Continued) The vector table should be filled by the user with the memory
locations of the specific interrupt service routines. For ex-
An interrupt service routine typically ends with an RETI in- ample, if the Software Trap routine is located at 0310 Hex,
struction. This instruction sets the GIE bit back to 1, pops the then the vector location 0yFE and -0yFF should contain the
address stored on the stack, and restores that address to the data 03 and 10 Hex, respectively. When a Software Trap in-
program counter. Program execution then proceeds with the terrupt occurs and the VIS instruction is executed, the pro-
next instruction that would have been executed had there gram jumps to the address specified in the vector table.
been no interrupt. If there are any valid interrupts pending, The interrupt sources in the vector table are listed in order of
the highest-priority interrupt is serviced immediately upon re- rank, from highest to lowest priority. If two or more enabled
turn from the previous interrupt. and pending interrupts are detected at the same time, the
one with the highest priority is serviced first. Upon return
VIS INSTRUCTION from the interrupt service routine, the next highest-level
The general interrupt service routine, which starts at address pending interrupt is serviced.
00FF Hex, must be capable of handling all types of inter- If the VIS instruction is executed, but no interrupts are en-
rupts. The VIS instruction, together with an interrupt vector abled and pending, the lowest-priority interrupt vector is
table, directs the device to the specific interrupt handling rou- used, and a jump is made to the corresponding address in
tine based on the cause of the interrupt. the vector table. This is an unusual occurrence, and may be
VIS is a single-byte instruction, typically used at the very be- the result of an error. It can legitimately result from a change
ginning of the general interrupt service routine at address in the enable bits or pending flags prior to the execution of
00FF Hex, or shortly after that point, just after the code used the VIS instruction, such as executing a single cycle instruc-
for context switching. The VIS instruction determines which tion which clears an enable flag at the same time that the
enabled and pending interrupt has the highest priority, and pending flag is set. It can also result, however, from inadvert-
causes an indirect jump to the address corresponding to that ent execution of the VIS command outside of the context of
interrupt source. The jump addresses (vectors) for all pos- an interrupt.
sible interrupts sources are stored in a vector table. The default VIS interrupt vector can be useful for applica-
The vector table may be as long as 32 bytes (maximum of 16 tions in which time critical interrupts can occur during the
vectors) and resides at the top of the 256-byte block contain- servicing of another interrupt. Rather than restoring the pro-
ing the VIS instruction. However, if the VIS instruction is at gram context (A, B, X, etc.) and executing the RETI instruc-
the very top of a 256-byte block (such as at 00FF Hex), the tion, an interrupt service routine can be terminated by return-
vector table resides at the top of the next 256-byte block. ing to the VIS instruction. In this case, interrupts will be
Thus, if the VIS instruction is located somewhere between serviced in turn until no further interrupts are pending and
00FF and 01DF Hex (the usual case), the vector table is lo- the default VIS routine is started. After testing the GIE bit to
cated between addresses 01E0 and 01FF Hex. If the VIS in- ensure that execution is not erroneous, the routine should
struction is located between 01FF and 02DF Hex, then the restore the program context and execute the RETI to return
vector table is located between addresses 02E0 and 02FF to the interrupted program.
Hex, and so on. This technique can save up to fifty instruction cycles (tc), or
Each vector is 15 bits long and points to the beginning of a more, (50µs at 10 MHz oscillator) of latency for pending in-
specific interrupt service routine somewhere in the 32 kbyte terrupts with a penalty of fewer than ten instruction cycles if
memory space. Each vector occupies two bytes of the vector no further interrupts are pending.
table, with the higher-order byte at the lower address. The To ensure reliable operation, the user should always use the
vectors are arranged in order of interrupt priority. The vector VIS instruction to determine the source of an interrupt. Al-
of the maskable interrupt with the lowest rank is located to though it is possible to poll the pending bits to detect the
0yE0 (higher-order byte) and 0yE1 (lower-order byte). The source of an interrupt, this practice is not recommended. The
next priority interrupt is located at 0yE2 and 0yE3, and so use of polling allows the standard arbitration ranking to be al-
forth in increasing rank. The Software Trap has the highest tered, but the reliability of the interrupt system is compro-
rank and its vector is always located at 0yFE and 0yFF. The mised. The polling routine must individually test the enable
number of interrupts which can become active defines the and pending bits of each maskable interrupt. If a Software
size of the table. Trap interrupt should occur, it will be serviced last, even
Table 9 shows the types of interrupts, the interrupt arbitration though it should have the highest priority. Under certain con-
ranking, and the locations of the corresponding vectors in ditions, a Software Trap could be triggered but not serviced,
the vector table. resulting in an inadvertent “locking out” of all maskable inter-
rupts by the Software Trap pending flag. Problems such as
this can be avoided by using VIS instruction.

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Interrupts (Continued) Note 14: y is VIS page, y ≠ 0
If, by accident, a VIS gets executed and no interrupt is ac-
TABLE 9. Interrupt Vector Table tive, then the PC (Program Counter) will branch to a vector
Vector located at 0yE0-0yE1.
Arbitration Address VIS Execution
Source
Ranking Hi-Low When the VIS instruction is executed it activates the arbitra-
Byte tion logic. The arbitration logic generates an even number
1 Software Trap 0yFE–0yFF between E0 and FE (E0, E2, E4, E6 etc...) depending on
which active interrupt has the highest arbitration ranking at
2 Reserved 0yFC–0yFD the time of the 1st cycle of VIS is executed. For example, if
3 CAN Receive 0yFA–0yFB the software trap interrupt is active, FE is generated. If the
4 CAN Error 0yF8–0yF9 external interrupt is active and the software trap interrupt is
not, then FA is generated and so forth. If the only active inter-
(transmit/receive)
rupt is software trap, than E0 is generated. This number re-
5 CAN Transmit 0yF6–0yF7 places the lower byte of the PC. The upper byte of the PC re-
6 Pin G0 Edge 0yF4–0yF5 mains unchanged. The new PC is therefore pointing to the
7 IDLE Timer Underflow 0yF2–0yF3 vector of the active interrupt with the highest arbitration rank-
ing. This vector is read from program memory and placed
8 Timer T1A/Underflow 0yF0–0yF1 into the PC which is now pointed to the 1st instruction of the
9 Timer T1B 0yEE–0yEF service routine of the active interrupt with the highest arbitra-
10 MlCROWIRE/PLUS 0yEC–0yED tion ranking.
11 PWM timer 0YEA–0yEB Figure 36 illustrates the different steps performed by the VIS
instruction. Figure 37 shows a flowchart for the VIS instruc-
12 Reserved 0yE8–0yE9 tion.
13 Reserved 0yE6–0yE7 The non-maskable interrupt pending flag is cleared by the
14 Reserved 0yE4–0yE5 RPND (Reset Non-Maskable Pending Bit) instruction (under
15 Port L/Wake Up 0yE2–0yE3 certain conditions) and upon RESET.
16 Default VIS Interrupt 0yE0–0yE1

DS101137-29

FIGURE 36. VIS Operation

39 www.national.com
 Interrupts (Continued)

DS101137-30

FIGURE 37. VIS Flowchart

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Interrupts (Continued)

Programming Example: External Interrupt

PSW =00EF
CNTRL =00EE
RBIT 0,PORTGC
RBIT 0,PORTGD ; G0 pin configured Hi-Z
SBIT IEDG, CNTRL ; Ext interrupt polarity; falling edge
SBIT EXEN, PSW ; Enable the external interrupt
SBIT GIE, PSW ; Set the GIE bit
WAIT: JP WAIT ; Wait for external interrupt
.
.
.
.=0FF ; The interrupt causes a
VIS ; branch to address 0FF
; The VIS causes a branch to
;interrupt vector table
.
.
.
.=01FA ; Vector table (within 256 byte
.ADDRW SERVICE ; of VIS inst.) containing the ext
; interrupt service routine
.
.
INT_EXIT:
RETI
.
.
SERVICE: RBIT EXPND, PSW ; Interrupt Service Routine
; Reset ext interrupt pend. bit
.
.
.
JP INT_EXIT ; Return, set the GIE bit

41 www.national.com
 Interrupts (Continued) flag; upon return to the first Software Trap routine, the
STPND flag will have the wrong state. This will allow
NON-MASKABLE INTERRUPT maskable interrupts to be acknowledged during the servicing
of the first Software Trap. To avoid problems such as this, the
Pending Flag user program should contain the Software Trap routine to
There is a pending flag bit associated with the non-maskable perform a recovery procedure rather than a return to normal
interrupt, called STPND. This pending flag is not memory- execution.
mapped and cannot be accessed directly by the software. Under normal conditions, the STPND flag is reset by a
The pending flag is reset to zero when a device Reset oc- RPND instruction in the Software Trap service routine. If a
curs. When the non-maskable interrupt occurs, the associ- programming error or hardware condition (brownout, power
ated pending bit is set to 1. The interrupt service routine supply glitch, etc.) sets the STPND flag without providing a
should contain an RPND instruction to reset the pending flag way for it to be cleared, all other interrupts will be locked out.
to zero. The RPND instruction always resets the STPND To alleviate this condition, the user can use extra RPND in-
flag. structions in the main program and in the WATCHDOG ser-
vice routine (if present). There is no harm in executing extra
Software Trap RPND instructions in these parts of the program.
The Software Trap is a special kind of non-maskable inter-
rupt which occurs when the INTR instruction (used to ac- PORT L INTERRUPTS
knowledge interrupts) is fetched from program memory and Port L provides the user with an additional eight fully select-
placed in the instruction register. This can happen in a vari- able, edge sensitive interrupts which are all vectored into the
ety of ways, usually because of an error condition. Some ex- same service subroutine.
amples of causes are listed below. The interrupt from Port L shares logic with the wake up cir-
If the program counter incorrectly points to a memory loca- cuitry. The register WKEN allows interrupts from Port L to be
tion beyond the available program memory space, the non- individually enabled or disabled. The register WKEDG speci-
existent or unused memory location returns zeroes which is fies the trigger condition to be either a positive or a negative
interpreted as the INTR instruction. edge. Finally, the register WKPND latches in the pending
If the stack is popped beyond the allowed limit (address 06F trigger conditions.
Hex), a 7FFF will be loaded into the PC, if this last location in The GIE (Global Interrupt Enable) bit enables the interrupt
program memory is unprogrammed or unavailable, a Soft- function.
ware Trap will be triggered. A control flag, LPEN, functions as a global interrupt enable
A Software Trap can be triggered by a temporary hardware for Port L interrupts. Setting the LPEN flag will enable inter-
condition such as a brownout or power supply glitch. rupts and vice versa. A separate global pending flag is not
The Software Trap has the highest priority of all interrupts. needed since the register WKPND is adequate.
When a Software Trap occurs, the STPND bit is set. The GIE Since Port L is also used for waking the device out of the
bit is not affected and the pending bit (not accessible by the HALT or IDLE modes, the user can elect to exit the HALT or
user) is used to inhibit other interrupts and to direct the pro- IDLE modes either with or without the interrupt enabled. If he
gram to the ST service routine with the VIS instruction. Noth- elects to disable the interrupt, then the device will restart ex-
ing can interrupt a Software Trap service routine except for ecution from the instruction immediately following the in-
another Software Trap. The STPND can be reset only by the struction that placed the microcontroller in the HALT or IDLE
RPND instruction or a chip Reset. modes. In the other case, the device will first execute the in-
The Software Trap indicates an unusual or unknown error terrupt service routine and then revert to normal operation.
condition. Generally, returning to normal execution at the (See HALT MODE for clock option wakeup information.)
point where the Software Trap occurred cannot be done re-
INTERRUPT SUMMARY
liably. Therefore, the Software Trap service routine should
reinitialize the stack pointer and perform a recovery proce- The device uses the following types of interrupts, listed be-
dure that restarts the software at some known point, similar low in order of priority:
to a device Reset, but not necessarily performing all the 1. The Software Trap non-maskable interrupt, triggered by
same functions as a device Reset. The routine must also ex- the INTR (00 opcode) instruction. The Software Trap is
ecute the RPND instruction to reset the STPND flag. Other- acknowledged immediately. This interrupt service rou-
wise, all other interrupts will be locked out. To the extent pos- tine can be interrupted only by another Software Trap.
sible, the interrupt routine should record or indicate the The Software Trap should end with two RPND instruc-
context of the device so that the cause of the Software Trap tions followed by a restart procedure.
can be determined. 2. Maskable interrupts, triggered by an on-chip peripheral
If the user wishes to return to normal execution from the block or an external device connected to the device. Un-
point at which the Software Trap was triggered, the user der ordinary conditions, a maskable interrupt will not in-
must first execute RPND, followed by RETSK rather than terrupt any other interrupt routine in progress. A
RETI or RET. This is because the return address stored on maskable interrupt routine in progress can be inter-
the stack is the address of the INTR instruction that triggered rupted by the non-maskable interrupt request. A
the interrupt. The program must skip that instruction in order maskable interrupt routine should end with an RETI in-
to proceed with the next one. Otherwise, an infinite loop of struction or, prior to restoring context, should return to
Software Traps and returns will occur. execute the VIS instruction. This is particularly useful
Programming a return to normal execution requires careful when exiting long interrupt service routiness if the time
consideration. If the Software Trap routine is interrupted by between interrupts is short. In this case the RETI instruc-
another Software Trap, the RPND instruction in the service tion would only be executed when the default VIS rou-
routine for the second Software Trap will reset the STPND tine is reached.

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Detection of Illegal Conditions MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the
The device can detect various illegal conditions resulting
MICROWIRE/PLUS to start shifting the data. It gets reset
from coding errors, transient noise, power supply voltage
when eight data bits have been shifted. The user may reset
drops, runaway programs, etc.
the BUSY bit by software to allow less than 8 bits to shift. If
Reading of undefined ROM gets zeroes. The opcode for enabled, an interrupt is generated when eight data bits have
software interrupt is zero. If the program fetches instructions been shifted. The device may enter the MICROWIRE/PLUS
from undefined ROM, this will force a software interrupt, thus mode either as a Master or as a Slave. Figure 39 shows how
signaling that an illegal condition has occurred. two COP888 family microcontrollers and several peripherals
The subroutine stack grows down for each call (jump to sub- may be interconnected using the MICROWIRE/PLUS ar-
routine), interrupt, or PUSH, and grows up for each return or rangements.
POP. The stack pointer is initialized to RAM location 02F Hex
during reset. Consequently, if there are more returns than Warning:
calls, the stack pointer will point to addresses 030 and 031 The SIO register should only be loaded when the SK clock is
Hex (which are undefined RAM). Undefined RAM from ad- low. Loading the SIO register while the SK clock is high will
dresses 030 to 03F Hex is read as all 1’s, which in turn will result in undefined data in the SlO register. SK clock is nor-
cause the program to return to address 7FFF Hex. This is an mally low when not shifting.
undefined ROM location and the instruction fetched (all 0’s)
Setting the BUSY flag when the input SK clock is high in the
from this location will generate a software interrupt signaling
MICROWIRE/PLUS slave mode may cause the current SK
an illegal condition.
clock for the SIO shift register to be narrow. For safety, the
Thus, the chip can detect the following illegal conditions: BUSY flag should only be set when the input SK clock is low.
1. Executing from undefined ROM.
2. Over “POP”ing the stack by having more returns than MICROWIRE/PLUS Master Mode Operation
calls. In the MlCROWIRE/PLUS Master mode of operation the
When the software interrupt occurs, the user can re-initialize shift clock (SK) is generated internally. The MICROWIRE
the stack pointer and do a recovery procedure before restart- Master always initiates all data exchanges. The MSEL bit in
ing (this recovery program is probably similar to that follow- the CNTRL register must be set to enable the SO and SK
ing reset, but might not contain the same program initializa- functions onto the G Port. The SO and SK pins must also be
tion procedures). selected as outputs by setting appropriate bits in the Port G
configuration register. Table 11 summarizes the bit settings
required for Master or Slave mode of operation.
MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous communications
interface. The MICROWIRE/PLUS capability enables the de-
vice to interface with any of National Semiconductor’s MI-
CROWIRE peripherals (i.e., A/D converters, display drivers,
E2PROMs etc.) and with other microcontrollers which sup-
port the MICROWIRE interface. It consists of an 8-bit serial
shift register (SIO) with serial data input (SI), serial data out-
put (SO) and serial shift clock (SK). Figure 38 shows a block
diagram of the MICROWlRE/PLUS logic.
The shift clock can be selected from either an internal source
or an external source. Operating the MICROWIRE/ PLUS ar-
rangement with the internal clock source is called the Master
mode of operation. Similarly, operating the MICROWIRE ar-
rangement with an external shift clock is called the Slave
mode of operation.
The CNTRL register is used to configure and control the DS101137-37

MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS, FIGURE 38. MICROWIRE/PLUS Block Diagram
the MSEL bit in the CNTRL register is set to one. In the mas-
ter mode the SK clock rate is selected by the two bits, SL0
and SL1, in the CNTRL register. Table 10 details the different
clock rates that may be selected.

43 www.national.com
 MICROWIRE/PLUS (Continued)

DS101137-38

FIGURE 39. MICROWIRE/PLUS Application

TABLE 10. MICROWIRE/PLUS TABLE 11. MICROWIRE/PLUS Mode Selection
Master Mode Clock Selection This table assumes that the control flag MSEL is set.
SL1 SL0 SK G4 (SO) G5 (SK) G4 G5

0 0 2 x tc Config. Config. Fun. Fun. Operation

Bit Bit
0 1 4 x tc
1 1 SO Int. MICROWIRE/PLUS
1 x 8 x tc
SK Master
Where tc is the instruction cycle clock
0 1 TRI- Int. MICROWIRE/PLUS
MICROWIRE/PLUS Slave Mode Operation STATE SK Master

In the MICROWIRE/PLUS Slave mode of operation the SK 1 0 SO Ext. MICROWIRE/PLUS

clock is generated by an external source. Setting the MSEL SK Slave
bit in the CNTRL register enables the SO and SK functions 0 0 TRI- Ext. MICROWIRE/PLUS
onto the G Port. The SK pin must be selected as an input STATE SK Slave
and the SO pin is selected as an output pin by setting and re-
setting the appropriate bit in the Port G configuration regis-
ter. Table 2 summarizes the settings required to enter the
Slave mode of operation.
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by the
Master will be shifted properly. After eight clock pulses the
BUSY flag will be cleared and the sequence may be re-
peated.

Alternate SK Phase Operation

The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK is normally low. In the normal mode
data is shifted in on the rising edge of the SK clock and the
data is shifted out on the falling edge of the SK clock. The
SIO register is shifted on each falling edge of the SK clock in
the normal mode. In the alternate SK phase mode the SIO
register is shifted on the rising edge of the SK clock.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alter-
nate SK clock. The SKSEL is mapped into the G6 configura-
tion bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.

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Memory Map Address Contents
All RAM, ports and registers (except A and PC) are mapped EA TMR1LO, Timer T1 Lower Byte
into data memory address space. EB TMR1HI, Timer T1 Upper Byte
Address Contents EC T1RALO, Timer T1 Autoload Register Lower
00 to 2F On-Chip RAM bytes (48 bytes) Byte
30 to 7F Unused RAM Address Space (Reads As All ED T1RAHI, Timer T1 Autoload Register T1RA
Ones) Upper Byte
80 to 9F Unused RAM Address Space (Reads EE CNTRL, Control Register
Undefined Data) EF PSW, Processor Status Word Register
A0 PSCAL, PWM timer Prescaler Register F0 to FB On-Chip RAM Mapped as Registers
A1 RLON, PWM timer On-Time Register FC X Register
A2 PWMCON, PWM Control Register FD SP Register
A3 to AF Reserved FE B Register
B0 TXD1, Transmit 1 Data FF Reserved (Note 16)
B1 TXD2, Transmit 2 Data Note 15: Reading memory locations 30–7F Hex will return all ones. Reading
other unused memory locations will return undefined data.
B2 TDLC, Transmit Data Length Code and
Note 16: In devices with more than 128 bytes of RAM, location 0FF is used
Identifier Low as the Segment register to switch between different Segments of RAM
B3 TID, Transmit Identifier High memory. In this device location 0FF can be used as a general purpose, on-
chip RAM mapped register. However, the user is advised that caution should
B4 RXD1, Receive Data 1 be taken in porting software utilizing this memory location to a chip with more
B5 RXD2, Receive Data 2 than 128 bytes of RAM.

B6 RIDL, Receive Data Length Code

B7 RID, Receive Identify High
Addressing Modes
There are ten addressing modes, six for operand addressing
B8 CSCAL, CAN Prescaler
and four for transfer of control.
B9 CTIM, Bus Timing Register
BA CBUS, Bus Control Register OPERAND ADDRESSING MODES
BB TCNTL, Transmit/Receive Control Register
Register Indirect
BC RTSTAT Receive/Transmit Status Register This is the “normal” addressing mode. The operand is the
BD TEC, Transmit Error Count Register data memory addressed by the B pointer or X pointer.
BE REC, Receive Error Count Register
Register Indirect (with auto post Increment or
BF Reserved
decrement of pointer)
C0 to C7 Reserved This addressing mode is used with the LD and X instruc-
C8 WKEDG, MIWU Edge Select Register tions. The operand is the data memory addressed by the B
C9 WKEN, MIWU Enable Register pointer or X pointer. This is a register indirect mode that au-
tomatically post increments or decrements the B or X regis-
CA WKPND, MIWU Pending Register
ter after executing the instruction.
CB to CF Reserved
D0 PORTLD, Port L Data Register Direct
D1 PORTLC, Port L Configuration Register The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
D2 PORTLP, Port L Input Pins (Read Only)
D3 CMPSL, Comparator control register Immediate
D4 PORTGD, Port G Data Register The instruction contains an 8-bit immediate field as the oper-
D5 PORTGC, Port G Configuration Register and.
D6 PORTGP, Port G Input Pins (Read Only)
Short Immediate
D7 to DB Reserved This addressing mode is used with the Load B Immediate in-
DC PORTD, Port D output register struction. The instruction contains a 4-bit immediate field as
DD to DF Reserved for Port D the operand.
E0 to E5 Reserved
Indirect
E6 T1RBLO, Timer T1 Autoload Register Lower This addressing mode is used with the LAID instruction. The
Byte contents of the accumuiator are used as a partial address
E7 T1RBHI, Timer T1 Autoload Register Upper (lower 8 bits of PC) for accessing a data operand from the
Byte program memory.
E8 ICNTRL, Interrupt Control Register
E9 SIOR, MICROWIRE/PLUS Shift Register

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 Addressing Modes (Continued) Instruction Set
TRANSFER OF CONTROL ADDRESSING MODES
Register and Symbol Definition
Relative Registers
This mode is used for the JP instruction, with the instruction A 8-Bit Accumulator Register
field being added to the program counter to get the new pro-
B 8-Bit Address Register
gram location. JP has a range from −31 to +32 to allow a
1-byte relative jump (JP + 1 is implemented by a NOP in- X 8-Bit Address Register
struction). There are no “pages” when using JP, since all 15 SP 8-Bit Stack Pointer Register
bits of PC are used. PC 15-Bit Program Counter Register
Absolute PU Upper 7 Bits of PC
This mode is used with the JMP and JSR instructions, with PL Lower 8 Bits of PC
the instruction field of 12 bits replacing the lower 12 bits of C 1-Bit of PSW Register for Carry
the program counter (PC). This allows jumping to any loca- HC 1-Bit of PSW Register for Half Carry
tion in the current 4k program memory segment.
GIE 1-Bit of PSW Register for Global Interrupt
Absolute Long Enable
This mode is used with the JMPL and JSRL instructions, with VU Interrupt Vector Upper Byte
the instruction field of 15 bits replacing the entire 15 bits of VL Interrupt Vector Lower Byte
the program counter (PC). This allows jumping to any loca-
tion up to 32k in the program memory space. Symbols
[B] Memory Indirectly Addressed by B Register
Indirect
[X] Memory Indirectly Addressed by X Register
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits of MD Direct Addressed Memory
PC) for accessing a location in the program memory. The Mem Direct Addressed Memory or [B]
contents of this program memory location serve as a partial Meml Direct Addressed Memory or [B] or
address (lower 8 bits of PC) for the jump to the next instruc- Immediate Data
tion.
Imm 8-Bit Immediate Data
Note: The VIS is a special case of the Indirect Transfer of Control addressing
mode, where the double byte vector associated with the interrupt is Reg Register Memory: Addresses F0 to FF
transferred from adjacent addresses in the program memory into the (Includes B, X and SP)
program counter (PC) in order to jump to the associated interrupt ser-
vice routine. Bit Bit Number (0 to 7)
← Loaded with
↔ Exchanged with

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Instruction Set (Continued)

INSTRUCTION SET

ADD A,Meml ADD A ←A + Meml

ADC A,Meml ADD with Carry A ←A + Meml + C, C← Carry,
HC ←Half Carry
SUBC A,Meml Subtract with Carry A ←A − MemI + C, C←Carry,
HC ←Half Carry
AND A,Meml Logical AND A ←A and Meml
ANDSZ A,Imm Logical AND Immed., Skip if Zero Skip next if (A and Imm) = 0
OR A,Meml Logical OR A ←A or Meml
XOR A,Meml Logical EXclusive OR A ←A xor Meml
IFEQ MD,Imm IF EQual Compare MD and Imm, Do next if MD = Imm
IFEQ A,Meml IF EQual Compare A and Meml, Do next if A = Meml
IFNE A,Meml IF Not Equal Compare A and Meml, Do next if A ≠ Meml
IFGT A,Meml IF Greater Than Compare A and Meml, Do next if A Meml
IFBNE # If B Not Equal Do next if lower 4 bits of B ≠ Imm
DRSZ Reg Decrement Reg., Skip if Zero Reg ←Reg − 1, Skip if Reg = 0
SBIT #,Mem Set BIT 1 to bit, Mem (bit = 0 to 7 immediate)
RBIT #,Mem Reset BIT 0 to bit, Mem
IFBIT #,Mem IF BIT If bit in A or Mem is true do next instruction
RPND Reset PeNDing Flag Reset Software Interrupt Pending Flag
X A,Mem EXchange A with Memory A ↔Mem
X A,[X] EXchange A with Memory [X] A ↔[X]
LD A,Meml LoaD A with Memory A ←Meml
LD A,[X] LoaD A with Memory [X] A ←[X]
LD B,Imm LoaD B with Immed. B ←Imm
LD Mem,Imm LoaD Memory Immed. Mem ←Imm
LD Reg,Imm LoaD Register Memory Immed. Reg ←Imm
X A, [B ± ] EXchange A with Memory [B] A↔[B], (B ←B ± 1)
X A, [X ± ] EXchange A with Memory [X] A↔[X], (X ← ± 1)
LD A, [B ± ] LoaD A with Memory [B] A←[B], (B←B ± 1)
LD A, [X ± ] LoaD A with Memory [X] A←[X], (X←X ± 1)
LD [B ± ],Imm LoaD Memory [B] Immed. [B] ←Imm, (B←B ± 1)
CLR A CLeaR A A←0
INC A INCrement A A←A + 1
DEC A DECrementA A←A − 1
LAID Load A InDirect from ROM A←ROM (PU,A)
DCOR A Decimal CORrect A A←BCD correction of A (follows ADC, SUBC)
RRC A Rotate A Right thru C C →A7→… →A0→C
RLC A Rotate A Left thru C C←A7←…←A0←C
SWAP A SWAP nibbles of A A7…A4↔A3…A0
SC Set C C←1, HC ←1
RC Reset C C←0, HC ←0
IFC IF C IF C is true, do next instruction
IFNC IF Not C If C is not true, do next instruction
POP A POP the stack into A SP←SP + 1, A←[SP]
PUSH A PUSH A onto the stack [SP]←A, SP←SP − 1
VIS Vector to Interrupt Service Routine PU ←[VU], PL ←[VL]
JMPL Addr. Jump absolute Long PC ←ii (ii = 15 bits, 0k to 32k)
JMP Addr. Jump absolute PC9…0 ←i (i = 12 bits)
JP Disp. Jump relative short PC ←PC + r (r is −31 to +32, except 1)

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 Instruction Set (Continued)

JSRL Addr. Jump SubRoutine Long [SP] ←PL, [SP−1]←PU,SP−2, PC ←ii

JSR Addr. Jump SubRoutine [SP] ← PL, [SP−1]←PU,SP−2, PC9…0←i
JID Jump InDirect PL←ROM (PU,A)
RET RETurn from subroutine SP + 2, PL ← [SP], PU ← [SP−1]
RETSK RETurn and SKip SP + 2, PL ←[SP],PU ← [SP−1]
RETI RETurn from Interrupt SP + 2, PL ←[SP],PU ←[SP−1],GIE ←1
INTR Generate an Interrupt [SP] ←PL, [SP−1]←PU, SP−2, PC ←0FF
NOP No OPeration PC ← PC + 1

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Instruction Execution Time
Most instructions are single byte (with immediate addressing Instructions Using A and C
mode instructions taking two bytes).
CLRA 1/1
Most single byte instructions take one cycle time to execute.
INCA 1/1
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped DECA 1/1
instruction opcode. LAID 1/3
See the BYTES and CYCLES per INSTRUCTION table for DCORA 1/1
details.
RRCA 1/1
Bytes and Cycles per Instruction
RLCA 1/1
The following table shows the number of bytes and cycles for
SWAPA 1/1
each instruction in the format of byte/cycle.
SC 1/1

Arithmetic and Logic Instructions RC 1/1

IFC 1/1
[B] Direct Immed.
IFNC 1/1
ADD 1/1 3/4 2/2
PUSHA 1/3
ADC 1/1 3/4 2/2
POPA 1/3
SUBC 1/1 3/4 2/2
ANDSZ 2/2
AND 1/1 3/4 2/2
OR 1/1 3/4 2/2
Transfer of Control
XOR 1/1 3/4 2/2 Instructions
IFEQ 1/1 3/4 2/2
JMPL 3/4
IFGT 1/1 3/4 2/2
JMP 2/3
IFBNE 1/1
JP 1/3
DRSZ 1/3
JSRL 3/5
SBIT 1/1 3/4
JSR 2/5
RBIT 1/1 3/4
JID 1/3
IFBIT 1/1 3/4
VIS 1/5
RPND 1/1 RET 1/5
RETSK 1/5
RETI 1/5
INTR 1/7
NOP 1/1

Memory Transfer Instructions

Register Direct Immed. Register Indirect
Indirect Auto Incr. and Decr.
[B] [X] [B+, B−] [X+, X−]
X A, (Note 17) 1/1 1/3 2/3 1/2 1/3
LD A, (Note 17) 1/1 1/3 2/3 2/2 1/2 1/3
LD B, Imm 1/1 (IF B < 16)
LD B, Imm 2/3 (IF B > 15)
LD Mem, Imm 2/2 3/3 2/2
LD Reg, Imm 2/3
IFEQ MD, Imm 3/3

Note 17: > Memory location addressed by B or X or directly.

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 Opcode Table
UPPER NIBBLE
F E D C B A 9 8 7 6 5 4 3 2 1 0

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JP−15 JP−31 LD 0F0, #i DRSZ RRCA RC ADC A, ADC IFBIT ANDSZ LD B, IFBNE 0 JSR JMP JP+17 INTR 0
0F0 #i A,[B] 0,[B] A, #i #0F x000–x0FF x000–x0FF
JP−14 JP−30 LD 0F1, #i DRSZ * SC SUBC SUB IFBIT * LD B, IFBNE 1 JSR JMP JP+18 JP+2 1
0F1 A, #i A,[B] 1,[B] #0E x100–x1FF x100–x1FF
JP−13 JP−29 LD 0F2, #i DRSZ X A, X A, IFEQ IFEQ IFBIT * LD B, IFBNE 2 JSR JMP JP+19 JP+3 2
0F2 [X+] [B+] A, #i A,[B] 2,[B] #0D x200–x2FF x200–x2FF
JP−12 JP−28 LD 0F3, #i DRSZ X A, X A, IFGT A, IFGT IFBIT * LD B, IFBNE 3 JSR JMP JP+20 JP+4 3
0F3 [X−] [B−] #i A,[B] 3,[B] #0C x300–x3FF x300–x3FF
JP−11 JP−27 LD 0F4, #i DRSZ VIS LAID ADD A, ADD IFBIT CLRA LD B, IFBNE 4 JSR JMP JP+21 JP+5 4
0F4 #i A,[B] 4,[B] #0B x400–x4FF x400–x4FF
JP−10 JP−26 LD 0F5, #i DRSZ RPND JID AND A, AND IFBIT SWAPA LD B, IFBNE 5 JSR JMP JP+22 JP+6 5
0F5 #i A,[B] 5,[B] #0A x500–x5FF x500–x5FF
JP−9 JP−25 LD 0F6, #i DRSZ X A, [X] X A, XOR A, XOR IFBIT DCORA LD B, IFBNE 6 JSR JMP JP+23 JP+7 6
0F6 [B] #i A,[B] 6,[B] #09 x600–x6FF x600–x6FF
JP−8 JP−24 LD 0F7, #i DRSZ * * OR A,#i OR IFBIT PUSHA LD B, IFBNE 7 JSR JMP JP+24 JP+8 7
0F7 A,[B] 7,[B] #08 x700–x7FF x700–x7FF

50
JP−7 JP−23 LD 0F8, #i DRSZ NOP RLCA LD A,#i IFC SBIT RBIT LD B, IFBNE 8 JSR JMP JP+25 JP+9 8
0F8 0,[B] 0,[B] #07 x800–x8FF x800–x8FF
JP−6 JP−22 LD 0F9, #i DRSZ IFNE A, IFEQ IFNE IFNC SBIT RBIT LD B, IFBNE 9 JSR JMP JP+26 JP+10 9
0F9 [B] Md,#i A,#i 1,[B] 1,[B] #06 x900–x9FF x900–x9FF
LOWER NIBBLE

JP−5 JP−21 LD 0FA, #i DRSZ LD A, LD A, LD INCA SBIT RBIT LD B, IFBNE 0A JSR JMP JP+27 JP+11 A
0FA [X+] [B+] [B+], #i 2,[B] 2,[B] #05 xA00–xAFF xA00–xAFF
JP−4 JP−20 LD 0FB, #i DRSZ LD A, LD A, LD DECA SBIT RBIT LD B, IFBNE 0B JSR JMP JP+28 JP+12 B
0FB [X−] [B−] [B−], #i 3,[B] 3,[B] #04 xB00–xBFF xB00–xBFF
JP−3 JP−19 LD 0FC, #i DRSZ LD JMPL X A,Md POPA SBIT RBIT LD B, IFBNE 0C JSR JMP JP+29 JP+13 C
0FC Md,#i 4,[B] 4,[B] #03 xC00–xCFF xC00–xCFF
JP−2 JP−18 LD 0FD, #i DRSZ DIR JSRL LD RETSK SBIT RBIT LD B, IFBNE 0D JSR JMP JP+30 JP+14 D
0FD A,Md 5,[B] 5,[B] #02 xD00–xDFF xD00–xDFF
JP−1 JP−17 LD 0FE, #i DRSZ LD A, LD A, LD RET SBIT RBIT LD B, IFBNE 0E JSR JMP JP+31 JP+15 E
0FE [X] [B] [B],#i 6,[B] 6,[B] #01 xE00–xEFF xE00–xEFF
JP−0 JP−16 LD 0FF, #i DRSZ * * LD B,#i RETI SBIT RBIT LD B, IFBNE 0F JSR JMP JP+32 JP+16 F
0FF 7,[B] 7,[B] #00 xF00–xFFF xF00–xFFF
where,
is the immediate data
Md is a directly addressed memory location
* is an unused opcode
The opcode 60 Hex is also the opcode for IFBIT #i,A
Development Tools Support cludes BCLIDE (Byte Craft Limited Integrated Develop-
ment Environment) for Win32, editor, optimizing C Cross-
Compiler, macro cross assembler, BC-Linker, and
OVERVIEW
MetaLink tools support. (DOS/SUN versions available;
National is engaged with an international community of inde- Compiler is installable under WCOP8 IDE; Compatible
pendent 3rd party vendors who provide hardware and soft- with DriveWay COP8).
ware development tool support. Through National’s interac-
tion and guidance, these tools cooperate to form a choice of • EWCOP8-KS: Very Low cost ANSI C-Compiler and Em-
solutions that fits each developer’s needs. bedded Workbench from IAR (Kickstart version:
COP8Sx/Fx only with 2k code limit; No FP). A fully inte-
This section provides a summary of the tool and develop- grated Win32 IDE, ANSI C-Compiler, macro assembler,
ment kits currently available. Up-to-date information, selec- editor, linker, Liberian, C-Spy simulator/debugger, PLUS
tion guides, free tools, demos, updates, and purchase infor- MetaLink EPU/DM emulator support.
mation can be obtained at our web site at:
www.national.com/cop8. • EWCOP8-AS: Moderately priced COP8 Assembler and
Embedded Workbench from IAR (no code limit). A fully in-
SUMMARY OF TOOLS tegrated Win32 IDE, macro assembler, editor, linker, li-
brarian, and C-Spy high-level simulator/debugger with
COP8 Evaluation Tools
I/O and interrupts support. (Upgradeable with optional
• COP8–NSEVAL: Free Software Evaluation package for C-Compiler and/or MetaLink Debugger/Emulator sup-
Windows. A fully integrated evaluation environment for port).
COP8, including versions of WCOP8 IDE (Integrated De-
• EWCOP8-BL: Moderately priced ANSI C-Compiler and
velopment Environment), COP8-NSASM, COP8-MLSIM,
Embedded Workbench from IAR (Baseline version: All
COP8C, DriveWay™ COP8, Manuals, and other COP8
COP8 devices; 4k code limit; no FP). A fully integrated
information. Win32 IDE, ANSI C-Compiler, macro assembler, editor,
• COP8–MLSIM: Free Instruction Level Simulator tool for linker, librarian, and C-Spy high-level simulator/debugger.
Windows. For testing and debugging software instruc- (Upgradeable; CWCOP8-M MetaLink tools interface sup-
tions only (No I/O or interrupt support). port optional).
• COP8–EPU: Very Low cost COP8 Evaluation & Pro- • EWCOP8: Full featured ANSI C-Compiler and Embed-
gramming Unit. Windows based evaluation and ded Workbench for Windows from IAR (no code limit). A
hardware-simulation tool, with COP8 device programmer fully integrated Win32 IDE, ANSI C-Compiler, macro as-
and erasable samples. Includes COP8-NSDEV, Drive- sembler, editor, linker, librarian, and C-Spy high-level
way COP8 Demo, MetaLink Debugger, I/O cables and simulator/debugger. (CWCOP8-M MetaLink tools inter-
power supply. face support optional).
• COP8–EVAL-ICUxx: Very Low cost evaluation and de- • EWCOP8-M: Full featured ANSI C-Compiler and Embed-
sign test board for COP8ACC and COP8SGx Families, ded Workbench for Windows from IAR (no code limit). A
from ICU. Real-time environment with add-on A/D, D/A, fully integrated Win32 IDE, ANSI C-Compiler, macro as-
and EEPROM. Includes software routines and reference sembler, editor, linker, librarian, C-Spy high-level
designs. simulator/debugger, PLUS MetaLink debugger/hardware
• Manuals, Applications Notes, Literature: Available free interface (CWCOP8-M).
from our web site at: www.national.com/cop8. COP8 Productivity Enhancement Tools
COP8 Integrated Software/Hardware Design Develop- • WCOP8 IDE: Very Low cost IDE (Integrated Develop-
ment Kits ment Environment) from KKD. Supports COP8C, COP8-
• COP8-EPU: Very Low cost Evaluation & Programming NSASM, COP8-MLSIM, DriveWay COP8, and MetaLink
Unit. Windows based development and hardware- debugger under a common Windows Project Manage-
simulation tool for COPSx/xG families, with COP8 device ment environment. Code development, debug, and emu-
programmer and samples. Includes COP8-NSDEV, lation tools can be launched from the project window
Driveway COP8 Demo, MetaLink Debugger, cables and framework.
power supply. • DriveWay-COP8: Low cost COP8 Peripherals Code
• COP8-DM: Moderate cost Debug Module from MetaLink. Generation tool from Aisys Corporation. Automatically
A Windows based, real-time in-circuit emulation tool with generates tested and documented C or Assembly source
COP8 device programmer. Includes COP8-NSDEV, code modules containing I/O drivers and interrupt han-
DriveWay COP8 Demo, MetaLink Debugger, power sup- dlers for each on-chip peripheral. Application specific
ply, emulation cables and adapters. code can be inserted for customization using the inte-
COP8 Development Languages and Environments grated editor. (Compatible with COP8-NSASM, COP8C,
and WCOP8 IDE.)
• COP8-NSASM: Free COP8 Assembler v5 for Win32.
Macro assembler, linker, and librarian for COP8 software • COP8-UTILS: Free set of COP8 assembly code ex-
development. Supports all COP8 devices. (DOS/Win16 amples, device drivers, and utilities to speed up code de-
v4.10.2 available with limited support). (Compatible with velopment.
WCOP8 IDE, COP8C, and DriveWay COP8). • COP8-MLSIM: Free Instruction Level Simulator tool for
• COP8-NSDEV: Very low cost Software Development Windows. For testing and debugging software instruc-
Package for Windows. An integrated development envi- tions only (No I/O or interrupt support).
ronment for COP8, including WCOP8 IDE, COP8-
NSASM, COP8-MLSIM.
• COP8C: Moderately priced C Cross-Compiler and Code
Development System from Byte Craft (no code limit). In-

51 www.national.com
 Development Tools Support COP8 Device Programmer Support
(Continued) • MetaLink’s EPU and Debug Module include development
device programming capability for COP8 devices.
COP8 Real-Time Emulation Tools • Third-party programmers and automatic handling equip-
• COP8-DM: MetaLink Debug Module. A moderately ment cover needs from engineering prototype and pilot
priced real-time in-circuit emulation tool, with COP8 de- production, to full production environments.
vice programmer. Includes COP8-NSDEV, DriveWay • Factory programming available for high-volume require-
COP8 Demo, MetaLink Debugger, power supply, emula- ments.
tion cables and adapters.
• IM-COP8: MetaLink iceMASTER ® . A full featured, real-
time in-circuit emulator for COP8 devices. Includes Met-
aLink Windows Debugger, and power supply. Package-
specific probes and surface mount adaptors are ordered
separately.

TOOLS ORDERING NUMBERS FOR THE COP87L84BC FAMILY DEVICES

Vendor Tools Order Number Cost Notes

National COP8-NSEVAL COP8-NSEVAL Free Web site download
COP8-NSASM COP8-NSASM Free Included in EPU and DM. Web site download
COP8-MLSIM COP8-MLSIM Free Included in EPU and DM. Web site download
COP8-NSDEV COP8-NSDEV VL Included in EPU and DM. Order CD from website
COP8-EPU Not available for this device
COP8-DM Contact MetaLink
Development COP87L84BC VL 16k OTP devices. No wondowed devices.
Devices
IM-COP8 Contact MetaLink
MetaLink COP8-EPU Not available for this device
COP8-DM DM4-COP8-888BC (10 M Included p/s (PS-10), target cable of choice (i.e.
MHz), plus PS-10, plus DM-COP8/28D), 16/20/28/40 DIP/SO and 44 PLCC
DM-COP8/xxx (ie. 28D) programming sockets
DM Target MHW-CONV39 L DM target converters for 28SO
Adapters
IM-COP8 IM-COP8-AD-464 (-220) H Base unit 10 MHz; -220 = 220V; add probe card
(10 MHz maximum) (required) and target adapter (if needed); included
software and manuals
IM-Probe Card PC-888BC28D5-AD-10 M 10 MHz 28 DIP probe card; 2.5V to 6.0V
IM Probe Target MHW-SOIC28 L 28 pin SOIC adapter for probe card
Adapter
ICU COP8-EVAL Not available for this device
KKD WCOP8-IDE WCOP8-IDE VL Included in EPU and DM
IAR EWCOP8-xx See summary above L-H Included all software and manuals
Byte COP8C COP8C M Included all software and manuals
Craft
Aisys DriveWay COP8 DriveWay COP8 L Included all software and manuals
OTP Programmers Contact vendor L-H For approved programmer listings and vendor
information, go to our OTP support page at:
www.national.com/cop8
Cost: Free; VL = < $100; L = $100 - $300; M = $300 - $1k; H = $1k - $3k; VH = $3k - $5k

www.national.com 52
Development Tools Support (Continued)

WHERE TO GET TOOLS

Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors.

Vendor Home Office Electronic Sites Other Main Offices

Aisys U.S.A.: Santa Clara, CA www.aisysinc.com Distributors
1-408-327-8820 info@aisysinc.com
fax: 1-408-327-8830
Byte Craft U.S.A. www.bytecraft.com Distributors
1-519-888-6911 info @bytecraft.com
fax: 1-519-746-6751
IAR Sweden: Uppsala www.iar.se U.S.A.: San Francisco
+46 18 16 78 00 info@iar.se 1-415-765-5500
fax: +46 18 16 78 38 info@iar.com fax: 1-415-765-5503
info@iarsys.co.uk U.K.: London
info@iar.de +44 171 924 33 34
fax: +44 171 924 53 41
Germany: Munich
+49 89 470 6022
fax: +49 89 470 956
ICU Sweden: Polygonvaegen www.icu.se Switzeland: Hoehe
+46 8 630 11 20 support@icu.se +41 34 497 28 20
fax: +46 8 630 11 70 support @icu.ch fax: +41 34 497 28 21
KKD Denmark: www.kkd.dk
MetaLink U.S.A.: Chandler, AZ www.metaice.com Germany: Kirchseeon
1-800-638-2423 sales @metaice.com 80-91-5696-0
fax: 1-602-926-1198 support @metaice.com fax: 80-91-2386
bbs: 1-602-962-0013 islanger@metalink.de
www.metalink.de Distributors Worldwide
National U.S.A.: Santa Clara, CA www.national.com/cop8 Europe: +49 (0) 180 530 8585
1-800-272-9959 support @nsc.com fax: +49 (0) 180 530 8586
fax: 1-800-737-7018 europe.support @nsc.com Distributors Worldwide

The following companies have approved COP8 program- Customer Support

mers in a variety of configurations. Contact your local office Complete product information and technical support is avail-
or distributor. You can link to their web sites and get the lat- able from National’s customer response centers, and from
est listing of approved programmers from National’s COP8 our on-line COP8 customer support sites.
OTP Support page at: www.national.com/cop8.
Advantech; Advin; BP Microsystems; Data I/O; Hi-Lo Sys-
tems; ICE Technology; Lloyd Research; Logical Devices;
MQP; Needhams; Phyton; SMS; Stag Programmers; Sys-
tem General; Tribal Microsystems; Xeltek.

53 www.national.com
COP87L84BC 8-Bit CMOS OTP Microcontrollers with 16k Memory, Comparators, and CAN
Interface
Physical Dimensions inches (millimeters) unless otherwise noted

Order Number COP87L84BC-xxx/M or COP684BC-xxx/M

NS Package Number M28B

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform
into the body, or (b) support or sustain life, and can be reasonably expected to cause the failure of
whose failure to perform when properly used in the life support device or system, or to affect its
accordance with instructions for use provided in the safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Asia Pacific Customer Japan Ltd.
Americas Fax: +49 (0) 1 80-530 85 86 Response Group Tel: 81-3-5639-7560
Tel: 1-800-272-9959 Email: europe.support@nsc.com Tel: 65-2544466 Fax: 81-3-5639-7507
Fax: 1-800-737-7018 Deutsch Tel: +49 (0) 1 80-530 85 85 Fax: 65-2504466
Email: support@nsc.com English Tel: +49 (0) 1 80-532 78 32 Email: sea.support@nsc.com
Français Tel: +49 (0) 1 80-532 93 58
www.national.com Italiano Tel: +49 (0) 1 80-534 16 80

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.