CAT24C32

32-Kb I2C CMOS Serial

EEPROM
Description
The CAT24C32 is a 32−Kb CMOS Serial EEPROM devices,
internally organized as 4096 words of 8 bits each. www.onsemi.com
It features a 32−byte page write buffer and supports the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol.
External address pins make it possible to address up to eight
CAT24C32 devices on the same bus. SOIC−8 UDFN8 US8 *
W SUFFIX HU4 SUFFIX US SUFFIX
Features CASE 751BD CASE 517AZ CASE 493
• Supports Standard, Fast and Fast−Plus I2C Protocol
• 1.7 V to 5.5 V Supply Voltage Range
• 32−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
PDIP−8 TSSOP−8
• Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs L SUFFIX Y SUFFIX
(SCL and SDA) CASE 646AA CASE 948AL
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
WLCSP5 WLCSP4
• 100 Year Data Retention C5A SUFFIX C4C SUFFIX
• Industrial and Extended Temperature Range CASE 567JQ CASE 567JY
• PDIP, SOIC, TSSOP, UDFN, US 8−lead, WLCSP 4−ball and 5−ball
Packages PIN CONFIGURATIONS (Top Views)
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS 1 2 3
Compliant
1 2
A
VCC VSS A VCC VSS
B
SDA
SCL SDA B
C
WLCSP4 (C4C) WP SCL

WLCSP5 (C5A)
1
A0 VCC
A1 WP
A2 SCL
VSS SDA
PDIP (L), SOIC (W), TSSOP (Y),
US (US), UDFN (HU4)

For the location of Pin 1, please consult the

corresponding package drawing.
* In Development; please contact factory for availability

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.

© Semiconductor Components Industries, LLC, 2015 1 Publication Order Number:

June, 2015 − Rev. 24 CAT24C32/D
 CAT24C32

DEVICE MARKINGS
(PDIP−8) (SOIC−8)

24C32F 24C32F
AXXX AYMXXX
YYWWG

24C32F = Specific Device Code

24C32F = Specific Device Code A = Assembly Location
A = Assembly Location Y = Production Year (Last Digit)
XXX = Last Three Digits of Assembly Lot Number M = Production Month (1−9, O, N, D)
YY = Production Year (Last Two Digits) XXX = Last Three Digits of Assembly Lot Number
WW = Production Week (Two Digits)
G = Pd−Free designator

(WLCSP−5) (WLCSP−4)

2 B
YM YM

2 = Specific Device Code B = Specific Device Code

Y = Production Year (Last Digit) Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D) M = Production Month (1−9, O, N, D)

(TSSOP−8) (UDFN−8)

C5U
C32F AXX
AYMXXX YM

C32F = Specific Device Code C5U = Specific Device Code

A = Assembly Location A = Assembly Location
Y = Production Year (Last Digit) XX = Last Two Digits of Assembly Lot Number
M = Production Month (1−9, O, N, D) Y = Production Year (Last Digit)
XXX = Last Three Digits of Assembly Lot Number M = Production Month (1−9, O, N, D)

VCC
PIN FUNCTION
Pin Name Function
SCL
A0, A1, A2 Device Address
SDA Serial Data
A2, A1, A0 CAT24C32 SDA
SCL Serial Clock
WP WP Write Protect
VCC Power Supply
VSS Ground
VSS

Figure 1. Functional Symbol

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 CAT24C32

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameters Ratings Units
Storage Temperature –65 to +150 °C

Voltage on any Pin with Respect to Ground (Note 1) –0.5 to +6.5 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.

Table 2. RELIABILITY CHARACTERISTICS (Note 2)

Symbol Parameter Min Units
NEND (Note 3) Endurance 1,000,000 Program/Erase Cycles

TDR Data Retention 100 Years

2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.

Table 3. D.C. OPERATING CHARACTERISTICS

(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICCR Read Current Read, fSCL = 400 kHz 1 mA
ICCW Write Current Write, fSCL = 400 kHz 2 mA
ISB Standby Current All I/O Pins at GND or VCC TA = −40°C to +85°C 1 mA
VCC ≤ 3.3 V
TA = −40°C to +85°C 3
VCC > 3.3 V
TA = −40°C to +125°C 5
IL I/O Pin Leakage Pin at GND or VCC 2 mA
VIL Input Low Voltage −0.5 VCC x 0.3 V
VIH Input High Voltage SCL, SDA Inputs VCC x 0.7 6.5 V
WP, A0, A1, A2 Inputs VCC x 0.7 VCC + 0.5
VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V
VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

Table 4. PIN IMPEDANCE CHARACTERISTICS

(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)
Symbol Parameter Conditions Max Units
CIN (Note 4) SDA I/O Pin Capacitance VIN = 0 V, TA = 25°C, f = 1.0 MHz 8 pF
CIN (Note 4) Input Capacitance (other pins) VIN = 0 V, TA = 25°C, f = 1.0 MHz 6 pF
IWP (Note 5) WP Input Current VIN < VIH, VCC = 5.5 V 130 mA
VIN < VIH, VCC = 3.3 V 120
VIN < VIH, VCC = 1.7 V 80
VIN > VIH 2
IA (Note 5) Address Input Current VIN < VIH, VCC = 5.5 V 50 mA
(A0, A1, A2)
Product Rev F VIN < VIH, VCC = 3.3 V 35
VIN < VIH, VCC = 1.7 V 25
VIN > VIH 2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.

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 CAT24C32

Table 5. A.C. CHARACTERISTICS

(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C.) (Note 6)
Fast−Plus (Note 9)
Standard Fast VCC = 2.5 V − 5.5 V
VCC = 1.7 V − 5.5 V VCC = 1.7 V − 5.5 V TA = −405C to +855C
Symbol Parameter Min Max Min Max Min Max Units
FSCL Clock Frequency 100 400 1,000 kHz
tHD:STA START Condition Hold Time 4 0.6 0.25 ms
tLOW Low Period of SCL Clock 4.7 1.3 0.45 ms
tHIGH High Period of SCL Clock 4 0.6 0.40 ms
tSU:STA START Condition Setup Time 4.7 0.6 0.25 ms
tHD:DAT Data In Hold Time 0 0 0 ms
tSU:DAT Data In Setup Time 250 100 50 ns
tR (Note 7) SDA and SCL Rise Time 1,000 300 100 ns
tF (Note 7) SDA and SCL Fall Time 300 300 100 ns
tSU:STO STOP Condition Setup Time 4 0.6 0.25 ms
tBUF Bus Free Time Between STOP 4.7 1.3 0.5 ms
and START
tAA SCL Low to Data Out Valid 3.5 0.9 0.40 ms
tDH (Note 7) Data Out Hold Time 100 100 50 ns
Ti (Note 7) Noise Pulse Filtered at SCL and 100 100 100 ns
SDA Inputs
tSU:WP WP Setup Time 0 0 0 ms
tHD:WP WP Hold Time 2.5 2.5 1 ms
tWR Write Cycle Time 5 5 5 ms
tPU (Notes 7, 8) Power−up to Ready Mode 1 1 1 ms
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
9. Fast−Plus (1 MHz) speed class available for product revision “F”. The die revision “F” is identified by letter “F” or a dedicated marking code
on top of the package.

Table 6. A.C. TEST CONDITIONS

Input Drive Levels 0.2 x VCC to 0.8 x VCC
Input Rise and Fall Time ≤ 50 ns
Input Reference Levels 0.3 x VCC, 0.7 x VCC
Output Reference Level 0.5 x VCC
Output Test Load Current Source IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF

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 CAT24C32

Power−On Reset (POR) I2C Bus Protocol

Each CAT24C32 incorporates Power−On Reset (POR) The 2−wire I2C bus consists of two lines, SCL and SDA,
circuitry which protects the internal logic against powering connected to the VCC supply via pull−up resistors. The
up in the wrong state. The device will power up into Standby Master provides the clock to the SCL line, and either the
mode after VCC exceeds the POR trigger level and will Master or the Slaves drive the SDA line. A ‘0’ is transmitted
power down into Reset mode when VCC drops below the by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data
POR trigger level. This bi−directional POR behavior transfer may be initiated only when the bus is not busy (see
protects the device against ‘brown−out’ failure following a A.C. Characteristics). During data transfer, SDA must
temporary loss of power. remain stable while SCL is HIGH.

Pin Description START/STOP Condition

SCL: The Serial Clock input pin accepts the clock signal An SDA transition while SCL is HIGH creates a START
generated by the Master. or STOP condition (Figure 2). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
SDA: The Serial Data I/O pin accepts input data and delivers the START, a Slave will not respond to the Master. The
output data. In transmit mode, this pin is open drain. Data is STOP completes all commands, and consists of a LOW to
acquired on the positive edge, and is delivered on the HIGH SDA transition, while SCL is HIGH.
negative edge of SCL.
A0, A1 and A2: The Address inputs set the device address Device Addressing
that must be matched by the corresponding Slave address The Master addresses a Slave by creating a START
bits. The Address inputs are hard−wired HIGH or LOW condition and then broadcasting an 8−bit Slave address. For
allowing for up to eight devices to be used (cascaded) on the the CAT24C32, the first four bits of the Slave address are set
same bus. When left floating, these pins are pulled LOW to 1010 (Ah); the next three bits, A2, A1 and A0, must match
internally. The Address inputs are not available for use with the logic state of the similarly named input pins. The devices
WLCSP 4−ball and 5−ball. in WLCSP (C5A and C4C) respond only to the Slave
Address with A2 A1 A0 = 0 0 0. The R/W bit tells the Slave
WP: When pulled HIGH, the Write Protect input pin
whether the Master intends to read (1) or write (0) data
inhibits all write operations. When left floating, this pin is
(Figure 3).
pulled LOW internally. The WP input is not available for the
WLCSP 4−ball, therefore all write operations are allowed Acknowledge
for the device in this package. During the 9th clock cycle following every byte sent to the
bus, the transmitter releases the SDA line, allowing the
Functional Description receiver to respond. The receiver then either acknowledges
The CAT24C32 supports the Inter−Integrated Circuit (ACK) by pulling SDA LOW, or does not acknowledge
(I2C) Bus protocol. The protocol relies on the use of a Master (NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
device, which provides the clock and directs bus traffic, and is illustrated in Figure 5.
Slave devices which execute requests. The CAT24C32
operates as a Slave device. Both Master and Slave can transmit
or receive, but only the Master can assign those roles.

SCL

SDA

START STOP
CONDITION CONDITION

Figure 2. Start/Stop Timing

1 0 1 0 A2 A1 A0 R/W

DEVICE ADDRESS*
* The devices in WLCSP 4−ball and 5−ball respond only to Slave Address byte with A2 A1 A0 = 0 0 0

Figure 3. Slave Address Bits

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 CAT24C32

BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER)

SCL FROM 1 8 9
MASTER

DATA OUTPUT
FROM TRANSMITTER

DATA OUTPUT
FROM RECEIVER

START ACK SETUP (≥ tSU:DAT)

ACK DELAY (≤ tAA)

Figure 4. Acknowledge Timing

tF tHIGH tR
tLOW tLOW

SCL

tSU:STA tHD:DAT
tHD:SDA tSU:DAT tSU:STO

SDA IN
tBUF
tAA tDH

SDA OUT

Figure 5. Bus Timing

WRITE OPERATIONS

Byte Write Acknowledge Polling

To write data to memory, the Master creates a START As soon (and as long) as internal Write is in progress, the
condition on the bus and then broadcasts a Slave address Slave will not acknowledge the Master. This feature enables
with the R/W bit set to ‘0’. The Master then sends two the Master to immediately follow−up with a new Read or
address bytes and a data byte and concludes the session by Write request, rather than wait for the maximum specified
creating a STOP condition on the bus. The Slave responds Write time (tWR) to elapse. Upon receiving a NoACK
with ACK after every byte sent by the Master (Figure 6). The response from the Slave, the Master simply repeats the
STOP starts the internal Write cycle, and while this request until the Slave responds with ACK.
operation is in progress (tWR), the SDA output is tri−stated
and the Slave does not acknowledge the Master (Figure 7). Hardware Write Protection
With the WP pin held HIGH, the entire memory is
Page Write protected against Write operations. If the WP pin is left
The Byte Write operation can be expanded to Page Write, floating or is grounded, it has no impact on the Write
by sending more than one data byte to the Slave before operation. The state of the WP pin is strobed on the last
issuing the STOP condition (Figure 8). Up to 32 distinct data falling edge of SCL immediately preceding the 1st data byte
bytes can be loaded into the internal Page Write Buffer (Figure 9). If the WP pin is HIGH during the strobe interval,
starting at the address provided by the Master. The page the Slave will not acknowledge the data byte and the Write
address is latched, and as long as the Master keeps sending request will be rejected.
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New Delivery State
data can therefore replace data loaded earlier. Following the The CAT24C32 is shipped erased, i.e., all bytes are FFh.
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (tWR).

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 CAT24C32

BUS ACTIVITY: S
T ADDRESS ADDRESS DATA S
A SLAVE BYTE BYTE BYTE T
MASTER R ADDRESS O
T a15 − a8 a7 − a0 d7 − d0 P
S * * * * P

A A A A
SLAVE C C C C
K K K K
*a15 − a12 are don’t care bits
Figure 6. Byte Write Sequence

SCL

SDA 8th Bit ACK

Byte n
tWR
STOP START ADDRESS
CONDITION CONDITION

Figure 7. Write Cycle Timing

BUS
ACTIVITY: S
T DATA DATA DATA S
A SLAVE ADDRESS ADDRESS BYTE BYTE BYTE T
MASTER R ADDRESS BYTE BYTE n n+1 n+P O
T P
S P

SLAVE A A A A A A A
C C C C C C C
n=1 K K K K K K K
P ≤ 31
Figure 8. Page Write Sequence

ADDRESS DATA
BYTE BYTE

1 8 9 1 8
SCL

SDA a7 a0 d7 d0
tSU:WP

WP

tHD:WP

Figure 9. WP Timing

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 CAT24C32

READ OPERATIONS

Immediate Read Write sequence by sending data, the Master then creates a
To read data from memory, the Master creates a START START condition and broadcasts a Slave address with the
condition on the bus and then broadcasts a Slave address R/W bit set to ‘1’. The Slave responds with ACK after every
with the R/W bit set to ‘1’. The Slave responds with ACK byte sent by the Master and then sends out data residing at
and starts shifting out data residing at the current address. the selected address. After receiving the data, the Master
After receiving the data, the Master responds with NoACK responds with NoACK and then terminates the session by
and terminates the session by creating a STOP condition on creating a STOP condition on the bus (Figure 11).
the bus (Figure 10). The Slave then returns to Standby mode.
Sequential Read
Selective Read If, after receiving data sent by the Slave, the Master
To read data residing at a specific address, the selected responds with ACK, then the Slave will continue
address must first be loaded into the internal address register. transmitting until the Master responds with NoACK
This is done by starting a Byte Write sequence, whereby the followed by STOP (Figure 12). During Sequential Read the
Master creates a START condition, then broadcasts a Slave internal byte address is automatically incremented up to the
address with the R/W bit set to ‘0’ and then sends two end of memory, where it then wraps around to the beginning
address bytes to the Slave. Rather than completing the Byte of memory.

N
BUS ACTIVITY S O
T S
A SLAVE A T
MASTER R ADDRESS CO
T K P
S P

A
SLAVE C DATA
K BYTE

SCL 8 9

SDA 8th Bit

DATA OUT NO ACK STOP
Figure 10. Immediate Read Sequence and Timing

BUS ACTIVITY: S S N
T T O S
A SLAVE ADDRESS ADDRESS A SLAVE A T
MASTER R ADDRESS BYTE BYTE R ADDRESS C O
T T K P
S S P

SLAVE A A A A
C C C C DATA
K K K K BYTE

Figure 11. Selective Read Sequence

N
BUS ACTIVITY: O S
SLAVE A A A A T
MASTER ADDRESS C C C C O
K K K K P
P

A
SLAVE C DATA DATA DATA DATA
K BYTE BYTE BYTE BYTE
n n+1 n+2 n+x

Figure 12. Sequential Read Sequence

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 CAT24C32

ORDERING INFORMATION
Specific
Device Package Lead
Device Order Number Marking Type Temperature Range Finish Shipping
CAT24C32HU4I−GT3 C5U UDFN8 I = Industrial NiPdAu Tape & Reel, 3,000 Units / Reel
(−40°C to +85°C)

CAT24C32HU4E−GT3 C5U UDFN8 E = Extended NiPdAu Tape & Reel, 3,000 Units / Reel
(Note 12) (−40°C to +125°C)

CAT24C32C5ATR 2 WLCSP5 I = Industrial SnAgCu Tape & Reel, 5,000 Units / Reel
(−40°C to +85°C)

CAT24C32C5CTR P WLCSP5 with I = Industrial SnAgCu Tape & Reel, 5,000 Units / Reel
Die Coat (−40°C to +85°C)

CAT24C32C4CTR B WLCSP4 with I = Industrial SnAg Tape & Reel, 5,000 Units / Reel
Die Coat (−40°C to +85°C)

CAT24C32LI−G 24C32F PDIP−8 I = Industrial NiPdAu Tube, 50 Units / Tube

(−40°C to +85°C)

CAT24C32WI−G 24C32F SOIC−8, I = Industrial NiPdAu Tube, 100 Units / Tube

JEDEC (−40°C to +85°C)

CAT24C32WI−GT3 24C32F SOIC−8, I = Industrial NiPdAu Tape & Reel, 3,000 Units / Reel
JEDEC (−40°C to +85°C)

CAT24C32WE−GT3 24C32F SOIC−8, E = Extended NiPdAu Tape & Reel, 3,000 Units / Reel
(Note 12) JEDEC (−40°C to +125°C)

CAT24C32YI−G C32F TSSOP−8 I = Industrial NiPdAu Tube, 100 Units / Tube

(−40°C to +85°C)

CAT24C32YI−GT3 C32F TSSOP−8 I = Industrial NiPdAu Tape & Reel, 3,000 Units / Reel
(−40°C to +85°C)

CAT24C32YE−GT3 C32F TSSOP−8 E = Extended NiPdAu Tape & Reel, 3,000 Units / Reel
(Note 12) (−40°C to +125°C)

CAT24C32USI−T3 TBD US8 I = Industrial Matte−Tin Tape & Reel, 3,000 Units / Reel
(In Development) (−40°C to +85°C)
10. All packages are RoHS−compliant (Lead−free, Halogen−free).
11. The standard lead finish is NiPdAu.
12. Please contact your nearest ON Semiconductor Sales office for availability.
13. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
14. Caution: The EEPROM devices delivered in WLCSP must never be exposed to ultraviolet light. When exposed to ultraviolet light
the EEPROM cells lose their stored data.

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 CAT24C32

PACKAGE DIMENSIONS

PDIP−8, 300 mils

CASE 646AA
ISSUE A

SYMBOL MIN NOM MAX

A 5.33
A1 0.38
A2 2.92 3.30 4.95
b 0.36 0.46 0.56

E1 b2 1.14 1.52 1.78

c 0.20 0.25 0.36
D 9.02 9.27 10.16
E 7.62 7.87 8.25
E1 6.10 6.35 7.11
e 2.54 BSC
eB 7.87 10.92
PIN # 1
IDENTIFICATION L 2.92 3.30 3.80
D

TOP VIEW
E

A2
A

A1

c
b2
L

eB
e b

SIDE VIEW END VIEW

Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.

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 CAT24C32

PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD
ISSUE O

SYMBOL MIN NOM MAX

A 1.35 1.75
A1 0.10 0.25
b 0.33 0.51
c 0.19 0.25
E1 E D 4.80 5.00
E 5.80 6.20
E1 3.80 4.00
e 1.27 BSC
h 0.25 0.50
L 0.40 1.27
PIN # 1
IDENTIFICATION θ 0º 8º

TOP VIEW

D h

A1 θ
A

c
e b L

SIDE VIEW END VIEW

Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.

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 CAT24C32

PACKAGE DIMENSIONS

TSSOP8, 4.4x3
CASE 948AL
ISSUE O
b

SYMBOL MIN NOM MAX

A 1.20
A1 0.05 0.15
A2 0.80 0.90 1.05
b 0.19 0.30
E1 E c 0.09 0.20
D 2.90 3.00 3.10
E 6.30 6.40 6.50
E1 4.30 4.40 4.50
e 0.65 BSC
L 1.00 REF
L1 0.50 0.60 0.75
θ 0º 8º

TOP VIEW

A2 c
A q1

A1 L1
L
SIDE VIEW END VIEW

Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.

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 CAT24C32

PACKAGE DIMENSIONS

UDFN8, 2x3 EXTENDED PAD

CASE 517AZ
ISSUE O

D A b e

DAP SIZE 1.8 x 1.8

E E2

PIN #1
IDENTIFICATION

A1
PIN #1 INDEX AREA D2

TOP VIEW SIDE VIEW BOTTOM VIEW

SYMBOL MIN NOM MAX

A 0.45 0.50 0.55
A1 0.00 0.02 0.05
A3 0.127 REF
0.065 REF DETAIL A A3 A
b 0.20 0.25 0.30
D 1.95 2.00 2.05 FRONT VIEW
D2 1.35 1.40 1.45
E 2.95 3.00 3.05
E2 1.25 1.30 1.35
e 0.50 REF
L 0.25 0.30 0.35

0.065 REF
Notes: A3 0.0 - 0.05
Copper Exposed
(1) All dimensions are in millimeters.
(2) Refer JEDEC MO-236/MO-252. DETAIL A

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 CAT24C32

PACKAGE DIMENSIONS

US8
CASE 493−02
ISSUE B NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
−X− 3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR.
A J MOLD FLASH. PROTRUSION AND GATE
8 5 −Y− BURR SHALL NOT EXCEED 0.140 MM
(0.0055”) PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTER−LEAD FLASH OR PROTRUSION.
INTER−LEAD FLASH AND PROTRUSION
DETAIL E SHALL NOT E3XCEED 0.140 (0.0055”) PER
SIDE.
B L 5. LEAD FINISH IS SOLDER PLATING WITH
THICKNESS OF 0.0076−0.0203 MM.
(300−800 “).
6. ALL TOLERANCE UNLESS OTHERWISE
SPECIFIED ±0.0508 (0.0002 “).

1 4 R MILLIMETERS INCHES
G S DIM MIN MAX MIN MAX
P A 1.90 2.10 0.075 0.083
U B 2.20 2.40 0.087 0.094
C 0.60 0.90 0.024 0.035
D 0.17 0.25 0.007 0.010
C F 0.20 0.35 0.008 0.014
G 0.50 BSC 0.020 BSC
−T− 0.10 (0.004) T H H 0.40 REF 0.016 REF
K J 0.10 0.18 0.004 0.007
SEATING D
PLANE N K 0.00 0.10 0.000 0.004
L 3.00 3.20 0.118 0.126
0.10 (0.004) M T X Y R 0.10 TYP M 0_ 6_ 0_ 6_
N 5_ 10 _ 5_ 10 _
P 0.23 0.34 0.010 0.013
V R 0.23 0.33 0.009 0.013
M S 0.37 0.47 0.015 0.019
U 0.60 0.80 0.024 0.031
V 0.12 BSC 0.005 BSC

F
DETAIL E

SOLDERING FOOTPRINT*
3.8
0.15

0.50 1.8
0.0197 0.07

0.30
0.012

1.0
0.0394
SCALE 8:1 ǒinches
mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com
14
 CAT24C32

PACKAGE DIMENSIONS

WLCSP5, 1.34x0.91
CASE 567JQ
ISSUE A
E A B NOTES:

ÈÈ
1. DIMENSIONING AND TOLERANCING PER ASME
PIN A1 Y14.5M, 1994.

ÈÈ
REFERENCE 2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
D 4. DIMENSION b IS MEASURED AT THE MAXIMUM
BALL DIAMETER PARALLEL TO DATUM C.
DIE COAT
2X 0.10 C (OPTIONAL) A3 MILLIMETERS
A2 DIM MIN MAX
A −−− 0.35
2X 0.10 C A1 0.08 0.12
TOP VIEW
A2 0.23 REF
A3 0.025 REF
DETAIL A A2 b 0.16 0.20
D 1.34 BSC
DETAIL A
0.10 C E 0.91 BSC
e 0.40 BSC
A e1 0.693 BSC
0.05 C
A1
SEATING
NOTE 3 SIDE VIEW C PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
PACKAGE
5X b e OUTLINE
A1
0.05 C A B e1
C 5X
0.03 C 0.18
B 0.69
PITCH
A

1 2 3
BOTTOM VIEW
0.40
PITCH
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com
15
 CAT24C32

PACKAGE DIMENSIONS

WLCSP4, 0.76x0.76
CASE 567JY
ISSUE O

ÈÈ
NOTES:
D A B 1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.

ÈÈ
PIN A1 2. CONTROLLING DIMENSION: MILLIMETERS.
REFERENCE 3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
E
2X 0.05 C MILLIMETERS
DIE COAT
A3 DIM MIN MAX
(OPTIONAL) A2 A −−− 0.35
2X 0.05 C TOP VIEW A1 0.0415 0.0715
A2 0.255 REF
A3 0.025 REF
b 0.15 0.16
DETAIL A DETAIL A D 0.76 BSC
A2 E 0.76 BSC
0.05 C e 0.40 BSC

A
0.05 C RECOMMENDED
A1 SEATING SOLDERING FOOTPRINT*
NOTE 3
SIDE VIEW C PLANE
A1 PACKAGE
OUTLINE

e
4X b e
4X
0.05 C A B 0.40
B 0.16
PITCH 0.40
0.03 C
A PITCH
1 2 DIMENSIONS: MILLIMETERS

BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.

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16