CAT24C128

128 kb I2C CMOS Serial

EEPROM
Description
The CAT24C128 is a 128 kb Serial CMOS EEPROM, internally
organized as 16,384 words of 8 bits each. http://onsemi.com
It features a 64−byte page write buffer and supports both the
Standard (100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C
protocol.
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory).
On−Chip ECC (Error Correction Code) makes the device suitable
PDIP−8 UDFN−8 TSSOP−8
for high reliability applications.* L SUFFIX HU4 SUFFIX Y SUFFIX
CASE 646AA CASE 517AZ CASE 948AL
Features
• Supports Standard, Fast and Fast−Plus I2C Protocol
• 1.8 V to 5.5 V Supply Voltage Range
• 64−Byte Page Write Buffer
SOIC−8 MSOP−8 UDFN−8***
• Hardware Write Protection for Entire Memory W SUFFIX Z SUFFIX HU3 SUFFIX
• Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs CASE 751BD CASE 846AD CASE 517AX
(SCL and SDA)
• Low Power CMOS Technology PIN CONFIGURATION
• 1,000,000 Program/Erase Cycles
A0 1 VCC
• 100 Year Data Retention
A1
• Industrial and Extended Temperature Range WP

• 8−lead PDIP, SOIC, TSSOP, MSOP and UDFN Packages A2 SCL

• This Device is Pb−Free, Halogen Free/BFR Free and RoHS VSS SDA
Compliant** PDIP (L), SOIC (W), TSSOP (Y), MSOP
(Z), UDFN (HU3***), UDFN (HU4)
VCC
For the location of Pin 1, please consult the
corresponding package drawing.
*** Not recommended for new design.
SCL

PIN FUNCTION
A2, A1, A0 CAT24C128 SDA
Pin Name† Function
WP A0, A1, A2 Device Address Inputs
SDA Serial Data Input/Output
SCL Serial Clock Input
VSS
WP Write Protect Input
Figure 1. Functional Symbol
VCC Power Supply

*Available for New Product (Rev. C) VSS Ground

** For additional information on our Pb−Free strategy and soldering details, †The exposed pad for the TDFN/UDFN packages can
please download the ON Semiconductor Soldering and Mounting Techniques be left floating or connected to Ground.
Reference Manual, SOLDERRM/D.

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.

© Semiconductor Components Industries, LLC, 2013 1 Publication Order Number:

August, 2013 − Rev. 15 CAT24C128/D
 CAT24C128

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Rating Units
Storage Temperature −65 to +150 °C
Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.

Table 2. RELIABILITY CHARACTERISTICS (Note 2)

Symbol Parameter Min Units
NEND (Notes 3, 4) Endurance 1,000,000 Program / Erase Cycles
TDR Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C
4. The new product revision (C) uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when
a single byte has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order
to benefit from the maximum number of write cycles.

Table 3. D.C. OPERATING CHARACTERISTICS − Mature Product (Rev B)

(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICCR Read Current Read, fSCL = 400 kHz 1 mA
ICCW Write Current Write, fSCL = 400 kHz 3 mA
ISB Standby Current All I/O Pins at GND or VCC TA = −40°C to +85°C 1 mA
TA = −40°C to +125°C 2
IL I/O Pin Leakage Pin at GND or VCC TA = −40°C to +85°C 1 mA
TA = −40°C to +125°C 2
VIL Input Low Voltage −0.5 VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V
VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V

Table 4. PIN IMPEDANCE CHARACTERISTICS − Mature Product (Rev B)

(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol Parameter Conditions Max Units
CIN (Note 5) SDA I/O Pin Capacitance VIN = 0 V 8 pF
CIN (Note 5) Input Capacitance (other pins) VIN = 0 V 6 pF
IWP (Note 6) WP Input Current VIN < VIH 200 mA
VIN > VIH 1 mA
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
6. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong;
therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.

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 CAT24C128

Table 5. D.C. OPERATING CHARACTERISTICS − New Product (Rev C) (Note 7)

(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICCR Read Current Read, fSCL = 400 kHz/1 MHz 1 mA
ICCW Write Current 3 mA
ISB Standby Current All I/O Pins at GND or VCC TA = −40°C to +85°C 2 mA
TA = −40°C to +125°C 5
IL I/O Pin Leakage Pin at GND or VCC TA = −40°C to +85°C 1 mA
TA = −40°C to +125°C 2
VIL1 Input Low Voltage 2.5 V ≤ VCC ≤ 5.5 V −0.5 0.3 VCC V
VIL2 Input Low Voltage 1.8 V ≤ VCC < 2.5 V −0.5 0.25 VCC V
VIH1 Input High Voltage 2.5 V ≤ VCC ≤ 5.5 V 0.7 VCC VCC + 0.5 V
VIH2 Input High Voltage 1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC + 0.5 V
VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V
VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V

Table 6. PIN IMPEDANCE CHARACTERISTICS − New Product (Rev C) (Note 7)

(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.)
Symbol Parameter Conditions Max Units
CIN (Note 8) SDA I/O Pin Capacitance VIN = 0 V 8 pF
CIN (Note 8) Input Capacitance (other pins) VIN = 0 V 6 pF
IWP, IA (Note 9) WP Input Current, Address Input VIN < VIH, VCC = 5.5 V 75 mA
Current (A0, A1, A2)
VIN < VIH, VCC = 3.3 V 50
VIN < VIH, VCC = 1.8 V 25
VIN > VIH 2
7. The product Rev C is identified by letter “C” or dedicated marking code on top of the package.
8. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
9. When not driven, the WP, A0, A1, A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.

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 CAT24C128

Table 7. A.C. CHARACTERISTICS

(VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C) (Note 10)
Fast−Plus (Note 13)
Standard Fast VCC = 2.5 V − 5.5 V
VCC = 1.8 V − 5.5 V VCC = 1.8 V − 5.5 V TA = −405C to +855C

Symbol Parameter Min Max Min Max Min Max Units

FSCL Clock Frequency 100 400 1,000 kHz
tHD:STA START Condition Hold Time 4 0.6 0.25 ms
tLOW Low Period of SCL Clock 4.7 1.3 0.45 ms
tHIGH High Period of SCL Clock 4 0.6 0.40 ms
tSU:STA START Condition Setup Time 4.7 0.6 0.25 ms
tHD:DAT Data In Hold Time 0 0 0 ms
tSU:DAT Data In Setup Time 250 100 50 ns
tR (Note 11) SDA and SCL Rise Time 1,000 300 100 ns
tF (Note 11) SDA and SCL Fall Time 300 300 100 ns
tSU:STO STOP Condition Setup Time 4 0.6 0.25 ms
tBUF Bus Free Time Between 4.7 1.3 0.5 ms
STOP and START

tAA SCL Low to Data Out Valid 3.5 0.9 0.40 ms

tDH Data Out Hold Time 100 100 50 ns
Ti (Note 11) Noise Pulse Filtered at SCL 100 100 50 ns
and SDA Inputs

tSU:WP WP Setup Time 0 0 0 ms

tHD:WP WP Hold Time 2.5 2.5 1 ms
tWR Write Cycle Time 5 5 5 ms
tPU Power-up to Ready Mode 1 1 0.1 1 ms
(Notes 11, 12)
10. Test conditions according to “A.C. Test Conditions” table.
11. Tested initially and after a design or process change that affects this parameter.
12. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
13. Fast−Plus (1 MHz) speed class available for new product revision “C”. The die revision “C” is identified by letter “C” or a dedicated marking
code on top of the package.

Table 8. A.C. TEST CONDITIONS

Input Levels 0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times v 50 ns
Input Reference Levels 0.3 x VCC, 0.7 x VCC
Output Reference Levels 0.5 x VCC
Output Load Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF

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 CAT24C128

Power−On Reset (POR) resistors. Master and Slave devices connect to the 2−wire
The CAT24C128 incorporates Power−On Reset (POR) bus via their respective SCL and SDA pins. The transmitting
circuitry which protects the device against powering up in device pulls down the SDA line to ‘transmit’ a ‘0’ and
the wrong state. releases it to ‘transmit’ a ‘1’.
The CAT24C128 will power up into Standby mode after Data transfer may be initiated only when the bus is not
VCC exceeds the POR trigger level and will power down into busy (see A.C. Characteristics).
Reset mode when VCC drops below the POR trigger level. During data transfer, the SDA line must remain stable
This bi−directional POR feature protects the device against while the SCL line is HIGH. An SDA transition while SCL
‘brown−out’ failure following a temporary loss of power. is HIGH will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
Pin Description consists of a HIGH to LOW transition on SDA while SCL
SCL: The Serial Clock input pin accepts the Serial Clock is HIGH. The START acts as a ‘wake−up’ call to all
generated by the Master. receivers. Absent a START, a Slave will not respond to
SDA: The Serial Data I/O pin receives input data and commands. The STOP condition completes all commands.
transmits data stored in EEPROM. In transmit mode, this pin It consists of a LOW to HIGH transition on SDA while SCL
is open drain. Data is acquired on the positive edge, and is is HIGH.
delivered on the negative edge of SCL.
Device Addressing
A0, A1 and A2: The Address pins accept the device address. The Master initiates data transfer by creating a START
When not driven, these pins are pulled LOW internally. condition on the bus. The Master then broadcasts an 8−bit
WP: The Write Protect input pin inhibits all write serial Slave address. The first 4 bits of the Slave address are
operations, when pulled HIGH. When not driven, this pin is set to 1010, for normal Read/Write operations (Figure 3).
pulled LOW internally. The next 3 bits, A2, A1 and A0, select one of 8 possible Slave
devices and must match the state of the external address pins.
Functional Description The last bit, R/W, specifies whether a Read (1) or Write (0)
The CAT24C128 supports the Inter−Integrated Circuit operation is to be performed.
(I2C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device Acknowledge
receiving data as a receiver. Data flow is controlled by a After processing the Slave address, the Slave responds
Master device, which generates the serial clock and all with an acknowledge (ACK) by pulling down the SDA line
START and STOP conditions. The CAT24C128 acts as a during the 9th clock cycle (Figure 4). The Slave will also
Slave device. Master and Slave alternate as either acknowledge all address bytes and every data byte presented
transmitter or receiver. Up to 8 devices may be connected to in Write mode. In Read mode the Slave shifts out a data byte,
the bus as determined by the device address inputs A0, A1, and then releases the SDA line during the 9th clock cycle. As
and A2. long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
I2C Bus Protocol not acknowledging the last data byte (NoACK) and by
The I2C bus consists of two ‘wires’, SCL and SDA. The issuing a STOP condition. Bus timing is illustrated in
two wires are connected to the VCC supply via pull−up Figure 5.

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 CAT24C128

SCL

SDA

START STOP
CONDITION CONDITION
Figure 2. START/STOP Conditions

DEVICE ADDRESS

1 0 1 0 A2 A1 A0 R/W

Figure 3. Slave Address Bits

BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER)

SCL FROM 1 8 9
MASTER

DATA OUTPUT
FROM TRANSMITTER

DATA OUTPUT
FROM RECEIVER

START ACK SETUP (≥ tSU:DAT)

ACK DELAY (≤ tAA)

Figure 4. Acknowledge Timing

tF tHIGH tR
tLOW tLOW

SCL

tSU:STA tHD:DAT
tHD:STA tSU:DAT tSU:STO

SDA IN

tBUF
tAA tDH

SDA OUT

Figure 5. Bus Timing

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 CAT24C128

Write Operations latched and the address count automatically increments to

and then wraps−around at the page boundary. Previously
Byte Write loaded data can thus be overwritten by new data. What is
Upon receiving a Slave address with the R/W bit set to ‘0’, eventually written to memory reflects the latest Page Write
the CAT24C128 will interpret the next two bytes as address Buffer contents. Only data loaded within the most recent
bytes. These bytes are used to initialize the internal address Page Write sequence will be written to memory.
counter; the 2 most significant bits are ‘don’t care’, the next
8 point to one of 256 available pages and the last 6 point to Acknowledge Polling
a location within a 64 byte page. A byte following the The ready/busy status of the CAT24C128 can be
address bytes will be interpreted as data. The data will be ascertained by sending Read or Write requests immediately
loaded into the Page Write Buffer and will eventually be following the STOP condition that initiated the internal
written to memory at the address specified by the 14 active Write cycle. As long as internal Write is in progress, the
address bits provided earlier. The CAT24C128 will CAT24C128 will not acknowledge the Slave address.
acknowledge the Slave address, address bytes and data byte.
The Master then starts the internal Write cycle by issuing a Hardware Write Protection
STOP condition (Figure 6). During the internal Write cycle With the WP pin held HIGH, the entire memory is
(tWR), the SDA output will be tri−stated and additional Read protected against Write operations. If the WP pin is left
or Write requests will be ignored (Figure 7). floating or is grounded, it has no impact on the operation of
the CAT24C128. The state of the WP pin is strobed on the
Page Write last falling edge of SCL immediately preceding the first data
By continuing to load data into the Page Write Buffer after byte (Figure 9). If the WP pin is HIGH during the strobe
the 1st data byte and before issuing the STOP condition, up interval, the CAT24C128 will not acknowledge the data byte
to 64 bytes can be written simultaneously during one and the Write request will be rejected.
internal Write cycle (Figure 8). If more data bytes are loaded
than locations available to the end of page, then loading will Delivery State
continue from the beginning of page, i.e. the page address is The CAT24C128 is shipped erased, i.e., all bytes are FFh.

BUS ACTIVITY: S
T ADDRESS ADDRESS S
A SLAVE BYTE BYTE DATA T
MASTER R ADDRESS a13−a8 a7−a0 BYTE O
T P

S * * P

A A A A
SLAVE C C C C
K K K K
* = Don’t Care Bit

Figure 6. Byte Write Sequence

SCL

SDA 8th Bit ACK

Byte n
tWR
STOP START ADDRESS
CONDITION CONDITION

Figure 7. Write Cycle Timing

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 CAT24C128

BUS ACTIVITY: S
T ADDRESS ADDRESS DATA DATA DATA S
A SLAVE BYTE BYTE BYTE BYTE BYTE T
MASTER R ADDRESS a13−a8 a7−a0 n n+1 n+P O
T P

S * * P

A A A A A A A
SLAVE C C C C C C C
K K K K K K K
* = Don’t Care Bit
P v 63 Figure 8. Page Write Sequence

ADDRESS DATA
BYTE BYTE

1 8 9 1 8
SCL

SDA a7 a0 d7 d0
tSU:WP

WP

tHD:WP

Figure 9. WP Timing

Read Operations with data, the Master instead follows up with an Immediate
Read sequence, then the CAT24C128 will use the 14 active
Immediate Read address bits to initialize the internal address counter and will
Upon receiving a Slave address with the R/W bit set to ‘1’, shift out data residing at the corresponding location. If the
the CAT24C128 will interpret this as a request for data Master does not acknowledge the data (NoACK) and then
residing at the current byte address in memory. The follows up with a STOP condition (Figure 11), the
CAT24C128 will acknowledge the Slave address, will CAT24C128 returns to Standby mode.
immediately shift out the data residing at the current address,
and will then wait for the Master to respond. If the Master Sequential Read
does not acknowledge the data (NoACK) and then follows If during a Read session the Master acknowledges the 1st
up with a STOP condition (Figure 10), the CAT24C128 data byte, then the CAT24C128 will continue transmitting
returns to Standby mode. data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure 12).
Selective Read In contrast to Page Write, during Sequential Read the
To read data residing at a specific location, the internal address count will automatically increment to and then
address counter must first be initialized as described under wrap−around at end of memory (rather than end of page).
Byte Write. If rather than following up the two address bytes

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 CAT24C128

BUS ACTIVITY: S N
T O S
A SLAVE A T
MASTER R ADDRESS C O
T K P

S P

A
SLAVE C DATA
K BYTE

SCL 8 9

SDA 8th Bit

DATA OUT NO ACK STOP

Figure 10. Immediate Read Sequence and Timing

BUS ACTIVITY: S S N
T ADDRESS ADDRESS T O S
A SLAVE BYTE BYTE A SLAVE A T
MASTER R ADDRESS a13−a8 a7−a0 R ADDRESS C O
T T K P

S * * S P

A A A A DATA
SLAVE C C C C
K K K K BYTE
* = Don’t Care Bit
Figure 11. Selective Read Sequence

N
BUS ACTIVITY: O S
SLAVE A T
MASTER ADDRESS C O
K P

A A A A
C DATA C DATA DATA DATA
SLAVE C C
K BYTE K BYTE K BYTE K BYTE
n n+1 n+2 n+x

Figure 12. Sequential Read Sequence

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 CAT24C128

PACKAGE DIMENSIONS

PDIP−8, 300 mils

CASE 646AA−01
ISSUE A

SYMBOL MIN NOM MAX

A 5.33
A1 0.38
A2 2.92 3.30 4.95
b 0.36 0.46 0.56

E1 b2 1.14 1.52 1.78

c 0.20 0.25 0.36
D 9.02 9.27 10.16
E 7.62 7.87 8.25
E1 6.10 6.35 7.11
e 2.54 BSC
eB 7.87 10.92
PIN # 1
IDENTIFICATION L 2.92 3.30 3.80
D

TOP VIEW
E

A2
A

A1

c
b2
L

eB
e b

SIDE VIEW END VIEW

Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.

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 CAT24C128

PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD−01
ISSUE O

SYMBOL MIN NOM MAX

A 1.35 1.75
A1 0.10 0.25
b 0.33 0.51
c 0.19 0.25
E1 E D 4.80 5.00
E 5.80 6.20
E1 3.80 4.00
e 1.27 BSC
h 0.25 0.50
L 0.40 1.27
PIN # 1
IDENTIFICATION θ 0º 8º

TOP VIEW

D h

A1 θ
A

c
e b L

SIDE VIEW END VIEW

Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.

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 CAT24C128

PACKAGE DIMENSIONS

TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b

SYMBOL MIN NOM MAX

A 1.20
A1 0.05 0.15
A2 0.80 0.90 1.05
b 0.19 0.30
E1 E c 0.09 0.20
D 2.90 3.00 3.10
E 6.30 6.40 6.50
E1 4.30 4.40 4.50
e 0.65 BSC
L 1.00 REF
L1 0.50 0.60 0.75
θ 0º 8º

TOP VIEW

A2 c
A q1

A1 L1
L
SIDE VIEW END VIEW

Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.

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 CAT24C128

PACKAGE DIMENSIONS

UDFN8, 2x3
CASE 517AX−01
ISSUE O

D A

DETAIL A

DAP SIZE 1.3 x 1.8

PIN #1
E2 IDENTIFICATION

A1
PIN #1 INDEX AREA D2

TOP VIEW SIDE VIEW BOTTOM VIEW

SYMBOL MIN NOM MAX

b
A 0.45 0.50 0.55
A1 0.00 0.02 0.05
L
A3 0.127 REF
K
b 0.20 0.25 0.30
e
D 1.90 2.00 2.10
DETAIL A
D2 1.50 1.60 1.70
E 2.90 3.00 3.10
E2 0.10 0.20 0.30
e 0.50 TYP
K 0.10 REF A3
A
L 0.30 0.35 0.40

Notes: A1
(1) All dimensions are in millimeters. FRONT VIEW
(2) Complies with JEDEC MO-229.

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 CAT24C128

PACKAGE DIMENSIONS

MSOP 8, 3x3
CASE 846AD−01
ISSUE O

SYMBOL MIN NOM MAX

A 1.10
A1 0.05 0.10 0.15
A2 0.75 0.85 0.95
b 0.22 0.38
c 0.13 0.23

E E1 D 2.90 3.00 3.10

E 4.80 4.90 5.00
E1 2.90 3.00 3.10
e 0.65 BSC
L 0.40 0.60 0.80
L1 0.95 REF
L2 0.25 BSC
θ 0º 6º

TOP VIEW

A A2
DETAIL A

A1 e b c

SIDE VIEW END VIEW

L2

Notes: L
(1) All dimensions are in millimeters. Angles in degrees. L1
(2) Complies with JEDEC MO-187.
DETAIL A

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 CAT24C128

PACKAGE DIMENSIONS

UDFN8, 2x3 EXTENDED PAD

CASE 517AZ−01
ISSUE O

D A b e

DAP SIZE 1.8 x 1.8

E E2

PIN #1
IDENTIFICATION

A1
PIN #1 INDEX AREA D2

TOP VIEW SIDE VIEW BOTTOM VIEW

SYMBOL MIN NOM MAX

A 0.45 0.50 0.55
A1 0.00 0.02 0.05
A3 0.127 REF
DETAIL A A3 A
b 0.20 0.25 0.30 0.065 REF
D 1.95 2.00 2.05 FRONT VIEW
D2 1.35 1.40 1.45
E 2.95 3.00 3.05
E2 1.25 1.30 1.35
e 0.50 REF
L 0.25 0.30 0.35

0.065 REF
Notes: A3 0.0 - 0.05
Copper Exposed
(1) All dimensions are in millimeters.
(2) Refer JEDEC MO-236/MO-252. DETAIL A

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 CAT24C128

ORDERING INFORMATION (Notes 14 thru 19)

Specific
Device Package
Device Order Number Marking* Type Temperature Range Lead Finish Shipping
CAT24C128LI−G 24128C PDIP−8 I = Industrial NiPdAu Tube, 50 Units / Tube
(−40°C to +85°C)

CAT24C128LE−G 24128C PDIP−8 E = Extended NiPdAu Tube, 50 Units / Tube

(−40°C to +125°C)

CAT24C128WI−GT3 24128C SOIC−8, I = Industrial NiPdAu Tape & Reel,

JEDEC (−40°C to +85°C) 3,000 Units / Reel

CAT24C128WE−GT3 24128C SOIC−8, E = Extended NiPdAu Tape & Reel,

JEDEC (−40°C to +125°C) 3,000 Units / Reel

CAT24C128YI−GT3 C28C TSSOP−8 I = Industrial NiPdAu Tape & Reel,

(−40°C to +85°C) 3,000 Units / Reel

CAT24C128YE−GT3 C28C TSSOP−8 E = Extended NiPdAu Tape & Reel,

(−40°C to +125°C) 3,000 Units / Reel

CAT24C128HU4IGT3 C7U UDFN−8 I = Industrial NiPdAu Tape & Reel,

(Note 19) (−40°C to +85°C) 3,000 Units / Reel

CAT24C128HU4EGT3 C7U UDFN−8 E = Extended NiPdAu Tape & Reel,

(Note 19) (−40°C to +125°C) 3,000 Units / Reel

CAT24C128HU3IGT3** BB UDFN−8 I = Industrial NiPdAu Tape & Reel,

(−40°C to +85°C) 3,000 Units / Reel

CAT24C128ZI−GT3 C7 MSOP−8 I = Industrial NiPdAu Tape & Reel,

(−40°C to +85°C) 3,000 Units / Reel

CAT24C128ZE−GT3 C7 MSOP−8 E = Extended NiPdAu Tape & Reel,

(−40°C to +125°C) 3,000 Units / Reel
14. All packages are RoHS−compliant (Lead−free, Halogen−free).
15. The standard lead finish is NiPdAu.
16. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
17. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
18. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
19. There are NO hyphens in the orderable part numbers.
*Marking for New Product (Rev C).
** Not recommended for new designs.

ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative

http://onsemi.com CAT24C128/D
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