CAT24C64

64-Kb I2C CMOS Serial EEPROM

FEATURES DEVICE DESCRIPTION

■ Supports Standard and Fast I2C Protocol The CAT24C64 is a 64-Kb Serial CMOS EEPROM,
■ 1.8 V to 5.5 V Supply Voltage Range internally organized as 128 pages of 64 bytes each, for
a total of 8,192 bytes of 8 bits each.
■ 64-Byte Page Write Buffer
It features a 64-byte page write buffer and supports
■ Hardware Write Protection for entire memory
both the Standard (100 kHz) as well as Fast (400 kHz)
■ Schmitt Triggers and Noise Suppression Filters I2C protocol.
on I2C Bus Inputs (SCL and SDA).
Write operations can be inhibited by taking the WP pin
■ Low power CMOS technology
High (this protects the entire memory).
■ 1,000,000 program/erase cycles
The CAT24C64 is available in RoHS compliant “Green”
■ 100 year data retention and “Gold” 8-lead PDIP, SOIC, TSSOP and TDFN
■ RoHS compliant “ ”&“ ” packages.
8-pin PDIP, SOIC, TSSOP and TDFN packages
■ Industrial temperature range

PIN CONFIGURATION FUNCTIONAL SYMBOL

PDIP (L)
SOIC (W)
TSSOP (Y) VCC
TDFN (ZD2)

A0 1 8 VCC SCL
A1 2 7 WP
A2 3 6 SCL
A2, A1, A0 CAT24C64 SDA
VSS 4 5 SDA

For the location of Pin 1, please consult the WP

corresponding package drawing.

VSS
PIN FUNCTIONS

A0, A1, A2 Device Address

SDA Serial Data
SCL Serial Clock
WP Write Protect
VCC Power Supply
VSS Ground * Catalyst carries the I2C protocol under a license from the Philips Corporation.

© 2005 by Catalyst Semiconductor, Inc. Doc. No. 1102, Rev. C

Characteristics subject to change without notice 1
CAT24C64

ABSOLUTE MAXIMUM RATINGS*

Storage Temperature -65°C to +150°C

Voltage on Any Pin with Respect to Ground(1) -0.5 V to +6.5 V
* Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

RELIABILITY CHARACTERISTICS(2)

Symbol Parameter Min Units

NEND(*) Endurance 1,000,000 Program/ Erase Cycles
TDR Data Retention 100 Years
(*) Page Mode, VCC = 5 V, 25°C

D.C. OPERATING CHARACTERISTICS

VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.

Symbol Parameter Test Conditions Min Max Units

ICC Supply Current Read or Write at 400 kHz 1 mA
ISB Standby Current All I/O Pins at GND or VCC 1 μA
IL I/O Pin Leakage Pin at GND or VCC 1 μA
VIL Input Low Voltage -0.5 VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low Voltage VCC > 2.5 V, IOL = 3.0 mA 0.4 V
VOL2 Output Low Voltage VCC > 1.8 V, IOL = 1.0 mA 0.2 V

PIN IMPEDANCE CHARACTERISTICS

TA = 25°C, f = 400 kHz, VCC = 5 V

Symbol Parameter Conditions Min Max Units

CIN(2) SDA I/O Pin Capacitance VIN = 0 V 8 pF
CIN(2) Input Capacitance (other pins) VIN = 0 V 6 pF
ZWPL WP Input Low Impedance VIN < 0.5 V 5 70 kΩ
ILWPH WP Input High Leakage VIN > VCC x 0.7 1 μA
Note:
(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.

Doc. No. 1102, Rev. C © 2005 by Catalyst Semiconductor, Inc.

2 Characteristics subject to change without notice
 CAT24C64

A.C. CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.

1.8 V - 5.5 V 2.5 V - 5.5 V

Symbol Parameter Min Max Min Max Units
FSCL Clock Frequency 100 400 kHz
TI(1) Noise Suppression Time Constant at 0.1 0.1 μs
SCL, SDA Inputs
tAA(2) SCL Low to SDA Data Out 3.5 0.9 μs
tBUF(1) Time the Bus Must be Free Before a 4.7 1.3 μs
New Transmission Can Start
tHD:STA Start Condition Hold Time 4 0.6 μs
tLOW Clock Low Period 4.7 1.3 μs
tHIGH Clock High Period 4 0.6 μs
tSU:STA Start Condition Setup Time 4.7 0.6 μs
tHD:DAT Data In Hold Time 0 0 μs
tSU:DAT Data In Setup Time 0.25 0.1 μs
tR(1) SDA and SCL Rise Time 1 0.3 μs
tF(1) SDA and SCL Fall Time 0.3 0.3 μs
tSU:STO Stop Condition Setup Time 4 0.6 μs
tDH Data Out Hold Time 0.1 0.1 μs
tWR Write Cycle Time 5 5 ms
tPU(1), (3) Power-up to Ready Mode 1 1 ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) For timing measurements the SDA line capacitance is ~ 100 pF; the SCL input is driven with rise and fall times of < 50 ns; the SDA I/O
is pulled-up by a 3 mA current source; input driving signals swing from 20% to 80% of VCC. Output level reference levels are 30% and
respectively 70% of VCC.
(3) tPU is the delay required from the time VCC is stable until the device is ready to accept commands.

Power-On Reset (POR)

The CAT24C64 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state.

The CAT24C64 will power up into Standby mode after

VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.

The POR circuitry triggers at the minimum VCC level

required for proper initialization of the internal state
machines. The POR trigger level automatically tracks the
internal CMOS device thresholds, and is naturally well
below the minimum recommended VCC supply voltage.

© 2005 by Catalyst Semiconductor, Inc. Doc No. 1102, Rev. C

Characteristics subject to change without notice 3
CAT24C64

PIN DESCRIPTION START

SCL: The Serial Clock input pin accepts the Serial Clock The START condition precedes all commands. It consists
generated by the Master. of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake-up’ call to all receivers. Absent
SDA: The Serial Data I/O pin receives input data and a START, a Slave will not respond to commands.
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge, STOP
and is delivered on the negative edge of SCL. The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
A0, A1 and A2: The Address pins accept the device ad- The STOP starts the internal Write cycle (when follow-
dress. These pins have on-chip pull-down resistors. ing a Write command) or sends the Slave into standby
WP: The Write Protect input pin inhibits all write op- mode (when following a Read command).
erations, when pulled HIGH. This pin has an on-chip Device Addressing
pull-down resistor.
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
FUNCTIONAL DESCRIPTION 8-bit serial Slave address. The first 4 bits of the Slave
address are set to 1010, for normal Read/Write opera-
The CAT24C64 supports the Inter-Integrated Circuit (I2C)
tions (Figure 2). The next 3 bits, A2, A1 and A0, select
Bus data transmission protocol, which defines a device
one of 8 possible Slave devices. The last bit, R/W,
that sends data to the bus as a transmitter and a device
specifies whether a Read (1) or Write (0) operation is
receiving data as a receiver. Data flow is controlled by
to be performed.
a Master device, which generates the serial clock and
all START and STOP conditions. The CAT24C64 acts Acknowledge
as a Slave device. Master and Slave alternate as either
After processing the Slave address, the Slave responds
transmitter or receiver. Up to 8 devices may be connected
with an acknowledge (ACK) by pulling down the SDA
to the bus as determined by the device address inputs
line during the 9th clock cycle (Figure 3). The Slave will
A0, A1, and A2.
also acknowledge the byte address and every data
byte presented in Write mode. In Read mode the Slave
I2C BUS PROTOCOL shifts out a data byte, and then releases the SDA line
during the 9th clock cycle. If the Master acknowledges
The I2C bus consists of two ‘wires’, SCL and SDA. The the data, then the Slave continues transmitting. The
two wires are connected to the VCC supply via pull-up Master terminates the session by not acknowledging
resistors. Master and Slave devices connect to the 2- the last data byte (NoACK) and by sending a STOP to
wire bus via their respective SCL and SDA pins. The the Slave. Bus timing is illustrated in Figure 4.
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).

During data transfer, the SDA line must remain stable

while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1).

Doc. No. 1102, Rev. C © 2005 by Catalyst Semiconductor, Inc.

4 Characteristics subject to change without notice
 CAT24C64

Figure 1. Start/Stop Timing

SDA

SCL

START BIT STOP BIT

Figure 2. Slave Address Bits

1 0 1 0 A2 A1 A0 R/W

DEVICE ADDRESS

Figure 3. Acknowledge Timing

SCL FROM 1 8 9
MASTER

DATA OUTPUT
FROM TRANSMITTER

DATA OUTPUT
FROM RECEIVER

START ACKNOWLEDGE

Figure 4. Bus Timing

tF tHIGH tR
tLOW tLOW

SCL

tSU:STA tHD:DAT
tHD:STA tSU:DAT tSU:STO

SDA IN
tBUF
tAA tDH

SDA OUT

© 2005 by Catalyst Semiconductor, Inc. Doc No. 1102, Rev. C

Characteristics subject to change without notice 5
CAT24C64

WRITE OPERATIONS
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, two byte address and data to be
written (Figure 5). The Slave acknowledges all 4 bytes,
and the Master then follows up with a STOP, which in
turn starts the internal Write operation (Figure 6). During
internal Write, the Slave will not acknowledge any Read
or Write request from the Master.

Page Write
The CAT24C64 contains 8,192 bytes of data, arranged
in 128 pages of 64 bytes each. A two byte address word,
following the Slave address, points to the first byte to be
written. The 3 most significant bits of the address word
are ‘don’t care’, the next 7 bits identify the page and the
last 6 bits identify the byte within the page. Up to 64 bytes
can be written in one Write cycle (Figure 7).

The internal byte address counter is automatically in-

cremented after each data byte is loaded. If the Master
transmits more than 64 data bytes, then earlier bytes will
be overwritten by later bytes in a ‘wrap-around’ fashion
(within the selected page). The internal Write cycle starts
immediately following the STOP.

Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT24C64 is busy writing or is ready to accept com-
mands. Polling is implemented by interrogating the
device with a ‘Selective Read’ command (see READ
OPERATIONS).

The CAT24C64 will not acknowledge the Slave address,

as long as internal Write is in progress.

Hardware Write Protection

With the WP pin held HIGH, the entire memory is pro-
tected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation
of the CAT24C64.

Doc. No. 1102, Rev. C © 2005 by Catalyst Semiconductor, Inc.

6 Characteristics subject to change without notice
 CAT24C64

Figure 5. Byte Write Timing

S
T S
BUS ACTIVITY: A SLAVE BYTE ADDRESS T
MASTER R ADDRESS A15–A8 A7–A0 DATA O
T P
SDA LINE S
* ** P

A A A A
C C C C
K K K K
* = Don't Care Bit

Figure 6. Write Cycle Timing

SCL

SDA 8th Bit ACK

Byte n tWR

STOP START ADDRESS

CONDITION CONDITION

Figure 7. Page Write Timing

S
T S
BUS ACTIVITY: A SLAVE BYTE ADDRESS T
MASTER R ADDRESS A15–A8 A7–A0 DATA DATA n DATA n+63 O
T P
SDA LINE S
*** P

A A A A A A A
C C C C C C C
K K K K K K K
* = Don't Care Bit

© 2005 by Catalyst Semiconductor, Inc. Doc No. 1102, Rev. C

Characteristics subject to change without notice 7
CAT24C64

READ OPERATIONS
Immediate Address Read
In standby mode, the CAT24C64 internal address counter
points to the data byte immediately following the last byte
accessed by a previous operation. If that ‘previous’ byte
was the last byte in memory, then the address counter
will point to the 1st memory byte, etc.

When, following a START, the CAT24C64 is presented

with a Slave address containing a ‘1’ in the R/W bit
position (Figure 8), it will acknowledge (ACK) in the 9th
clock cycle, and will then transmit data being pointed
at by the internal address counter. The Master can stop
further transmission by issuing a NoACK, followed by a
STOP condition.

Selective Read
The Read operation can also be started at an address
different from the one stored in the internal address
counter. The address counter can be initialized by per-
forming a ‘dummy’ Write operation (Figure 9). Here the
START is followed by the Slave address (with the R/W
bit set to ‘0’) and the desired two byte address. Instead
of following up with data, the Master then issues a 2nd
START, followed by the ‘Immediate Address Read’ se-
quence, as described earlier.

Sequential Read
If the Master acknowledges the 1st data byte transmitted
by the CAT24C64, then the device will continue trans-
mitting as long as each data byte is acknowledged by
the Master (Figure 10). If the end of memory is reached
during sequential Read, then the address counter will
‘wrap-around’ to the beginning of memory, etc. Sequential
Read works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting
byte address.

Doc. No. 1102, Rev. C © 2005 by Catalyst Semiconductor, Inc.

8 Characteristics subject to change without notice
 CAT24C64

Figure 8. Immediate Address Read Timing

S
T S
BUS ACTIVITY: A SLAVE T
MASTER R ADDRESS O
T P
SDA LINE S P

A N
C DATA O
K
A
C
K

SCL 8 9

SDA 8th Bit

DATA OUT NO ACK STOP

Figure 9. Selective Read Timing

S S
T T S
BUS ACTIVITY: A SLAVE BYTE ADDRESS A SLAVE T
MASTER R ADDRESS A15–A8 A7–A0 R ADDRESS DATA O
T T P

SDA LINE S
*** S P

A A A A N
C C C C O
K K K K A
* = Don't Care Bit C
K

Figure 10. Sequential Read Timing

S
BUS ACTIVITY: SLAVE T
MASTER ADDRESS DATA n DATA n+1 DATA n+2 DATA n+x O
P
SDA LINE P

A A A A N
C C C C O
K K K K
A
C
K

© 2005 by Catalyst Semiconductor, Inc. Doc No. 1102, Rev. C

Characteristics subject to change without notice 9
CAT24C64

8-LEAD 300 MIL WIDE PLASTIC DIP (L)

E1

E
D

A2
A

A1 L

e eB

b2

SYMBOL MIN NOM MAX

A 0.120 0.210
A1 0.015
A2 0.115 0.130 0.195
b 0.014 0.018 0.022
b2 0.045 0.060 0.070
D 0.355 0.365 0.400
D2 0.300 0.325
E 0.300 0.310 0.325
E1 0.240 0.250 0.280
e 0.100 BSC
eB 0.430
L 0.115 0.130 0.150 24C64_8-LEAD_DIP_(300P).eps

Notes:
1. Complies with JEDEC Standard MS001.
2. All dimensions are in inches.
3. Dimensioning and tolerancing per ANSI Y14.5M-1982

Doc. No. 1102, Rev. C © 2005 by Catalyst Semiconductor, Inc.

10 Characteristics subject to change without notice
 CAT24C64

8-LEAD 150 MIL WIDE SOIC (W)

E1
E

C
A
θ1
e
A1
L
b

SYMBOL MIN NOM MAX

A1 0.0040 0.0098
A2 0.0532 0.0688
b 0.013 0.020
C 0.0075 0.0098
D 0.1890 0.1968
E 02284 0.2440
E1 0.149 0.1574
e 0.050 BSC
f 0.0099 0.0196
24C64_8-LEAD_SOIC.eps
θ1 0° 8°

Notes:
1. Complies with JEDEC specification MS-012 dimensions.
2. All linear dimensions in millimeters.

© 2005 by Catalyst Semiconductor, Inc. Doc No. 1102, Rev. C

Characteristics subject to change without notice 11
CAT24C64

8-LEAD TSSOP (Y)

8 5
SEE DETAIL A

E E1

E/2

GAGE PLANE
1 4

PIN #1 IDENT.
0.25
θ1
A2 L
SEATING PLANE
SEE DETAIL A

e A1
b

SYMBOL MIN NOM MAX

A 1.20
A1 0.05 0.15
A2 0.80 0.90 1.05
b 0.19 0.30
c 0.09 0.20
D 2.90 3.00 3.10
E 6.30 6.4 6.50
E1 4.30 4.40 4.50
e 0.65 BSC
L 0.50 0.60 0.75
θ1 0.00 8.00

Notes:
1. All dimensions in millimeters.

Doc. No. 1102, Rev. C © 2005 by Catalyst Semiconductor, Inc.

12 Characteristics subject to change without notice
 CAT24C64

8-Pad TDFN 3x4.9 Package (ZD2)

PIN 1 INDEX AREA A1

D

D2
A2

A3

SYMBOL MIN NOM MAX

A 0.70 0.75 0.80
A1 0.00 0.02 0.05 E2
A2 0.45 0.55 0.65
A3 0.20 REF
b 0.20 0.25 0.30 PIN 1 ID
D 1.90 2.00 2.10
D2 1.30 1.40 1.50
E 2.90 3.00 3.10
E2 1.20 1.30 1.40 L
e 0.50 TYP
L 0.20 0.30 0.40 b
e
3xe

NOTE:
1. ALL DIMENSIONS IN MM. ANGLES IN DEGREES.
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMNALS. COPLANARITY SHALL NOT EXCEED 0.08 mm.
3. WARPAGE SHALL NOT EXCEED 0.10 mm.
4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC.
5. REFER JEDEC MO-229.
TDFN2X3 (03).eps

© 2005 by Catalyst Semiconductor, Inc. Doc No. 1102, Rev. C

Characteristics subject to change without notice 13
CAT24C64

ORDERING INFORMATION

Prefix Device # Suffix

CAT 24C64 Y I GT3

Company ID Product Temperature Range

Number I = Industrial (-40°C to +85°C)

Package Lead Finish/Tape & Reel

L: PDIP (Lead-free, Halogen-free) G: NiPdAu Lead Plating
W: SOIC, JEDEC (Lead-free, Halogen-free) T: Tape & Reel
Y: TSSOP (Lead-free, Halogen-free) 3: 3000/Reel
ZD2: TDFN (Lead-free, Halogen-free)

Notes:
(1) The device used in the above example is a CAT24C64YI-GT3 (TSSOP, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage,
Tape & Reel)
(2) For additional package and temperature options, please contact your nearest Catalyst Semiconductor sales office.

Doc. No. 1102, Rev. C © 2005 by Catalyst Semiconductor, Inc.

14 Characteristics subject to change without notice
 CAT24C64

PACKAGE MARKING

8-Lead PDIP 8-Lead SOIC

24C64LI 24C64WI
YYWWD YYWWD

CSI = Catalyst Semiconductor, Inc. CSI = Catalyst Semiconductor, Inc.

24C64L = Device Code 24C64W = Device Code
I = Temperature Range I = Temperature Range
YY = Production Year YY = Production Year
WW = Production Week WW = Production Week
D = Product Revision D = Product Revision

8-Lead TSSOP 8-Lead TDFN

YMD C C F E
NNNN
24C64I
YMOO

Y = Production Year CCFE = Device Code

M = Production Month NNNN = Traceability Code
D = Die Revision Y = Production Year
24C64 = Device Code M = Production Month
I = Industrial Temperature Range OO = Origin Country

Notes:
(1) The circle on the package marking indicates the location of Pin 1.

© 2005 by Catalyst Semiconductor, Inc. Doc No. 1102, Rev. C

Characteristics subject to change without notice 15
CAT24C64

TAPE AND REEL

Direction of Feed Device Orientation
SPROKET HOLE

TOP COVER
TAPE THICKNESS (t1)
0.10mm (0.004) MAX THICK

EMBOSSED DEVICE ORIENTATION

CARRIER
PIN 1 PIN 1 PIN 1
EMBOSSMENT

TDFN SOIC TSSOP

Reel Dimensions(1)
40mm (1.575) MIN. T
ACCESS HOLE
AT SLOT LOCATION

B*

A D* C N

FULL RADIUS*
TAPE SLOT IN CORE
FOR TAPE START.
2.5mm (0.098) MIN WIDTH
10mm (0.394) MIN DEPTH
* DRIVE SPOKES OPTIONAL, IF USED
ASTERISKED DIMENSIONS APPLY. G (MEASURED AT HUB)

Embossed Carrier Dimensions

A
Tape
Size Max Qty/Reel B Min C D* Min N Min G T Max
8.4 (0.328) 14.4
8MM
330 1.5 12.80 (0.504) 20.2 50 9.9 (1.389) (0.566)
3000
(13.00) (0.059) 13.20 (0.5200) (0.795) (1.969) 12.4 (0.488) 18.4
12MM
14.4 (0.558) (0.724)

Embossed Carrier Dimensions

Component Package Type Tape Size (W) Part Pitch (P)

8L SOIC J. S. W. V 12mm 8mm
8L TDFN 2x3mm SP2, VP2 8mm 4mm
Note:
(1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses.

Doc. No. 1102, Rev. C © 2005 by Catalyst Semiconductor, Inc.

16 Characteristics subject to change without notice
 CAT24C64

Embossed Carrier Dimensions (12 Tape Only)

10 PITCHES
K CUMULATIVE TOLERANCE
D P0 ON TAPE 0.2mm( 0.008)
T P2
TOP E
COVER (2)
TAPE
A0
F
W
(2)
B1 K0 B0

P CENTER LINES D1
OF CAVITY FOR COMPONENTS
EMBOSSMENT 2.0mm X 1.2mm
AND LARGER
FOR MACHINE REFERENCE ONLY
INCLUDING DRAFT AND RADII USER DIRECTION OF FEED
CONCENTRIC ABOUT B0

Embossed Tape—Constant Dimensions (1)

Tape Sizes D E P0 T Max. D1 Min. A0 B0 K0(2)

1.5 (0.059) 1.65 (0.065) 3.9 (0.153) 400 1.5
12mm
1.6 (0.063) 1.85 (0.073) 4.1 (0.161) (0.016) (0.059)

Embossed Carrier Dimensions (12 Tape Only)

Tape Sizes B1 Max. F K Max. P2 R Min. W P

8.2 5.45 (0.0215) 4.5 1.95 (0.077) 30 11.7 (0.460) 7.9 (0.275)
12mm
(0.0323) 5.55 (0.219) (0.177) 2.05 (0.081) (1.181) 12.3 (0.484) 8.1 (0.355)
Note:
(1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses.
(2) A0 B0 K0 are determined by component size. The clearance between the component and the cavity must be within 0.05 (0.002) min. to
0.65 (0.026) max. for 12mm tape, 0.05 (0.002) min. to 0.90 (0.035) max. for 16mm tape, and 0.05 (0.002) min. to 1.00 (0.039) max. for
24mm tape and larger. The component cannot rotate more than 20° within the determined cavity, see Component Rotation.

© 2005 by Catalyst Semiconductor, Inc. Doc No. 1102, Rev. C

Characteristics subject to change without notice 17
CAT24C64

REVISION HISTORY

Date Revision Comments

10/07/05 A Initial Issue
11/16/05 B Update Ordering Information
Add Tape and Reel Specifications

02/02/06 C Update Ordering Information

Doc. No. 1102, Rev. C © 2005 by Catalyst Semiconductor, Inc.

18 Characteristics subject to change without notice
 CAT24C64

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issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.

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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
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Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.

© 2005 by Catalyst Semiconductor, Inc. Doc No. 1102, Rev. C

Characteristics subject to change without notice 19
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000 Publication #: 1102
Fax: 408.542.1200 Revison: C
www.catalyst-semiconductor.com Issue date: 02/02/06