Advanced Information

CAT25C11/03/05/09/17
1K/2K/4K/8K/16K SPI Serial CMOS E2PROM
FEATURES
■ 1,000,000 Program/Erase Cycles
■ 10 MHz SPI Compatible
■ 100 Year Data Retention
■ 1.8 to 6.0 Volt Operation
■ Self-Timed Write Cycle
■ Hardware and Software Protection
■ 8-Pin DIP/SOIC, 8/14-Pin TSSOP and 8-Pin MSOP
■ Zero Standby Current
■ 16/32-Byte Page Write Buffer
■ Low Power CMOS Technology
■ Write Protection
■ SPI Modes (0,0 & 1,1)
– Protect First Page, Last Page, Any 1/4 Array
■ Commercial, Industrial and Automotive or Lower 1/2 Array
Temperature Ranges
DESCRIPTION
The CAT25C11/03/05/09/17 is a 1K/2K/4K/8K/16K-Bit input (SCK), data in (SI) and data out (SO) are required
SPI Serial CMOS E2PROM internally organized as to access the device. The HOLD pin may be used to
128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst’s ad- suspend any serial communication without resetting the
vanced CMOS Technology substantially reduces de- serial sequence. The CAT25C11/03/05/09/17 is de-
vice power requirements. The CAT25C11/03/05 fea- signed with software and hardware write protection
tures a 16-byte page write buffer. The 25C09/17 fea- features including Block Write protection. The device is
tures a 32-byte page write buffer.The device operates available in 8-pin DIP, 8-pin SOIC, 8/14-pin TSSOP and
via the SPI bus serial interface and is enabled though a 8-pin MSOP packages.
Chip Select (CS). In addition to the Chip Select, the clock
PIN CONFIGURATION
TSSOP Package (U14) SOIC Package (S) DIP Package (P) TSSOP Package (U)
CS 1 8 VCC CS 1 8 VCC
CS 1 14 VCC CS 1 8 VCC
SO 2 13 HOLD SO 2 7 HOLD SO 2 7 HOLD SO 2 7
12 HOLD
NC 3 NC WP 3 6 SCK WP 3 6 SCK 3 6
11 WP SCL
NC 4 NC VSS 4 5 SI VSS 4 5 4 5
NC 5 10 NC SI VSS SI
WP 6 9 SCK
VSS 7 8 SI MSOP Package (R)* BLOCK DIAGRAM
CS 1 8 VCC SENSE AMPS
SO 2 7 HOLD SHIFT REGISTERS
WP 3 6 SCK
VSS 4 5 SI
*CAT25C11/03 only
PIN FUNCTIONS WORD ADDRESS COLUMN
BUFFERS DECODERS
Pin Name Function
SO Serial Data Output SO I/O
SI CONTROL
CONTROL LOGIC

SCK Serial Clock

CS E2PROM
SPI XDEC ARRAY
WP Write Protect WP CONTROL
HOLD LOGIC
VCC +1.8V to +6.0V Power Supply SCK

VSS Ground BLOCK

PROTECT
CS Chip Select LOGIC

SI Serial Data Input DATA IN

STORAGE
HOLD Suspends Serial Input
HIGH VOLTAGE/
NC No Connect TIMING CONTROL
STATUS
REGISTER
25C128 F02

© 1999 by Catalyst Semiconductor, Inc. Doc. No. 25068-00 5/00

Characteristics subject to change without notice 1
CAT25C11/03/05/09/17 Advanced Information

ABSOLUTE MAXIMUM RATINGS* *COMMENT

Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum
Storage Temperature ....................... –65°C to +150°C Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
Voltage on any Pin with of the device at these or any other conditions outside of
Respect to VSS(1) .................. –2.0V to +VCC +2.0V those listed in the operational sections of this specifica-
VCC with Respect to VSS ................................ –2.0V to +7.0V tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
Package Power Dissipation mance and reliability.
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA

RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Reference Test Method
NEND (3) Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
TDR(3) Data Retention 100 Years MIL-STD-883, Test Method 1008
VZAP(3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(3)(4) Latch-Up 100 mA JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
ICC1 Power Supply Current 5 mA VCC = 5V @ 5MHz
(Operating Write) SO=open; CS=Vss
ICC2 Power Supply Current 3 mA VCC = 5.5V
(Operating Read) FCLK = 5MHz
ISB Power Supply Current 0 µA CS = VCC
(Standby) VIN = VSS or VCC
ILI Input Leakage Current 2 µA
ILO Output Leakage Current 3 µA VOUT = 0V to VCC,
CS = 0V
VIL(3) Input Low Voltage -1 VCC x 0.3 V
VIH(3) Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low Voltage 0.4 V 4.5V V CC<5.5V
IOL = 3.0mA
VOH1 Output High Voltage VCC - 0.8 V
IOH = -1.6mA

VOL2 Output Low Voltage 0.2 V 1.8V V CC<2.7V

VOH2 Output High Voltage VCC-0.2 V IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

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Advanced Information CAT25C11/03/05/09/17

Figure 1. Sychronous Data Timing

tCS
VIH

CS
VIL
tCSH
tCSS
VIH
SCK tWH tWL
VIL
tSU tH
VIH
SI VALID IN
VIL
tRI
tFI

tV tHO tDIS
VOH HI-Z HI-Z
SO
VOL

Note: Dashed Line= mode (1, 1) – – – –

A.C. CHARACTERISTICS

Limits
1.8V-6.0V 2.5V-6.0V 4.5V-5.5V Test
SYMBOL PARAMETER Min. Max. Min. Max. Min. Max. UNITS Conditions
tSU Data Setup Time 50 20 20 ns VIH = 2.4V
tH Data Hold Time 50 20 20 ns CL = 100pF
tWH SCK High Time 250 75 40 ns VOL = 0.8V
tWL SCK Low Time 250 75 40 ns VOH = 2.0v
fSCK Clock Frequency DC 1 DC 5 DC 10 MHz
tLZ HOLD to Output Low Z 50 50 50 ns
tRI (1) Input Rise Time 2 2 2 µs CL = 50pF
tFI (1) Input Fall Time 2 2 2 µs
tHD HOLD Setup Time 100 40 40 ns
tCD HOLD Hold Time 100 40 40 ns CL = 100pF
tWC Write Cycle Time 10 5 5 ms
tV Output Valid from Clock Low 250 80 80 ns
tHO Output Hold Time 0 0 0 ns
tDIS Output Disable Time 250 75 75 ns
tHZ HOLD to Output High Z 150 50 50 ns
tCS CS High Time 500 100 100 ns
tCSS CS Setup Time 500 100 100 ns
tCSH CS Hold Time 500 100 100 ns
tWPS WP Setup Time 150 50 50 ns
tCSH CS Hold Time 150 50 50 ns
NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter.

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CAT25C11/03/05/09/17 Advanced Information

FUNCTIONAL DESCRIPTION
The CAT25C11/03/05/09/17 supports the SPI bus data and the 25C11/03/05/09/17. Opcodes, byte addresses,
transmission protocol. The synchronous Serial Periph- or data present on the SI pin are latched on the rising
eral Interface (SPI) helps the CAT25C11/03/05/09/17 to edge of the SCK. Data on the SO pin is updated on the
interface directly with many of today’s popular falling edge of the SCK for SPI modes (0,0 & 1,1).
microcontrollers. The CAT25C11/03/05/09/17 contains
CS
CS: Chip Select
an 8-bit instruction register. (The instruction set and the
operation codes are detailed in the instruction set table) CS is the Chip select pin. CS low enables the CAT25C11/
03/05/09/17 and CS high disables the CAT25C11/03/
After the device is selected with CS going low, the first
05/09/17. CS high takes the SO output pin to high
byte will be received. The part is accessed via the SI pin,
impedance and forces the devices into a Standby Mode
with data being clocked in on the rising edge of SCK.
(unless an internal write operation is underway) The
The first byte contains one of the six op-codes that define
CAT25C11/03/05/09/17 draws ZERO current in the
the operation to be performed.
Standby mode. A high to low transition on CS is required
prior to any sequence being initiated. A low to high
PIN DESCRIPTION transition on CS after a valid write sequence is what
initiates an internal write cycle.
SI: Serial Input
SI is the serial data input pin. This pin is used to input all WP
WP: Write Protect
opcodes, byte addresses, and data to be written to the WP is the Write Protect pin. The Write Protect pin will
25C11/03/05/09/17.Input data is latched on the rising allow normal read/write operations when held high.
edge of the serial clock for SPI modes (0, 0 & 1, 1). When WP is tied low, all write operations to the device
are inhibited. WP going low while CS is still low will
SO: Serial Output interrupt a write to the status register. If the internal write
SO is the serial data output pin. This pin is used to cycle has already been initiated, WP going low will have
transfer data out of the 25C11/03/05/09/17. During a no effect on any write operation to the status register.
read cycle, data is shifted out on the falling edge of the
serial clock for SPI modes (0,0 & 1,1). HOLD
HOLD: Hold

SCK: Serial Clock HOLD is the HOLD pin. The HOLD pin is used to pause
SCK is the serial clock pin. This pin is used to synchro- transmission to the CAT25C11/03/05/09/17 while in the
nize the communication between the microcontroller

INSTRUCTION SET
Instruction Opcode Operation
WREN 0000 0110 Enable Write Operations
WRDI 0000 0100 Disable Write Operations
RDSR 0000 0101 Read Status Register
WRSR 0000 0001 Write Status Register
READ 0000 X011(1) Read Data from Memory
WRITE 0000 X010(1) Write Data to Memory

Power-Up Timing(2)(3)
Symbol Parameter Max. Units
tPUR Power-up to Read Operation 1 ms
tPUW Power-up to Write Operation 1 ms

Note:
(1) X=0 for 25C11, 25C03, 25C09, 25C17. X=A8 for 25C05
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

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Advanced Information CAT25C11/03/05/09/17

middle of a serial sequence without having to re-transmit instruction.

entire sequence at a later time. To pause, HOLD must be
brought low while SCK is low. The SO pin is in a high The BP0, BP1 and BP2 bits indicate which part of the
impedance state during the time the part is paused, and memory array is currently protected. These bits are set
transitions on the SI pins will be ignored. To resume by the user issuing the WRSR instruction. The user is
communication, HOLD is brought high, while SCK is allowed to protect from one page to as much as half the
low. (HOLD should be held high any time this function entire array. Once the three protection bits are set the
is not being used.) HOLD may be tied high directly to associated memory can be read but not written until the
VCC or tied to VCC through a resistor. Figure 9 illustrates protection bits are reset. These bits are non volatile.
hold timing sequence.
The WPEN (Write Protect Enable) is an enable b it for the
STATUS REGISTER WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect fea-
The Status Register indicates the status of the device. ture. Hardware write protection is enabled when WP is
The RDY (Ready) bit indicates whether the CAT25C11/ low and WPEN bit is set to high. The user cannot write
03/05/09/17 is busy with a write operation. When set to to the status register, (including the block protect bits
1 a write cycle is in progress and when set to 0 the and the WPEN bit) and the block protected sections in
device indicates it is ready. This bit is read only the WEL the memory array when the chip is hardware write
(Write Enable) bit indicates the status of the write protected. Only the sections of the memory array that
enable latch. When set to 1, the device is in a Write are not block protected can be written. Hardware write
Enable state and when set to 0 the device is in a Write protection is disabled when either WP pin is high or the
Disable state. The WEL bit can only be set by the WPEN bit is zero.
WREN instruction and can be reset by the WRDI

STATUS REGISTER
7 6 5 4 3 2 1 0
WPEN PR_MODE SPI_MODE BP2 BP1 BP0 WEL RDY

MEMORY PROTECTION

BP2 BP1 BP0 25C11 25C03 25C05 25C09 25C17

0 0 0 Non-Protection Q1 00-1F 00-3F 000-07F 000-0FF 000-1FF
0 0 1 Q1 Protected Q2 20-3F 40-7F 080-0FF 100-1FF 200-3FF
0 1 0 Q2 Protected Q3 40-5F 80-BF 100-17F 200-2FF 400-5FF
0 1 1 Q3 Protected Q4 60-7F C0-FF 180-1FF 300-3FF 600-7FF
1 0 0 Q4 Protected H1 00-3F 00-7F 000-0FF 000-1FF 000-3FF
1 0 1 H1 Protected P0 00-0F 00-0F 000-00F 000-01F 000-01F
1 1 0 P0 Protected Pn 70-7F F0-FF 1F0-1FF 3E0-3FF 7E0-7FF
1 1 1 Pn Protected

WRITE PROTECT ENABLE OPERATION

Protected Unprotected Status

WPEN WP WEL Blocks Blocks Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable

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CAT25C11/03/05/09/17 Advanced Information

DEVICE OPERATION After the correct read instruction and address are sent,
Write Enable and Disable the data stored in the memory at the selected address is
The CAT25C11/03/05/09/17 contains a write enable shifted out on the SO pin. The data stored in the memory
latch. This latch must be set before any write operation. at the next address can be read sequentially by continu-
The device powers up in a write disable state when Vcc ing to provide clock pulses. The internal address pointer
is applied. WREN instruction will enable writes (set the is automatically incremented to the next higher address
latch) to the device. WRDI instruction will disable writes after each byte of data is shifted out. When the highest
(reset the latch) to the device. Disabling writes will address is reached, the address counter rolls over to
protect the device against inadvertent writes. 0000h allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by pulling the CS
READ Sequence high. Read sequece is illustrated in Figure 4. Reading
The part is selected by pulling CS low. The 8-bit read status register is illustrated in Figure 5. To read the status
instruction is transmitted to the CAT25C11/03/05/09/17, register, RDSR instruction should be sent. The contents
followed by the 16-bit address for 25C09/17 (only 10-bit of the status register are shifted out on the SO line. If a
addresses are used for 25C09, 11-bit addresses are non-volatile write is in progress, the RDSR instruction
used for 25C17. The rest of the bits are don't care bits) returns a high on SO. When the non-volatile write cycle
and 8-bit address for 25C11/03/05 (for the 25C05, bit 3 is completed, the status register data is read out.
of the read data instruction contains address A8).

Figure 2. WREN Instruction Timing

CS

SK

SI 0 0 0 0 0 1 1 0

HIGH IMPEDANCE
SO

Note: Dashed Line= mode (1, 1) – – – –

Figure 3. WRDI Instruction Timing

CS

SK

SI 0 0 0 0 0 1 0 0

HIGH IMPEDANCE
SO

Note: Dashed Line= mode (1, 1) – – – –

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Advanced Information CAT25C11/03/05/09/17

WRITE Sequence Byte Write

The CAT25C11/03/05/09/17 powers up in a Write Dis- Once the device is in a Write Enable state, the user may
able state. Prior to any write instructions, the WREN proceed with a write sequence by setting the CS low,
instruction must be sent to CAT25C11/03/05/09/17. issuing a write instruction via the SI line, followed by the
The device goes into Write enable state by pulling the 16-bit address for 25C09/17. (only 10-bit addresses are
CS low and then clocking the WREN instruction into used for 25C09, 11-bit addresses are used for 25C17.
CAT25C11/03/05/09/17. The CS must be brought high The rest of the bits are don't care bits) and 8-bit address
after the WREN instruction to enable writes to the for 25C11/03/05 (for the 25C05, bit 3 of the read data
device. If the write operation is initiated immediately instruction contains address A8). Programming will start
after the WREN instruction without CS being brought after the CS is brought high. Figure 6 illustrates byte
high, the data will not be written to the array because the write sequence.
write enable latch will not have been properly set. Also,
for a successful write operation the address of the
memory location(s) to be programmed must be outside
the protected address field.

Figure 4. Read Instruction Timing

CS

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
SK

OPCODE

SI 0 0 0 0 0 0 1 1 BYTE ADDRESS*

DATA OUT
HIGH IMPEDANCE
SO 7 6 5 4 3 2 1 0
MSB

*Please check the instruction set table for address

Note: Dashed Line= mode (1, 1) – – – –

Figure 5. RDSR Instruction Timing

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCK

OPCODE

SI 0 0 0 0 0 1 0 1

DATA OUT
HIGH IMPEDANCE
SO 7 6 5 4 3 2 1 0
MSB

Note: Dashed Line= mode (1, 1) – – – –

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CAT25C11/03/05/09/17 Advanced Information

Page Write
The CAT25C11/03/05/09/17 features page write capa- and overwrite any data that may have been written. The
bility. After the initial byte, the host may continue to write CAT25C11/03/05/09/17 is automatically returned to the
up to 16 bytes of data to the CAT25C11/03/05 and 32 write disable state at the completion of the write cycle.
bytes of data for 25C09/17. After each byte of data Figure 8 illustrates the page write sequence.
received, lower order address bits are internally
incremented by one; the high order bits of address To write to the status register, the WRSR instruction
willremain constant.The only restriction is that the X should be sent. Only Bit 2, Bit 3, Bit 4 and Bit 7 of the
(X=16 for 25C11/03/05 and X=32 for 25C09/17) bytes status register can be written using the write status
must reside on the same page. If the address counter register instruction. Figure 7 illustrates the sequence of
reaches the end of the page and clock continues, the writing to status register.
counter will “roll over” to the first address of the page

Figure 6. Write Instruction Timing

CS

0 1 2 3 4 5 6 7 8 21 22 23 24 25 26 27 28 29 30 31
SK

OPCODE DATA IN

SI 0 0 0 0 0 0 1 0 ADDRESS D7 D6 D5 D4 D3 D2 D1 D0

HIGH IMPEDANCE
SO

Note: Dashed Line= mode (1, 1) – – – –

Figure 7. WRSR Instruction Timing

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK

OPCODE DATA IN
SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0
MSB

HIGH IMPEDANCE
SO

Note: Dashed Line= mode (1, 1) – – – –

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Advanced Information CAT25C11/03/05/09/17

DESIGN CONSIDERATIONS
The CAT25C11/03/05/09/17 powers up in a write dis- Access to the array during an internal write cycle is
able state and in a low power standby mode. A WREN ignored and programming is continued. On power up,
instruction must be issued to perform any writes to the SO is in a high impedance. If an invalid op code is
device after power up. Also,on power up CS should be received, no data will be shifted into the CAT25C11/03/
brought low to enter a ready state and receive an 05/09/17, and the serial output pin (SO) will remain in a
instruction. After a successful byte/page write or status high impedance state until the falling edge of CS is
register write the CAT25C11/03/05/09/17 goes into a detected again.
write disable mode. CS must be set high after the proper
number of clock cycles to start an internal write cycle.

Figure 8. Page Write Instruction Timing

CS

0 1 2 3 4 5 6 7 8 21 22 23 24-31 32-39 24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1

SK

DATA IN
OPCODE
Data Data Data Data Byte N
SI 0 0 0 0 0 0 1 0 ADDRESS Byte 1 Byte 2 Byte 3 7..1 0

HIGH IMPEDANCE
SO

Note: Dashed Line= mode (1, 1) – – – –

Figure 9. HOLD Timing

CS

tCD tCD

SCK

tHD
tHD
HOLD

tHZ
HIGH IMPEDANCE
SO
tLZ

Figure 10. WP Timing tWPS tWPH

CS
tCSH

SCK

WP

WP

Note: Dashed Line= mode (1, 1) – – – –

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CAT25C11/03/05/09/17 Advanced Information

ORDERING INFORMATION

Prefix Device # Suffix

CAT 25C17 S I -1.8 TE13

Optional Product Temperature Range Tape & Reel

Company ID Number Blank = Commercial (0°C to +70°C) TE13: 2000/Reel
25C17:16K I = Industrial (-40°C to +85°C) 2
25C09: 8K A = Automotive (-40°C to +105°C)
25C05: 4K
25C03: 2K
25C11: 1K
Package Operating Voltage
P = 8-pin PDIP Blank (Vcc=2.5 to 6.0V)
R = 8-pin MSOP3 1.8 (Vcc=1.8 to 6.0V)
S = 8-pin SOIC
U = 8-pin TSSOP
U14 = 14-pin TSSOP

Notes:
(1) The device used in the above example is a 25C17SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel)
(2) -40°C to 125°C is available upon request
(3) CAT25C11 and CAT25C03 only.

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