VNP10N07
”OMNIFET”:
                       FULLY AUTOPROTECTED POWER MOSFET
     TYPE      V clamp     R DS(on)     I l im
VNP10N07        70 V       0.1 Ω       10 A
■   LINEAR CURRENT LIMITATION
■   THERMAL SHUT DOWN
■   SHORT CIRCUIT PROTECTION
■   INTEGRATED CLAMP
■   LOW CURRENT DRAWN FROM INPUT PIN
■   DIAGNOSTIC FEEDBACK THROUGH INPUT                                                   3
    PIN                                                                             2
                                                                                1
■   ESD PROTECTION
■   DIRECT ACCESS TO THE GATE OF THE
                                                                       TO-220
    POWER MOSFET (ANALOG DRIVING)
■   COMPATIBLE WITH STANDARD POWER
    MOSFET
■   STANDARD TO-220 PACKAGE
DESCRIPTION
The VNP10N07 is a monolithic device made           current limitation and overvoltage clamp protect
using SGS-THOMSON Vertical Intelligent Power       the chip in harsh enviroments.
M0 Technology, intended for replacement of         Fault feedback can be detected by monitoring the
standard power MOSFETS in DC to 50 KHz             voltage at the input pin.
applications. Built-in thermal shut-down, linear
BLOCK DIAGRAM
April 1996                                                                                     1/11
VNP10N07
ABSOLUTE MAXIMUM RATING
 Symbol                              Parameter                                                    Value                   Unit
    V DS         Drain-source Voltage (V in = 0)                                          Internally Clamped                  V
       V in      Input Voltage                                                                     18                         V
       ID        Drain Current                                                             Internally Limited                 A
       IR        Reverse DC O utput Current                                                        -14                        A
   V esd         Electrostatic Discharge (C= 100 pF , R=1.5 KΩ)                                   2000                        V
    P to t       Total Dissipation at T c = 25 o C                                                 50                         W
                                                                                                                              o
       Tj        Operating Junction T emperature                                           Internally Limited                     C
                                                                                                                              o
       Tc        Case Operating T emperature                                               Internally Limited                     C
                                                                                                                              o
    T st g       Storage Temperature                                                            -55 to 150                        C
THERMAL DATA
                                                                                                                          o
  R t hj-ca se   Thermal Resistance Junction-case                                         Max              2.5                C/W
                                                                                                                          o
  R t hj- amb    Thermal Resistance Junction-ambient                                      Max             62.5                C/W
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)
OFF
 Symb ol                Parameter                           Test Cond ition s                    Min.     Typ .    Max.   Un it
  V CLAMP        Drain-source Clamp          I D = 200 mA        V in = 0                         60         70     80        V
                 Voltage
   V CL TH       Drain-source Clamp          I D = 2 mA       V in = 0                            55                          V
                 Threshold Voltage
   V I NCL       Input-Source Reverse        I in = -1 mA                                         -1               -0.3       V
                 Clamp Voltage
    I DSS        Zero Input Voltage          V DS = 13 V       V in = 0                                             50        µA
                 Drain Current (V in = 0)    V DS = 25 V       V in = 0                                            200        µA
       I I SS    Supply Current from         V DS = 0 V       Vin = 10 V                                     250   500        µA
                 Input Pin
ON (∗)
 Symb ol                Parameter                           Test Cond ition s                    Min.     Typ .    Max.   Un it
   V IN(th)      Input Threshold             V DS = Vin      ID + Ii n = 1 mA                     0.8               3         V
                 Voltage
  R DS( on)      Static Drain-source On      V i n = 10 V    ID = 5 A                                               0.1       Ω
                 Resistance                  Vi n = 5 V      ID = 5 A                                              0.14       Ω
DYNAMIC
 Symb ol                Parameter                           Test Cond ition s                    Min.     Typ .    Max.   Un it
   g fs (∗)      Forward                     V DS = 13 V        ID = 5 A                           6          8               S
                 Transconductance
    C oss        Output Capacitance          V DS = 13 V       f = 1 MHz        Vin = 0                      350   500        pF
2/11
                                                                                                           VNP10N07
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING (∗∗)
  Symb ol              Parameter                             Test Cond ition s             Min.   Typ .   Max.   Un it
    t d(on)      Turn-on Delay Time           V DD = 15 V          Id = 5 A                        50     100     ns
       tr        Rise Time                    V gen = 10 V         R gen = 10 Ω                    80     160     ns
    t d(of f)    Turn-off Delay Time          (see figure 3)                                      230     400     ns
       tf        Fall T ime                                                                       100     180     ns
    t d(on)      Turn-on Delay Time           V DD = 15 V          Id = 5 A                       600     900     ns
       tr        Rise Time                    V gen = 10 V         R gen = 1000 Ω                 0.9      2      µs
    t d(of f)    Turn-off Delay Time          (see figure 3)                                      3.8      6      µs
       tf        Fall T ime                                                                       1.7     2.5     µs
  (di/dt) on     Turn-on Current Slope        V DD = 15 V        ID = 5 A                          60            A/µs
                                              V i n = 10 V       R gen = 10 Ω
      Qi         Total Input Charge           V DD = 12 V       ID = 5 A     V in = 10 V           30            nC
SOURCE DRAIN DIODE
  Symb ol              Parameter                             Test Cond ition s             Min.   Typ .   Max.   Un it
  V SD (∗)       Forward O n Voltage          I SD = 5 A      V in = 0                                    1.6     V
   t r r (∗∗)    Reverse Recovery             I SD = 5 A    di/dt = 100 A/µs                      125             ns
                 Time                         V DD = 30 V     Tj = 25 oC
  Q r r (∗∗)     Reverse Recovery             (see test circuit, figure 5)                        0.3            µC
                 Charge
 I RRM (∗∗)      Reverse Recovery                                                                 4.8             A
                 Current
PROTECTION
  Symb ol              Parameter                             Test Cond ition s             Min.   Typ .   Max.   Un it
      I lim      Drain Current Limit          V i n = 10 V     VDS = 13 V                   7      10      14     A
                                              Vi n = 5 V       V DS = 13 V                  7      10      14     A
  t dl im (∗∗)   Step Response                V i n = 10 V                                         20      30     µs
                 Current Limit                Vi n = 5 V                                           50      80     µs
                                                                                                                  o
  T jsh (∗∗)     Overtemperature                                                           150                        C
                 Shutdown
                                                                                                                  o
  T j rs (∗∗)    Overtemperature Reset                                                     135                        C
   I gf (∗∗)     Fault Sink Current           V i n = 10 V     VDS = 13 V                          50            mA
                                              Vi n = 5 V       V DS = 13 V                         20            mA
  E as (∗∗)      Single Pulse                 starting T j = 25 o C  V DD = 20 V           0.4                    J
                 Avalanche Energy             V i n = 10 V R gen = 1 KΩ L = 10 mH
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(∗∗) Parameters guaranteed by design/characterization
                                                                                                                      3/11
VNP10N07
PROTECTION FEATURES
During normal operation, the Input pin is             - OVERTEMPERATURE AND SHORT CIRCUIT
electrically connected to the gate of the internal      PROTECTION: these are based on sensing
power MOSFET. The device then behaves like a            the chip temperature and are not dependent on
standard power MOSFET and can be used as a              the input voltage. The location of the sensing
switch from DC to 50 KHz. The only difference           element on the chip in the power stage area
from the user’s standpoint is that a small DC           ensures fast, accurate detection of the junction
current (Iiss) flows into the Input pin in order to     temperature. Overtemperature cutout occurs at
supply the internal circuitry.                          minimum 150oC. The device is automatically
The device integrates:                                  restarted when the chip temperature falls
- OVERVOLTAGE         CLAMP     PROTECTION:             below 135oC.
  internally set at 70V, along with the rugged        - STATUS FEEDBACK: In the case of an
  avalanche characteristics of the Power                 overtemperature fault condition, a Status
  MOSFET stage give this device unrivalled               Feedback is provided through the Input pin.
  ruggedness and energy handling capability.             The internal protection circuit disconnects the
  This feature is mainly important when driving          input from the gate and connects it instead to
  inductive loads.                                       ground via an equivalent resistance of 100 Ω.
- LINEAR CURRENT LIMITER CIRCUIT: limits                 The failure can be detected by monitoring the
  the drain current Id to Ilim whatever the Input        voltage at the Input pin, which will be close to
  pin voltage. When the current limiter is active,       ground potential.
  the device operates in the linear region, so        Additional features of this device are ESD
  power dissipation may exceed the capability of      protection according to the Human Body model
  the heatsink. Both case and junction                and the ability to be driven from a TTL Logic
  temperatures increase, and if this phase lasts      circuit (with a small increase in RDS(on)).
  long enough, junction temperature may reach
  the overtemperature threshold Tjsh.
4/11
                                                                                 VNP10N07
Thermal Impedance                            Derating Curve
Output Characteristics                       Transconductance
Static Drain-Source On Resistance vs Input   Static Drain-Source On Resistance
Voltage
                                                                                      5/11
VNP10N07
Static Drain-Source On Resistance         Input Charge vs Input Voltage
Capacitance Variations                    Normalized Input Threshold Voltage vs
                                          Temperature
Normalized On Resistance vs Temperature   Normalized On Resistance vs Temperature
6/11
                                                                            VNP10N07
Turn-on Current Slope                 Turn-on Current Slope
Turn-off Drain-Source Voltage Slope   Turn-off Drain-Source Voltage Slope
Switching Time Resistive Load         Switching Time Resistive Load
                                                                                 7/11
VNP10N07
Switching Time Resistive Load   Current Limit vs Junction Temperature
Step Response Current Limit     Source Drain Diode Forward Characteristics
8/11
                                                                                        VNP10N07
Fig. 1: Unclamped Inductive Load Test Circuits      Fig. 2: Unclamped Inductive Waveforms
Fig. 3: Switching Times Test Circuits For           Fig. 4: Input Charge Test Circuit
Resistive Load
Fig. 5: Test Circuit For Inductive Load Switching   Fig. 6: Waveforms
And Diode Recovery Times
                                                                                             9/11
VNP10N07
                                TO-220 MECHANICAL DATA
                                 mm                                          inch
        DIM.
                   MIN.          TYP.              MAX.         MIN.         TYP.                MAX.
         A         4.40                            4.60         0.173                            0.181
         C         1.23                            1.32         0.048                            0.051
         D         2.40                            2.72         0.094                            0.107
        D1                       1.27                                        0.050
         E         0.49                            0.70         0.019                            0.027
         F         0.61                            0.88         0.024                            0.034
        F1         1.14                            1.70         0.044                            0.067
        F2         1.14                            1.70         0.044                            0.067
         G         4.95                            5.15         0.194                            0.203
        G1          2.4                             2.7         0.094                            0.106
        H2         10.0                            10.40        0.393                            0.409
        L2                       16.4                                        0.645
        L4         13.0                            14.0         0.511                            0.551
        L5         2.65                            2.95         0.104                            0.116
        L6         15.25                           15.75        0.600                            0.620
        L7          6.2                             6.6         0.244                            0.260
        L9          3.5                            3.93         0.137                            0.154
        DIA.       3.75                            3.85         0.147                            0.151
                                                                                    E
               A
                                                                 D
                   C
                                        D1
                                              L2
                                                                        F1
                                                                               G1
                                                                                            H2
                                                                                        G
                                 Dia.
                                                                                F
                                                                 F2
                           L5
                                                           L9
                                L7
                                         L6                      L4
                                                                                            P011C
10/11
                                                                                                                             VNP10N07
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
                               1996 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved
                                         SGS-THOMSON Microelectronics GROUP OF COMPANIES
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                                                                    .
                                                                                                                                        11/11
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