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Fetch Decode Execute

1. The fetch-execute cycle describes how a processor executes instructions from a program stored in memory one at a time. 2. It first fetches the instruction from memory and decodes it, then executes it. 3. It then fetches the next instruction and repeats this process until the entire program is completed.

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213 views13 pages

Fetch Decode Execute

1. The fetch-execute cycle describes how a processor executes instructions from a program stored in memory one at a time. 2. It first fetches the instruction from memory and decodes it, then executes it. 3. It then fetches the next instruction and repeats this process until the entire program is completed.

Uploaded by

VRAJ PATEL
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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The Fetch-Decode and Execute

Cycle
The Fetch-Execute
► To execute a program you must first load the program and any
Cycle
relevant data in to the computer’s memory (RAM) from disk.

► The program and data is stored in memory until needed by the


processor (the stored program concept).

Main Addre
Memory
10101010 ss 00001001
11000000
11101000 11000000 00001001
00110001 11000000 00000111
10100010 11000000 00000110
11100000 11000000 00000101
Processor 00001000 11000000 00000100
10100010 11000000 00000011
11110011 11000000 00000010
11111000
11000000 00000001
00110000
11000000 00000000
The Fetch-Execute
Cycle
► A program may contain thousands of instructions but the
processor can only execute one instruction at a time.

► The first instruction is fetched from memory in to the processor


where it is decoded and executed.
► Then the second instruction is fetched and then executed and so
on until the program ends.
► This is known as the FETCH – EXECUTE CYCLE .

Process
or
LDA #B5
Memory Read
Operation
Process Main Addre
or Memory ss
Memor Address 00001001
y Bus 00001000
00000111
Other Addre 00000110
Registe ss 00000101
rs Regist Data Bus
Memor 00000100
er
y 00000011
00000010
Data
00000001
Regist 00000000
er
Contr
ALU ol Control
Unit Bus

1. The processor sets up the address bus with the required memory
address by placing it in the MAR
Memory Read
Operation
Process Main Addre
or Memory ss
Memor Address 00001001
y Bus 00001000
00000111
Other Addre 00000110
Registe ss 00000101
rs Regist Data Bus
Memor 00000100
er
y 00000011
00000010
Data
00000001
Regist 00000000
er
Contr
ALU ol Control
Unit Bus

2. The control unit activates the read line on the control bus
Memory Read
Operation
Process Main Addre
or Memory ss
Memor Address 00001001
y Bus 00001000
00000111
Other Addre 11110011 00000110
Registe ss 00000101
rs Regist Data Bus
Memor 00000100
er
y 00000011
00000010
Data
00000001
Regist 00000000
er
Contr
ALU ol Control
Unit Bus

3. The address bus opens the relevant memory location at that address
Memory Read
Operation
Process Main Addre
or Memory ss
Memor Address 00001001
y Bus 00001000
00000111
Other Addre 11110011 00000110
Registe ss 00000101
rs Regist Data Bus
Memor 00000100
er
y 00000011
00000010
Data
00000001
Regist 00000000
er
Contr
ALU ol Control
Unit Bus

4. The contents of the memory location are released, sent along the
data bus and into the MDR
Memory Read
Operation
Process Main Addre
or Memory ss
Memor Address 00001001
y Bus 00001000
00000111
Other Addre 00000110
Registe ss 00000101
rs Regist Data Bus
Memor 00000100
er
y 00000011
00000010
Data
00000001
Regist 00000000
er
Contr
ALU ol Control
Unit Bus

5. The data is then decoded and executed


Memory Write
Operation
Process Main Addre
or Memory ss
Memor Address 00001001
y Bus 00001000
00000111
Other Addre 00000110
Registe ss 00000101
rs Regist Data Bus
Memor 00000100
er
y 00000011
00000010
Data
00000001
Regist 00000000
er
Contr
ALU ol Control
Unit Bus

1. The processor sets up the address bus with the required memory
address by placing it in the MAR
Memory Write
Operation
Process Main Addre
or Memory ss
Memor Address 00001001
y Bus 00001000
00000111
Other Addre 00000110
Registe ss 00000101
rs Regist Data Bus
Memor 00000100
er
y 00000011
00000010
Data
00000001
Regist 00000000
er
Contr
ALU ol Control
Unit Bus

2. The processor sets up the data bus with the value to be stored in
memory by placing it in the MDR
Memory Write
Operation
Process Main Addre
or Memory ss
Memor Address 00001001
y Bus 00001000
00000111
Other Addre 00000110
Registe ss 00000101
rs Regist Data Bus
Memor 00000100
er
y 00000011
00000010
Data
00000001
Regist 00000000
er
Contr
ALU ol Control
Unit Bus

3. The control unit activates the write line on the control bus
Memory Write
Operation
Process Main Addre
or Memory ss
Memor Address 00001001
y Bus 00001000
00000111
Other Addre 00000110
Register ss 00000101
s Regist Data Bus
Memor 00000100
er
y 00000011
00000010
Data
00000001
Regist 00000000
er
Contr
ALU ol Control
Unit Bus

4. The address bus opens the relevant memory location at that address
Memory Write
Operation
Process Main Addre
or Memory ss
Memor Address 00001001
y Bus 00001000
00000111
Other Addre 11000111 00000110
Registe ss 00000101
rs Regist Data Bus
Memor 00000100
er
y 00000011
00000010
Data
00000001
Regist 00000000
er
Contr
ALU ol Control
Unit Bus

5. The contents of the memory data register are released, sent along
the data bus and into the memory location

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