Product Specification

AU OPTRONICS CORPORATION

( ) Preliminary Specifications
(V ) Final Specifications

Module 17,3”(17.25”) FHD 16:9 Color TFT-LCD

with LED Backlight design

Model Name B173HW01 V4 (H/W:0A) X919N

Note ( ) LED Backlight with driving circuit design

Customer Date Approved by Date

Beyond Yang 09/15/2009

Checked &
Date Prepared by Date
Approved by

Jeff Hou 09/15/2009

Note: This Specification is subject to change NBBU Marketing Division

without notice. AU Optronics corporation

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Contents
1. Handling Precautions .............................................................. 4
2. General Description ................................................................ 5
2.1 General Specification ..........................................................................................................................5
2.2 Optical Characteristics ........................................................................................................................6
3. Functional Block Diagram ..................................................... 11
4. Absolute Maximum Ratings................................................... 12
4.1 Absolute Ratings of TFT LCD Module.............................................................................................12
4.2 Absolute Ratings of Environment .....................................................................................................12
5. Electrical Characteristics....................................................... 13
5.1 TFT LCD Module..............................................................................................................................13
5.2 Backlight Unit ...................................................................................................................................15
6. Signal Interface Characteristic.............................................. 16
6.1 Pixel Format Image ...........................................................................................................................16
6.2 The Input Data Format ......................................................................................................................17
6.3 Integration Interface Requirement.....................................................................................................18
6.4 Interface Timing ................................................................................................................................20
7. Panel Reliability Test ............................................................ 22
7.1 Vibration Test ....................................................................................................................................22
7.2 Shock Test .........................................................................................................................................22
7.3 Reliability Test...................................................................................................................................22
8. Mechanical Characteristics.................................................... 23
8.1 LCM Outline Dimension...................................................................................................................23
8.2 Screw Hole Depth and Center Position.............................................................................................25
9. Shipping and Package ........................................................... 26
9.1 Shipping Label Format ......................................................................................................................26
12.2 Definition of customer PPID Label and Revision Code .................................................................26
9.2 Carton Package..................................................................................................................................27
9.3 Shipping Package of Palletizing Sequence........................................................................................27
10. Appendix: EDID Description................................................ 28

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Record of Revision

Version and Date Page Old description New Description Remark

0.1 2009/02/26 All First Edition for Customer

0.2 2009/07/28 All Update Label

0.3 2009/09/08 All Update Label and EDID (A00)

1.0 2009/09/15 All Final Specifications )

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1. Handling Precautions

1) Since front polarizer is easily damaged, pay attention not to scratch it.
2) Be sure to turn off power supply when inserting or disconnecting from input
connector.
3) Wipe off water drop immediately. Long contact with water may cause discoloration
or spots.
4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.
5) Since the panel is made of glass, it may break or crack if dropped or bumped on
hard surface.
6) Since CMOS LSI is used in this module, take care of static electricity and insure
human earth when handling.
7) Do not open nor modify the Module Assembly.
8) Do not press the reflector sheet at the back of the module to any directions.
9) At the insertion or removal of the Signal Interface Connector, be sure not to rotate
nor tilt the Interface Connector of the TFT Module.
11) After installation of the TFT Module into an enclosure (Notebook PC Bezel, for
example), do not twist nor bend the TFT Module even momentary. At designing the
enclosure, it should be taken into consideration that no bending/twisting forces are
applied to the TFT Module from outside. Otherwise the TFT Module may be
damaged.
12) Small amount of materials having no flammability grade is used in the LCD module. The
LCD module should be supplied by power complied with requirements of Limited Power
Source (IEC60950 or UL1950), or be applied exemption.
13) Disconnecting power supply before handling LCD modules, it can prevent electric shock,
DO NOT TOUCH the electrode parts, cables, connectors and LED circuit part of TFT
module that a LED light bar build in as a light source of back light unit. It can prevent
electrostic breakdown.

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2. General Description
B173HW01 V4 is a Color Active Matrix Liquid Crystal Display composed of a TFT LCD
panel, a driver circuit, and LED backlight system. The screen format is intended to support
the FHD (1920(H) x 1080(V) screen and 262k colors (RGB 6-bits data driver) with LED
backlight driving circuit. All input signals are LVDS interface compatible.
B173HW01 V4 is designed for a display unit of notebook style personal computer and
industrial machine.
2.1 General Specification
The following items are characteristics summary on the table at 25 ℃ condition:
Items Unit Specifications
Screen Diagonal [mm] 438.15
Active Area [mm] 381.89 X214.81

Pixels H x V 1920x3(RGB) x 1050

Pixel Pitch [mm] 0.1989X0.1989

Pixel Format R.G.B. Vertical Stripe

Display Mode Normally White

White Luminance (ILED=20mA) [cd/m2] 300 typ. (5 points average)

(Note: ILED is LED current) 270 min. (5 points average)
Luminance Uniformity 1.25 max. (5 points)
Contrast Ratio 600 typ
Response Time [ms] 8 typ / 16 Max
Nominal Input Voltage VDD [Volt] +3.3 typ.
Power Consumption [Watt] 12 W max. (Include Logic and Blu power)
Weight [Grams] 600 max.
Physical Size [mm] Min. Typ. Max.
Length 397.6 398.1 398.6
Width 232.3 232.8 233.3
Thickness - - 6.0
Electrical Interface 2 channel LVDS
Glass Thickness [mm] 0.5
Surface Treatment Glare, Hardness 4H,

Support Color 262K colors ( RGB 6-bit )

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Temperature Range
o
Operating [ C] 0 to +50
o
Storage (Non-Operating) [ C] -20 to +60
RoHS Compliance RoHS Compliance

2.2 Optical Characteristics

℃ (Room Temperature) :
The optical characteristics are measured under stable conditions at 25
Item Symbol Conditions Min. Typ. Max. Unit Note
White Luminance 5 points average 2
270 300 - cd/m 1, 4, 5.
ILED=20mA
θR Horizontal (Right) 60 70 -
degree
θL CR = 10 (Left) 60 70 -
Viewing Angle 4, 9
ψH Vertical (Upper) 50 60 -
ψL CR = 10 (Lower) 50 60 -
Luminance
δ5P 5 Points - - 1.25 1, 3, 4
Uniformity
Luminance
δ13P 13 Points - - 1.50 2, 3, 4
Uniformity
Contrast Ratio CR 500 600 - 4, 6
Cross talk % 4 4, 7
Tr Rising - TBD -
Response Time Tf Falling - TBD - msec 4, 8
TRT Rising + Falling - 8 16
Rx 0.639 0.669 0.699
Red
Ry 0.282 0.312 0.342
Gx 0.192 0.222 0.252
Color / Green
Gy 0.619 0.649 0.679
Chromaticity
Coodinates Bx CIE 1931 0.112 0.142 0.172 4
Blue -
By 0.040 0.070 0.100
Wx 0.263 0.313 0.363
White
Wy 0.279 0.329 0.379
NTSC % 90

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Note 1: 5 points position (Ref: Active area)

W
W /4 W /4 W /4 W /4

H /4

1 2
H /4

H 3

H /4

4 5

H /4

Note 2: 13 points position (Ref: Active area)

W /4 W /4 W /4 W /4
10 10

10
1 2 3
H /4

4 5

H /4

H 6 7 8

H /4

9 10

H /4 11 12 13
10

Note 3: The luminance uniformity of 5 or13 points is defined by dividing the maximum luminance values by the
minimum test point luminance

δ
Maximum Brightness of five points
W5 =
Minimum Brightness of five points

δ
Maximum Brightness of thirteen points
W13 =
Minimum Brightness of thirteen points

Note 4: Measurement method

The LCD module should be stabilized at given temperature for 30 minutes to avoid abrupt temperature change
during measuring. In order to stabilize the luminance, the measurement should be executed after lighting

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Backlight for 30 minutes in a stable, windless and dark room, and it should be measured in the center of screen.

Photo detector

Field=2°

50 cm

LCD Panel TFT-LCD Module

Center of the screen

Note 5 ： Definition of Average Luminance of White (YL):

Measure the luminance of gray level 63 at 5 points ，Y = [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / 5
L

L (x) is corresponding to the luminance of the point X at Figure in Note (1).

Note 6 ： Definition of contrast ratio:

Contrast ratio is calculated with the following formula.

Brightness on the “White” state

Contrast ratio (CR)=
Brightness on the “Black” state

Note 7 ： Definition of Cross Talk (CT)

CT = | YB – YA | / YA × 100 (%)

Where
YA = Luminance of measured location without gray level 0 pattern (cd/m2)

YB = Luminance of measured location with gray level 0 pattern (cd/m2)

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Note 8: Definition of response time:

The output signals of BM-7 or equivalent are measured when the input signals are changed from “Black” to
“White” (falling time) and from “White” to “Black” (rising time), respectively. The response time interval between
the 10% and 90% of amplitudes. Refer to figure as below.

"Black"
"White" "White"
100%
Signal(Relative value)

90%

10%
0%
Tr Tf

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Note 9. Definition of viewing angle

Viewing angle is the measurement of contrast ratio ≧10, at the screen center, over a 180° horizontal and
180° vertical range (off-normal viewing angles). The 180° viewing angle range is broken down as follows; 90°
(θ) horizontal left and right and 90° (Φ) vertical, high (up) and low (down). The measurement direction is
typically perpendicular to the display surface with the screen rotated about its center to develop the desired
measurement viewing angle.

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3. Functional Block Diagram

The following diagram shows the functional block of the 17.3 inches wide Color TFT/LCD 40 Pin Dual
channel Module

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4. Absolute Maximum Ratings

An absolute maximum rating of the module is as following:

4.1 Absolute Ratings of TFT LCD Module

Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage Vin -0.3 +4.0 [Volt] Note 1,2

4.2 Absolute Ratings of Environment

Item Symbol Min Max Unit Conditions
o
Operating Temperature TOP 0 +50 [ C] Note 4
Operation Humidity HOP 5 95 [%RH] Note 4
o
Storage Temperature TST -20 +60 [ C] Note 4
Storage Humidity HST 5 95 [%RH] Note 4

Note 1: At Ta (25℃)
Note 2: Permanent damage to the device may occur if exceed maximum values
Note 3: LED specification refer to section 5.2
Note 4: For quality performance, please refer to AUO IIS (Incoming Inspection Standard).

Twb=39°C

Operating Range Storage Range

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5. Electrical Characteristics
5.1 TFT LCD Module
5.1.1 Power Specification
Input power specifications are as follows;

The power specification are measured under 25 ℃ and frame frenquency under 60Hz
Symble Parameter Min Typ Max Units Note
VDD Logic/LCD Drive 3.0 3.3 3.6 [Volt]
Voltage
PDD VDD Power - - 2 [Watt] Note 1
IDD IDD Current - - 606 [mA] Note 1
IRush Inrush Current - - 2000 [mA] Note 2
VDDrp Allowable - - 100 [mV]
Logic/LCD Drive p-p
Ripple Voltage

Note 1 : Maximum Measurement Condition ：Black Pattern at 3.3V driving voltage. (Pmax=V3.3 x Iblack)

Note 2：Measure Condition

90% 3.3V

10%
0V
0.5ms

Vin rising time

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5.1.2 Signal Electrical Characteristics

Input signals shall be low or High-impedance state when VDD is off.

Signal electrical characteristics are as follows;

Parameter Condition Min Max Unit

VTH Differential Input High 100
Threshold (Vcm=+1.2V) [mV]
VTL Differential Input Low -100 -
Threshold (Vcm=+1.2V) [mV]
|VID| Differential Input
Voltage 100 600 [mV]
Differential Input
VCM Common Mode Voltage
1.125 1.375 [V]

Note: LVDS Signal Waveform

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5.2 Backlight Unit

5.2.1 LED characteristics

Parameter Symbol Min Typ Max Units Condition

Backlight Power PLED - - 10
℃
[Watt] (Ta=25 ), Note 1
Consumption Vin =12V

LED Life-Time N/A 10,000 - - Hour (Ta=25℃), Note 2

IF=20 mA

Note 1: Calculator value for reference PLED = VF (Normal Distribution) * IF (Normal Distribution) / Efficiency
Note 2: The LED life-time define as the estimated time to 50% degradation of initial luminous.

5.2.2 Backlight input signal characteristics

Parameter Symbol Min Typ Max Units Remark

LED Power Supply VLED 6.0 12.0 21.0 [Volt]

LED Enable Input 2.5 - 5.5 [Volt]

High Level
VLED_EN
LED Enable Input - - 0.8 [Volt]
Low Level Define as
PWM Logic Input 2.5 - 5.5 [Volt] Connector
High Level
VPWM_EN Interface
PWM Logic Input
Low Level
- - 0.8 [Volt] (Ta=25 ℃)
PWM Input Frequency FPWM 200 - 1K Hz

PWM Duty Ratio Duty 5 -- 100 %

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6. Signal Interface Characteristic

6.1 Pixel Format Image
Following figure shows the relationship of the input signals and LCD pixel format.

1 1280

1st Line R G B R GB R G B R GB

800th Line R G B R GB R G B R GB

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6.2 The Input Data Format

Signal Name Description

R5 Red Data 5 (MSB) Red-pixel Data
R4 Red Data 4 Each red pixel's brightness data consists of these 6 bits pixel data.
R3 Red Data 3
R2 Red Data 2
R1 Red Data 1
R0 Red Data 0 (LSB)

Red-pixel Data
G5 Green Data 5 (MSB) Green-pixel Data
G4 Green Data 4 Each green pixel's brightness data consists of these 6 bits pixel
G3 Green Data 3 data.
G2 Green Data 2
G1 Green Data 1
G0 Green Data 0 (LSB)

Green-pixel Data
B5 Blue Data 5 (MSB) Blue-pixel Data
B4 Blue Data 4 Each blue pixel's brightness data consists of these 6 bits pixel data.
B3 Blue Data 3
B2 Blue Data 2
B1 Blue Data 1
B0 Blue Data 0 (LSB)

Blue-pixel Data
RxCLKIN Data Clock The signal is used to strobe the pixel data and DE signals. All pixel
data shall be valid at the falling edge when the DE signal is high
DE Display Timing This signal is strobed at the falling edge of
RxCLKIN. When the signal is high, the pixel data shall be valid to
be displayed.
VS Vertical Sync The signal is synchronized to RxCLKIN .
HS Horizontal Sync The signal is synchronized to RxCLKIN .

Note: Output signals from any system shall be low or High-impedance state when VDD is off.

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6.3 Integration Interface Requirement

6.3.1 Connector Description

Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following
components.

Connector Name / Designation For Signal Connector

Manufacturer IPEX or compatible
Type / Part Number IPEX 20455-040E-12 or compatible

Mating Housing/Part Number IPEX 20353-040T-11 or compatible

6.3.2 Pin Assignment

LVDS is a differential signal technology for LCD interface and high speed data transfer device.
PIN # SIGNAL NAME DESCRIPTION
1 DIAG_LOOP Diag pin for Dell testing. Pin 1 & 34 must be connected together on the PCB board
2 VDD Power Supply, 3.3 V (typical)
3 VDD Power Supply, 3.3 V (typical)
4 V EEDID DDC 3.3V power
5 TEST Panel Self Test
6 Clk EEDID DDC Clock
7 DATA EEDID DDC Data
8 Odd_Rin0- - LVDS differential data input (R0-R5, G0) (odd pixels)
9 Odd_Rin0+ + LVDS differential data input (R0-R5, G0) (odd pixels)
10 VSS Ground – Shield
11 Odd_Rin1- - LVDS differential data input (G1-G5, B0-B1) (odd pixels)
12 Odd_Rin1+ + LVDS differential data input (G1-G5, B0-B1) (odd pixels)
13 VSS Ground – Shield
14 Odd_Rin2- - LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
15 Odd_Rin2+ + LVDS differential data input (B2-B5, HS, VS, DE) (odd pixels)
16 VSS Ground – Shield
17 Odd_ClkIN- - LVDS differential clock input (odd pixels)
18 Odd_ClkIN+ + LVDS differential clock input (odd pixels)
19 VSS Ground – Shield
20 Even_Rin0- - LVDS differential data input (R0-R5, G0) (even pixels)
21 Even_Rin0+ + LVDS differential data input (R0-R5, G0) (even pixels)
22 VSS Ground – Shield
23 Even_Rin1- - LVDS differential data input (G1-G5, B0-B1) (even pixels)
24 Even_Rin1+ + LVDS differential data input (G1-G5, B0-B1) (even pixels)
25 VSS Ground – Shield
26 Even_Rin2- - LVDS differential data input (B2-B5, HS, VS, DE) (even pixels)
27 Even_Rin2+ + LVDS differential data input (B2-B5, HS, VS, DE) (even pixels)
28 VSS Ground – Shield
29 Even_ClkIN- - LVDS differential clock input (even pixels)
30 Even_ClkIN+ + LVDS differential clock input (even pixels)
31 VLED_GND LED Ground
32 VLED_GND LED Ground
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33 VLED_GND LED Ground

34 DIAG_LOOP Diag pin for Dell testing.Pin 1 & 34 must be connected together on the PCB board
35 VPWM_EN PWM logic input level
36 VLED_EN LED enable input level
37 NC No Connection (Reserve)
38 VLED LED Power Supply
39 VLED LED Power Supply
40 VLED LED Power Supply

Connector

Pin 40 Pin 1
VLED

NC

Note1: Input signals shall be low or High-impedance state when VDD is off.

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6.4 Interface Timing

6.4.1 Timing Characteristics
Basically, interface timings should match the 1920x1080 /60Hz manufacturing guide line timing.

Parameter Symbol Min. Typ. Max. Unit

Frame Rate - 50 60 - Hz
Clock frequency 1/ TClock 64.63 71.2 - MHz
Period TV 1088 1130 -
Vertical
Active TVD 1080 TLine
Section
Blanking TVB 8 50 -
Period TH 990 1050 -
Horizontal
Active THD 960 TClock
Section
Blanking THB 30 90 -

Note : DE mode only

6.4.2 Timing diagram

TCLOCK Input Timing Definition ( DE Mode)

DOTCLK

Input Invaild Pixel Pixel Pixel Pixel Pixel Invaild Pixel

Data Data 1 2 3 N-1 N Data 1

DE
THB THD

TH

DE
TVB
TVD

TV

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6.5 Power ON/OFF Sequence

Power on/off sequence is as follows. Interface signals and LED on/off sequence are also shown in
the chart. Signals from any system shall be Hi-Z state or low level when VDD is off

Power Sequence Timing

Value
Parameter Min. Typ. Max. Units
T1 0.5 - 10
T2 0 - 50
T3 200 - -
T4 0.5 - 10
T5 10 - -
T6 10 - -
T7 0 - - ms

T8 10 - -
T9 0 - 10
T10 200 - -
T11 0.5 - 50
T12 0 - 10
T13 400 - -

Note:If T3,T5,T6 couldn’t match above specifications, must request T3+T5+T6 > 200ms at least

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7. Panel Reliability Test

7.1 Vibration Test

Test Spec:

Test method: Non-Operation

Acceleration: 1.5 G

Frequency: 10 - 500Hz Random

Sweep: 30 Minutes each Axis (X, Y, Z)

7.2 Shock Test

Test Spec:

Test method: Non-Operation

Acceleration: 220 G , Half sine wave

Active time: 2 ms

Pulse: X,Y,Z .one time for each side

7.3 Reliability Test

Items Required Condition Note

Temperature
℃, 90%RH, 300h
Ta= 40℃
Humidity Bias
High Temperature
℃, Dry, 300h
Ta= 50℃
Operation
Low Temperature
℃, 300h
Ta= 0℃
Operation
High Temperature
℃, 35%RH, 300h
Ta= 60℃
Storage
Low Temperature
℃, 50%RH, 250h
Ta= -20℃
Storage
Thermal Shock
℃to 60℃
Ta=-20℃ ℃, Duration at 30 min, 100 cycles
Test
Contact : ±8 KV Note 1
ESD
Air : ±15 KV

Note1: According to EN 61000-4-2 , ESD class B: Some performance degradation allowed. Self-recoverable.
No data lost, No hardware failures.
Remark: MTBF (Excluding the LED): 30,000 hours with a confidence level 90%

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8. Mechanical Characteristics
8.1 LCM Outline Dimension

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Note: Prevention IC damage, IC positions not allowed any overlap over these areas.

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8.2 Screw Hole Depth and Center Position

Maximum Screw penetration from side surface is 2.2 mm

The center of screw hole center location is 3.1 ± 0.2mm from front surface

Screw Torque: Maximum 2.5 kgf-cm

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9. Shipping and Package

9.1 Shipping Label Format

Manufactured MM/WW C US Pb
E204356
Model No: B173HW01 V4 RoHS
AU Optronics
MADE IN CHINA(S03)
CN -0X919N-72090-
XXX-XXXX-A00 H/W: 0A F/W:1
Made In China
DP/N 0X919N

12.2 Definition of customer PPID Label and Revision Code

Please refer to the Dell Part identification Label Specification, Number:13190

Build Name(s): PPID Revision Code(s):

Sub System Test (SST)

Working Sample (WS) X00, X01, X02, …, X0n

ENG 2

Product Test (PT)

Engineering Sample (ES) X10, X11, X12, …, X1n

ENG 3

System Test (ST)

Customer Sample (CS) X20, X21, X22, … X2n

ENG 4

X-Build (XB)

Mass Production (MP) A00, A01, A02, … A0n

ENG 5

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9.2 Carton Package

The outside dimension of carton is 455 (L)mm x 380 (W)mm x 355 (H)mm

9.3 Shipping Package of Palletizing Sequence

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10. Appendix: EDID Description

Byte Value Value Value
Field Name and Comments
(hex) (hex) (binary) (DEC)
0 Header 00 00000000 0
1 Header FF 11111111 255
2 Header FF 11111111 255
Header

3 Header FF 11111111 255

4 Header FF 11111111 255
5 Header FF 11111111 255
6 Header FF 11111111 255
7 Header 00 00000000 0
8 EISA manufacture code = 3 Character ID 06 00000110 6
9 EISA manufacture code (Compressed ASCII) AF 10101111 175
0A Panel Supplier Reserved – Product Code 9D 10011101 157
Vendor / Product

0B Panel Supplier Reserved – Product Code 14 00010100 20

EDID Version

0C LCD module Serial No - Preferred but Optional (“0” if not used) 00 00000000 0
0D LCD module Serial No - Preferred but Optional (“0” if not used) 00 00000000 0
0E LCD module Serial No - Preferred but Optional (“0” if not used) 00 00000000 0
0F LCD module Serial No - Preferred but Optional (“0” if not used) 00 00000000 0
10 Week of manufacture 01 00000001 1
11 Year of manufacture 13 00010011 19
12 EDID structure version # = 1 01 00000001 1
13 EDID revision # = 3 03 00000011 3
14 Video I/P definition = Digital I/P (90 (6-bit) or A0 (8-Bit)) 90 10010000 144
Parameters

15 Max H image size = ?? cm(Rounded to cm) 26 00100110 38

Display

16 Max V image size = ?? cm(Rounded to cm) 15 00010101 21

17 Display gamma = (gamma ×100)-100 = Example: ( 2.2×100 ) – 100 = 120 78 01111000 120
18 Feature support ( no DPMS, Active off, RGB, timing BLK 1) ==> fix=0A 0A 00001010 10
19 Red/Green Low bit (RxRy/GxGy) 7D 01111101 125
1A Blue/White Low bit (BxBy/WxWy) 45 01000101 69
1B Red X Rx = 0.??? AB 10101011 171
1C Red Y Ry = 0.??? 4F 01001111 79
Coordinates
Panel Color

1D Green X Rx = 0.??? 38 00111000 56

1E Green Y Ry = 0.??? A6 10100110 166
1F Blue X Rx = 0.??? 24 00100100 36
20 Blue Y Ry = 0.??? 12 00010010 18
21 White X Rx = 0.??? 50 01010000 80
22 White Y Ry = 0.??? 54 01010100 84
23 Established timings 1 (00h if not used) 00 00000000 0
Establi

Timing
shed

24 Established timings 2 (00h if not used) 00 00000000 0

s

25 Manufacturer’s timings (00h if not used) 00 00000000 0

26 Standard timing ID1 (01h if not used) 01 00000001 1
27 Standard timing ID1 (01h if not used) 01 00000001 1
28 Standard timing ID2 (01h if not used) 01 00000001 1
29 Standard timing ID2 (01h if not used) 01 00000001 1
2A Standard timing ID3 (01h if not used) 01 00000001 1
Standard Timing ID

2B Standard timing ID3 (01h if not used) 01 00000001 1

2C Standard timing ID4 (01h if not used) 01 00000001 1
2D Standard timing ID4 (01h if not used) 01 00000001 1
2E Standard timing ID5 (01h if not used) 01 00000001 1
2F Standard timing ID5 (01h if not used) 01 00000001 1
30 Standard timing ID6 (01h if not used) 01 00000001 1
31 Standard timing ID6 (01h if not used) 01 00000001 1
32 Standard timing ID7 (01h if not used) 01 00000001 1
33 Standard timing ID7 (01h if not used) 01 00000001 1
34 Standard timing ID8 (01h if not used) 01 00000001 1
35 Standard timing ID8 (01h if not used) 01 00000001 1

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 Product Specification
AU OPTRONICS CORPORATION

36 Pixel Clock/10,000 (LSB) A0 10100000 160

37 Pixel Clock/10,000 (MSB) 37 00110111 55
38 Horizontal Active = ???? pixels (lower 8 bits) 80 10000000 128
39 Horizontal Blanking (Thbp) = 320 pixels (lower 8 bits) B4 10110100 180
3A Horizontal Active/Horizontal blanking (Thbp) (upper4:4 bits) 70 01110000 112
3B Vertical Active = ??? lines 38 00111000 56
3C Vertical Blanking (Tvbp) = ?? lines (DE Blanking typ. for DE only panels) 32 00110010 50
3D Vertical Active : Vertical Blanking (Tvbp) (upper4:4 bits) 40 01000000 64
3E Horizontal Sync, Offset (Thfp) = ?? pixels 6C 01101100 108
Timing Descripter #1

3F Horizontal Sync, Pulse Width = ??? pixels 30 00110000 48

40 Vertical Sync, Offset (Tvfp) = ? lines Sync Width = ? lines AA 10101010 170
41 Horizontal Vertical Sync Offset/Width upper 2 bits 00 00000000 0
42 Horizontal Image Size =??? mm 7D 01111101 125
43 Vertical image Size = ??? mm D6 11010110 214
44 Horizontal Image Size / Vertical image size 10 00010000 16
45 Horizontal Border = 0 (Zero for Notebook LCD) 00 00000000 0
46 Vertical Border = 0 (Zero for Notebook LCD) 00 00000000 0
Bit[7] 0: Non-interlace, 1: Interlace
Bit[6:5] 00: Normal display, no strero, see VESA EDID Spec 1.3
Bit[4:3] 00: Analog composite, 01: Bipolar analog composite, 10: Digital
composite, 11: Digital separate
Bit[2:1] : The interpretation of bits 2 and 1 is dependent on the decode of
bits 4 and 3 - see VESA EDID Spec 1.3
Bit[0] : See VESA EDID Spec 1.3
47 ==> fix=1A 1A 00011010 26
48 Pixel Clock/10,000 (LSB) A0 10100000 160
49 Pixel Clock/10,000 (MSB) 37 00110111 55
4A Horizontal Active = xxxx pixels (lower 8 bits) 80 10000000 128
4B Horizontal Blanking (Thbp) = xxxx pixels (lower 8 bits) B4 10110100 180
4C Horizontal Active/Horizontal blanking (Thbp) (upper4:4 bits) 70 01110000 112
4D Vertical Active = xxxx lines 38 00111000 56
4E Vertical Blanking (Tvbp) = xxxx lines (DE Blanking typ. for DE only panels) 32 00110010 50
4F Vertical Active : Vertical Blanking (Tvbp) (upper4:4 bits) 40 01000000 64
50 Horizontal Sync, Offset (Thfp) = xxxx pixels 6C 01101100 108
(=Timing Descripter #1)
Timing Descripter #2

51 Horizontal Sync, Pulse Width = xxxx pixels 30 00110000 48

52 Vertical Sync, Offset (Tvfp) = xx lines Sync Width = xx lines AA 10101010 170
53 Horizontal Vertical Sync Offset/Width upper 2 bits 00 00000000 0
54 Horizontal Image Size =xxx mm 7D 01111101 125
55 Vertical image Size = xxx mm D6 11010110 214
56 Horizontal Image Size / Vertical image size 10 00010000 16
57 Horizontal Border = 0 (Zero for Notebook LCD) 00 00000000 0
58 Vertical Border = 0 (Zero for Notebook LCD) 00 00000000 0
Bit[7] 0: Non-interlace, 1: Interlace
Bit[6:5] 00: Normal display, no strero, see VESA EDID Spec 1.3
Bit[4:3] 00: Analog composite, 01: Bipolar analog composite, 10: Digital
composite, 11: Digital separate
Bit[2:1] : The interpretation of bits 2 and 1 is dependent on the decode of
bits 4 and 3 - see VESA EDID Spec 1.3
Bit[0] : See VESA EDID Spec 1.3
59 ==> fix=1A 1A 00011010 26
5A Flag 00 00000000 0
5B Flag 00 00000000 0
5C Flag 00 00000000 0
5D Data Type Tag: Alphanumeric Data String (ASCII) ==> fix=FE FE 11111110 254
5E Flag 00 00000000 0
st
5F Dell P/N 1 Character 58 01011000 88
60 Dell P/N 2nd Character 39 00111001 57
Dell specific information
Timing Descripter #3

rd
61 Dell P/N 3 Character 31 00110001 49
62 Dell P/N 4th Character 39 00111001 57

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 Product Specification
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6C Flag 00 00000000 0
6D Flag 00 00000000 0
6E Flag 00 00000000 0
6F Data Type Tag: Manufacturer Specified Data 00 ==>fix=00 00 00000000 0
70 Flag 00 00000000 0
71 SMBUS Value = ?? Nits ==> fix=00(for M09) 00 00000000 0
72 SMBUS Value = ?? Nits ==> fix=00(for M09) 00 00000000 0
73 SMBUS Value = ?? Nits ==> fix=00(for M09) 00 00000000 0
Timing Descripter #4

74 SMBUS Value = ?? Nits ==> fix=00(for M09) 00 00000000 0

75 SMBUS Value = ?? Nits ==> fix=00(for M09) 00 00000000 0
76 SMBUS Value = ?? Nits ==> fix=00(for M09) 00 00000000 0
77 SMBUS Value = ?? Nits ==> fix=00(for M09) 00 00000000 0
78 SMBUS Value = ?? Nits ==> fix=00(for M09) 00 00000000 0
Bit[1:0] 00: reserved, 01: single LVDS, 10: dual LVDS, 11: reserved
Bit[2] 0: No RTC support, 1: RTC support
79 Bit[7:3] Reserved 02 00000010 2
Bit[0] 0: No BIST support, 1: BIST support
7A Bit[7:1] Reserved 01 00000001 1
7B (If <13 char, then terminate with ASCII code 0Ah, set remaining char = 20h) 0A 00001010 10
Checksum

7C (If <13 char, then terminate with ASCII code 0Ah, set remaining char = 20h) 20 00100000 32
7D (If <13 char, then terminate with ASCII code 0Ah, set remaining char = 20h) 20 00100000 32
7E Extension flag (# of optional 128 EDID extension blocks to follow, Typ = 0) 00 00000000 0
7F Checksum (The 1-byte sum of all 128 bytes in this EDID block shall = 0) 26 00100110 38

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