Characterization of a Generic 90nm is generally made up of a heavily doped piece of
poly-silicon often called poly. PMOS on other hand
CMOS Technology is fabricated on a n – type substrate, whereas the
source and drain terminals are formed by heavily
doped p regions. When the voltage at gate terminal
Abstract-- This paper presents Characterization of a increases, the width of the depletion region and the
Generic 90nm CMOS Technology. The output I-V potential at the oxide silicon interface also increases.
characteristics: drain to source current ( IDS) vs. When the interface potential reaches a sufficiently
drain to source voltage (VDS), transfer positive value, electrons start flowing from source to
characteristics: drain to source current (I DS) vs. gate drain. At this point, we say that a ‘channel’ is formed
to source voltage (VGS), drain to source resistance under the gate oxide between drain and source and
(rds) and trans conductance (gm) of NMOS and the transistor is turned on. The value of VGS for which
PMOS transistors are presented. The first, second this inversion occurs is called the ‘threshold voltage’,
and third order derivatives of trans conductance and VTH. In other words, MOSFET is a Voltage
transfer I-V characteristics are also plotted that help controlled current source. The channel constitutes of
us to observe the dependencies of I DS on higher electrons for a p-type substrate and holes for a n –
powers of VGS and VDS . type substrate which explains the slow speed of
PMOS devices. There is one more connection made
Introduction to the substrate of the MOSFET. The Voltage at this
connection is generally kept equal to the source
MOSFET stands for Metal Oxide Semiconductor voltage to minimize the body effects. This makes
Field Effect Transistor. MOSFET technology is an MOSFET a four-terminal device. Because of the
enhancement on bipolar technology. Fig 1 shows a electrical insulation of gate from the channel, the
simplified structure of an n – type MOS device MOSFET has a large input impedance which makes
(NMOS). it useful for designing high power amplifiers.
Depending upon the values of applied voltages, the
operation of MOSFET can be divided into three
regions. The case of NMOS is presented below:-
Cutoff Region :This region is characterized by zero
drain current. It exists for all the values of VGS < VTH.
Ideally, the region under gate is devoid of any
carriers for very small values of VGS and there is no
channel formed to conduct the current.
Triode/Linear Region :This region exists for values
of VGS > VTH and VDS < VGS -VTH .A uniform channel
exists under the gate region which conducts the
current depending upon the applied V GS and VTH. as
shown in equation (1).
Fig 1 Basic n - MOSFET
(1)
The device is fabricated on a p – type substrate and
Saturation Region : This region occurs for VGS >
consists of two heavily doped n regions forming the
VTH and VDS > VGS -VTH. Increasing the drain voltage
source and drain terminals, and a thin layer of silicon
decreases the potential between gate and drain and
dioxide(Sio2) insulating the gate from substrate. Gate
thus decreases the density of carriers near the drain
terminal. At one point, the carrier concentration near MOSFE
drain becomes zero and this point is termed as pinch
off point. The corresponding drain to source voltage
is termed as Saturation voltage. In this region, the
drain current is relatively constant with respect to
VDS. as shown by first order current equation (2)
(2)
Fig 2 shows the output characteristics with different
regions of operation of MOSFET
Fig 3 Test bench for NMOS
It is important to note that the source and body
contacts are connected together and then to the
Fig 2 Different Operating Regions of NMOS on ground thereby making the potential between source
output IV curves. and bulk as zero. This is done to minimize the body
effects which arise due to a finite potential difference
NMOS CHARACTERIZATION
between source and bulk.
In order to study the characteristics of NMOS
Output I-V Characteristics:- In order to obtain the
transistor, we used nmos1V module from gpdk090
output I-V curves, we perform the dc analysis by
library with channel length 100nm and width 120nm
sweeping the drain to source voltage,V2 from 0 to 1V
thus giving us the aspect ratio of 1.2.This W/L ratio
in steps of 10mV.The voltage V1 is assigned a
greatly effects the value of drain current for a given
variable value ‘a’ in order to perform the parametric
VGS and VDS. Fig 3 shows the test bench schematic
analysis .It helps us to analyze the effect of different
that was used to study the characteristics of NMOS
transistor. Two independent voltage sources V1 and
V2 are used to bias the Gate and Drain terminal of
values of VGS on the output I-V curves. It is seen that the Ids increases with increase in V GS
as expected from the drain current equation (2).This
effect could be attributed to the increase in channel
charge density with increase in V GS thus providing a
greater current.
Drain to Source Resistance (rDS):-The rDS or the
channel resistance helps us to model the effects of
VDS on IDS in the saturation region. In the analysis of
channel pinch off, it is noted that the actual length of
channel gradually decreases with increase in potential
between the gate and drain decreases. In other words,
the channel length decreases as V DS is increased by
keeping VGS constant. This effect is called “channel
length modulation” and is modeled in the MOSFET
device model with the help of rDS which is computed
Fig 4 Output IV curve for VGS = 0.5V
by taking the derivative of VDS with respect to IDS as
Fig 4 shows the I-V curves obtained by keeping the shown in equation (3) and (4).
value of ‘a’ variable (VGS) = 0.5. The curve depicts
rDS=VDS/D (3)
that as the VDS increases, the transistor operating
2
region of MOSFET gradually changes from triode to rDS = 1/(1/2*u*Cox*W/L(VGS –Vth) .
active for a given VGS. One can observe that the curve
Fig 6 shows the plots obtained by taking the first
in triode region is not perfectly linear indicating the
order derivative of output characteristics and then
dependence of Ids on higher orders of VDS. Also in
taking its inverse. These results are computed with
the active region, the curve is not perfectly constant.
the help of calculator tool provided in Cadence. In
This is because of the Channel length modulation
other words, Fig 6 shows us the variation of r DS with
effect (explained later) that makes the Ids to increase
VDS.
with VDS even after the drain to source saturation
voltage .
Now, in order to observe the effect of VGS on the
output characteristics, the parameter ‘a’ is varied
from 0 to 1V in steps of 10mV and the results are
shown in Fig 5.
Fig 6 Plot of rDS Vs VDS
Fig 7 and Fig 8 shows us the first and second order
derivatives of rDS with respect to VDS.
Fig 5 Output I-V curve for different values of VGS
Fig 7 First Order Derivative of rDS
The rDS curve should be a constant according to
equation (4) as it does not vary VDS But the first and dc (V)
second order derivatives depict the dependency of I DS
Fig 10 Transfer Curves for different VDS
on higher powers of VDS .
The test bench used is same as shown in Fig 3 with a
difference that V1 is swept this time from 0 to 1V in
steps of 100mvand V2 is assigned a parametric value
‘a’.Fig 9 shows the transfer characteristics obtained
by setting VDC = 0.5V. Then, VDC is varied from 0 to
1V in steps of 10mV and transfer characteristics
obtained are shown in are shown in Fig 10.
Tran conductance: - It is a change in drain current
divided by the change in gate source voltage with
drain source voltage kept constant. It represents the
sensitivity of device
Fig 8 Second Order Derivative of rDS gm = DSVDS | VDS ,const . (5)
Transfer Characteristics:- The transfer
characteristics depicts the relationship between the
IDS and VGS for different values of VDS.
Fig 11 Transconductance Curves for different VDS
dc (V)
From the IV characteristics plot of the Figure 11, we
Fig 9 Transfer Curves for VDS = 0.5V can observe that the IDS depend upon VGS in triode and
cut off region. Fig 12 and Fig 13 shows the second
and third order derivative of IDS with respect to VGS.
Test bench for PMOS
For PMOS, we plot the output I-V characteristics
Fig 12 Second Order Derivative of IDS with VGS using source to drain voltage (VSD) and transfer
characteristics using source to gate voltage (VSG).
Output Characteristics:-Voltage V1 (VSG) is
assigned a parametric value “a” and V2 (VSD) is
swept from a value of 0 to 1 V in steps of 10mV to
obtain the output characteristics. Fig 15 shows the
plot of IDS Vs VSD with VSG = 0.5V. It is pertinent to
note that the current in PMOS flows from source to
drain.
Fig 13 Third Order Derivative of IDS with VGS
PMOS Characteristics:-The characteristics for the
PMOS can be obtained by using the test bench shown
in Fig 14. In PMOS, the source is always kept at a
higher potential than drain and gate. This condition is
implemented in the test bench by keeping the source
at ground potential and applying negative potential to
Fig 15 Output Characteristics for VSG = 0.5V
the gate and drain terminal.
For studying the effect of various values of VSG on
the output characteristics, a parametric analysis is
performed in the Analog Environment of Cadence
and the following curves as shown in Fig 16 are
obtained. The value of variable voltage ‘a’ i.e. VSG
goes from 0 to 1 V in steps of 100mV.
Fig 18 First order Derivative of rDS
Fig 16 Output I-V Curves for different values of VSG
Fig 19 Second Order Derivative of rDS
Drain to Source Resistance (r DS) ;- The rDS for PMOS
is calculated similarly to the NMOS by taking the Transfer Characteristics : As in case of NMOS, the
inverse of the derivative of ISD vs VSD as mentioned in transfer characteristic curves are obtained by
equation (3). sweeping the value of VSG from 0 to 1 in steps of
10mV and VSD is assigned a parametric value ‘a’.
Fig 20 Plot of ISD vs VSG for VSD = 0.5 V
Fig 17 rDS curve with respect to VDS
Fig 20 shows the plot for ‘a’ = 0.5V and Fig 21
Fig 17 shows the plot of r DS with VDS for different shows the plots for different values of parameter ‘a’
values of VGS. The first order and second order or VSD.
derivatives of rDS have been shown in Fig 18 and Fig
19.
Fig 21 Transfer curves for different values of VSD
The transconductance, second and third order Analysis of Tranconductance:- The
derivatives curves are plotted on similar lines as in maximum value of first order derivative of transfer
NMOS and are shown in Fig 22, 23 and 24 curves in our case is obtained at V DS = 1V and VGS =
respectively. 0.89V giving a value of gm = 0.1141m (mho) for
NMOS. For PMOS transistor the maximum value of
transconductance gm=57.89µ(mho) occurs at
V1=VSG=0.98V and V2=VSD=1.0 V.
According to our analysis of g m, the trans
conductance plot can be divided into three regions
depending upon the value of VGS .
1) VGS < VTH : The device is in cut off region and
there is no current flowing from drain to source and
hence gm = 0.
2) VTH < VGS < VDS +VTH : The device is in saturation
region as VDS is greater than the overdrive voltage.
Fig 22 Transconductance curve for different VDS Differentiating the first order Ids equation, we get the
trans-conductance as :
Gm = d/dx(1/2. un. W/L.(VGS –VTH)2).(1 +VDS))
=un.Cox.W/L.(VGS – VTH).(1 +VDS) (6)
which tells us that the gm varies linearly with VGS and
increases with increase in V DS. But looking at the
second order derivatives in the region between VTH
<VGS < VTH + VTH in Fig 12, we observe that the
curve has a positive slope instead of a constant which
indicates that gm depends upon VGS in saturation
region too and the that’s why the gm vs VGS curve is
not perfectly linear in this region. The maximum
value of VGS for which the NMOS can stay in
Fig 23 Second Order Derivative of IDS with VGS
saturation region is VDS + VTH. This point also gives
us the maximum value of gm. This could be
confirmed by looking at the value of IDS in second
order derivative plot at VGS = VTH + VDS which is zero
indicating maximum value of VGS at that point.
3) VGS > VDS + VTH: - The device is in triode region
as VDS is less than the overdrive voltage. By
differentiating the first order equation of IDS in triode
region we, get
gm = ux..Cox.W/L(VDS) ((1 +VDS) (7)
indicating that the value of gm gets constant in this
Fig 24 Third Order Derivative of IDS with VGS region. But we observe a decrease in the value of g m
with increase in VGS. This could be accounted by
looking at the second and third order derivative plots already known theoretical results obtained by
of Ids in this region. As per the first order equation of analyzing the first order differential equations and
gm, the second order derivative value in this region certain discrepancies are found in the results
should be zero but we see non-zero values in both obtained. It is observed that the results obtained by
second and third order derivative plots indicating that Cadence calculator are more accurate than those
there is dependency of gm on higher orders of VGS. computed by first order calculations because Cadence
Moreover the negative values of second and third tool takes into account the dependency of drain
derivative indicates the decreasing or negative effect current on higher orders of VGS and VDS.
of the higher powers of VGS in triode region which
are responsible for decrease in transconductance References :
value.
[1] “Design of Analog CMOS Integrated
Analysis of Off Currents: Ioff is defined as the Circuits” by Behzad Razavi, Tata McGraw Hill
Publication.
drain current measured with VGS = 0 and VDS = V DD
which is 1 Volt in our case. It is important to keep
this off current to a very low value in order to
minimize the static power that a circuit consumes
even in standby mode. In our experient, the value of
this current for NMOS is 25.0650 nA with VGS = 0 and
VDS = 1V. For PMOS this value is 6.13731 nA.
Fig 25: Plot of NMOS IDS for VGS = 0
This off current comes into existence due to reverse
saturation current generated by reverse biased p – n
junctions formed between drain – bulk and source –
bulk regions.
Conclusion: Through this assignment, we
accomplished the goal of learning and implementing
the Cadence tool for analyzing the characteristics of
NMOS and PMOS transistors using the generic 90nm
CMOS technology. The results obtained by Cadence
simulation tool, SpectreS are compared with the
