Chapter-2 Parallel Interfacing With Microprocessor Based System ‘A Parallel Interfacing is a method of conveying multiple bits of data simultaneously. ¢ It is widely used in Ics,Peripheral buses, memory devices such as RAM. ‘+ It achieves faster communication but becomes expensive due to need of multiple wires. “ In addition, Parallel data channels are susceptible to OE ne electromagnetics interference between wires. + It transfers n-bit data at same time using n no. of wires. goRees: Serial interface example (MSB first) ~ nse ase "Se 7, BESS ES2.1 Methods of Parallel data transfer :- * Itis used for short distance where speed of information transfer is critical. * This form is found in newer type of computer peripheral equipment with transfer speed of to one million characters. * The information exchanged between a up and an I/O interface circuit consist of i/p or o/p data and control information. * If the device operates at different speeds ,then yp can be used to select a particular speed of operation of device. The techniques used to transfer data between different speed devices and computer is called synchronizing. Some of the ways of synchronizing are :- simple I/O, Simple strobe I/O, Single/Double Handshaking. 2.1.1 Simple I/O :- Data can be read or written at any time . * When you need to o/p data to a simply display like LED, you have to connect i/p of the LED buffer on o/p port line and o/p require logic level(‘1’ or ‘0’) to turn on light. The LED is always there and ready to accept data at any time. * To get digital data from a simple switch into yp, switch is connected on i/p port line from which port can be read.+ The data is always present and ready to read at any time. * useful when the data timing is unimportant. * For input --The microprocessor reads the interface chip and the interface chip returns the voltage levels on the input port pins to the microprocessor. * For output --The interface chip places the data that it received from the microprocessor directly on the output port pins. DATABUS x = where cross lines represent the time at which a new This timing waveform illustrates the simple 1/O. data byte becomes valid on the output lines of the port.Absences of other waveforms indicate that this output operation is not directly dependent on any other signals. For e. Switch and LED interfacing with Microprocessor2.1.2 Simple Strobe I/O :- Only valid data is read or written using strobe signal. * valid data is present on an external device only at a certain time and must be read in at that time. * Here a strobe pulse is supplied to indicate the time at which data is being transmitted. * E.g. the ASCIl-encoded keyboard. When a key is pressed, circuitry on the keyboard sends out the ASCII code for the pressed key on eight parallel data lines, and then sends out a strobe signal on another line to indicate that valid data is present on the eight data lines. * lp need to wait until device is =| =... Sf ready for operation and also known as Ds simple wait 1/0. DATA BUS x ml * Strobe I/O is time dependent that means data can be read or written at interval of time when strobe signal tells data is valid, * It doesn’t work for higher speed data transfer.The sending device, such as a keyboard, outputs a parallel data on the data lines, and then outputs an STB signal to let you know that valid data is present. For low rates of data transfer, such as from a keyboard to a MP, a simple strobe transfer works well. However, for higher speed data transfer, this method does not work because there is no signal which tells the sending device when it is safe to send the next data byte. In other words, the sending system might send data bytes faster than the receiving system could read them. To prevent this problem, a handshake data transfer scheme is used. For input -- the interface chip latches the data into its data register using the strobe signal. For output --the interface chip places the data on port pins that it received from the microprocessor and asserts the strobe signal. The output device latches the data using the strobe signal.Handshaking - microprocessor. + Handshaking is the method that synchronize the I/O device with microprocessor. Handshake data transfer use signal between the microprocessor and the peripheral devices for communicating. * Types of handshakes in parallel interfacing: Single handshake & Double handshake. 2.1.3 Single Handshaking :- It can have two transfer schemes i.e. “Input Handshake(Peripheral to Microprocessor) :- + The peripheral outputs some data and send signal to microprocessor to tell “Here is the data for you”. _ A * Microprocessor detects asserted signal, reads \ / the data and sends an acknowledge signal (ACK) to indicate data has been read and peripheral can send next data, “I got that ACK one, send me another”. * Microprocessor sends or receives data when peripheral >#* is ready. 1/0 devices accept or release information at much slower rate than the Fig: Single Handshaking+ Output Handshake (Peripheral from Microprocessor): Microprocessor outputs data to peripheral and asserts a strobe (STB’) signal. If peripheral is ready it answers back with acknowledgement (ACK) signal to microprocessor. 2.1.4 Double Handshaking:-For data transfers where even more coordination is required between the sending system and the receiving system, a double handshake is used. It can have two transfer schemes. a. Input Handshake (Peripheral to Microprocessor): ara: - \ a + The peripheral asserts its line low to ask t { Nd microprocessor “Are you ready?” Dw —— + The microprocessor raises its ACK line high to say “Iam ready”. a * Peripheral then sends data and raises its line low to say “Here is some valid data for you.” + Microprocessor then reads the data and drops its ACK line to say, “I have the data, thank you, and | await your request to send the next byte of data.” Fig: Double Handanasingb. Output Handshake (Peripheral from Microprocessor): Microprocessor sends a strobe (STB’) signal and data and peripheral sends acknowledgement (ACK) signal. 2.2 8255 as General Purpose Programmable I/O Device and its interfacing examples :-The Intel 8255 A is a general purpose programmable I/O device designed for use with Intel microprocessors. * 8255A is widely used programmable parallel I/O device. It can be programmed to transfer data under various conditions, from simple |/O to interrupt 1/O. It is flexible, versatile and economical (when multiple |/O ports are required), but somewhat complex. It is an important general purpose I/O device that can be used with almost any microprocessor. + 8255 Programmable Peripheral Device (PP!) is a general purpose programmable 1/O device designed to interface the CPU with its outside world such as ADC, DAC, keyboard etc. We can program it according to the given condition. It can be used with almost any microprocessor. * It can be used with other yp 8085,8086,8088,pentium etc. * It has 24 1/O pins that can be grouped primarily in two 8-bit parallel ports: A and B, with the remaining bits as port C. The 8-bits of port C can be used as individual bits or be grouped in two 4-bits ports: C upper (Cu) and C lower (Cl). The functions of these ports are defined by writing a control word in the control register.Pin Description :- LS] FUNCTION OF PIN 0-07 (Data Bus) PAO-PA7 (Port A) PBO-PB7 (Port B) These are bidirectional, tri-state data bus lines are connected to the system data bus. They are used to transfer data and control word from microprocessor (8085) to 8255 or receive data or status word from 8255 to the 8085. These are 8 Bit bidirectional I/O pins used to send data to output device and to receive date from input device. It functions as an & Bit data output latch/buffer when used in output mode and as an 8 Bit data input latch/butfer when used in input mode. These are & Bit bidirectional I/O pins used to send data to output device and to receive data from input device. It functions as an 8 Bit data output latch/buffer when used in output mode and as an 8 Bit data input latch/buffer when used in input mode, Pas pra, Pa? 39 B pay Pa ]3 38 Ba, Paola a7 BPA, ws 36 Fw Sas 35 reser ono 7 34 Fp, acs 3 Fo, As 2 Ep, Pc, h10 31, ran 8255A ,, soy Pes hia 2 Ap, Pots =D Peo 14 af, PC 415 BD Vec Pe 446 25 Hee, PC haz 24 DPB, P18 23 Fee, Po, Ch19 2be, 8, C420 21 Aes, Pin Diagram of 8255 PPIEa Biter ean These are 8 bit bidirectional I/O pins divided into two groups PCL (PC3-PC) and PCU (PC7-PC4).these groups can individually transfer PCO-PC7 data in or out when programmed for simple I/O, and used as. (Port C) handshake signals when programmed for handshake or bidirectional modes. = When this pin is low, the CPU can read data in the ports or the status RD word through the data bus buffer. - When this pin is low, the CPU can write data on the ports or in the WR control register through the data bus buffer. - This pin can be enabled for data transfer operation between the CPU cs and 8255. This used to reset 8255.i.e control register gets cleared and all RESET the ports are set to the input mode.Em FUNCTION OF PIN The selection of input port and control word register is done by using AO and Al pins In conjunction with RD and WR pins. A0-AL 0 x RK RROOROO xX RK RORGOKO BRRROOO Rox 1 a) i. oO o ° oO x a x o o oO o °o ° oO a o oO PORT A TO DATA BUS PORT B TO DATA BUS PORT C TO DATA BUS. DATA BUS TO PORTA DATA BUS TO PORT B DATA BUS TO PORT C DATA BUS TO CONTROL REGISTER DATA BUS TRI STATED ILLEGAL CONDITION DATA BUS TRI STATEDIntel 8255A Architecture :- — Fig: Block diagram of 82554.It has following blocks which is described below:- Data bus buffer :- It is tristate 8-bit bidirectional bus. It is used to interface 8255 to system bus. Data is transmitted (tx.) or received (rx.) by buffer upon execution of |/O instruction by CPU control word and status information are also transferred through data bus buffer. * It is used to connect the internal bus of 8255 with the system bus so as to establish proper interfacing between the two. The data bus buffer allows the read/write operation to be performed from/to the CPU. b) Read/Write Control logic :- The function of the block is to manage all of the internal and external transfers of both data and control or status words. a * It accepts inputs from the CPU address and control buses and in turn, issues commands to both of the control groups. Chip select(Cs’):A LOW on this input selects the chip and enables the communication between the 8255A and the CPU. It is connected to the decoded address, and AO & Al are connected to the microprocessor address lines. Their result depends on the following conditions:cs AL Ao Result ° ° ° PORT A o ° 1 PORT B ° a © PORT C ° 1 1 Control Register 1 x x No Selection Write(WR’):This control signal enables the write operation. When this signal goes low, the microprocessor writes into a selected I/O port or control register. Read (RD’): This control signal enables the Read operation. When the signal is low, the microprocessor reads the data from the selected I/O port of the 8255. RESET: This is an active high signal. It clears the control register and sets all ports in the input mode. AO and A1: These input signals work with RD, WR, and one of the control signal. Following is the table showing their various signals with their result.c)Group A and Group B controls: Functional configuration of each port is programmed by the system software. * In essence, the CPU outputs a control word to the 8255A. * The control word contains information such as “mode”, “bit set’, “bit reset”, etc. that initialize the functional configuration of the 8255A. * Each of the control blocks (Group A and Group B) accepts “commands” from the Read/Write control logic, receives control word from the internal data bus and issues the proper commands to its associated ports. Control Group A— Port A and Port C Upper (C7 - C4) Control Group B — Port B and Port C Lower (C3 - CO) 8255 functions in two modes: “Bit Set/Reset mode: The BSR mode is used to set or reset the bits in port C. + yo mode: The I/O mode is further divided into three modes: mode 0, mode 1 and mode * mode 0: In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit ports. Each port can be programmed in either input mode or output mode where outputs are latched and inputs are not latched. Ports do not have interrupt capability.* Mode 1: In this mode, Port A and B is used as 8-bit I/O ports. They can be configured as either input or output ports. Each port uses three lines from port C as handshake signals. Inputs and outputs are latched. * Mode 2: In this mode, Port A can be configured as the bidirectional port and Port B either in mode 0 or mode 1. Port A uses five signals from Port C as handshake signals for data transfer. The remaining three signals from Port C can be used either as simple I/O or as handshake for port B. Control Word :- When AO and Ai pins have value 1, the mapped address addresses the control register which is the 8-bit register to write the specific content according to the port conditions although it cannot be read. The content of this register is called control word which specifies an I/O function for each port. * The MSB (D7) of the control word tells which control word we are sending it that is it specifies either the I/O function or the Bit Set/Reset function. * If bit D7=1, bits D6-DO determine 1/O functions in various modes as shown in figure. If bit D7=0, port C operates in the Bit Set/Reset (BSR) mode.The BSR control word does not affect the functions of ports A and BTo communicate with peripherals through 8255, following are the steps are necessary. * Determine the Port addresses of Ports A, B and C and of the control register according to * Chip Select logic and address lines A1 and AO. * Write a control word in control register. * Write 1/0 instructions to communicate with peripherals through Ports A, B and CREFERENCES * Insights on Instrumentation II by Er. Hari Prasad Aryal & Er.Shyam Dahal * Microprocessor Architecture,programming and applications with 8085 by Ramesh Gaonkar. * Notes by Er.Saban kumar k.c.