Johnson Counter (/verilog/verilog-johnson-counter)
Mod-N Counter (/verilog/verilog-modn-counter)
Gray Counter (/verilog/verilog-gray-counter)
Misc
n-bit Shift Register (/verilog/verilog-n-bit-shift-register)
Priority Encoder (/verilog/verilog-priority-encoder)
4x1 multiplexer (/verilog/verilog-4to1-mux)
Full adder (/verilog/verilog-full-adder)
Single Port RAM (/verilog/verilog-single-port-ram)
D Latch
A flip-flop captures data at its input at the positive or negative
edge of a clock. The important thing to note is that whatever
happens to data after the clock edge until the next clock edge
will not be reflected in the output. A latch on the other hand,
does not capture at the edge of a clock, instead the output
follows input as long as the enable pin is asserted.
Design
In this example, we'll build a latch that has three inputs and
one output. The input d stands for data which can be either 0
or 1, rstn stands for active-low reset and en stands for enable
which is used to make the input data latch to the output.
Reset being active-low simply means that the design element
will be reset when this input goes to 0 or in other words, reset
is active when its value is low. The value of output q is
dictated by the inputs d, en and rstn.
(/images/verilog/latch1.png)
1 module d_latch ( input d, // 1-bit inp
2 input en, // 1-bit inp
3 input rstn, // 1-bit inp
4 output reg q); // 1-bit out
5
6 // This always block is "always" triggered whe
7 // If reset is asserted then output will be ze
8 // Else as long as enable is high, output q fo
9 always @ (en or rstn or d)
10 if (!rstn)
11 q <= 0;
12 else
13 if (en)
14 q <= d;
15 endmodule
Note that the sensitivity list to the always block contains all
the signals required to update the output. This block will be
triggered whenever any of the signals in the sensitivity list
changes its value. Also q will get the value of d only when en
is high, and hence is a positive latch.
Schematic
(/images/verilog/schematic/d_latch_schematic.png)
Testbench
(/images/verilog/latch2.png)
1 module tb_latch;
2 // Declare variables that can be used to drive
3 reg d;
4 reg en;
5 reg rstn;
6 reg [2:0] delay;
7 reg [1:0] delay2;
8 integer i;
10 // Instantiate design and connect design ports
11 d_latch dl0 ( .d (d),
12 .en (en),
13 .rstn (rstn),
14 .q (q));
15
16 // This initial block forms the stimulus to te
17 initial begin
18 $monitor ("[%0t] en=%0b d=%0b q=%0b", $time
19
20 // 1. Initialize testbench variables
21 d <= 0;
22 en <= 0;
23 rstn <= 0;
24
25 // 2. Release reset
26 #10 rstn <= 1;
27
28 // 3. Randomly change d and enable
29 for (i = 0; i < 5; i=i+1) begin
30 delay = $random;
31 delay2 = $random;
32 #(delay2) en <= ~en;
33 #(delay) d <= i;
34 end
35 end
36 endmodule
To make our testbench assert and deassert signals in a more
random manner, we have declared a reg variable called
delay of size 3 bits so that it can take any value from 0 to 7.
Then the delay variable is used to delay the assignment of d
and en to get different patterns in every loop.
Output
Simulation Log
ncsim> run
[0] en=0 d=0 q=0
[11] en=1 d=0 q=0
[18] en=0 d=0 q=0
[19] en=0 d=1 q=0
[20] en=1 d=1 q=1
[25] en=1 d=0 q=0
[27] en=0 d=0 q=0
[32] en=0 d=1 q=0
[33] en=1 d=1 q=1
[34] en=1 d=0 q=0
ncsim: *W,RNQUIE: Simulation is complete.
Click on the image to make it larger.
(/images/verilog/d-latch.PNG)
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