Omria46ion. Advanced Information Preliminary Datasheet 0V2640 Color CMOS UXGA (2.0 MegaPixel) CamernaCuip™ with OmniPixel2™ Technology General Description ‘The OV2640 CamrenaCiie™ is a low voltage CMOS image sensor thal provides ihe ful functionally of & single-chip UXGA (1632x1232) camera and image processor in a smal footprint package, The OV2640" grevides full ammo, subsampled, scaled or windowed 8-1/T0-bl images in a sp ange ol ora conraleg vough he Sota Camera Applications Callular and Camera Phones Toys PC Multimedia Digital Stil Camocas Key Specifications Control Bs (SCCB) interface ay UXGA TOOT Tis product has an image aay capabie of operating a Core | RWI to 18 frames per second {(ps) im UXGA ‘esoluton with | Power Supply Rnalog|2.5 ~ 80VDo_——| Compete user corto! over image aualiy. formatting end ahr Iviesav —————] pul cata raster All required image processing tunetons, 25 mW (lr 15 ps, UGS iing exposure contol, gamma. while balance, color Po IYUV mode} Saturation, hue convo, while. pixel canceling, nose wer ‘Active 4g a (or 1516s, UXGA | Ganeeling, and: more, ar9 also programmable tough the | Requirements| eae eos as: ‘SCGB inlodaco, "The ‘OV2640 also Includes a comprossion ar engine "for ncreased processing “power. in 'eddlion, — | —yassraraeg Srrnivietn CaverAcin use preptetay sensor technology PRFSTUFS Stable Image|0-C 0 50°C fo improve mage quality by reducing or @immnating comman nae Homioflctien sours mage Contamination, such ae f ruveaaazoyveucrs fixed pattern noise, smearing, el. to produce a clean, fuly Qt i ‘ sable color image. Output Formats (6b). 5.5 compressed data + 8:/10-0t Raw GB cata Note: The OV2640 uses a lead-free Lens Size] 1 package ‘hier Ray Anglo 25° ron-tnear ‘Woximum| UXGA'SXGA|'5 jos image ‘SVGAISO ps Features. ‘Transter Rate|” ‘CIF|50 ips + High sensitivity fr lowight operation ‘Sensitivity 0.8 Voss igh sensitviy for wright operation sgnattyj 06 Vn + Low operating voltage for embedded portable apps + Standard SCCB interface + Output suppor for Raw RGB, RGB (AGBSESISSS), ‘GRB422, YUV (420/420) and YCbCr (4:2:2) formats + Supports image sizes: UXGA, SKGA, SVGA, and any ‘ize scaling dawn tram SXGA to 40x30 \VarioPixel® method for sub-samping + Automatic image contr! functions inélusing Automatic Exposure Control (AEC), Automatic Gain Control (AGC), Automatic White Belance (AWB), Automatic Band Filler (ABF), and Automatic Black-Level Calibration (ABLC) + Image quality contro including color saturation, ‘gamma, sharpness (edge enhancement), lens ‘correction, white pixel cancoling, noise cancating, and 50/80 H2 luminanice detection + Line optical black level ouput capabity + Video or snapshot operation Zooming, panning, and windowing functions Intexnalextemal frame synchrorization Variable frame rate conto! Supports LED and flash strobe mode Supporss scaling Supparis camprossian Embedded microcontroller Ordering Information Product Package (OVO2640-VLA (Color, leac-iee) | 96-pin CSP2. Dynamic Range|50 dB "Sean Wode| Progressive [Maximum Exposure Interval] 1247 x ‘Gamma Correction [Programmable Pheel Size|2.2 jim x 2.2 am Dark Current|15 mVis at 60°C. ‘Well Capacity|12 Ke. Fixed Pattern Noise|<1% oT Vera Tevage Area] 3500 umn ¥ 2664 Uh Package Dimensions| Figure 1 0V2640 Pin Diagram (Top View) x 6285 um ® @ © ® @ ® ® ® @ @ ovo @ ® @@ Version 1.8, April 14, 2008, ‘Proprietary to OmuiVision Technologies TOV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CameRacnip™ OnMBF Functional Description Figure 2 shows the functional block diagram of the ©V2640 image sensor. The OV2640 includes: + Image Sensor Array (1632 x 1282 total image array) + Analog Signal Processor + 10BitAID Converters + Digital Signal Processor (DSP) + Output Formatter + Compression Engine + Microcontroller + SOCB Interface + Digital video Port Figure 2. Functional Block Diagram =a Be bees [ae J rom ta ae ee OS | i react = gq fab! 5 Lt ES | 2 Propriciary © OmniVision Techologies ‘Version 1.8, April 14, 2006Onion Functional Description Image Sensor Array ‘The OV2640 sensor has an image array of 1632 columns, by 1232 rows (2,010,624 pixels), Figure 3 shows a cross-section of the image sensor array. Figure 3. Sensor Array Region Color Filter Layout enn 555585 The color fiters ate arranged in a Bayer pattor, The) primary color BG/GR array is arranged in line: alternating fashion, Of the 2,010,624 pixels, 1,991,040 (1682x1220) are active, The other pixels are used for black level calibration and interpolation. ‘The sensor array design is based on afield integration read-out system with line-by-line tansler and an electronic shutter with a synchronous pixel) read-out sehemo. Analog Amplifier When the coldmn sampieitold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. Gain Control ‘The ampliior gain can either be programmed by the user Cr controled by the internal automatic gain control circuit (asc). ‘Version 1.8, April 14, 2008 ‘Proprietary to OmaiVision Technologies 30v2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CameRaCHip™ On ME jure 4 Windowing ‘column columns Start End wees [| coum py 7 ow start le, Display ie Window ow End ‘Sensor Array Boundary Zooming and Panning Mode ‘Tho 0V2640 provides zooming and panning modes. The user can select this mode under SVGA/CIF mode timing. The related zoom ratios willbe 2:1 of UXGA for SVGA and 4:1 of UXGA for CIF, Registers ZOOMS|7:0) (0x48) and COMIS{1:0} (Ox48) define the vertical line start point Rogister ARCOM2[2} (0x34) defines the horizontal start point ‘Sub-sampling Mode ‘The 0V2640 supports two sub-sampling modes: Each sui-sampling mode has different resolution and maximum frame rate. These modes are described in the following sections. SVGA mode The 0V2640 can be programmed to output 800 x 600 (SVGA) sized images for applications where higher resolution image capture is not required. In this mode, booth horizontal and vertical pixels will be sub-sampled with an aspect ratio of 4:2.a5 shown in Figure 6 Figure 5 SVGA Sub-Sampling Mode Cetin». ———————> Hho ros CIF Mode ‘The OV2640 can also operate at a higher frame rate to output 400 x 296 sized images. Figure 6 shows the sub:sampling diagram in both horizontal and vertical irections for CIF made. Figure 6 CIF Sub-Sampling Mode Timing Generator and Control Logic In general, the timing generator controls the following + Frame Exposure Mode Timing + Frame Rate Adjust + Frame Rate Timing Frame Exposure Mode Timing Tho OV2640 supports frame exposure mode. Typically, the frame exposure mode must work with the aid of an external shutter ‘The frame exposure pin, FREX (pin B2), Is the frame exposure mode enable pin and the EXPST_& pin (pin A2) serves as the sensor's excosure start trigger. When the external master device asserts the FREX pin high, the sensor array Is quickly pre-charged and stays in reset mode until the EXPST_B pin goes low (sensor exposure time can be defined as the period between EXPST_B low and shutter close). After the FREX pin is pulled low, the Video data stream is then clocked to the output port in a line-by-ine manner. After completing one frame of data 7 Propriciary OmniVision Techuologies ‘Version 1.8, April 14, 2006Onion Functional Description ‘output, the OV2640 will output continuous lve video data Unless in single frame transfer mode. Figure 18 and Figure 19 show the detailed timing and Tabio 11 shows, the timing specifications for this made. Frame Rate Adjust The OV2640 offers thee methods for trame rate agjustment + Clock prescaler: (see "CLKAC" on page 23) By changing the system clock divide ratio and PLL, the frame rate and pixel rate will change together. This method can be used for dividing the frame’pixel rate by: 1/2, 1/3, 1/4 ... 1/84 ofthe input clock rate. + Line adjustment: (see "REG2A” on page 26 and “FRARL’ on page 20) By adding a dummy pixel timing in each Ine (Between HSYNC and pixel data out), the trame rate can be changed while leaving the pixel rate ass. + Vertical sync adjustment: By adding dummy line periods to the vertical sync period (see “ADDVSL” on page 26 and “ADDVSH' ‘on page 26 oF see “FLL” on page 27 and "FLH" on page 27), the frame rate can be altered while the pixel rate remains the same, Frame Rate Timing Detaut frame timing is ilustated in Figure 15, Figure 16, and Figure 17. Refer to Table 1 for the actual pixel rate at different frame rates. Table 1 —_Frame(Pixel Rates in UXGA Mode Frame Rate(tps) | 15 | 7.6 | 25 | 1.25 PCLK (MHz) 36 | io) 6 3 Digital Signal Processor (DSP) This block conttOls the interpolation from Raw data 10 RGB and some image quality contol. + Edge’enhiancement (a two-dimensional high pass filter) + Color space converter (can change Raw data to RGB or YUV¥CDCr) + RGB matrix to eliminate color cross talk + Hue and saturation control + Programmable gamma control + Transfer 10-bit data to 8-bit + White pixel canceling + De-noise Output Formatter This block contros all output and data formating required prior to sending the image out, Scaling Image Output The OV2640 is capable of scaling down the image size {rom CIF to 40x30. By using SCCB registers, the user can ‘output the desired image size. At certain image sizes, HREF is not consistent in frame. Compression Engine As shown i Figuf® 7, the Compression Engine consists ‘of three major blocks: + por + a +. Entropy Encoder Figure 7 Compression Engine Block Diagram 0a) (YE) (Ar Microcontroller ‘The OV2640 embeds an Bbit microcontroller with 512-byte data memory and 4 KB program memory. It provides the flexibility of decoding protocol commands from the host for controling the system, as well as the ability to fine tune image quality SCCB Interface “The Serial Camera Control Bus (SCCB) interface controls the CAMERACHIP operation. Refer to OmniVision Technologies Serial Camera Control Bus (SCCB) ‘Specification for detailed usage of the serial contol por. Slave Operation Mode ‘The OV2640 can be programmed to operate in slave mode (default is master mode), ‘When used as a slave device, COM7[3] (0x12), CLKRCI6] (0x11), and COM2[2} (0x09) register bits should be set to ‘Version 1.8, April 14, 2008 ‘Proprietary to OmuiVision Technologies 50v2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CameRaCHip™ On ME 1" and the 0V2640 will use PWON and RESETS pins as vertical and horizontal synchronization triggers supplied by a master device, The master device must provide tho following signals: 1, System clock MCLK to XVCLK pin 2, Horizontal sync MHSYNC to RESETE pin 3. Vertical frame syne MVSYNC to PWDN pin ‘See Figure 8 for stave mode connections and Figure ® for detailed timing considerations. Figure 8 Slave Mode Connection ve:0) F— resers |——| syne pwon | mvsyne xvetk fe micux ov2640 Master Device Figure 9 Slave Mode Timing Power Down Mode Two methods are available to place the OV2640 into power-down mode: hardware power-down and SCCB software power-down, To initate hardware power-down, the PWON pin (pin BS) must be tied to high. When this ocours, the OV2640 intemal device clock is halted and all internal counters are reset. The current draw is less than 15 uA in this standby mode. Executing a software power-down through the SCCB interface suspends internal circuit activity but does not halt the device clock. The current requirements drop to less than 1 mA in this mode, All register content is maintained in standby mode, Digital Video Port MSB/LSB Swap ‘The OV2640 has a 10-bit digital video port. The MSB and LSB can be swapped with the control registers. Figure 10 shows some examples of connections with external devices. Figure 10. Connection Examples Note: 2 Tine 1) Tug > 6 Tes TV8> Tine “ps me 1922 x Tox (UXGA) Tine= 1190 ¥ Tex (SVGA); eo eo" Tina = 595 xT (CIF) a ally 3) Thane = 1248 X Ting (UXGA); Tyne = 872 x Thy (SVGAY wee sl" Thame = 998 x Tine (CIF) senj—e _| [wey ‘Strobe Mode, ‘The OV2640 nas a Strobe mode that allows itto work with ‘an external lash and LED. Reset ‘The ©V2640 includes a RESETS pin (pin C6) that forces a complete hardware reset when itis pulled low (GND). ‘The OV2640 clears all registers and resets them to thelr default values when a hardware reset occurs. A reset can also be initiated through the SCCB interface. és Propriciary © OmniVision Techologies ‘Version 1.8, April 14, 2006Onion Functional Description Line/Pixel Timing ‘The OV2640 cigital video port can be programmed 10 work in either master or slave mode. In both master and slave mades, pixel data output is synchronous with PCLK (or MCLK if port is a slave), HREF, and VSYNC. The default PCLK edge for valid data, Is the negative edge but may be programmed using register COM0(4] for the positive edge. Basic line/pixel ‘output timing and pixel timing specifications are shown in Figure 14 and Table 10. ‘Also, using register COM 0[S}, PCLK output can be gated PeuK Pixel Output Pattern ‘Table 2 shows the output data order from the OV2640. ‘The dala output sequence following the frst HREF and alter VSYNG is: Byo Go, Boa Go-- Bosece Go s00 ‘Ate the second HREF the outbutis Gy 0 Ry 3 Gy2 Rha. G 4598 Ry y500--». ete. If the OV2640 is programmed to output SVGA resolution data, horzontal and vertical sub-sampling wil occur. The defauit ouput sequence for the first line of output willbe: By 9 Gos Bp « Gps Bo 1506 Go 97. The second line of output wil Be: Gyo Ry,1 Gg Ry. 5-- Gy,1596 Fy 1597. ec sce a aBE HREF PeuK Table2 Data Pattern by the active video period defined by the HREF signal See Figure 11 for details. rc|o | + |2 {| 3 1508 | 1590 Figure 11 PCLK Output Only at Valid Pixels © | Boo | (Gor | Boz | Sos Bosse | Go.sse 1 | G0 | Fas | Gia | Ais Sassae | Pescoe 2 | Boo [Gos | Bee | ra Bossan | Gassea 3 | Geo | Ran)] G22 | Fas Gajsse | Pe.sso0 vsyne JL n ‘The specifications shown in Table 10 apply for VDD =+1.2V, DOVDD = +28 V, Ty = 25°C, sensor working at 15 fps, external loading = 20 pF. 1198 | 84990|61198.|81198|Sr1689] --- [81106 1509| St. .00 1199 |Gris9o]F 11903 |Grisa2|Riv9ea] -[Sr199 1298] 199.199 Version 1-8, April 14, 2008, ‘Proprietary to OmuiVision Technologies 7OV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CameRacnip™ OnMBF Pin Description Table3 Pin Description Al DOGND Ground — | Ground for cata video port Snapshot Exposure Stan Trager exest.s | input Sans een ot een ane nce Noto: There is no intemal pul-uppul:down resistor 8 ‘AGND Ground | Ground for analog crit a SGND Ground | Ground for sensor array a5 VREFN | Reference | Internal analog reference - connect o ground using a0.1 uF capactor Flash control output 6 STROBE v0 Default: Input Note: There is no intertal pull-up/pul-down resistor. Bt bovpp Power | Power for digital video port ut | Snapshot trigger use to activate a snapshot sequence B2 FREX 'nput | Note: There is no internal pul-uprpull-down resistor. 83 VDD Power | Power for analog ercut Be ‘svoD Power | Poworforsensor aray 85 svoD Power | Power for sensor array Powerdown made enable, active high 86 PWON 'npUt__s}'Note: There is an internal pul-down resistor. or sI0_D VO | SCCB serial interface data VO ce s10.¢ Inpur | SCOB Serial intertace clock input Note: There is no internal pul-up‘pull-down resistor. Horzontal reference output 3 HREF 10 Default: Input Note: There is no internal pull-upipull-down resistor. ‘System clock input oe ace Input | Note: There isn internal pul-up/pull-down resistor. cs VREFH Reference | Internal analog reference - connect to ground using a 0.1 HF capacitor off nee, inpur | Reset mode, active ow Note: There is an internal pull-up resistor. Vertical synchronization output D2 vsyne v0 Default: Input Note: There Is no internal pull-up/pull-down resistor. D6 No . No connection Video port output bit(t] et v1 v0 Default: Input Note: There is no internal pull-up/pull-down resistor. a Propriciary © OmniVision Techologies ‘Version 1.8, Apr 14, 2006Onion Pin Description Table3 Pin Description Video port output bt{O] e2 Yo v0 Default: Input Note: There is no internal pull-up/puil-down resistor. Pixel clock output &3 POLK vo Default: Input Note: There is no internal pull-up/pull-down fesistor. Ea GND Ground | Ground for intemal regulator Video port output bit(6] Es Ye v0 Default: Input Note: There is no internal pull upipull-down resistor. 6 DGND Ground | Ground tor digital core a EvoD Power | Power for internal regulator Fe vob Power | Sensor digital power (Core) Video port outputbit(2] F3 ye v0 Dafault: Input Note: There is no internal pull-up/pull-down resistor. Video port autput bitf4] Fa va v0 Default: Input Nota: There is no internal pull-up/pull-down resistor. Video port output btfs) FS Ye v0 Default: Input Note: There is no internal pull-upipuil-down resistor. Fe vp Power | Sensor digital power (Core) Gt VoD Power | Power for internal regulator ce DaND Ground | Ground for digital core ‘Video port output bit{3] os Ys 10 Default: Input Note: There is no internal pull-up/pull-down resistor. Video port output bt(S] 4 Ys v0 Default: Input Note: There is no internal pull-up/pull-down resistor. Video port output bit(7] 65 vr v0 Default: Input Note: There is no internal pull-upipull-down resistor Video port output bit(9] 6 Yo v0 Dofault: Input Note: There is no internal pull-upipull-down resistor. Version 1.8, April 14, 2008, ‘Proprietary ta OmaiVision TechnologiesOV2640 Color CMOS UXGA (2.0 MegaPixel) OmniPixel2™ CameRacnip™ Figure 12 Pinout Diagram @® ® ® ® & & DOGND EXPST_B AGND SGND VREFN STROBE @ ® ® ® ® DOVDD FREX AVDD SVDD SVDD PWDN @@e&®® ® SIO_D SIO_C HREF XVCLK VREFH RESETB ov2640 sync Nc © ® ®@ YO PCLK EGND 6 DGND ® ® ® ® ® ® EVDD DvD 2 a Y8 DVDD agesee EVDD DGND 3 Table4 Ball Matrix A DOGND EXPST_B AGND SGND VREFN STROBE ae ea Sante ee ‘Version 1.8, April 14, 2006OmMFoo Electrical Characteristics Electrical Characteristics Table5 Absolute Maximum Ratings “Ambient Storage Temperature 40°C t0 195°C Yoon |45V ‘Supply Voltages (with respect to Ground) Vooe SV Vooo | 45V ‘All Input Output Voltages (with respect to Ground) -03V 10 VopiotV Lead-‘ree Temperature, Surlace-mount process 2450 NOTE: —Excoeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may result in permanent device damage. Table6 DC Characteristics (-30°C < Ty < 70°C) ) Voo-a | Supply voltage 2st 28 30 Voo.0 | Supoty voltage 1.24 18 1.96 Voo10 | Supoty voltage? al 28 33 ‘oona —_ | Active (Operating) Current® 20 40 ma 80 (YUV) 40 (YUV) Ioonn | Active (Operating) Current? 45 (Compressed) | 60 Compressed) | ™® oom _ | Active (Operating) Current® 6 18 ma I 1 2 ma loos soos by Curent loos-pwon 600 1200 HA Vu. Input voltage LOW, 0.54 v Vn Input votage HIGH 1.26 Cn Input capacitor 10 PF Vou Output voltage HIGH 162 Vou Output voltage LOW 0.18: v Ve SIO_CandSi0_D 05 ° 054 v Vi ‘SIO_C and SIO_D. 1.26 18 23 v Musing internal reguiatar for DVDD. Voo a requires greater than or equal 10 2.65V_ b. 1.8V UO is supported. Contac your local OmrVision FAE or further details. © Vop.a=28¥. Voo.0= 1.8¥. and Voo 19 = 1.8V for 15 lps in UXGA mode 4. loos soca rfers to SCCB inated Standby, while Ipps eyo Ffers to PWDN pad inated Standby Version 1.8, April 14, 2008, ‘Proprietary to OmuiVision Technologies 1