Avalon Interface Specifications

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Contents

1. Introduction to the Avalon Interface Specifications...................................... 1-1

1.1 Avalon Properties and Parameters......................................................................................................1-4
1.2 Signal Roles ............................................................................................................................................1-4
1.3 Interface Timing ................................................................................................................................... 1-4
1.4 Related Documents ...............................................................................................................................1-4

2. Avalon Clock and Reset Interfaces ................................................................. 2-1

2.1 Avalon Clock Sink Signal Roles .......................................................................................................... 2-1
2.2 Clock Sink Properties ........................................................................................................................... 2-2
2.3 Associated Clock Interfaces .................................................................................................................2-2
2.4 Avalon Clock Source Signal Roles ......................................................................................................2-2
2.5 Clock Source Properties........................................................................................................................2-3
2.6 Reset Sink ............................................................................................................................................... 2-3
2.7 Reset Sink Interface Properties............................................................................................................ 2-3
2.8 Associated Reset Interfaces ..................................................................................................................2-4
2.9 Reset Source ...........................................................................................................................................2-4
2.10 Reset Source Interface Properties......................................................................................................2-4

3. Avalon Memory-Mapped Interfaces............................................................... 3-1

3.1 Introduction to Avalon Memory-Mapped Interfaces ..................................................................... 3-1
3.2 Avalon Memory-Mapped Interface Signal Roles.............................................................................. 3-3
3.3 Interface Properties .............................................................................................................................. 3-8
3.4 Timing .................................................................................................................................................. 3-11
3.5 Transfers .............................................................................................................................................. 3-11
3.5.1 Typical Read and Write Transfers .....................................................................................3-12
3.5.2 Read and Write Transfers with Fixed Wait-States ..........................................................3-13
3.5.3 Pipelined Transfers ..............................................................................................................3-14
3.5.4 Burst Transfers .....................................................................................................................3-16
3.6 Address Alignment .............................................................................................................................3-19
3.7 Avalon-MM Slave Addressing .......................................................................................................... 3-19

4. Avalon Interrupt Interfaces ............................................................................4-1

4.1 Interrupt Sender ....................................................................................................................................4-1
4.1.1 Avalon Interrupt Sender Signal Roles .................................................................................4-1
4.1.2 Interrupt Sender Properties ..................................................................................................4-1
4.2 Interrupt Receiver .................................................................................................................................4-2
4.2.1 Avalon Interrupt Receiver Signal Roles ..............................................................................4-2
4.2.2 Interrupt Receiver Properties ...............................................................................................4-2
4.2.3 Interrupt Timing ....................................................................................................................4-3

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5. Avalon Streaming Interfaces .......................................................................... 5-1

5.1 Terms and Concepts .............................................................................................................................5-2
5.2 Avalon Streaming Interface Signal Roles .......................................................................................... 5-3
5.3 Signal Sequencing and Timing ........................................................................................................... 5-4
5.3.1 Synchronous Interface .......................................................................................................... 5-4
5.3.2 Clock Enables ......................................................................................................................... 5-4
5.4 Avalon-ST Interface Properties .......................................................................................................... 5-4
5.5 Typical Data Transfers ......................................................................................................................... 5-5
5.6 Signal Details ......................................................................................................................................... 5-6
5.7 Data Layout ............................................................................................................................................5-6
5.8 Data Transfer without Backpressure ..................................................................................................5-7
5.9 Data Transfer with Backpressure ....................................................................................................... 5-7
5.10 Packet Data Transfers ........................................................................................................................ 5-9
5.11 Signal Details ..................................................................................................................................... 5-10
5.12 Protocol Details .................................................................................................................................5-10

6. Avalon Conduit Interfaces ............................................................................. 6-1

6.1 Avalon Conduit Signal Roles .............................................................................................................. 6-2
6.2 Conduit Properties ............................................................................................................................... 6-2

7. Avalon Tristate Conduit Interface ................................................................. 7-1

7.1 Avalon Tristate Conduit Signal Roles ................................................................................................7-3
7.2 Tristate Conduit Properties .................................................................................................................7-4
7.3 Tristate Conduit Timing ......................................................................................................................7-4

A. Deprecated Signals.........................................................................................A-1

B. Additional Information................................................................................. B-1

B.1 How to Contact Altera......................................................................................................................... B-2
B.2 Typographic Conventions................................................................................................................... B-3

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Introduction to the Avalon Interface
Specifications 1
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Avalon® interfaces simplify system design by allowing you to easily connect components in an Altera®
FPGA. The Avalon interface family defines interfaces appropriate for streaming high-speed data, reading
and writing registers and memory, and controlling off-chip devices. These standard interfaces are
designed into the components available in Qsys. You can also use these standardized interfaces in your
custom components. By using these standard interfaces, you enhance the interoperability of your designs.
This specification defines all of the Avalon interfaces. After reading it, you should understand which
interfaces are appropriate for your components and which signal roles to use for particular behaviors.
This specification defines the following seven interfaces:
• Avalon Streaming Interface (Avalon-ST)—an interface that supports the unidirectional flow of data,
including multiplexed streams, packets, and DSP data.
• Avalon Memory Mapped Interface (Avalon-MM)—an address-based read/write interface typical of
master–slave connections.
• Avalon Conduit Interface— an interface type that accommodates individual signals or groups of
signals that do not fit into any of the other Avalon types. You can connect conduit interfaces inside a
Qsys system. Or, you can export them to make connections to other modules in the design or to FPGA
pins.
• Avalon Tri-State Conduit Interface (Avalon-TC) —an interface to support connections to off-chip
peripherals. Multiple peripherals can share pins through signal multiplexing, reducing the pin count of
the FPGA and the number of traces on the PCB.
• Avalon Interrupt Interface—an interface that allows components to signal events to other components.
• Avalon Clock Interface—an interface that drives or receives clocks.
• Avalon Reset Interface—an interface that provides reset connectivity.
A single component can include any number of these interfaces and can also include multiple instances of
the same interface type. For example, in the first figure below, the Ethernet Controller includes the
following six different interface types:
• Avalon-MM
• Avalon-ST
• Avalon Conduit
• Avalon-TC
• Avalon Interrupt
• Avalon Clock.

© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance ISO
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any 9001:2008
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, Registered
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
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Note: Avalon interfaces are an open standard. No license or royalty is required to develop and sell
products that use, or are based on Avalon interfaces.
The following figures illustrate the use of the Avalon interfaces in system designs.
Figure 1-1: Avalon Interfaces in a System Design with Scatter Gather DMA Controller and Nios II
Processor

Printed Circuit Board SSRAM Flash DDR3

Cn Cn Cn

Cn
Altera FPGA
Tristate Conduit
Bridge
M Cn TCS
Avalon-MM Master Avalon Conduit
S Avalon-MM Slave TCM Avalon-TC Master
Src Avalon-ST Source TCS Avalon-TC Slave TCM
Snk Avalon-ST Sink CSrc Avalon Clock Source Tristate Conduit
Pin Sharer
CSnk Avalon Clock Sink TCS TCS

IRQ4
IRQ3 Nios II TCM TCM Cn
IRQ1 UART
IRQ2 Timer Tristate Cntrl Tristate Cntrl DDR3
SSRAM Flash Controller
C1 M C1 S C1 S C1 S C1 S C2 S

Avalon-MM

S M
S
Scatter Gather IRQ4
DMA
Cn Src
Avalon-ST Avalon-ST Snk
Conduit
Ethernet FIFO Buffer S M
Controller C2
Avalon-ST Avalon-ST IRQ3
Snk Src
C2 FIFO Buffer Scatter Gather
C2 DMA

CSrc
CSnk PLL C1
Ref Clk CSrc
C2

In this figure, the Nios® II processor accesses the control and status registers of on-chip components using
an Avalon-MM interface. The scatter gather DMAs send and receive data using Avalon-ST interfaces.
Four components include interrupt interfaces serviced by software running on the Nios II processor. A
PLL accepts a clock via an Avalon Clock Sink interface and provides two clock sources. Two components

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include Avalon-TC interfaces to access off-chip memories. Finally, the DDR3 controller accesses external
DDR3 memory using an Avalon Conduit interface.
Figure 1-2: Avalon Interfaces in a System Design with PCI Express Endpoint and External Processor

Printed Circuit Board

PCI Express External
Root Port CPU

Altera FPGA
IRQ1 IRQ2 IRQ3 IRQ5
IRQ4 External Bus
Ethernet Custom PCI Express IRQ3
MAC Logic Endpoint Protocol
IRQ2 Bridge
IRQ1
C1 M C1 M C1 M M
C1

Avalon-MM

S S S S IRQ4 S IRQ5
Tristate Cntrl Tristate Cntrl SDRAM Custom
SSRAM Flash Controller UART Logic
TCS TCS Cn
C1 C2 C2

TCM TCM
Tristate Conduit
Pin Sharer
TCS

TCM CSrc
CSnk PLL C1
Tristate Conduit
Ref Clk CSrc
Bridge C2
Cn

Cn Cn Cn

SSRAM Flash SDRAM

In the previous figure, an external processor accesses the control and status registers of on-chip
components via an external bus bridge with an Avalon-MM interface. The PCI Express Root Port controls
devices on the printed circuit board and the other components of the FPGA by driving an on-chip PCI
Express Endpoint with an Avalon-MM master interface. An external processor handles interrupts from
five components. A PLL accepts a reference clock via a Avalon Clock sink interface and provides two
clock sources. The flash and SRAM memories use an Avalon-TC interface to share FPGA pins. Finally, an
SDRAM controller accesses an external SDRAM memory using an Avalon Conduit interface.

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1-4 1.1 Avalon Properties and Parameters 2015.03.04

1.1 Avalon Properties and Parameters

Avalon interfaces use properties to describe their behavior. For example, the maxChannel property of
Avalon-ST interfaces allows you to specify the number of channels supported by the interface. The
clockRate property of the Avalon Clock interface provides the frequency of a clock signal. The
specification for each interface type defines all of its properties and specifies the default values.

1.2 Signal Roles

Each of the Avalon interfaces defines a number of signal roles and their behavior. Many signal roles are
optional. You have the flexibility to select only the signal roles necessary to implement the required
functionality. For example, the Avalon-MM interface includes optional beginbursttransfer and
burstcount signal roles for use in components that support bursting. The Avalon-ST interface includes
the optional startofpacket and endofpacket signal roles for interfaces that support packets.
With the exception of Avalon Conduit interfaces, each interface may include only one signal of each
signal role. Active-low signals are permitted for many signal roles. Active-high signals are generally used
in this document.

1.3 Interface Timing

Subsequent chapters of this document include timing information that describes transfers for individual
interface types. There is no guaranteed performance for any of these interfaces. Actual performance
depends on many factors, including component design and system implementation.
Most Avalon interfaces must not be edge sensitive to signals other than the clock and reset. Other signals
may transition multiple times before they stabilize. The exact timing of signals between clock edges varies
depending upon the characteristics of the selected Altera device. This specification does not specify
electrical characteristics. Refer to the appropriate device documentation for electrical specifications.

1.4 Related Documents

For more information on related topics in the following documents and design examples, refer to the
following documents:

Related Information
• Creating a System with Qsys.
For an overview of the Qsys system integration tool
• Creating Qsys Components
For information about creating Qsys components, composed components, and dynamic file
generation
• Optimizing Qsys System Performance.
For information about system design, including: hierarchy, concurrency, pipelining, throughput,
reducing logic utilization and power consumption

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• Component Interface Tcl Reference

For information about defining Qsys components and a reference for component Tool Command
Language (Tcl)
• Qsys System Design Components
For information about system design components available in the IP Catalog
• Qsys Tutorial Design Example
For tutorial that shows how to build a memory test system using components with Avalon interfaces

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Avalon Clock and Reset Interfaces
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Avalon Clock interfaces define the clock or clocks used by a component. Components can have clock
inputs, clock outputs, or both. A phase locked loop (PLL) is an example of a component that has both a
clock input and clock outputs.
The following figure is a simplified illustration showing the most important inputs and outputs of a PLL
component.
Figure 2-1: PLL Core Clock Outputs and Inputs

PLL Core
altpll Megafunction

reset Reset Clock Clock Output

Sink Source Interface1

Clock Clock Output

Source Interface2

ref_clk Clock Clock Clock Output

Sink Source Interface_n

2.1 Avalon Clock Sink Signal Roles

A clock sink provides a timing reference for other interfaces and internal logic.

Table 2-1: Clock Sink Signal Roles

Signal Role Width Direction Required Description

clk 1 Input Yes A clock signal. Provides synchronization for
internal logic and for other interfaces.

© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance ISO
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any 9001:2008
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, Registered
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.

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2-2 2.2 Clock Sink Properties 2015.03.04

2.2 Clock Sink Properties

Table 2-2: Clock Sink Properties

Name Default Value Legal Values Description

clockRate 0 0–232–1 Indicates the frequency in Hz of the clock sink interface.
If 0, the clock rate allows any frequency. If non-zero,
Qsys issues a warning if the connected clock source is
not the specified frequency.

2.3 Associated Clock Interfaces

All synchronous interfaces have an associatedClock property that specifies which clock source on the
component is used as a synchronization reference for the interface. This property is illustrated in the
following figure.
Figure 2-2: associatedClock Property

rx_clk Clock Clock tx_clk

Sink Sink
Dual Clock FIFO

rx_data ST associatedClock = "rx_clk" associatedClock = "tx_clk" ST tx_data

Sink Source

2.4 Avalon Clock Source Signal Roles

An Avalon Clock source interface drives a clock signal out of a component.

Table 2-3: Clock Source Signal Roles

Signal Role Width Direction Required Description

clk 1 Output Yes An output clock signal.

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2.5 Clock Source Properties

Table 2-4: Clock Source Properties

Name Default Legal Description

Value Values
associatedDirectClock N/A an input The name of the clock input that directly drives
clock name this clock output, if any.
clockRate 0 0–232–1 Indicates the frequency in Hz at which the
clock output is driven.
clockRateKnown false true, false Indicates whether or not the clock frequency is
known. If the clock frequency is known, this
information can be used to customize other
components in the system.

2.6 Reset Sink

Table 2-5: Reset Input Signal Roles

The reset_req signal is an optional signal that you can use to prevent memory content corruption by performing
reset handshake prior to an asynchronous reset assertion..
Signal Role Width Direction Required Description
reset, 1 Input Yes Resets the internal logic of an interface or
reset_n component to a user-defined state. The
synchronous properties of the reset are defined
by the synchronousEdges parameter.
reset_req 1 input No Early indication of reset signal. When asserted
the component is expected to prepare itself to
be reset.

2.7 Reset Sink Interface Properties

Table 2-6: Reset Input Signal Roles

Name Default Legal Description

Value Values
associatedClock N/A a clock The name of a clock to which this interface is
name synchronized. Required if the value of
synchronousEdges is DEASSERT or BOTH.

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Name Default Legal Description

Value Values
synchronous-Edges DEASSERT NONE Indicates the type of synchronization the reset
DEASSERT input requires. The following values are
BOTH defined:
• NONE–no synchronization is required
because the component includes logic for
internal synchronization of the reset signal.
• DEASSERT–the reset assertion is asynchro‐
nous and deassertion is synchronous.
BOTH–reset assertion and deassertion are
synchronous.

2.8 Associated Reset Interfaces

All synchronous interfaces have an associatedReset property that specifies which reset signal resets the
interface logic.

2.9 Reset Source

Table 2-7: Reset Output Signal Roles

The reset_req signal is an optional signal that you can use to prevent memory content corruption by performing
reset handshake prior to an asynchronous reset assertion.
Signal Role Width Direction Required Description
reset 1 Output Yes Resets the internal logic of an interface or
reset_n component to a user-defined state.
reset_req 1 Output Optional Enables reset request generation, which is an
early signal that is asserted before reset
assertion. Once asserted, this cannot be
deasserted until the reset is completed.

2.10 Reset Source Interface Properties

Table 2-8: Reset Interface Properties

Name Default Legal Description

Value Values
associatedClock N/A a clock The name of a clock to which this interface
name synchronized. Required if the value of
synchronousEdges is DEASSERT or BOTH.

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Name Default Legal Description

Value Values
associatedDirectReset N/A a reset The name of the reset input that directly drives
name this reset source through a one-to-one link.
associatedResetSinks N/A a reset Specifies reset inputs which will eventually
name cause a reset source to assert reset. For example,
a reset synchronizer ORs a number of reset
inputs to generate a reset output.
synchronousEdges DEASSERT NONE Indicates the reset output's synchronization.
The following values are defined:
DEASSERT
• NONE–The reset interface is asynchronous.
BOTH • DEASSERT–the reset assertion is asynchro‐
nous and deassertion is synchronous.
• BOTH–reset assertion and deassertion are
synchronous.

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Avalon Memory-Mapped Interfaces
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3.1 Introduction to Avalon Memory-Mapped Interfaces

You can use Avalon Memory-Mapped (Avalon-MM) interfaces to implement read and write interfaces
for master and slave components. The following are examples of component that typically include
memory-mapped interfaces:
• Microprocessors
• Memories
• UARTs
• DMAs
• Timers
Avalon-MM interfaces range from simple to complex. For example, SRAM interfaces that have fixed-cycle
read and write transfers have simple Avalon-MM interfaces. Pipelined interfaces capable of burst transfers
are complex.

© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance ISO
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any 9001:2008
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, Registered
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.

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Figure 3-1: Focus on Avalon-MM Slave Transfers

The following figure shows a typical system, highlighting the Avalon-MM slave interface connection to
the interconnect fabric.

Ethernet
PHY

Avalon-MM System
Processor Ethernet MAC Custom Logic
Avalon-MM Avalon-MM Avalon-MM
Master Master Master

Interconnect

Avalon-MM Avalon-MM Avalon-MM Avalon-MM Avalon-MM

Avalon
Slave Slave Slave Slave Slave
Slave Port
Flash SRAM RAM UART Custom
Controller Controller Controller Logic

Tristate Conduit Slave

Tristate Conduit Pin Sharer &
Tristate Conduit Bridge
Tristate Conduit Master

Tristate Tristate RS-232

Conduit Conduit RAM
Slave Slave Memory

Flash SRAM
Memory Memory

Avalon-MM components typically include only the signals required for the component logic.

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Figure 3-2: Example Slave Component

The 16-bit general-purpose I/O peripheral shown in the following figure only responds to write requests.
This component includes only the slave signals required for write transfers.

Avalon-MM Peripheral
Application-
writedata[15..0] pio_out[15..0]
D Q Specific
Interface
Avalon-MM
Interface
(Avalon-MM write CLK_EN
Slave Interface)
clk

Each signal in an Avalon-MM slave corresponds to exactly one Avalon-MM signal role. An Avalon-MM
interface can use only one instance of each signal role.

3.2 Avalon Memory-Mapped Interface Signal Roles

The following table lists the signal roles that constitute the Avalon-MM interface. The signal roles allow
you to create masters that use bursts for reads and writes. When necessary, the interconnect enables the
connection between the master and slave pair. When the master and slave interfaces match, a direct
connection is possible.
This specification does not require all signals to exist in an Avalon-MM interface. In fact, there is no one
signal that is always required. The minimum requirements are readdata for a read-only interface or
writedata and write for a write-only interface.

Table 3-1: Avalon-MM Signal Roles

All Avalon signals can be active high. Avalon signals that can be defined as active low. When active low, the signal
role ends with _n in the Signal role column.
Signal Role Width Direction Description
Fundamental Signals
address 1 - 64 Master → Slave Masters: By default, the address signal
represents a byte address. The value of the
address must be aligned to the data width. To
write to specific bytes within a data word, the
master must use the byteenable signal. Refer
to the addressUnits interface property for
word addressing.
Slaves: By default, the interconnect translates
the byte address into a word address in the
slave’s address space. Each slave access is for a
word of data from the perspective of the slave.

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Signal Role Width Direction Description

For example, address = 0= 0 selects the first

word of the slave. address = 1 selects the
second word of the slave. Refer to the
addressUnits interface property for byte
addressing.

byteenable 2, 4, 8, 16, 32, Master → Slave Enables specific byte lane(s) during transfers on
64, 128 interfaces of width greater than 8 bits. Each bit
byteenable_n
in byteenable corresponds to a byte in
writedata and readdata. The master bit <n>
of byteenable indicates whether byte <n> is
being written to. During writes, byteenables
specify which bytes are being written to. Other
bytes should be ignored by the slave. During
reads, byteenables indicate which bytes the
master is reading. Slaves that simply return
readdata with no side effects are free to ignore
byteenables during reads. If an interface does
not have a byteenable signal, the transfer
proceeds as if all byteenables are asserted.
When more than one bit of the byteenable
signal is asserted, all asserted lanes are adjacent.
The number of adjacent lines must be a power
of 2. The specified bytes must be aligned on an
address boundary for the size of the data. For
example, the following values are legal for a 32-
bit slave:
• 1111 writes full 32 bits
• 0011 writes lower 2 bytes
• 1100 writes upper 2 bytes
• 0001 writes byte 0 only
• 0010 writes byte 1 only
• 0100 writes byte 2 only
• 1000 writes byte 3 only
To avoid unintended side effects, Altera
strongly recommends that you use the
byteenable signal in systems with different
word sizes.

debugaccess 1 Master → Slave When asserted, allows the Nios II processor to

write on-chip memories configured as ROMs.
read 1 Master → Slave Asserted to indicate a read transfer. If present,
readdata is required.
read_n

readdata 8,16, 32, 64, Slave → Master The readdata driven from the slave to the
128, 256, 512, master in response to a read transfer.
1024

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Signal Role Width Direction Description

response 2 Slave → Master The response signal indicates the status of a

read transaction. Asserted simultaneously with
readdata. The following encodings are
defined:
• 00: OKAY—Successful response for a
transaction.
• 01: RESERVED—Encoding is reserved.
• 10: SLAVEERROR—Error from an endpoint
slave. Indicates an unsuccessful transaction.
• 11: DECODEERROR—Indicates attempted
access to an undefined location.
Every readdata item in a burst receives a read
response. A read burst of length <n> results in
<n> responses. Although <n> are required, the
response values may be different for each
readdata item in a burst.

To support read responses, the interface must

be read capable.
When a read response returns an error, the
slave determines the readdata value, and the
master ignores the readdata value.
All read transactions must return a response if
the component supports read responses.

write 1 Master → Slave Asserted to indicate a write transfer. If present,

writedata is required.
write_n

writedata 8,16, 32, 64, Master → Slave Data for write transfers. The width must be the
128, 256, 512, same as the width of readdata if both are
1024 present.
Wait-State Signals
lock 1 Master → Slave lock ensures that once a master wins arbitra‐
tion, it maintains access to the slave for
multiple transactions. It is asserted coincident
with the first read or write of a locked
sequence of transactions. It is deasserted on the
final transaction of a locked sequence of
transactions. lock assertion does not guarantee
that arbitration will be won. After the lock-
asserting master has been granted, it retains
grant until it is deasserted.
A master equipped with lock cannot be a burst
master. Arbitration priority values for lock-
equipped masters are ignored.

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Signal Role Width Direction Description

lock is particularly useful for read-modify-

write (RMW) operations. The typical read-
modify-write operation includes the following
steps:
1. Master A asserts lock and reads 32-bit data
that has multiple bit fields.
2. Master A deasserts lock, changes one bit
field, and writes the 32-bit data back.
lock prevents master B from performing a
write between Master A’s read and write.

waitrequest 1 Slave → Master Asserted by the slave when it is unable to

respond to a read or write request. Forces the
waitrequest_n
master to wait until the interconnect is ready to
proceed with the transfer. At the start of all
transfers, a master initiates the transfer and
waits until waitrequest is deasserted. A master
must make no assumption about the assertion
state of waitrequest when the master is idle:
waitrequest may be high or low, depending
on system properties.
When waitrequest is asserted, master control
signals to the slave are to remain constant with
the exception of beginbursttransfer. For a
timing diagram illustrating the beginburst-
transfer signal, refer to the figure in Read
Bursts.
An Avalon-MM slave may assert waitrequest
during idle cycles. An Avalon-MM master may
initiate a transaction when waitrequest is
asserted and wait for that signal to be
deasserted. To avoid system lockup, a slave
device should assert waitrequest when in
reset.

Pipeline Signals

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Signal Role Width Direction Description

readdatavalid 1 Slave → Master Used for variable-latency, pipelined read
transfers. When asserted, indicates that the
readdatavalid_n
readdata signal contains valid data. A slave
with readdatavalid must assert this signal for
one cycle for each read access received. There
must be at least one cycle of latency between
acceptance of the read and assertion of
readdatavalid. For a timing diagram
illustrating the readdatavalid signal, refer to
Pipelined Read Transfer with Variable Latency.
A slave may assert readdatavalid to transfer
data to the master independently of whether or
not the slave is stalling a new command with
waitrequest.

Required if the master supports pipelined reads.

Bursting masters with read functionality must
include the readdatavalid signal.

Burst Signals
burstcount 1 – 11 Master → Slave Used by bursting masters to indicate the
number of transfers in each burst. The value of
the maximum burstcount parameter must be a
power of 2. A burstcount interface of width <n>
can encode a max burst of size 2(<n>-1). For
example, a 4-bit burstcount signal can support
a maximum burst count of 8. The minimum
burstcount is 1. The constantBurstBehavior
property controls the timing of the burstcount
signal. Bursting masters with read functionality
must include the readdatavalid signal.
For bursting masters and slaves using byte
addresses, the following restriction applies to
the width of the address:
<address_w> >= <burstcount_w>
+log2(<symbols_per_word_of_interface>).

For bursting masters and slaves using word

addresses, the log2 term above is omitted.

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Signal Role Width Direction Description

beginburst- 1 Interconnect → Asserted for the first cycle of a burst to indicate
transfer Slave when a burst transfer is starting. This signal is
deasserted after one cycle regardless of the
value of waitrequest. For a timing diagram
illustrating beginbursttransfer, refer to the
figure in Read Bursts.
beginbursttransfer is optional. A slave can
always internally calculate the start of the next
write burst transaction by counting data
transfers.
Altera recommends that you do not use this
signal. This signal exists to support legacy
memory controllers.

Related Information
• Typical Read and Write Transfers on page 3-12
• Read Bursts on page 3-18
• Pipelined Read Transfer with Variable Latency on page 3-14

3.3 Interface Properties

Table 3-2: Avalon-MM Interface Properties

Name Default Legal Description

Value Values
addressUnits Master - words, Specifies the unit for addresses. A symbol is
symbols symbols typically a byte.
Slave - Refer to the definition of address in the Avalon
words Memory-Mapped Interface Sginal Types table
for the typical use of of this property.

burstCountUnits words words, This property specifies the units for the
symbols burstcount signal. For symbols, the burstcount
value is interpreted as the number of symbols
(bytes) in the burst. For words, the burstcount
value is interpreted as the number of word
transfers in the burst.
burstOnBurstBoundarie- false true, false If true, burst transfers presented to this
sOnly interface begin at addresses which are multiples
of the burst size in bytes.

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Name Default Legal Description

Value Values
constantBurstBehavior Master - true, false Masters: When true, declares that the master
false holds address and burstcount constant
throughout a burst transaction. When false
Slave - (default), declares that the master holds address
false and burstcount constant only for the first beat
of a burst.
Slaves: When true, declares that the slave
expects address and burstcount to be held
constant throughout a burst. When false
(default), declares that the slave samples
address and burstcount only on the first beat of
a burst.

holdTime(1) 0 0 – 1000 Specifies time in timingUnits between the

cycles deassertion of write and the deassertion of
address and data. (Only applies to write
transactions.)
linewrapBursts false true, false Some memory devices implement a wrapping
burst instead of an incrementing burst. When a
wrapping burst reaches a burst boundary, the
address wraps back to the previous burst
boundary. Only the low-order bits are required
for address counting. For example, a wrapping
burst to address 0xC with burst boundaries
every 32 bytes across a 32-bit interface writes to
the following addresses:
• 0xC
• 0x10
• 0x14
• 0x18
• 0x1C
• 0x0
• 0x4
• 0x8

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Name Default Legal Description

Value Values
maximumPendingReadTran- 1(2) 1 – 64 Slaves: This parameter is the maximum number
sactions (1) of pending reads that the slave can queue. For a
timing diagram that illustrates this property,
refer to Figure 3-5. Do not set this parameter to
0. (For backwards compatibility, the software
supports a parameter setting of 0. However,
you should not use this setting in new designs).
Refer to Pipelined Read Transfer with
Variable Latency on page 3-14 for additional
information about using waitrequest and
readdatavalid with multiple outstanding
reads.
Masters: This property is the maximum
number of outstanding read transactions that
the master can generate. Do not set this
parameter to 0. (For backwards compatibility,
the software supports a parameter setting of 0.
However, you should not use this setting in
new designs).

readLatency(1) 0 0 – 63 Read latency for fixed-latency Avalon-MM

slaves. Not used on interfaces that include the
readdatavalid signal. For a timing diagram
that uses a fixed latency read, refer to Figure
3-6.
readWaitTime(1) 1 0 – 1000 For interfaces that don’t use the waitrequest
cycles signal. readWaitTime indicates the timing in
timingUnits before the slave accepts a read
command. The timing is as if the slave asserted
waitrequest for readWaitTime cycles.

setupTime(1) 0 0 – 1000 Specifies time in timingUnits between the

cycles assertion of address and data and assertion of
read or write.

timingUnits(1) cycles cycles, Specifies the units for setupTime, holdTime,

nanosecon writeWaitTime and readWaitTime. Use cycles
ds for synchronous devices and nanoseconds for
asynchronous devices. Almost all Avalon-MM
slave devices are synchronous.
An Avalon-MM component that bridges from
an Avalon-MM slave interface to an off-chip
device may be asynchronous. That off-chip
device might have a fixed settling time for bus
turnaround.

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Name Default Legal Description

Value Values
writeWaitTime(1) 0 0 – 1000 For interfaces that do not use the waitrequest
Cycles signal, writeWaitTime specifies the timing in
timingUnits before a slave accepts a write. The
timing is as if the slave asserted waitrequest
for writeWaitTime cycles or nanoseconds.
For a timing diagram that illustrates the use of
writeWaitTime, refer to Figure 3-4.

Interface Relationship Properties

associatedClock N/A N/A Name of the clock interface to which this
Avalon-MM interface is synchronous.
associatedReset N/A N/A Name of the reset interface which resets the
logic on this Avalon-MM interface.
bridgesToMaster 0 Avalon- An Avalon-MM bridge consists of a slave and a
MM master, and has the property that an access to
Master the slave requesting a particular byte or bytes
name on will cause the same byte or bytes to be
the same requested by the master. The Avalon-MM
component Pipeline Bridge in the Qsys component library
implements this functionality.
Notes:
1. Although this property characterizes a slave device, masters can declare this property to enable direct
connections between matching master and slave interfaces.
2. If a slave interface accepts more read transfers than allowed, the interconnect's pending read FIFO may
overflow with unpredictable results. The slave may lose readdata or route readdata to the wrong
master interface. Or, the system may lock up. The slave interface must assert waitrequest to prevent
this overflow.

Related Information
Avalon Memory-Mapped Interface Signal Roles on page 3-3

3.4 Timing
The Avalon-MM interface is synchronous. Each Avalon-MM interface is synchronized to an associated
clock interface. Signals may be combinational if they are driven from the outputs of registers that are
synchronous to the clock signal. This specification does not dictate how or when signals transition
between clock edges. Timing diagrams are devoid of fine-grained timing information.

3.5 Transfers
This section defines two basic concepts before introducing the transfer types:

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• Transfer—A transfer is a read or write operation of a word or one or more symbol of data. Transfers
occur between an Avalon-MM interface and the interconnect. Transfers take one or more clock cycles
to complete.
Both masters and slaves are part of a transfer. The Avalon-MM master initiates the transfer and the
Avalon-MM slave responds to it.
• Master-slave pair—This term refers to the master interface and slave interface involved in a transfer.
During a transfer, the master interface control and data signals pass through the interconnect fabric
and interact with the slave interface.

3.5.1 Typical Read and Write Transfers

This section describes a typical Avalon-MM interface that supports read and write transfers with slave-
controlled waitrequest. The slave can stall the interconnect for as many cycles as required by asserting
the waitrequest signal. If a slave uses waitrequest for either read or write transfers, it must use
waitrequest for both.

A slave typically receives address, byteenable, read or write, and writedata after the rising edge of the
clock. A slave asserts waitrequest before the rising clock edge to hold off transfers. When the slave
asserts waitrequest, the transfer is delayed. While waitrequest is asserted, the address and other
control signals are held constant. Transfers complete on the rising edge of the first clk after the slave
interface deasserts waitrequest.
There is no limit on how long a slave interface can stall. Therefore, you must ensure that a slave interface
does not assert waitrequest indefinitely. The following figure shows read and write transfers using
waitrequest. In this example, the master and slave both have a readdatavalid signal.

Note: waitrequest can be decoupled from the read and write request signals. waitrequest may be
asserted during idle cycles. An Avalon-MM master may initiate a transaction when waitrequest is
asserted and wait for that signal to be deasserted. Decoupling waitrequest from read and write
requests may improve system timing. Decoupling eliminates a combinational loop including the
read, write, and waitrequest signals.
Figure 3-3: Read and Write Transfers with Waitrequest

1 2 3 45 6 7
clk
address address
byteenable byteenable

read
write
waitrequest
readdatavalid
readdata readdata
response response
writedata writedata

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The numbers in this timing diagram, mark the following transitions:

1. address, byteenable, and read are asserted after the rising edge of clk. The slave asserts
waitrequest, stalling the transfer.
2. waitrequest is sampled. Because waitrequest is asserted, the cycle becomes a wait-state. address,
read, write, and byteenable remain constant.
3. The slave deasserts waitrequest after the rising edge of clk.
4. readdata, response and deasserted waitrequest are sampled, completing the transfer.
5. address, writedata, byteenable, and write signals are asserted after the rising edge of clk. The slave
asserts waitrequest stalling the transfer.
6. The slave deasserts waitrequest after the rising edge of clk.
7. The slave captures write data ending the transfer.

3.5.2 Read and Write Transfers with Fixed Wait-States

A slave can specify fixed wait-states using the readWaitTime and writeWaitTime properties. Using fixed
wait-states is an alternative to using waitrequest to stall a transfer. The address and control signals
(byteenable, read, and write) are held constant for the duration of the transfer. Setting readWaitTime
or writeWaitTime to <n> is equivalent to asserting waitrequest for <n> cycles per transfer.
In the following figure, the slave has a writeWaitTime = 2 and readWaitTime = 1.
Figure 3-4: Read and Write Transfer with Fixed Wait-States at the Slave Interface

1 2 3 4 5
clk
address address address
byteenable byteenable
read
write
readdata readdata
response response
writedata writedata

The numbers in this timing diagram mark the following transitions:

1. The master asserts address and read on the rising edge of clk.
2. The next rising edge of clk marks the end of the first and only wait-state cycle. The readWaitTime is 1.
3. The slave asserts readdata and response on the rising edge of clk. The read transfer ends.
4. writedata, address, byteenable, and write signals are available to the slave.
5. The write transfer ends after 2 wait-state cycles.
Transfers with a single wait-state are commonly used for multicycle off-chip peripherals. The peripheral
captures address and control signals on the rising edge of clk. The peripheral has one full cycle to return
data.
Components with zero wait-states are allowed. However, components with zero wait-states may decrease
the achievable frequency. Zero wait-states requires the component to generate the response in the same
cycle that the request was presented.

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3.5.3 Pipelined Transfers

Avalon-MM pipelined read transfers increase the throughput for synchronous slave devices that require
several cycles to return data for the first access. Such devices can can typically return one data value per
cycle for some time thereafter. New pipelined read transfers can start before readdata for the previous
transfers is returned. Write transfers cannot be pipelined.
A pipelined read transfer has an address phase and a data phase. A master initiates a transfer by
presenting the address during the address phase. A slave fulfills the transfer by delivering the data during
the data phase. The address phase for a new transfer (or multiple transfers) can begin before the data
phase of a previous transfer completes. The delay is called pipeline latency. The pipeline latency is the
duration from the end of the address phase to the beginning of the data phase.
Transfer timing for wait-states and pipeline latency have the following key differences:
• Wait-states—Wait-states determine the length of the address phase. Wait-states limit the maximum
throughput of a . If a slave requires one wait-state to respond to a transfer request, the requires two
clock cycles per transfer.
• Pipeline Latency—Pipeline latency determines the time until data is returned independently of the
address phase. A pipelined slave with no wait-states can sustain one transfer per cycle. However, it may
require several cycles of latency to return the first unit of data.
Wait-states and pipelined reads can be supported concurrently. Pipeline latency can be either fixed or
variable.

3.5.3.1 Pipelined Read Transfer with Variable Latency

After capturing address and control signals, an Avalon-MM pipelined slave takes one or more cycles to
produce data. A pipelined slave may have multiple pending read transfers at any given time. Variable-
latency pipelined read transfers require one additional signal, readdatavalid. readdatavalid indicates
when read data is valid. Variable-latency pipelined read transfers also include the same set of signals as
non-pipelined read transfers. Slave peripherals that use readdatavalid are considered pipelined with
variable latency. The readdata and readdatavalid signals corresponding to a particular read command
can be asserted the cycle after that read command is asserted, at the earliest.
The slave must return readdata in the same order that it accepted the read commands. Pipelined slave
ports with variable latency must use waitrequest. The slave can assert waitrequest to stall transfers to
maintain an acceptable number of pending transfers. A slave may assert readdatavalid to transfer data
to the master independently of whether or not the slave is stalling a new command with waitrequest.
Note: The maximum number of pending transfers is a property of the slave interface. The interconnect
fabric builds logic to route readdata to requesting masters using this number. The slave interface,
not the interconnect fabric, must track the number of pending reads. The slave must assert
waitrequest to prevent the number of pending reads from exceeding the maximum number.

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Figure 3-5: Pipelined Read Transfers with Variable Latency

The following figure shows several slave read transfers. The slave is pipelined with variable latency. In this
figure, the slave can accept a maximum of two pending transfers. The slave uses waitrequest to avoid
overrunning this maximum.

1 2 3 4 5 6 7 8 9 10 11

clk

address addr1 addr2 addr3 addr4 addr5

read

waitrequest

readdata data 1 data2 data 3 data4 data5

readdatavalid

The numbers in this timing diagram, mark the following transitions:

1. The master asserts address and read, initiating a read transfer.
2. The slave captures addr1.
3. The slave captures addr2.
4. The slave asserts waitrequest because it has accepted a maximum of two pending reads, causing the
third transfer to stall.
5. The slave asserts data1, the response to addr1. It deasserts waitrequest.
6. The slave captures addr3.
7. The slave captures addr4. The interconnect captures data2.
8. The slave drives readdatavalid and readdata in response to the third read transfer.
9. The slave captures addr5. The interconnect captures data3.
10.The interconnect captures data4.
11.The slave drives data5 and asserts readdatavalid completing the data phase for the final pending
read transfer.
If the slave cannot handle a write transfer while it is processing pending read transfers, the slave must
assert its waitrequest and stall the write operation until the pending read transfers have completed. The
Avalon-MM specification does not define the value of readdata in the event that a slave accepts a write
transfer to the same address as a currently pending read transfer.

3.5.3.2 Pipelined Read Transfers with Fixed Latency

The address phase for fixed latency read transfers is identical to the variable latency case. After the address
phase, a pipelined slave with fixed read latency takes a fixed number of clock cycles to return valid
readdata. The readWaitTime property specifies the number of clock cycles to return valid readdata.
The interconnect captures readdata on the appropriate rising clock edge, ending the data phase.
During the address phase, the slave can assert waitrequest to hold off the transfer. Or, the slave specifies
the readWaitTime for a fixed number of wait states. The address phase ends on the next rising edge of clk
after wait states, if any.
During the data phase, the slave drives readdata after a fixed latency. For a read latency of <n>, the slave
must present valid readdata on the <nth> rising edge of clk after the end of the address phase.

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Figure 3-6: Pipelined Read Transfer with Fixed Latency of Two Cycles
The following figure shows multiple data transfers between a master and a pipelined slave . The slave
drives waitrequest to stall transfers. and has a fixed read latency of 2 cycles.
1 2 3 4 5 6
clk

address addr1 addr2 addr3

read

waitrequest

readdatavalid

readdata data1 data2 data3

The numbers in this timing diagram, mark the following transitions:

1. A master initiates a read transfer by asserting read and addr1.
2. The slave asserts waitrequest to hold off the transfer for one cycle.
3. The slave captures addr1 at the rising edge of clk. The address phase ends here.
4. The slave presents valid readdata after 2 cycles, ending the transfer.
5. addr2 and read are asserted for a new read transfer.
6. The master initiates a third read transfer during the next cycle, before the data from the prior transfer
is returned.

3.5.4 Burst Transfers

A burst executes multiple transfers as a unit, rather than treating every word independently. Bursts may
increase throughput for slave ports that achieve greater efficiency when handling multiple words at a time,
such as SDRAM. The net effect of bursting is to lock the arbitration for the duration of the burst. A
bursting Avalon-MM interface that supports both reads and writes must support both read and write
bursts.
Bursting Avalon-MM interfaces include a burstcount output signal. If a slave has a burstcount input, it
is considered burst capable.
The burstcount signal behaves as follows:
• At the start of a burst, burstcount presents the number of sequential transfers in the burst.
• For width <n> of burstcount, the maximum burst length is 2(<n>-1).The minimum legal burst length
is one.
To support slave read bursts, a slave must also support:
• Wait states with the waitrequest signal.
• Pipelined transfers with variable latency with the readdatavalid signal.
At the start of a burst, the slave sees the address and a burst length value on burstcount. For a burst with
an address of <a> and a burstcount value of <b>, the slave must perform <b> consecutive transfers
starting at address <a>. The burst completes after the slave receives (write) or returns (read) the <bth>
word of data. The bursting slave must capture address and burstcount only once for each burst. The
slave logic must infer the address for all but the first transfers in the burst. A slave can also use the input
signal beginbursttransfer, which the interconnect asserts on the first cycle of each burst.

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3.5.4.1 Write Bursts

These rules apply when a write burst begins with burstcount greater than one:
• When a burstcount of <n> is presented at the beginning of the burst, the slave must accept <n>
successive units of writedata to complete the burst. Arbitration between the master-slave pair is
locked until the burst completes. This lock guarantees that no other master can execute transactions on
the slave until the write burst is completes.
• The slave must only capture writedata when write is asserted. During the burst, the master can
deassert write indicating that writedata is invalid. Deasserting write does not terminate the burst.
It delays it. When a burst is delayed, no other masters can access the slave, reducing the transfer
efficiency.
• The constantBurstBehavior property specifies the behavior of the burst signals. When constant-
BurstBehavior is true for a master, it indicates that the master holds address and burstcount stable
throughout a burst. When constantBurstBehavior is false, it indicates that the master holds address
and burstcount stable only for the first transaction of a burst. When true for a slave, constantBurst-
Behavior declares that the slave expects address and burstcount to be held stable throughout a
burst. When constantBurstBehavior is false, it indicates that the slave samples address and
burstcount only on the first transaction of a burst.
• The slave can delay a transfer by asserting waitrequest forcing writedata, write, burstcound, and
byteenable to be held constant.
• The functionality of the byteenable signal is the same for bursting and non-bursting slaves. For a 32-
bit master burst-writing to a 64-bit slave, starting at byte address 4, the first write transfer seen by the
slave is at its address 0, with byteenable = 8'b11110000. The byteenables can change for different
words of the burst.
• The byteenable signals do not all have to be asserted. A burst master writing partial words can use the
byteenable signal to identify the data being written.

Figure 3-7: Write Burst with constantBurstBehavior Set to False for Master and Slave
The following figure demonstrates a slave write burst of length 4. In this example, the slave asserts
waitrequest twice delaying the burst.

1 2 3 4 5 6 7 8
clk
address addr1
beginbursttransfer
burstcount 4
write
writedata data1 data2 data3 data4
waitrequest

The numbers in this timing diagram, mark the following transitions:

1. The master asserts address, burstcount, write, and drives the first unit of writedata.
2. The slave immediately asserts waitrequest, indicating that it is not ready to proceed with the transfer.
3. waitrequest is low. The slave captures addr1, burstcount, and the first unit of writedata . On
subsequent cycles of the transfer, address and burstcount are ignored.
4. The slave captures the second unit of data at the rising edge of clk.
5. The burst is paused while write is deasserted.

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6. The slave captures the third unit of data at the rising edge of clk.
7. The slave asserts waitrequest. In response, all outputs are held constant through another clock cycle.
8. The slave captures the last unit of data on this rising edge of clk. The slave write burst ends.
In the figure above, the beginbursttransfer signal is asserted for the first clock cycle of a burst and is
deasserted on the next clock cycle. Even if the slave asserts waitrequest, the beginbursttransfer signal
is only asserted for the first clock cycle.
For information about Avalon-MM properties, refer to Table 3-2.
Related Information
Interface Properties on page 3-8

3.5.4.2 Read Bursts

Read bursts are similar to pipelined read transfers with variable latency. A read burst has distinct address
and data phases. readdatavalid indicates when the slave is presenting valid readdata. Unlike pipelined
read transfers, a single read burst address results in multiple data transfers.
These rules apply to read bursts:
• When burstcount is <n>, the slave must return <n> words of readdata to complete the burst.
• The slave presents each word by providing readdata and asserting readdatavalid for a cycle.
Deassertion of readdatavalid delays but does not terminate the burst data phase.
• The byteenables presented with a read burst command apply to all cycles of the burst. A byteenable
value of 1 means that the least significant byte is being read across all of the read cycles.
Note: Altera recommends that burst capable slaves not have read side effects. (This specification does not
guarantee how many bytes will be read from the slave in order to satisfy a request.)
Figure 3-8: Read Burst
The following figure illustrates a system with two bursting masters accessing a slave. Note that Master B
can drive a read request before the data has returned for Master A.
1 2 3 4 5 6
clk
address A0 (master A) A1 (master B)
read
beginbursttransfer
waitrequest
burstcount 4 2
readdatavalid
readdata D(A0) D(A0+1) D(A0+2) D(A0+3) D(A1) D(A1+1)

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The numbers in this timing diagram, mark the following transitions:

1. Master A asserts address (A0), burstcount, and read after the rising edge of clk. The slave asserts
waitrequest, causing all inputs except beginbursttransfer to be held constant through another
clock cycle.
2. The slave captures A0 and burstcount at this rising edge of clk. A new transfer could start on the next
cycle.
3. Master B drives address (A1), burstcount, and read. The slave asserts waitrequest, causing all
inputs except beginbursttransfer to be held constant. The slave could have returned read data from
the first read request at this time, at the earliest.
4. The slave presents valid readdata and asserts readdatavalid, transferring the first word of data for
master A.
5. The second word for master A is transferred. The slave deasserts readdatavalid pausing the read
burst. The slave port can keep readdatavalid deasserted for an arbitrary number of clock cycles.
6. The first word for master B is returned.

3.5.4.3 Line–Wrapped Bursts

Processors with instruction caches gain efficiency by using line-wrapped bursts. When a processor
requests data that is not in the cache, the cache controller must refill the entire cache line. For a processor
with a cache line size of 64 bytes, a cache miss causes 64 bytes to be read from memory. If the processor
reads from address 0xC when the cache miss occurred, then an inefficient cache controller could issue a
burst at address 0, resulting in data from read addresses 0x0, 0x4, 0x8, 0xC, 0x10, 0x14, 0x18, . . . 0x3C.
The requested data is not available until the fourth read. With line-wrapping bursts, the address order is
0xC, 0x10, 0x14, 0x18, . . . 0x3C, 0x0, 0x4, and 0x8. The requested data is returned first. The entire cache
line is eventually refilled from memory.

3.6 Address Alignment

The interconnect only supports aligned accesses. A master can only issue addresses that are a multiple of
its data width in symbols. A master can write partial words by deasserting some byteenables. For
example, a write of 2 bytes at address 2 would have 4’b1100 for the byteenables.

3.7 Avalon-MM Slave Addressing

Dynamic bus sizing manages data during transfers between master-slave pairs of differing data widths.
Slave data are aligned in contiguous bytes in the master address space.
If the master data width is wider than the slave data width, words in the master address space map to
multiple locations in the slave address space. For example, a 32-bit master read from a 16-bit slave results
in two read transfers on the slave side. The reads are to consecutive addresses.
If the master is narrower than the slave, then the interconnect manages the slave byte lanes. During
master read transfers, the interconnect presents only the appropriate byte lanes of slave data to the
narrower master. During master write transfers, the interconnect automatically asserts the byteenable
signals to write data only to the specified slave byte lanes.
Slaves must have a data width of 8, 16, 32, 64, 128, 256, 512 or 1024 bits. The following table shows how
slave data of various widths is aligned within a 32-bit master performing full-word accesses. In this table,
OFFSET[N] refers to a slave word size offset into the slave address space.

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Table 3-3: Dynamic Bus Sizing Master-to-Slave Address Mapping

32-Bit Master Data

Master Byte
Access When Accessing When Accessing When Accessing
Address (1)
an 8-Bit Slave Interface a 16-Bit Slave Interface a 64-Bit Slave Interface
1 OFFSET[0]7..0 OFFSET[0]15..0 (2) OFFSET[0]31..0

2 OFFSET[1]7..0 OFFSET[1]15..0 —
0x00
3 OFFSET[2]7..0 — —
4 OFFSET[3]7..0 — —
1 OFFSET[4]7..0 OFFSET[2]15..0 OFFSET[0]63..32

2 OFFSET[5]7..0 OFFSET[3]15..0 —
0x04
3 OFFSET[6]7..0 — —
4 OFFSET[7]7..0 — —
1 OFFSET[8]7..0 OFFSET[4]15..0 OFFSET[1]31..0

2 OFFSET[9]7..0 OFFSET[5]15..0 —
0x08
3 OFFSET[10]7..0 — —
4 OFFSET[11]7..0 — —
1 OFFSET[12]7..0 OFFSET[6]15..0 OFFSET[1]63..32

2 OFFSET[13]7..0 OFFSET[7]15..0 —
0x0C
3 OFFSET[14]7..0 — —
4 OFFSET[15]7..0 — —
... ... ...

Notes:
1. Although the master is issuing byte addresses, it is accessing full 32-bit words.
2. For all slave entries, [<n>] is the word offset and the subscript values are the bits in the word.

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Avalon Interrupt Interfaces
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Avalon Interrupt interfaces allow slave components to signal events to master components. For example,
a DMA controller can interrupt a processor when it has completed a DMA transfer.

4.1 Interrupt Sender

An interrupt sender drives a single interrupt signal to an interrupt receiver. The timing of the irq signal
must be synchronous to the rising edge of its associated clock. irq has no relationship to any transfer on
any other interface. irq must be asserted until acknowledged on the associated Avalon-MM slave
interface.
Interrupts are component specific. The receiver typically determines the appropriate response by reading
an interrupt status register from an Avalon-MM slave interface.

4.1.1 Avalon Interrupt Sender Signal Roles

Table 4-1: Interrupt Sender Signal Roles

Signal Role Width Direction Required Description

irq 1 Output Yes Interrupt Request. A slave asserts irq when it
needs service. The interrupt receiver
irq_n
determines the relative priority of the
interrupts.

4.1.2 Interrupt Sender Properties

Table 4-2: Interrupt Sender Properties

Property Name Default Legal Values Description

Value
associatedAddres- N/A Name of Avalon- The name of the Avalon-MM slave interface
sablePoint MM slave on this that provides access to the registers to service
component. the interrupt.

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trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance ISO
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any 9001:2008
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, Registered
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
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4-2 4.2 Interrupt Receiver 2015.03.04

Property Name Default Legal Values Description

Value
associatedClock N/A Name of a clock The name of the clock interface to which this
interface on this interrupt sender is synchronous. The sender
component. and receiver may have different values for this
property.
associatedReset N/A Name of a reset The name of the reset interface to which this
interface on this interrupt sender is synchronous.
component.

4.2 Interrupt Receiver

An interrupt receiver interface receives interrupts from interrupt sender interfaces. Components with
Avalon-MM master interfaces can include an interrupt receiver to detect interrupts asserted by slave
components with interrupt sender interfaces. The interrupt receiver accepts interrupt requests from each
interrupt sender as a separate bit.

4.2.1 Avalon Interrupt Receiver Signal Roles

Table 4-3: Interrupt Receiver Signal Roles

Signal Role Width Direction Required Description

irq 1–32 Input Yes irq is an <n>-bit vector, where each bit
corresponds directly to one IRQ sender with no
inherent assumption of priority.

4.2.2 Interrupt Receiver Properties

Table 4-4: Interrupt Receiver Properties

Property Name Default Legal Description

Value Values
associatedAddressable N/A Name of The name of the Avalon-MM master interface
Point Avalon- used to service interrupts received on this
MM interface.
master
interface
associatedClock N/A Name of an The name of the Avalon Clock interface to
Avalon which this interrupt receiver is synchronous.
Clock The sender and receiver may have different
interface values for this property.

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Property Name Default Legal Description

Value Values
associatedReset N/A Name of an The name of the reset interface to which this
Avalon interrupt receiver is synchronous.
Reset
interface

4.2.3 Interrupt Timing

The Avalon-MM master services the priority 0 interrupt before the priority 1 interrupt.
Figure 4-1: Interrupt Timing
In the following figure, interrupt 0 has higher priority. The interrupt receiver is in the process of handling
int1 when int0 is asserted. The int0 handler is called and completes. Then, the int1 handler resumes.
The diagram shows int0 deasserts at time 1. int1 deasserts at time 2.
1 2
clk
Individual int0
Requests
int1

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Avalon Streaming Interfaces
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You can use Avalon Streaming (Avalon-ST) interfaces for components that drive high bandwidth, low
latency, unidirectional data. Typical applications include multiplexed streams, packets, and DSP data. The
Avalon-ST interface signals can describe traditional streaming interfaces supporting a single stream of
data without knowledge of channels or packet boundaries. The interface can also support more complex
protocols capable of burst and packet transfers with packets interleaved across multiple channels.
Figure 5-1: Avalon-ST Interface - Typical Application of the Avalon-ST Interface

Printed Circuit Board

Altera FPGA
Avalon-ST Interfaces (Data Plane)

Scheduler

Rx IF Core Tx IF Core
Avalon-ST 2 Avalon-ST
ch
Input 1 Output
Source 0-2 Sink Source Sink
0

Avalon-MM Interface (Control Plane)

Avalon-MM Avalon-MM Avalon-MM

Master Interface Master Interface Slave Interface
Processor IO Control SDRAM Cntl

SDRAM
Memory

© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance ISO
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any 9001:2008
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, Registered
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.

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All Avalon-ST source and sink interfaces are not necessarily interoperable. However, if two interfaces
provide compatible functions for the same application space, adapters are available to allow them to
interoperate.
Avalon-ST interfaces support datapaths requiring the following features:
• Low latency, high throughput point-to-point data transfer
• Multiple channel support with flexible packet interleaving
• Sideband signaling of channel, error, and start and end of packet delineation
• Support for data bursting
• Automatic interface adaptation

5.1 Terms and Concepts

The Avalon-ST interface protocol defines the following terms and concepts:
• Avalon Streaming System—An Avalon Streaming system contains one or more Avalon-ST
connections that transfer data from a source interface to a sink interface. The system shown above
consists of Avalon-ST interfaces to transfer data from the system input to output. Avalon-MM control
and status register interfaces provide for software control.
• Avalon Streaming Components—A typical system using Avalon-ST interfaces combines multiple
functional modules, called components. The system designer configures the components and connects
them together to implement a system.
• Source and Sink Interfaces and Connections—When two components are connected, the data flows
from the source interface to the sink interface. The combination of a source interface connected to a
sink interface is referred to as a connection.
• Backpressure—Backpressure allows a sink to signal a source to stop sending data. Support for
backpressure is optional. The sink uses backpressure to stop the flow of data for the following reasons:
• When its FIFOs are full
• When there is congestion on its output interface.
• Transfers and Ready Cycles—A transfer results in data and control propagation from a source
interface to a sink interface. For data interfaces, a ready cycle is a cycle during which the sink can
accept a transfer.
• Symbol—A symbol is the smallest unit of data. For most packet interfaces, a symbol is a byte. One or
more symbols make up the single unit of data transferred in a cycle.
• Channel—A channel is a physical or logical path or link through which information passes between
two ports.
• Beat—A beat is a single cycle transfer between a source and sync interface made up of one or more
symbols.
• Packet—A packet is an aggregation of data and control signals that is transmitted together. A packet
may contain a header to help routers and other network devices direct the packet to the correct
destination. The packet format is defined by the application, not this specification. Avalon-ST packets
can be variable in length and can be interleaved across a connection. With an Avalon-ST interfaces, the
use of packets is optional.

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5.2 Avalon Streaming Interface Signal Roles

Each signal in an Avalon-ST source or sink interface corresponds to one Avalon-ST signal role. An
Avalon-ST interface may contain only one instance of each signal role. All Avalon-ST signal roles apply to
both sources and sinks and have the same meaning for both.

Table 5-1: Avalon-ST Interface Signals

In the following table, all signal roles are active high.
Signal Role Width Direction Description
Fundamental Signals
channel 1 – 128 Source → Sink The channel number for data being transferred
on the current cycle.
If an interface supports the channel signal, it must
also define the maxChannel parameter.

data 1 – 4,096 Source → Sink The data signal from the source to the sink,
typically carries the bulk of the information being
transferred.
The contents and format of the data signal is
further defined by parameters.

error 1 – 256 Source → Sink A bit mask used to mark errors affecting the data
being transferred in the current cycle. A single bit
in error is used for each of the errors recognized
by the component, as defined by the errorDe-
scriptor property.

ready 1 Sink → Source Asserted high to indicate that the sink can accept
data. ready is asserted by the sink on cycle <n> to
mark cycle <n + readyLatency> as a ready cycle.
The source may only assert valid and transfer
data during ready cycles.
Sources without a ready input cannot be
backpressured. Sinks without a ready output
never need to backpressure.

valid 1 Source → Sink Asserted by the source to qualify all other source
to sink signals. The sink samples data other
source-to-sink signals on ready cycles where
valid is asserted. All other cycles are ignored.

Sources without a valid output implicitly

provide valid data on every cycle that they are not
being backpressured. Sinks without a valid input
expect valid data on every cycle that they are not
backpressuring.

Packet Transfer Signals

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Signal Role Width Direction Description

empty 1–8 Source → Sink Indicates the number of symbols that are empty,
that is, do not represent valid data. The empty
signal is not used on interfaces where there is one
symbol per beat.
endofpacket 1 Source → Sink Asserted by the source to mark the end of a
packet.
startofpacket 1 Source → Sink Asserted by the source to mark the beginning of a
packet.

5.3 Signal Sequencing and Timing

5.3.1 Synchronous Interface
All transfers of an Avalon-ST connection occur synchronous to the rising edge of the associated clock
signal. All outputs from a source interface to a sink interface, including the data, channel, and error
signals, must be registered on the rising edge of clock. Inputs to a sink interface do not have to be
registered. Registering signals at the source facilitates high frequency operation.

5.3.2 Clock Enables

Avalon-ST components typically do not include a clock enable input. The Avalon-ST signaling itself is
sufficient to determine the cycles that a component should and should not be enabled. Avalon-ST
compliant components may have a clock enable input for their internal logic. But, they must ensure that
the timing of the interface control signals still adheres to the protocol.

5.4 Avalon-ST Interface Properties

Table 5-2: Avalon-ST Interface Properties

Property Name Default Legal Description

Value Values
symbolsPerBeat 1 1 – 32 The number of symbols that are transferred on
every valid cycle.
associatedClock 1 Clock The name of the Avalon Clock interface to
interface which this Avalon-ST interface is synchronous.
associatedReset 1 Reset The name of the Avalon Reset interface to
interface which this Avalon-ST interface is synchronous.

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Property Name Default Legal Description

Value Values
beatsPerCycle 8 Specifies the number of beats that are
transferred in a single cycle. This property
allows you to transfer 2 separate, but correlated
streams using the same start_of_packet,
end_of_packet, ready and valid signals.

beatsPerCycle is a rarely used feature of the

Avalon-ST protocol.

dataBitsPerSymbol 8 1 – 512 Defines the number of bits per symbol. For

example, byte-oriented interfaces have 8-bit
symbols. This value is not restricted to be a
power of 2.
emptyWithinPacket false true, false When true, empty is valid for the entire packet.
errorDescriptor 0 List of A list of words that describe the error
strings associated with each bit of the error signal. The
length of the list must be the same as the
number of bits in the error signal. The first
word in the list applies to the highest order bit.
For example, “crc, overflow" means that bit[1]
of error indicates a CRC error. Bit[0] indicates
an overflow error.
firstSymbolInHigh true true, false When true, the first-order symbol is driven to
OrderBits the most significant bits of the data interface.
The highest-order symbol is labeled D0 in this
specification. When this property is set to false,
the first symbol appears on the low bits. D0
appears at data[7:0]. For a 32-bit bus, if true,
D0 appears on bits[31:24].

maxChannel 0 0 – 255 The maximum number of channels that a data

interface can support.
readyLatency 0 0–8 Defines the relationship between assertion and
deassertion of ready and cycles which are
considered to be available for data transfer. The
readyLatency is defined separately for each
interface.

5.5 Typical Data Transfers

This section defines the transfer of data from a source interface to a sink interface. In all cases, the data
source and the data sink must comply with the specification. It is not the responsibility of the data sink to
detect source protocol errors.

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5.6 Signal Details

The following figure shows the signals that are typically included in an Avalon-ST interface. As this figure
indicates, a typical Avalon-ST source interface drives the valid, data, error, and channel signals to the
sink. The sink can apply backpressure using the ready signal.
Figure 5-2: Typical Avalon-ST Interface Signals

Data Source Data Sink

ready
valid
data
error
channel
<max_channel>

Here are more details about these signals:

• ready—On interfaces supporting backpressure, the sink asserts ready to mark the cycles where
transfers may take place. If ready is asserted on cycle <n>, cycle <n + readyLatency> is considered a
ready cycle.
• valid—The valid signal qualifies valid data on any cycle where data is being transferred from the
source to the sink. On each valid cycle the data signal and other source to sink signals are sampled by
the sink.
• data—The data signal typically carries the bulk of the information being transferred from the source
to the sink. The data signal consists of one or more symbols being transferred on every clock cycle. The
dataBitsPerSymbol parameter defines how the data signal is divided into symbols.
• error—Errors are signaled with the error signal, where each bit in error corresponds to a possible
error condition. A value of 0 on any cycle indicates the data on that cycle is error-free. The action that
a component takes when an error is detected is not defined by this specification.
• channel—The optional channel signal is driven by the source to indicate the channel to which the
data belongs. The meaning of channel for a given interface depends on the application. Some applica‐
tions use channel as a interface number indication. Other applications use channel as a page number
or timeslot indication. When the channel signal is used, all of the data transferred in each active cycle
belongs to the same channel. The source may change to a different channel on successive active cycles.
An interface that uses the channel signal must define the maxChannel parameter to indicate the
maximum channel number. If the number of channels an interface supports changes dynamically,
maxChannel is the maximum number the interface can support.

5.7 Data Layout

Figure 5-3: Data Symbols
The following figure shows a 64-bit data signal with dataBitsPerSymbol=16. Symbol 0 is the most
significant symbol.
63 48 47 32 31 16 15 0
symbol 0 symbol 1 symbol 2 symbol 3

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Figure 5-4: Layout of Data

The timing diagram in the following figure shows a 32-bit example where dataBitsPerSymbol=8.
clk
ready
valid
channel
error
data[31:24] D0 D4 D8 DC D10
data[23:16] D1 D5 D9 DD D11
data[15:8] D2 D6 DA DE D12
data[7:0] D3 D7 DB DF D13

5.8 Data Transfer without Backpressure

The data transfer without backpressure is the most basic of Avalon-ST data transfers. On any given clock
cycle, the source interface drives the data and the optional channel and error signals, and asserts valid.
The sink interface samples these signals on the rising edge of the reference clock if valid is asserted.
Figure 5-5: Data Transfer without Backpressure

clk
valid
channel
error
data D0 D1 D2 D3

5.9 Data Transfer with Backpressure

The sink asserts ready for a single clock cycle to indicate it is ready for an active cycle. Cycles during
which the sink is ready for data are called ready cycles. During a ready cycle, the source may assert valid
and provide data to the sink. If it has no data to send, it deasserts valid and can drive data to any value.
Each interface that supports backpressure defines the readyLatency parameter to indicate the number of
cycles from the time that ready is asserted until valid data can be driven. If the readyLatency is nonzero,
cycle <n + readyLatency> is a ready cycle if ready is asserted on cycle <n>. Any interface that includes
the ready signal and defines the readyLatency parameter supports backpressure.
When readyLatency = 0, data is transferred only when ready and valid are asserted on the same cycle.
In this mode, the source does not receive the sink’s ready signal before it begins sending valid data. The
source provides the data and asserts valid whenever it can. The source waits for the sink to capture the
data and assert ready. The source can change the data it is providing at any time. The sink only captures
input data from the source when ready and valid are both asserted.
When readyLatency >= 1, the sink asserts ready before the ready cycle itself. The source can respond
during the appropriate cycle by asserting valid. It may not assert valid during a cycle that is not a ready
cycle.

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Figure 5-6: Avalon-ST Interface with readyLatency = 4

clock

ready

readyLatency = 4 readyLatency = 4

valid

source may not assert valid

source may assert valid

data[31:0] 1 2 3 4

Figure 5-7: Transfer with Backpressure, readyLatency=0

The following figure illustrates these events:
1. The source provides data and asserts valid on cycle 1, even though the sink is not ready.
2. The source waits until cycle 2, when the sink does assert ready, before moving onto the next data
cycle.
3. In cycle 3, the source drives data on the same cycle and the sink is ready to receive it. The transfer
occurs immediately.
4. In cycle 4, the sink asserts ready, but the source does not drive valid data.

0 1 2 3 4 5 6 7 8
clk
ready
valid
channel
error
data D0 D1 D2 D3

Figure 5-8: Transfer with Backpressure, readyLatency=1

The following figures show data transfers with readyLatency=1 and readyLatency=2, respectively. In
both these cases, ready is asserted before the ready cycle, and the source responds 1 or 2 cycles later by
providing data and asserting valid. When readyLatency is not 0, the source must deassert valid on
non-ready cycles.
clk
ready
valid
channel
error
data D0 D1 D2 D3 D4 D5

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Figure 5-9: Transfer with Backpressure, readyLatency=2

clk
ready
valid
channel
error
data D0 D1 D2 D3

5.10 Packet Data Transfers

The packet transfer property adds support for transferring packets from a source interface to a sink
interface. Three additional signals are defined to implement the packet transfer. Both the source and sink
interfaces must include these additional signals to support packets. You can only connect source and sink
interfaces with matching packet properties. Qsys does not automatically add the startofpacket ,
endofpacket, and empty signals to source or sink interfaces that do not include these signals.

Figure 5-10: Avalon-ST Packet Interface Signals

Data Source Data Sink

ready
valid
data
error
channel
<max channel>
startofpacket
endofpacket
empty

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5.11 Signal Details

• startofpacket—All interfaces supporting packet transfers require the startofpacket signal.
startofpacket marks the active cycle containing the start of the packet. This signal is only interpreted
when valid is asserted.
• endofpacket—All interfaces supporting packet transfers require the endofpacket signal.
endofpacket marks the active cycle containing the end of the packet. This signal is only interpreted
when valid is asserted. startofpacket and endofpacket can be asserted in the same cycle. No idle
cycles are required between packets. The startofpacket signal can follow immediately after the
previous endofpacket signal.
• empty—The optional empty signal indicates the number of symbols that are empty the endofpacket
cycle. The sink only checks the value of the empty during active cycles that have endofpacket asserted.
The empty symbols are always the last symbols in data, those carried by the low-order bits when
firstSymbolInHighOrderBits = true. The empty signal is required on all packet interfaces whose
data signal carries more than one symbol of data and have a variable length packet format. The size of
the empty signal in bits is log2(<symbols per cycle>) - 1.

5.12 Protocol Details

Packet data transfer follows the same protocol as the typical data transfer with the addition of the
startofpacket, endofpacket, and empty.

Figure 5-11: Packet Transfer

The following figure illustrates the transfer of a 17-byte packet from a source interface to a sink interface,
where readyLatency=0. It illustrates the following events:
1. Data transfer occurs on cycles 1, 2, 4, 5, and 6, when both ready and valid are asserted.
2. During cycle 1, startofpacket is asserted. The first 4 bytes of packet are transferred.
3. During cycle 6, endofpacket is asserted. empty has a value of 3. This value indicates that this is the end
of the packet and that 3 of the 4 symbols are empty. In cycle 6, the high-order byte, data[31:24] drives
valid data.

1 2 3 4 5 6 7
clk
ready
valid
startofpacket
endofpacket
empty 3
channel 0 0 0 0 0
error 0 0 0 0 0
data[31:24] D0 D4 D8 D12 D16
data[23:16] D1 D5 D9 D13
data[15:8] D2 D6 D10 D14
data[7:0] D3 D7 D11 D15

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Avalon Conduit Interfaces
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Avalon Conduit interfaces group an arbitrary collection of signals. You can specify any role for conduit
signals. However, when you connect conduits, the roles and widths must match and the directions must
be opposite. An Avalon Conduit interface can include input, output, and bidirectional signals. A module
can have multiple Avalon Conduit interfaces to provide a logical signal grouping. Conduit interfaces can
declare an associated clock. When connected conduit interfaces are in different clock domains, Qsys
generates an error message.
Note: If possible, you should use the standard Avalon-MM or Avalon-ST interfaces instead of creating an
Avalon Conduit interface. Qsys provides validation and adaptation for these interfaces. It cannot
provide validation or adaptation for Avalon Conduit interfaces.
Conduit interfaces typically used to drive off-chip device signals, such as an SDRAM address, data and
control signals.

© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance ISO
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any 9001:2008
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, Registered
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.

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6-2 6.1 Avalon Conduit Signal Roles 2015.03.04

Figure 6-1: Focus on the Conduit Interface

Ethernet
PHY

Avalon-MM System
Processor Ethernet MAC Custom Logic
Avalon-MM Avalon-MM Avalon-MM
Master Master Master

System Interconnect Fabric

Avalon-MM Avalon
Slave Slave
SDRAM Custom
Controller Logic

Conduit
Interface
Custom
SDRAM
Logic
Memory

6.1 Avalon Conduit Signal Roles

Table 6-1: Conduit Signal Roles

Signal Role Width Direction Description

<any> <n> In, out, or A conduit interface consists of one or more input, output, or
bidirectional bidirectional signals of arbitrary width. Conduits can have any
user-specified role. You can connect compatible Conduit
interfaces inside a Qsys system provided the roles and widths
match and the directions are opposite.

6.2 Conduit Properties

There are no properties for conduit interfaces.

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Avalon Tristate Conduit Interface
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The Avalon Tristate Conduit Interface (Avalon-TC) is a point-to-point interface designed for on-chip
controllers that drive off-chip components. This interface allows data, address, and control pins to be
shared across multiple tristate devices. Sharing conserves pins in systems that have multiple external
memory devices.
The Avalon-TC interface restricts the more general Avalon Conduit Interface in two ways:
• The Avalon-TC requires request and grant signals. These signals enable bus arbitration when
multiple Tristate Conduit Masters (TCM) are requesting access to a shared bus.
• The pin type of a signal must be specified using suffixes appended to a signal’s role. The three suffixes
are: _out, _in, and _outen. Matching role prefixes identify signals that share the same I/O Pin. The
following illustrates the naming conventions for Avalon-TC shared pins.
Figure 7-1: Shared Pin Types

Bidirectional Pin Tri-State Output Only Pin Output Only Pin Input Only Pin
Altera FPGA Altera FPGA Altera FPGA Altera FPGA
data_outen reset_outen ~reset
data_out data reset_out reset busy_in busy
data_in

write_out write

The next figure illustrates pin sharing using Avalon-TC interfaces. This figure illustrates the following
points.

© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance ISO
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any 9001:2008
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, Registered
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.

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• The Tristate Conduit Pin Sharer includes separate Tristate Conduit Slave Interfaces for each Tristate
Conduit Master. Each master and slave pair has its own request and grant signals.
• The Tristate Conduit Pin Sharer identifies signals with identical roles as tristate signals that share the
same FPGA pin. In this example, the following signals are shared: addr_out, data_out, data_in,
read_out, and write_out.
• The Tristate Conduit Pin Sharer drives a single bus including all of the shared signals to the Tristate
Conduit Bridge. If the widths of shared signals differ, the Tristate Conduit Pin Sharer aligns them on
their 0th bit. It drives the higher-order pins to 0 whenever the smaller signal has control of the bus.
• Signals that are not shared propagate directly through the Tristate Conduit Pin Sharer. In this example,
the following signals are not shared: chipselect0_out, irq0_out, chipselect1_out, and irq1_out.
• All Avalon-TC interfaces connected to the same Tristate Conduit Pin Sharer must be in the same clock
domain.

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Figure 7-2: Tristate Conduit Interfaces

The following illustrates the typical use of Avalon-TC Master and Slave interfaces and signal naming.

Altera FPGA
TCM Tristate Conduit Master Tristate Conduit Tristate Conduit
TCS Tristate Conduit Slave Pin Sharer TCM TCS Bridge
S Avalon-MM Slave
Controller TCM TCS
for 2 MByte CS chipselect_out chipselect_out
IRQ
x32 SSRAM A[20:0] addr_out_[20:0]
D_EN dataout_outen
Avalon-MM D[31:0] dataout_out[31:0] request
DI[31:0] data_in[31:0] grant
Master S Rd read_out
Wr write_out
Request request
Grant grant

addr_out<n>
clock
Arb
data_outen<n>
data_out<n>
data_in<n>

read_out
Controller
for 8 MByte TCM TCS write_out
x16 Flash Grant request
Req grant
A[22:0] addr_out_[22:0]
D_EN dataout_outen
dataout_out[15:0]
S D[15:0]
DI[15:0] data_in[15:0]
Rd read_out
Wr write_out
CS chipselect_out chipselect_out
IRQ irq_in irq_in

For more information about the Generic Tristate Controller and Tristate Conduit Pin Sharer, refer to the
Avalon Tristate Conduit Components User Guide.

Related Information
Avalon Tristate Conduit Components User Guide

7.1 Avalon Tristate Conduit Signal Roles

The following table lists the signal defined for the Avalon Tristate Conduit interface. All Avalon-TC
signals apply to both masters and slaves and have the same meaning for both

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Table 7-1: Tristate Conduit Interface Signal Roles

Signal Role Width Direction Required Description

request 1 Master → Slave Yes The meaning of request depends on the state
of the grant signal, as the following rules
dictate.
When request is asserted and grant is
deasserted, request is requesting access for
the current cycle.
When request is asserted and grant is
asserted, request is requesting access for the
next cycle. Consequently, request should be
deasserted on the final cycle of an access.
The request is deasserted in the last cycle of
a bus access. It can be reasserted immediately
following the final cycle of a transfer. This
protocol makes both rearbitration and
continuous bus access possible if no other
masters are requesting access.
Once asserted, request must remain asserted
until granted. Consequently, the shortest bus
access is 2 cycles. Refer to Tristate Conduit
Arbitration Timing for an example of arbitra‐
tion timing.

grant 1 Slave → Master Yes When asserted, indicates that a tristate

conduit master has been granted access to
perform transactions. grant is asserted in
response to the request signal. It remains
asserted until 1 cycle following the deasser‐
tion of request.
<name>_in 1 – 1024 Slave → Master No The input signal of a logical tristate signal.
<name>_out 1 – 1024 Master → Slave No The output signal of a logical tristate signal.
<name>_ 1 Master → Slave No The output enable for a logical tristate signal.
outen

7.2 Tristate Conduit Properties

There are no special properties for the Avalon-TC Interface.

7.3 Tristate Conduit Timing

The following illustrates arbitration timing for the Tristate Conduit Pin Sharer. Note that a device can
drive or receive valid data in the granted cycle.

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Figure 7-3: Tristate Conduit Arbitration Timing

This figure shows the following sequence of events:
1. In cycle 1, the tristate conduit slave asserts grant. The slave drives valid data in cycles1 and 2.
2. In cycle 4, the tristate conduit slave asserts grant. The slave drives valid data in cycles 5–8.
3. In cycle 9, the tristate conduit slave asserts grant. The slave drives valid data in cycles 10–17.
4. Cycles 3, 4 and 9 do not contain valid data.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

clk

request

grant

data_out[31:0] 0 . a b c d e f 10 11 12 13 14 15 16 17

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Deprecated Signals
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Deprecated signals implement functionality that is no longer required or has been superceded.

begintransfer
An output of Avalon-MM masters. Asserted for a single cycle at the beginning of a transfer. This is signal
is not used and not necessary.

chipselect or chipselect_n
chipselect or chipselect_n: The chip select signal as described below was deprecated with the release
of the Avalon Tristate Conduct (Avalon-TC) interface type which includes a chip select signal.
Formerally chipselect was a 1-bit input to an Avalon Memory-Mapped (Avalon-MM) slave interface
signalling the beginning of a read or write transfer. The current Qsys interconnect filters read and write
signals from masters according to the address and address map. The Qsys interconnect only drives read
and write signals to the appropriate Avalon-MM slave, making a chip select unnecessary.
This signal dates from very early microprocessor designs. CPLDs decoded microprocessor addresses and
generated chip selects for peripherals that typically were frequently asynchronous. With synchronous
systems this signal is typically unnecessary.

flush
This signal was removed version 1.2 of the Avalon Interface Specifications. Formerly available to masters
to clear pending transfers for pipelined reads.

© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance ISO
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any 9001:2008
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, Registered
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.

www.altera.com
101 Innovation Drive, San Jose, CA 95134
 2015.03.04
Additional Information
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Table B-1: Document Revision History

Date Version Changes

March 2015 14.1 Fixed typo in Figure 1-1.
January 2015 14.1 Made the following changes:
• Clarified address alignment example. The Avalon-MM master
and slave interfaces are different widths.
• Improved discussion of Pipelined read Transfers with Variable
Latency. Corrected timing marker 2 which should be exactly
on the rising edge of clock.
• Improved discussion of Pipelined Read Transfer with Fixed
Latency of Two Cycles.
• Clarified use of beatsPerCycle property.
• Corrected the address range for line-wrapped bursts. The
correct address range for a 64-byte burst is 0x0–0x3C, not
0x0–0x1C.
• Corrected description of the Tristate Conduit Arbitration
Timing diagram in the following ways:
• The tristate conduit slave asserts grant, not the tristate
conduit master.
• The final grant comes in cycle 9, not cycle 8.
• Added a Deprecated Signals appendix.
• Added read response signal.
• Improved definitions of clock and reset signal types.
• Corrected definition of clock sink properties.
• Corrected definition of synchronousEdges for reset source
interface.
• Clarified the Avalon-MM response signal type.
• Updated definition of empty. The signal must be interpreted
emptyWithinPacket is true.
• Edited for clarity and consistency.

© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance ISO
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any 9001:2008
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, Registered
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.

www.altera.com
101 Innovation Drive, San Jose, CA 95134
 MNL-AVABUSREF
B-2 B.1 How to Contact Altera 2015.03.04

Date Version Changes

June 2014 14.0 • Updated the Avalon-MM Signals table, begintransfer,
readdatavalid, and readdatavalid_n.
• Updated the Read and Write Transfers with Waitrequest
figure:
• Moved deassertion of write to cycle 6.
• Moved assertion of readdatavalid and readdata to cycle
4.
• Updated the Pipelined Read Transfers with Variable Latency
figure:
• Moved assertion of data1 to just after cycle 5, and
assertion of data2 to cycle 6.
• Moved assertion of readdatavalid to match data1 and
data2.

April 2014 13.01 Corrected Read and Write Transfers with Waitrequest In Avalon
Memory-Mapped Interfaces chapter .
May 2013 13.0 Made the following changes:
• Minor updates to Avalon Memory-Mapped Interfaces.
• Minor updates to Avalon Streaming Interfaces.
• Updated Avalon Conduit Interfaces to describe the signal roles
supported by Avalon conduit interfaces.
• Updated Shared Pin Types figure in the Avalon Tristate
Conduit Interface chapter.

May 2011 11.0 Initial release of the Avalon Interface Specifications supported by
Qsys.

B.1 How to Contact Altera

To locate the most up-to-date information about Altera products, refer to the following table.

Table B-2: Altera Contact Information

Contact (1) Contact Method Address

Technical support Website www.altera.com/support

Website www.altera.com/training
Technical training
Email custrain@altera.com

Product literature Website www.altera.com/literature

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Contact (1) Contact Method Address

Nontechnical support (general) Email nacomp@altera.com

Nontechnical support (software Email authorization@altera.com

licensing)

Note to Table:
1. You can also contact your local Altera sales office or sales representative.

Related Information
• www.altera.com/support
• www.altera.com/training
• custrain@altera.com
• www.altera.com/literature
• nacomp@altera.com
• authorization@altera.com

B.2 Typographic Conventions

The following table shows the typographic conventions this document uses.

Visual Cue Meaning

Bold Type with Initial Indicate command names, dialog box titles, dialog box options, and
Capital Letters other GUI labels. For example, Save As dialog box. For GUI
elements, capitalization matches the GUI.
bold type Indicates directory names, project names, disk drive names, file
names, file name extensions, software utility names, and GUI labels.
For example, \qdesigns directory, D: drive, and chiptrip.gdf file.
Italic Type with Initial Indicate document titles. For example, Stratix IV Design Guidelines.
Capital Letters
italic type Indicates variables. For example, n + 1.
Variable names are enclosed in angle brackets (< >). For example,
<file name> and <project name>.pof file.

Initial Capital Letters Indicate keyboard keys and menu names. For example, the Delete
key and the Options menu.
“Subheading Title” Quotation marks indicate references to sections within a document
and titles of Quartus II Help topics. For example, “Typographic
Conventions.”

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Visual Cue Meaning

Courier type Indicates signal, port, register, bit, block, and primitive names. For
example, data1, tdi, and input. The suffix n denotes an active-low
signal. For example, reset_n.
Indicates command line commands and anything that must be
typed exactly as it appears. For example, c:\qdesigns\tutorial\
chiptrip.gdf.

Also indicates sections of an actual file, such as a Report File,

references to parts of files (for example, the AHDL keyword
SUBDESIGN), and logic function names (for example, TRI).

r An angled arrow instructs you to press the Enter key.

1., 2., 3., and Numbered steps indicate a list of items when the sequence of the
a., b., c., and so on items is important, such as the steps listed in a procedure.
■■■ Bullets indicate a list of items when the sequence of the items is not
important.
1 The hand points to information that requires special attention.
h A question mark directs you to a software help system with related
information.
f The feet direct you to another document or website with related
information.
c A caution calls attention to a condition or possible situation that
can damage or destroy the product or your work.
w A warning calls attention to a condition or possible situation that
can cause you injury.

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