0% found this document useful (0 votes)
141 views12 pages

STD9N10 STD9N10-1: N-CHANNEL 100V - 0.23 - 9A Dpak/Ipak Power Mos Transistor

This datasheet provides specifications for an N-channel 100V power MOS transistor. It includes maximum ratings, electrical characteristics tables, and graphs of key parameters like output characteristics, thermal impedance, and capacitance variations.

Uploaded by

Eligio Vásquez
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
141 views12 pages

STD9N10 STD9N10-1: N-CHANNEL 100V - 0.23 - 9A Dpak/Ipak Power Mos Transistor

This datasheet provides specifications for an N-channel 100V power MOS transistor. It includes maximum ratings, electrical characteristics tables, and graphs of key parameters like output characteristics, thermal impedance, and capacitance variations.

Uploaded by

Eligio Vásquez
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 12

STD9N10

STD9N10-1
N-CHANNEL 100V - 0.23 Ω - 9A DPAK/IPAK
POWER MOS TRANSISTOR

Table 1. General Features Figure 1. Package


Type VDSS RDS(on) ID

STD9N10 100 V < 0.27 Ω 9A


STD9N10-1 100 V < 0.27 Ω 9A

FEATURES SUMMARY
■ TYPICAL RDS(on) = 0.23 Ω

■ AVALANCHE RUGGED TECHNOLOGY


3 3
■ 100% AVALANCHE TESTED 2
1 1
■ REPETITIVE AVALANCHE DATA AT 100°C
■ LOW GATE CHARGE
IPAK DPAK
■ HIGH CURRENT CAPABILITY
TO-251 TO-252
■ 175°C OPERATING TEMPERATURE
■ APPLICATION ORIENTED
CHARACTERIZATION
■ THROUGH-HOLE IPAK (TO-251) POWER
Figure 2. Internal Schematic Diagram
PACKAGE IN TUBE (SUFFIX "-1")
■ SURFACE-MOUNTING DPAK (TO-252)
POWER PACKAGE IN TAPE & REEL
(SUFFIX "T4")

APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING

■ SOLENOID AND RELAY DRIVERS


■ REGULATORS
■ DC-DC & DC-AC CONVERTERS
■ MOTOR CONTROL, AUDIO AMPLIFIERS
■ AUTOMOTIVE ENVIRONMENT (INJECTION,
ABS, AIR-BAG, LAMPDRIVERS, Etc.)

Table 2. Order Codes


Part Number Marking Package Packaging
STD9N10T4 D9N10 DPAK TAPE & REEL
STD9N10-1 D9N10 IPAK TUBE

REV. 2
May 2004 1/12

This datasheet has been downloaded from http://www.digchip.com at this page


STD9N10/STD9N10-1

Table 3. Absolute Maximum Ratings


Symbol Parameter Value Unit
VDS Drain-source Voltage (VGS = 0) 100 V
VDGR Drain- gate Voltage (RGS = 20 kΩ) 100 V
VGS Gate-source Voltage ± 20 V
ID Drain Current (cont.) at TC = 25 °C 9 A
ID Drain Current (cont.) at TC = 100 °C 6 A

IDM (1) Drain Current (pulsed) 36 A

Ptot Total Dissipation at TC = 25 °C 45 W


Derating Factor 0.3 W°/C
Tstg Storage Temperature -65 to 175 °C
Tj Max. Operating Junction Temperature 175 °C
Note: 1. Pulse width limited by safe operating area.

Table 4. Thermal Data


Symbol Parameter Value Unit
Rthj-case Thermal Resistance Junction-case Max 3.33 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 100 °C/W
Tl Maximum Lead Temperature For Soldering Purpose 275 °C

Table 5. Avalanche Characteristics


Symbol Parameter Max Value Unit
IAR Avalanche Current, Repetitive or Not-Repetitive 9 A
(pulse width limited by Tj max, δ < 1%)
EAS Single Pulse Avalanche Energy 30 mJ
(starting Tj = 25 °C; ID = IAR; VDD = 25 V)
EAR Repetitive Avalanche Energy 7 mJ
(pulse width limited by Tj max, δ < 1%)
IAR Avalanche Current, Repetitive or Not-Repetitive 6 A
(Tc = 100 °C, pulse width limited by Tj max, δ < 1%)

2/12
STD9N10/STD9N10-1

ELECTRICAL CHARACTERISTICS (Tcase = 25°C unless otherwise specified)

Table 6. Off
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source ID = 250 µA; VGS = 0 100 V
Breakdown Voltage
IDSS Zero Gate Voltage VDS = Max Rating 250 µA
Drain Current (VGS = 0) VDS = Max Rating x 0.8; Tc = 125 °C 1000 µA
IGSS Gate-body Leakage VGS = ± 20 V ± 100 nA
Current (VDS = 0)

Table 7. On (1)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VGS(th) Gate Threshold Voltage VDS = VGS; ID = 250 µA 2 3 4 V
RDS(on) Static Drain-source On VGS = 10V; ID = 4.5 A 0.23 0.27 Ω
Resistance VGS = 10V; ID = 4.5 A; Tc = 100 °C 0.54 Ω
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %

Table 8. Dynamic
Symbol Parameter Test Conditions Min. Typ. Max. Unit

gfs (1) Forward VDS > ID(on) x RDS(on)max; ID = 4.5 A 2 4 S


Transconductance
Ciss Input Capacitance VDS = 25 V; f = 1 MHz; VGS = 0 330 450 pF
Coss Output Capacitance 90 120 pF
Crss Reverse Transfer 25 40 pF
Capacitance
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %

Table 9. Switching On
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(on) Turn-on Time VDD = 50 V; ID = 4.5 A; RG = 4.7 Ω 10 15 ns
tr Rise Time VGS = 10 V (see test circuit, Figure 22) 40 60 ns
(di/dt)on Turn-on Current Slope VDD = 80 V; ID = 9 A; RG = 4.7 Ω 440 A/µs
VGS = 10 V (see test circuit, Figure 22)
Qg Total Gate Charge VDD = 80 V; ID = 9 A; VGS = 10 V 15 25 nC
Qgs Gate-Source Charge 6 nC
Qgd Gate-Drain Charge 5 nC

Table 10. Switching Off


Symbol Parameter Test Conditions Min. Typ. Max. Unit
tr(Voff) Off-voltage Rise Time VDD = 80 V; ID = 9 A; RG = 4.7 Ω 15 25 ns
tf Fall Time VGS = 10 V (see test circuit, Figure 24) 25 35 ns
tc Cross-over Time 50 70 ns

3/12
STD9N10/STD9N10-1

Table 11. Source Drain Diode


Symbol Parameter Test Conditions Min. Typ. Max. Unit
ISD Source-drain Current 9 A

ISDM (1) Source-drain Current 36 A


(pulsed)

VSD (2) Forward On Voltage ISD = 9 A; VGS = 0 1.5 V

trr Reverse Recovery Time ISD = 9 A; di/dt = 100 A/µs 80 ns


VDD = 20 V; Tj = 150 °C
Qrr Reverse RecoveryCharge 0.2 µC
(see test circuit, Figure 24)
IRRAM Reverse RecoveryCurrent 5 A
Note: 1. Pulse width limited by safe operating area
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %

Figure 3. Safe Operating Area Figure 4. Thermal Impedance

Figure 5. Derating Curve Figure 6. Output Characteristics

4/12
STD9N10/STD9N10-1

Figure 7. Transfer Characteristics Figure 8. Transconductance

Figure 9. Static Drain-source On Resistance Figure 10. Gate Charge vs Gate-source Voltage

Figure 11. Capacitance Variations Figure 12. Normalized Gate Threshold Voltage
vs Temperature

5/12
STD9N10/STD9N10-1

Figure 13. Normalized On Resistance vs Figure 14. Turn-on Current Slope


Temperature

Figure 15. Turn-off Drain-source Voltage Slope Figure 16. Cross-over Time

Figure 17. Switching Safe Operating Area Figure 18. Accidental Overload Area

6/12
STD9N10/STD9N10-1

Figure 19. Source-drain Diode Forward


Characteristics

7/12
STD9N10/STD9N10-1

Figure 20. Unclamped Inductive Load Test Figure 21. Unclamped Inductive Waveforms
Circuit

Figure 22. Switching Times Test Circuits For Figure 23. Gate Charge Test Circuit
Resistive Load

Figure 24. Test Circuit For Inductive Load


Switching And Diode Recovery Times

8/12
STD9N10/STD9N10-1

PACKAGE MECHANICAL

Table 12. DPAK Mechanical Data


millimeters inches
Symbol
Min Typ Max Min Typ Max
A 2.20 2.40 0.087 0.094
A1 0.90 1.10 0.035 0.043
A2 0.03 0.23 0.001 0.009
B 0.64 0.90 0.025 0.035
B2 5.20 5.40 0.204 0.213
C 0.45 0.60 0.018 0.024
C2 0.48 0.60 0.019 0.024
D 6.00 6.20 0.236 0.244
E 6.40 6.60 0.252 0.260
G 4.40 4.60 0.173 0.181
H 9.35 10.10 0.368 0.398
L2 0.8 0.031
L4 0.60 1.00 0.024 0.039
V2 0° 8° 0° 0°

Figure 25. DPAK Package Dimensions

P032P_B

Note: Drawing is not to scale.

9/12
STD9N10/STD9N10-1

Table 13. IPAK Mechanical Data


millimeters inches
Symbol
Min Typ Max Min Typ Max
A 2.2 2.4 0.086 0.094
A1 0.9 1.1 0.035 0.043
A3 0.7 1.3 0.027 0.051
B 0.64 0.9 0.025 0.031
B2 5.2 5.4 0.204 0.212
B3 0.85 0.033
B5 0.63 0.012
B6 0.95 0.037
C 0.45 0.6 0.017 0.023
C2 0.48 0.6 0.019 0.023
D 6 6.2 0.236 0.244
E 6.4 6.6 0.252 0.260
G 4.4 4.6 0.173 0.181
H 15.9 16.3 0.626 0.641
L 9 9.4 0.354 0.370
L1 0.8 1.2 0.031 0.047
L2 0.8 1 0.031 0.039

Figure 26. IPAK Package Dimensions

H
C
A

A3
C2

A1

L2 D L
B3

B6

B5
B
3
=

=
B2

G
E

2
=

L1
0068771-E

Note: Drawing is not to scale.

10/12
STD9N10/STD9N10-1

REVISION HISTORY

Table 14. Revision History


Date Revision Description of Changes

March-1996 1 First Issue

3-May-2004 2 Stylesheet update. No content change.

11/12
STD9N10/STD9N10-1

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.


All other names are the property of their respective owners

© 2004 STMicroelectronics - All rights reserved

STMicroelectronics GROUP OF COMPANIES


Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com

12/12

You might also like