Answer Key CSE 105 II - CIA
PART A (10X2=20)
1. How to calculate branch target address in the datapath?
The address specified in a branch, which becomes the new program counter (PC) if the branch is
taken. In the MIPS architecture the branch target is given by the sum of the offset field of the
instruction and the address of the instruction following the branch.
2. Illustrate the mechanism involved in generating ALU control input.
We can generate the 4-bit ALU control input using a small control unit that has as inputs the
function field of the instruction and a 2-bit control field, which we call ALUOp.
3. List the methods to improve the throughput of the processor.
a) Decreasing the execution time of an individual instruction (Cycle Time Reduction)
b) Pipelining
4. Classify the hazards in the pipeline based on its recoverable nature and justify.
Structural hazard (Non Recoverable)
Data and Control hazard (Recoverable)
5. When will the forwarding method fail and give a suitable example?
Forwarding will fail for load- use case. (1)
Any one load instruction for the example. (1)
6. Which control signals involved in the execution stage of pipelined datapath?
RegDst, ALUop, ALUSrc
7. Construct five-stage pipeline with the graphical representations for the given instruction
lw $10, 20 ($1)
8. Identify the dependencies in the following instruction sequence and detect the possible
hazards
sub $2, $1, $3
and $12, $2, $5
or $13, $6, $2
$2 register dependency (1)
Data hazard (1)
9. What is loop unrolling?
A technique to get more performance from loops that access arrays, in which multiple copies of
the loop body are made and instructions from different iterations are scheduled together.
10. Define hit time and miss penalty.
Hit time is the time to access the upper level of the memory hierarchy, which includes the time
needed to determine whether the access is a hit or a miss.
The miss penalty is the time to replace a block in the upper level with the corresponding block
from the lower level, plus the time to deliver this block to the processor.
PART B (3X10 =30)
11. Construct the MIPS datapath neatly with all the control signals and explain the operation of
branch-on-equal instruction by high lighting the active blocks in that datapath.
For MIPS data path for BEQ with active and non active blocks (5 Marks)
Explanation for deployment of BEQ (5 Marks)
12. What is branch penalty? Explain in detail about the available handling methods to reduce it.
Clock cycles wasted in wrongly fetching subsequent instruction in pipeline before the calculation
of branch address during control hazard is called as branch penalty. (2 Marks)
Methods of handling control hazards with proper explanation (8 Marks)
13. a) Summarize the concept of speculation. (3 Marks)
Speculation definition (1 Mark)
Concept of speculation and it uses (2 Marks)
b) Compare static and dynamic multiple-issue processors. (3 Marks)
Any three points
c) Model the architecture for dynamically scheduled pipeline and explain how dynamic
pipeline scheduling is done? (4 Marks)
For diagram 2 Marks
Explanation for how the dynamic scheduling is done 2 Marks
14. a) Classify the memories based on speed, access time, size, cost, technology and arrange
them in hierarchical order. (4)
Diagram with the above related illustration of various parameters (4 Marks)
b) Given this instruction sequence,
50hex sub $1, $12, $14
54hex and $2, $12, $15
58hex or $3, $12, $16
5Chex add $11, $12, $11
60hex slt $5, $16, $17
64hex lw $6, 50($17)
…
Assume the instructions to be invoked on an exception begin like this:
50000150hex sw $22, 2000($0)
50000154hex sw $23, 2004($0)
….
If an overflow exception occurs in the add instruction, answer the following:
i) Deduct the clock cycle at which the exception will be taken into pipeline (assume
instruction at 50hex address fetched in CC1)?
Cycle 7 ( With calculation) (2 Marks)
ii) Interpret the PC register value during overflow and after exception?
PC Value During overflow 50000150hex (1 Mark)
PC Value after exception 60hex (1 Mark)
iii) What happens in the pipeline registers during exception?
Flushing of instructions after add instruction in the pipeline from the pipeline
registers will happen. (2 Marks)
