1.

The relation CPU Time = (Instruction Count × CPI) / Clock Rate suggests that performance

can be improved by:

a) Increasing instruction count

b) Reducing CPI

c) Reducing clock rate

d) Increasing memory latency

Answer: b) Reducing CPI

2.If a processor has a clock cycle of 2 ns and executes 10⁹ instructions with an average CPI

of 2, the execution time is:

a) 2 seconds

b) 1 second

c) 4 seconds

d) 0.5 seconds

Answer: b) 1 second

8085 8086 Architectures

3.The 8085 microprocessor has how many address lines?

a) 8
 b) 16

c) 20

d) 24

Answer: b) 16

Modern Architectures

4.Which of the following features is most associated with ARM Cortex processors?

a) Complex Instruction Set Computing (CISC)

b) Energy efficiency and RISC design

c) Hyper-threading

d) High transistor count for desktop CPUs

Answer: b) Energy efficiency and RISC design

Instruction Sets, Formats, and Addressing Modes

5.In an instruction format, the opcode field specifies:

a) Location of operand in memory

b) The operation to be performed

c) The address of next instruction

d) The size of the instruction

Answer: b) The operation to be performed

 6.Which addressing mode allows the effective address to be determined by adding a constant

value to the contents of a register?

a) Immediate

b) Direct

c) Indexed

d) Register direct

Answer: c) Indexed

Number Systems

7.The decimal number 255 is represented as in hexadecimal:

a) 11111111

b) 0xFF

c) 0xF0

d) 0xAA

Answer: b) 0xFF

8.If the Program Counter (PC) = 2050H and the instruction stored there is a 2-byte

instruction, after the instruction fetch and decode, the new value of PC will be:

a) 2051H

b) 2052H

c) 2053H

d) 2050H

Answer: b) 2052H
 9.In the 8086 microprocessor, the physical address is calculated as:

a) Segment × 16 + Offset

b) Segment + Offset

c) Segment ÷ 16 + Offset

d) Segment × Offset

Answer: a) Segment × 16 + Offset

10.A CPU executes 10⁶ instructions with an average CPI = 2.5 on a processor with a 2 GHz

clock. The CPU execution time is:

a) 1.25 ms

b) 2.0 ms

c) 0.5 ms

d) 3.25 ms

Answer: a) 1.25 ms

Ii unit

1. 2’s complement addition – BL3 (Apply) – CO3

2. Carry look-ahead vs ripple adder – BL2 (Understand) – CO2

3. Booth’s encoding – BL2 (Understand) – CO2

4. Non-restoring division – BL2 (Understand) – CO2

5. IEEE754 single precision fields – BL1 (Remember) – CO2

 6. IEEE754 double precision bits – BL1 (Remember) – CO2

7. Sign bit of –7.25 – BL3 (Apply) – CO3

8. Instruction execution cycle – BL2 (Understand) – CO2

9. Pipeline throughput – BL2 (Understand) – CO2

10. Booth’s multiplication (–6 × 7) – BL3 (Apply) – CO3

Integer Arithmetic

1. In signed 2’s complement representation, the result of (0101)₂ + (1011)₂ (4-bit numbers)

is:

a) 10000 → 0 (overflow ignored)

b) 0000 → 0

c) 1111 → –1

d) 1001 → –7

Answer: b) 0000 → 0

2. Which of the following is a main advantage of carry look-ahead adders compared to

ripple-carry adders?

a) Lower hardware cost

b) Faster addition by parallel carry computation

c) Requires fewer gates

 d) Simplifies subtraction

Answer: b) Faster addition by parallel carry computation

3. Which of the following sequences represents a Booth’s algorithm encoding for the

multiplier bits?

a) 0 → +M, 1 → –M

b) 00 → no operation, 01 → +M, 10 → –M, 11 → no operation

c) 10 → shift left, 11 → shift right

d) 0 → double, 1 → add

Answer: b) 00 → no operation, 01 → +M, 10 → –M, 11 → no operation

4. The main advantage of non-restoring division over restoring division is:

a) It uses fewer registers

b) It avoids adding back the divisor after negative result

c) It doubles the speed of multiplication

d) It requires fewer shifts

Answer: b) It avoids adding back the divisor after negative result

Floating Point Arithmetic (IEEE 754)

5.In IEEE 754 single precision, the number of bits allocated for exponent and fraction are:

a) 8 and 23

b) 10 and 21

c) 11 and 52
 d) 12 and 51

Answer: a) 8 and 23

6.The IEEE 754 double precision format uses how many total bits?

a) 32

b) 48

c) 64

d) 128

Answer: c) 64

7. The number –7.25 in IEEE 754 single precision will have the sign bit as:

a) 0

b) 1

c) Depends on exponent

d) Cannot be represented

Answer: b) 1

Fundamental Concepts of Processing

8.The correct sequence of instruction execution cycle is:

a) Decode → Fetch → Execute

b) Fetch → Decode → Execute

c) Execute → Decode → Fetch

d) Fetch → Execute → Decode

Answer: b) Fetch → Decode → Execute

 9.A processor with 5 pipeline stages ideally executes one instruction per:

a) 5 cycles

b) 1 cycle after pipeline fill

c) 2 cycles

d) Depends on instruction type

Answer: b) 1 cycle after pipeline fill

10.Using Booth’s algorithm, the multiplication of (–6 × 7) in 4-bit signed binary produces:

a) 00101010 (+42)

b) 11010110 (–42)

c) 11101010 (–22)

d) 00010110 (+22)

Answer: b) 11010110 (–42)

Iii unit

1. ALU operation vs fetch – BL2 (Understand) – CO2

2. ALU control signals – BL3 (Apply) – CO3

3. Pipeline cycle calculation – BL3 (Apply) – CO3

4. Pipeline efficiency with hazards – BL3 (Apply) – CO3

5. Multiple bus advantage – BL2 (Understand) – CO2

6. Control bus role – BL2 (Understand) – CO2

7. Processor throughput (2 ns clock) – BL3 (Apply) – CO3

8. Data hazard type – BL2 (Understand) – CO2

9. Dispatch unit role – BL2 (Understand) – CO2

10. Hyper-threading vs SMT – BL2 (Understand) – CO2

1. Which of the following is NOT an arithmetic and logic unit (ALU) operation?

a) AND

b) OR

c) SHIFT LEFT

d) FETCH

Answer: d) FETCH

2. If the ALU supports (AND, OR, ADD, SUB, XOR, NOT), how many control signals

(min bits) are needed to uniquely select these operations?

a) 2 bits

b) 3 bits

c) 4 bits

d) 6 bits

Answer: b) 3 bits

3. A 5-stage pipeline has stages: IF, ID, EX, MEM, WB. If one instruction takes 5 cycles

without pipelining, how many cycles are needed to execute 10 instructions in pipeline

(ideal case)?

a) 14

b) 15
 c) 19

d) 50

Answer: b) 14

4.If pipeline has CPI = 1, but due to hazards average CPI increases to 1.5, the pipeline efficiency

is:

a) 50%

b) 66%

c) 75%

d) 90%

Answer: b) 66%

Multiple Bus Organization

5.A primary advantage of multiple bus organization over single bus is:

a) Reduced hardware complexity

b) Reduced data transfer conflicts (higher throughput)

c) Requires fewer control lines

d) Eliminates the need for cache memory

Answer: b) Reduced data transfer conflicts (higher throughput)

6.In a three-bus system (instruction, data, and control), the control bus is responsible for:

a) Carrying operands to the ALU

b) Synchronization signals like read/write and clock

c) Transferring addresses
d) Fetching instructions

Answer: b) Synchronization signals like read/write and clock

7.If a processor has a clock cycle of 2 ns and completes one instruction every cycle after

pipeline fill, its throughput is:

a) 0.5 GIPS

b) 1 GIPS

c) 2 GIPS

d) 5 GIPS

Answer: b) 1 GIPS

8.Instruction I1: R1 ← R2 + R3 and I2: R4 ← R1 + R5 causes a hazard. Which type?

a) Structural hazard

b) Data hazard (RAW)

c) Data hazard (WAR)

d) Control hazard

Answer: b) Data hazard (RAW)

9. The dispatch unit in a superscalar processor:

a) Fetches instructions from memory

b) Schedules and sends instructions to appropriate execution units

c) Stores results of execution

d) Performs logical operations

Answer: b) Schedules and sends instructions to appropriate execution units

 10.The difference between Hyper-threading and Simultaneous Multithreading (SMT) is:

a) SMT uses more physical cores

b) Hyper-threading executes one thread per cycle, SMT can execute multiple

c) Hyper-threading is for GPUs, SMT for CPUs

d) SMT eliminates hazards completely

Answer: b) Hyper-threading executes one thread per cycle, SMT can execute multiple

Iv unit

1. Fastest cache – BL1 (Remember) – CO2

2. Memory latency – BL2 (Understand) – CO2

3. DRAM storage principle – BL2 (Understand) – CO2

4. HDD storage principle – BL2 (Understand) – CO2

5. DRAM vs SRAM – BL2 (Understand) – CO2

6. NAND Flash (SSD wear leveling) – BL2 (Understand) – CO2

7. Multi-level cache reason – BL2 (Understand) – CO2

8. Cache misses (sequential array) – BL2 (Understand) – CO2

9. NAND Flash usage – BL1 (Remember) – CO2

10. SSD vs HDD – BL2 (Understand) – CO2

1. The fastest memory type in the cache hierarchy is:

a) L1 cache
 b) L2 cache

c) L3 cache

d) Main memory

Answer: a) L1 cache

Performance Measures

2.Memory latency refers to:

a) Time to transfer one block of data

b) Delay between request and availability of data

c) Number of instructions executed per cycle

d) Maximum data transfer rate

Answer: b) Delay between request and availability of data

Advanced Memory Technologies

3.DRAM stores each bit using:

a) A flip-flop of transistors

b) A capacitor and a transistor

c) Magnetic orientation

d) Optical reflection

Answer: b) A capacitor and a transistor

4.In magnetic storage devices like HDDs, data is stored using:

a) Electric charges

b) Magnetic orientation of particles on a platter

c) Optical reflection of light

d) Semiconductor gates

Answer: b) Magnetic orientation of particles on a platter

5.Which of the following is true?

a) DRAM is faster but consumes more power than SRAM.

b) SRAM is used in main memory; DRAM in cache.

c) DRAM requires refresh; SRAM does not.

d) Both SRAM and DRAM are non-volatile.

Answer: c) DRAM requires refresh; SRAM does not.

6.Which statement is most accurate regarding NAND Flash in SSDs?

a) NAND Flash allows unlimited write cycles.

b) SSDs use wear leveling to extend NAND lifetime.

c) NAND Flash is volatile memory.

d) NAND Flash has faster writes than DRAM.

Answer: b) SSDs use wear leveling to extend NAND lifetime.

7.Which of the following best explains why modern CPUs use multiple levels of cache (L1,

L2, L3)?

a) To reduce manufacturing cost.

b) To balance speed, size, and power efficiency.

c) To avoid virtual memory usage.

d) To replace main memory entirely.

Answer: b) To balance speed, size, and power efficiency.

 8. A program repeatedly accesses a large array sequentially. Most of the cache misses

observed are:

a) Conflict misses

b) Compulsory misses

c) Capacity misses

d) Coherence misses

Answer: b) Compulsory misses

9. NAND Flash memory is commonly used in:

a) Magnetic tapes

b) Hard disk drives

c) Solid State Drives (SSDs)

d) Optical disks

Answer: c) Solid State Drives (SSDs)

10.A key advantage of SSDs over HDDs is:

a) Lower cost per GB

b) Higher durability and faster access time

c) Infinite write endurance

d) Larger storage capacity in all cases

Answer: b) Higher durability and faster access time

V unit

1. Software interrupts – BL2 (Understand) – CO2

2. Memory-mapped I/O vs I/O mapped – BL2 (Understand) – CO2

3. Vectored interrupt – BL2 (Understand) – CO2

4. PCI interrupts – BL2 (Understand) – CO2

5. Pipeline interrupt effect – BL2 (Understand) – CO2

6. Exceptions vs traps – BL2 (Understand) – CO2

7. Cycle stealing DMA – BL2 (Understand) – CO2

8. Bus arbitration – BL2 (Understand) – CO2

9. USB communication – BL2 (Understand) – CO2

10. DMA vs CPU transfer – BL2 (Understand) – CO2

1. Which of the following is true about software interrupts?

a) Triggered by external devices

b) Generated by executing a special instruction (e.g., INT in x86)

c) Cannot be disabled

d) Always vectored

Answer: b) Generated by executing a special instruction (e.g., INT in x86)

2. Which of the following is true for memory-mapped I/O but not for I/O-mapped I/O?

a) Uses separate control lines for I/O operations.

b) Allows the same instruction set for accessing both memory and I/O.

c) Provides a smaller address space for I/O devices.

 d) Needs special I/O instructions like IN and OUT.

Answer: b) Allows the same instruction set for accessing both memory and I/O.

Interrupt Handling

3.A vectored interrupt means:

a) Interrupts have no priority

b) The processor automatically jumps to a predefined address for the ISR

c) Interrupt vector table gives ISR addresses

d) All interrupts share the same ISR

Answer: c) Interrupt vector table gives ISR addresses

4.PCI interrupts are typically handled using:

a) Edge-triggered signals only

b) Level-triggered signals (shared interrupts)

c) Software polling

d) Non-maskable instructions

Answer: b) Level-triggered signals (shared interrupts)

5. A pipeline interrupt may cause:

a) Stalling and flushing of pipeline stages

b) Faster execution of instructions

c) Disabling of cache memory

 d) Memory fragmentation

Answer: a) Stalling and flushing of pipeline stages

6. Exceptions differ from traps because:

a) Exceptions are intentional, traps are unintentional

b) Traps are synchronous, exceptions are asynchronous

c) Exceptions are unplanned events like divide-by-zero, traps are intentional like system

calls

d) Both are identical terms

Answer: c) Exceptions are unplanned events like divide-by-zero, traps are intentional like

system calls

7.In cycle stealing DMA, the DMA controller:

a) Steals CPU registers

b) Suspends CPU operations and transfers a word of data

c) Transfers data only after CPU finishes a program

d) Uses cache memory for data movement

Answer: b) Suspends CPU operations and transfers a word of data

Bus Architecture

8.Bus arbitration is required when:

a) Multiple devices compete for bus access

b) Only one device uses the bus

c) Memory is directly mapped

d) CPU executes non-pipelined instructions

Answer: a) Multiple devices compete for bus access

9.USB uses which type of communication method?

a) Parallel, asynchronous

b) Serial, synchronous or asynchronous

c) Parallel, synchronous

d) Optical signaling only

Answer: b) Serial, synchronous or asynchronous

10.Compared to CPU-based data transfer, DMA improves performance mainly because:

a) DMA uses more powerful instructions.

b) DMA allows parallel data transfer without involving CPU cycles.

c) DMA executes faster than CPU.

d) DMA has its own cache memory.

Answer: b) DMA allows parallel data transfer without involving CPU cycles.