1.1.

10 Pin Descriptions of STC15F2K60S2 series MCU

Pin Number
MNEMONIC SOP28 DESCRIPTION
LQFP44 PLCC44PDIP40 SOP32 LQFP32 TSSOP20
SKDIP28
P0.0/AD0 40 2 1 1 29 - P0.0 common I/O port PORT0[0]
P0.1/AD1 41 3 2 2 30 - P0.1 common I/O port PORT0[1]
P0.2/AD2 42 4 3 3 31 - P0.2 common I/O port PORT0[2]
P0.3/AD3 43 5 4 4 32 - P0.3 common I/O port PORT0[3]
P0.4/AD4 44 6 5 - - - P0.4 common I/O port PORT0[4]
P0.5/AD5 1 7 6 - - - P0.5 common I/O port PORT0[5]
P0.6/AD5 2 8 7 - - - common I/O port PORT0[6]
P0.7/AD7 3 9 8 - - - common I/O port PORT0[7]
P1.0 common I/O port PORT1[0]
ADC0 ADC input channel-0

P1.0/ADC0/ Capture of external signal(measure

4 10 9 5 1 3 1 frequency or be used as external
CCP1/RxD2 CCP1
interrupts) high-speed Pulse and Pulse-
Width Modulation output channel-1
RxD2 Receive Data Port of UART2
P1.1 common I/O port PORT1[1]
ADC1 ADC input channel-1

P1.1/ADC1/ Capture of external signal(measure

5 11 10 6 2 4 2 frequency or be used as external
CCP0/TxD2 CCP0
interrupts) high-speed Pulse and Pulse-
Width Modulation output channel-0
TxD2 Transit Data Port of UART2
P1.2 common I/O port PORT1[2]
ADC2 ADC input channel-2
P1.2/ADC2/SS/ Slave selection signal of synchronous
7 13 11 7 3 5 20 SS
ECI serial peripheral interface----SPI
External pulse input pin of CCP/PCA
ECI
counter
P1.3 common I/O port PORT1[3]
P1.3/ADC3/
8 14 12 8 4 6 19 ADC3 ADC input channel-3
MOSI
MOSI Master Output Slave Input of SPI
P1.4 common I/O port PORT1[4]
P1.4/ADC4/
9 15 13 9 5 7 3 ADC4 ADC input channel-4
MISO
MISO Master Iutput Slave Onput of SPI
P1.5 common I/O port PORT1[5]
P1.5/ADC5/ ADC5 ADC input channel-5
10 16 14 10 6 8 4
SCLK Clock Signal of synchronous serial
SCLK
peripheral interface----SPI
 Pin Number
MNEMONIC SOP28 DESCRIPTION
LQFP44 PLCC44 PDIP40 SOP32 LQFP32 TSSOP20
SKDIP28
P1.6 common I/O port PORT1[6]
ADC6 ADC input channel--6
P1.6/ADC6/ RxD_3 Receive Data Port of UART1
11 17 15 11 7 9 5
RxD_3/XTAL2 Output from the inverting amplifier
of internal clock circuit. This pin
XTAL2
should be floated when an external
oscillator is used.
P1.7 common I/O port PORT1[7]
ADC7 ADC input channel--7
TxD_3 Transit Data Port of UART1
P1.7/ADC7/
12 18 16 12 8 10 6 Input to the inverting oscillator
TxD_3/XTAL1
amplifier of internal clock circuit.
XTAL1 Receives the external oscillator
signal when an external oscillator
is used.
P2.0 common I/O port PORT2[0]
P2.0/ the pin output low after power-on
30 36 32 25 21 23
RSTOUT_LOW RSTOUT_LOW and during reset, which can be set
to output high by software
P2.1 common I/O port PORT2[1]
P2.1/SCLK_2 31 37 33 26 22 24 Clock Signal of synchronous serial
SCLK_2
peripheral interface----SPI
P2.2 common I/O port PORT2[2]
P2.2/MISO_2 32 38 34 27 23 25
MISO_2 Master Iutput Slave Onput of SPI
P2.3 common I/O port PORT2[3]
P2.3/MOSI_2 33 39 35 28 24 26
MOSI_2 Master Output Slave Input of SPI
P2.4 common I/O port PORT2[4]
External pulse input pin of CCP/
ECI_3
P2.4/ECI_3/ PCA counter
34 40 36 29 25 27
SS_2 Slave selection signal of
SS_2 synchronous serial peripheral
interface----SPI
P2.5 common I/O port PORT2[5]
Capture of external signal(measure
P2.5/CCP0_3 35 41 37 30 26 28 frequency or be used as external
CCP0_3 interrupts) high-speed Pulse and
Pulse-Width Modulation output
channel-0
P2.6 common I/O port PORT2[6]
Capture of external signal(measure
P2.6/CCP1_3 42 38 31 27 1 frequency or be used as external
CCP1_3 interrupts) high-speed Pulse and
Pulse-Width Modulation output
channel-1
 Pin Number
MNEMONIC SOP28 DESCRIPTION
LQFP44 PLCC44 PDIP40 SOP32 LQFP32 TSSOP20
SKDIP28
P2.7 common I/O port PORT2[7]
Capture of external signal(measure
P2.7/CCP2_3 37 43 39 32 28 2 frequency or be used as external
CCP2_3
interrupts) high-speed Pulse and Pulse-
Width Modulation output channel-2
P3.0 common I/O port PORT3[0]
RxD Receive Data Port of UART1
P3.0/RxD/ External interrupt 4, which only can be
INT4 18 24 21 17 13 15 11 INT4 generated on falling edge.
/INT4 supports power-down waking-up
/T2CLKO
T2 Clock Output
T2CLKO The pin can be configured for T2CLKO
by setting INT_CLKO[2] bit /T2CLKO
P3.1 common I/O port PORT3[1]
P3.1/TxD/T2 19 25 22 18 14 16 12 TxD Transit Data Port of UART1
T2 External input of Timer/Counter 2
P3.2 common I/O port PORT3[2]
External interrupt 0, which both can be
generated on rising and falling edge.
INT0 only can generate interrupt on
P3.2/INT0 20 26 23 19 15 17 13
INT0 falling edge if IT0 (TCON.0) is set
to 1. And, INT0 both can generate
interrupt on rising and falling edge if IT0
(TCON.0) is set to 0.
P3.3 common I/O port PORT3[3]
External interrupt 1, which both can be
generated on rising and falling edge.
INT1 only can generate interrupt on
P3.3/INT1 21 27 24 20 16 18 18 falling edge if IT1 (TCON.2) is set
INT1
to 1. And, INT1 both can generate
interrupt on rising and falling edge if IT1
(TCON.2) is set to 0.
INT1 supports power-down waking-up
P3.4 common I/O port PORT3[4]
T0 External input of Timer/Counter 0
P3.4/T0/ T1 Clock Output
T1CLKO/ 22 28 25 21 17 19 14 T1CLKO The pin can be configured for T1CLKO
ECI_2 by setting INT_CLKO[1] bit /T1CLKO
External pulse input pin of CCP/PCA
ECI_2
counter
P3.5 common I/O port PORT3[5]
T1 External input of Timer/Counter 1
T0 Clock Output
P3.5/T1/ T0CLKO The pin can be configured for T0CLKO
T0CLKO/ 23 29 26 22 18 20 15 by setting INT_CLKO[0] bit /T0CLKO
CCP0_2 Capture of external signal(measure
frequency or be used as external
CCP0_2
interrupts) high-speed Pulse and Pulse-
Width Modulation output channel-0
 Pin Number
MNEMONIC SOP28 DESCRIPTION
LQFP44 PLCC44 PDIP40 SOP32 LQFP32 TSSOP20
SKDIP28
P3.6 common I/O port PORT3[6]
External interrupt 2, which only can be
INT2 generated on falling edge.
P3.6/INT2 /INT2 supports power-down waking-up
/RxD_2/ 24 30 27 23 19 21 16 RxD_2 Receive Data Port of UART1
CCP1_2
Capture of external signal(measure
frequency or be used as external
CCP1_2
interrupts) high-speed Pulse and Pulse-
Width Modulation output channel-1
P3.7 common I/O port PORT3[7]
External interrupt 3, which only can be
INT3 generated on falling edge.
/INT3 supports power-down waking-up
TxD_2 Transit Data Port of UART1
P3.7/INT3 Capture of external signal(measure
/TxD_2/CCP2/ 25 31 28 24 20 22 17
frequency or be used as external
CCP2_2 CCP2
interrupts) high-speed Pulse and Pulse-
Width Modulation output channel-2
Capture of external signal(measure
frequency or be used as external
CCP2_2
interrupts) high-speed Pulse and Pulse-
Width Modulation output channel-2
P4.0 common I/O port PORT4[0]
P4.0/MOSI_3 17 23 - - - -
MISO_3 Master Iutput Slave Onput of SPI
P4.1 common I/O port PORT4[1]
P4.1/MISO_3 26 32 29 - - -
MOSI_3 Master Output Slave Input of SPI
P4.2 common I/O port PORT4[2]
P4.2/WR 27 33 30 - - -
WR Write pulse of external data memory
P4.3 PORT4[3]
P4.3/SCLK_3 28 34 - - - - Clock Signal of synchronous serial
SCLK_3
peripheral interface----SPI
P4.4 common I/O port PORT4[4]
P4.4/RD 29 35 31 - - -
RD Read pulse of external data memory
P4.5 common I/O port PORT4[5]
P4.5/ALE 38 44 40 - - - Address Latch Enable. It is used for
ALE
external data memory cycles (MOVX)
P4.6 common I/O port PORT4[6]
P4.6/RxD2_2 39 1 - - - -
RxD2_2 Receive Data Port of UART2
P4.7 common I/O port PORT4[7]
P4.7/TxD2_2 6 12 - - - -
TxD2_2 Transit Data Port of UART2
 Pin Number
MNEMONIC SOP28 DESCRIPTION
LQFP44 PLCC44 PDIP40 SOP32 LQFP32 TSSOP20
SKDIP28
P5.4 common I/O port PORT5[4]
Reset pin.
A high on this pin for at least
RST
two machine cycles will reset
the device.
Master clock output; the
output frequency can be
P5.4/RST/ MCLK/1, MCLK/2 and
13 19 17 13 9 11 7
MCLKO/SS_3 MCLK/4.
MCLKO
The master clock can either
be internal R/C clock or the
external input clock or the
external crystal oscillator.
Slave selection signal of
SS_3 synchronous serial peripheral
interface----SPI
P5.5 15 21 19 15 11 13 9 common I/O port PORT5[5]
Vcc 14 20 18 14 10 12 8 The positive pole of power
Gnd 16 22 20 16 12 14 10 The negative pole of power, Gound