High Level Verification with SystemVerilog SV Datatype
SV Datatype Lab Exercise
Lab 9: Typedef and Structures
Abhishek Kumar Singh | EVD18I031
Problem Statement
1. Define a user defined 7 bit type
2. Encapsulate the fields of the following packet in a structure using your new type
3. Assign the header to 7’h5A
4. Print entire packet
Goal: Write SV code, simulate and verify manually. Submit your SV code and log
Solution
Except for the header, all other components of the packet are zero, as they are
constructed from a new data type which is built on bit data type.
Simulation
module structype();
typedef bit [6:0] newtype;
typedef struct {
newtype header;
newtype cmd;
newtype data;
1
High Level Verification with SystemVerilog SV Datatype
newtype crc;
} newstruct;
newstruct newpacket;
initial begin
newpacket.header = 7'h5A;
$display("newpacket = %x %x %x %x ", newpacket.header,
newpacket.cmd, newpacket.data, newpacket.crc);
end
endmodule
Log:
[2022-03-31 06:54:57 UTC] xrun -Q -unbuffered '-timescale' '1ns/1ns' '-sysv' '-access'
'+rw' design.sv testbench.sv
TOOL: xrun 20.09-s003: Started on Mar 31, 2022 at 02:54:58 EDT
xrun: 20.09-s003: (c) Copyright 1995-2020 Cadence Design Systems, Inc.
Top level design units:
structype
xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009
SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV
2009 simulation semantics.
Loading snapshot worklib.structype:sv .................... Done
xmsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009
SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV
2009 simulation semantics.
xcelium> source /xcelium20.09/tools/xcelium/files/xmsimrc
xcelium> run
newpacket = 5a 00 00 00
xmsim: *W,RNQUIE: Simulation is complete.
xcelium> exit
TOOL: xrun 20.09-s003: Exiting on Mar 31, 2022 at 02:54:59 EDT (total: 00:00:01)
Done
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