4.
SPICE LEVEL 1 MOSFET MODEL
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Four mask layout and cross section of a N channel MOS Transistor.
4: MOSFET Model
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Layout and cross section of a n-well CMOS technology.
4: MOSFET Model
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Equations for the different operation regions
I DS = 0
I DS = KP (W Leff )VDS [2(VGS VTH ) VDS ](1 + LAMBDA VDS ) 2
(VGS VTH )
(0 VDS VGS VTH )
I DS =
KP (W Leff )(VGS VTH )2 (1 + LAMBDA VDS ) 2
(0 VGS VTH VDS )
Where the threshold voltage is given by:
VTH = VT 0 + GAMMA 2 PHI VBS 2 PHI
and the channel length:
Leff = L 2 LD
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4: MOSFET Model
Where L is the length of the polysilicon gate and LD is the gate overlap of the source and drain. The elements in the large signal MOSFET model are shown in the following figure.
4: MOSFET Model
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MOSFET SPICE PARAMETERS.
Parameter Name Channel length SPICE Symbol Leff Analytical Symbol L Units M
Poly gate length Lateral diffusion/ Gate-source overlap Transconductance parameter Threshold voltage/ Zero-bias threshold Channel-length modulation parameter Bulk threshold/ Backgate effect parameter Surface potential/ Depletion drop in inversion
Lgate
LD
LD nCOX VTO n n
M A/V2
KP
VTO
V V-1 V1/2
LAMBDA
GAMMA
PHI
-P
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4: MOSFET Model
Specifying MOSFET Geometry in SPICE.
Mname D G S B MODname L= W= AD= AS= PD= PS= NRD= NRS=
4: MOSFET Model
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LEVEL 1 MOSFET MODEL PARAMETERS.
.MODEL MODname NMOS/PMOS VTO= KP= GAMMA= PHI= LAMBDA= RD= RS= RSH= CBD= CBS= CJ= MJ= CJSW= MJSW= PB= IS= CGDO= CGSO= CGBO= TOX= LD= where: NMOS/PMOS- MOSFET type. VTO- Threshold voltage (V) KP- Transconductance parameter (A/V2) GAMMA- Bulk threshold parameter (V1/2) PHI- Surface potential (V) LAMBDA- Channel length modulation parameter (V-1) RD- Drain resistance ()
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4: MOSFET Model
LEVEL 1 MOSFET MODEL PARAMETERS.
RS- Source resistance () RSH- Sheet resistance of the drain/source diffusions (/ ) CBD- Zero bias drain-bulk junction capacitance (F) CBS- Zero bias source-bulk junction capacitance (F) MJ- Bulk junction grading coefficient (dimensionless) PB- Built-in potential for the bulk junction (V) With CBD, CBS, MJ and PB, SPICE computes the voltage dependences of the drain-bulk and source-bulk capacitances:
C BD (VBD ) = CBD (1 VBD PB )MJ
C BS (VBS ) = CBS (1 VBS PB )MJ
4: MOSFET Model
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Large-signal, charge-storage capacitors of the MOS device.
4: MOSFET Model
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LEVEL 1 MOSFET MODEL PARAMETERS.
CJ- Zero bias planar bulk junction capacitance (F/m2) CJSW- Zero bias sidewall bulk junction capacitance (F/m) MJSW- Sidewall junction grading coefficient (dimensionless) If CJ, CJSW, and MJSW are given, a more accurated simulation of these capacitances is performed using the following equations:
C BD (VBD ) =
CJ AD CJSW PD + MJ (1 VBD PB ) (1 VBD PB )MJSW CJ AS CJSW PS + MJ (1 VBS PB ) (1 VBS PB )MJSW
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C BS (VBS ) =
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Bottom and Sidewall components of the bulk junction capacitors.
Bottom=ABCD Sidewall=ABEF+BCFG+DCGH+ADEH
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LEVEL 1 MOSFET MODEL PARAMETERS.
IS- Saturation current of the junction diode (A) CGDO- Overlap capacitance of the gate with drain (F) CGSO- Overlap capacitance of the gate with source (F) CGBO- Overlap capacitance of the gate with bulk (F) TOX- Gate oxide thickness (m) LD- Lateral diffusion (m)
4: MOSFET Model
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Overlap Capacitances of an MOS transistor.
(a) Top view showing the overlap between the source or drain and the gate. (b) Side view.
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Example of MOSFET model parameters values.
Parameter Name Gate oxide thickness TOX Transconductance parameter KP N Channel MOSFET 150 50 x 10-6 P Channel MOSFET 150 25 x 10-6 Units Angstroms A/V2
Threshold voltage Channel-length modulation parameter LAMBDA Bulk threshold parameter GAMMA
1.0 0.1/L (L in m)
-1.0 0.1/L (L in m)
V V-1
0.6
0.6
V1/2
Surface potential PHI Gate-Drain overlap capacitance. CGDO Gate-Source overlap capacitance. CGSO Zero-bias planar bulk depeltion capacitance CJ Zero-bias sidewall bulk depletion capacitance CJSW Bulk junction potential PB Planar bulk junction grading coefficient MJ Sidewall bulk junction grading coefficient MJSW
0.8 5 x 10-10 5 x 10-10 10-4 5 x 10-10
0.8 5 x 10-10 5 x 10-10 3 x 10-4 3.5 x 10-10
F/m
F/m F/m2
F/m
0.95
0.95
0.5
0.5
0.33
0.33
4: MOSFET Model
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