Synopsys TestMAX™ Manager User

Guide
Version T-2022.03, March 2022
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Contents
New in This Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Related Products, Publications, and Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1. Understanding Synopsys TestMAX™ Manager . . . . . . . . . . . . . . . . . . . . . . . . . . 11

TestMAX Manager Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2. Working With the TestMAX Manager Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Configuring the TestMAX Manager Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Using the User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3. Preparing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Defining the Search Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Setting Up Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Reading the RTL Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Reading System Verilog Files and Designs Containing Multiple HDL Files and
Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Prerequisite to Modifying a RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Modifying the RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Validating the Modified Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Preventing the Creation of Intermediate Hierarchy Objects in the RTL . . . . . . . . . . 26
Example: Preparing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Overview of Basic DFT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Configuring DFT in the TestMAX Manager Tool . . . . . . . . . . . . . . . . . . . . . . . . .29
Defining the Scan Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Defining Test Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Identifying Weighted Clock Groups for XLBIST . . . . . . . . . . . . . . . . . . . . . . 32
Example: Configuring Weighted Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

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Isolating Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Specifying a Location for the DFT Logic Insertion . . . . . . . . . . . . . . . . . . . . . . . 34
Passing Options to TestMAX Advisor Using Template-based Flow . . . . . . . . . . . . . 35
Overview of RTL Test Point Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Running RTL Test Point Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Comparison of the set_testability_configuration Command Options . . . . . . . . . 38
Checking the Design for Scan Readiness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Creating the Test Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4. The TestMAX Manager DFT Insertion Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Generating the DFT IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Fusion Compiler In-Compile Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Connecting DFT IP to RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Checking Unsupported Constructs in the Input RTL . . . . . . . . . . . . . . . . . . . . . 49
Defining the Format of SpyGlass Design Constraints . . . . . . . . . . . . . . . . . . . . 50
Connecting DFT IP to the Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Connecting DFT IP to Netlist Using TestMAX Manager With DFTMAX
Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Validating the Connections Made Within the IP to the RTL . . . . . . . . . . . . . . . . . . . 52
Identifying Existing Ports When Integrating the Core-Level to the SoC-Level . . . . . 53
Writing Out the Test Protocol and Test Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Writing the Constraints File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Synthesis of DFT IP and Scan Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Generating SDC Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5. Hierarchical Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Hierarchical Adaptive Scan Synthesis (HASS) flow . . . . . . . . . . . . . . . . . . . . . . . . . 58
Integrating the HASS Flows of Compressed Scan Cores . . . . . . . . . . . . . . . . . . . . 59
Integrating the Hybrid Flow at the Top Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Performing Top Level Hybrid Integration With Partitions . . . . . . . . . . . . . . . . . . . . . 60
Using Multiple Test Modes in Hierarchical Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Connecting the Shift Power Control Disable Signal to the Core Block . . . . . . . . . . . 60
Limitations of the Integration of Hierarchical Flows With the TestMAX Manager
Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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6. On-Chip Clocking (OCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Clock Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
OCC Controller Structure and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
OCC Controller Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Clock Chain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Enabling On-Chip Clocking Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Inserting an On-Chip Clock Controller at the Top Level . . . . . . . . . . . . . . . . . . . 65
Retaining the Delay Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Specifying the DFT-Inserted On-Chip Clock Controller . . . . . . . . . . . . . . . . . . . . . . 66
Defining Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
ATE Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PLL-Generated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Defining Global Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Configuring the OCC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
On-Chip Clock Controller Configuration Options . . . . . . . . . . . . . . . . . . . . . 69
Generating Synchronised Output Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Enabling the Synchronised Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . 71
Configuring the Clock Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Handling Long Clock Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Configuring the Clock-Chain Clock Connection . . . . . . . . . . . . . . . . . . . . . . 72
Defining Integrated Clock-Gating Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
On-Chip Clock Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7. TestMAX Manager-Based DFTMAX/DFTMAX Ultra Compression Insertion . . . 76

Configuring DFTMAX Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Scan Compression and On-Chip Clocking Controllers . . . . . . . . . . . . . . . . . . . .77
Defining External Clock Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Configuring DFTMAX Ultra Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Configuring Multiple Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Defining Multiple Configurations in the TestMAX Manager Tool . . . . . . . . . 83
Defining Multiple Configurations in TestMAX ATPG . . . . . . . . . . . . . . . . . . .84
Using On-Chip Clock Controllers With DFTMAX Ultra Compression . . . . . . . . . 85
Reducing Scan Shift Power Using Shift Power Groups . . . . . . . . . . . . . . . . . . . 85
Sharing Codec Scan I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Specifying the I/O Sharing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

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Codec I/O Sharing With Identical Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Sharing Codec Inputs With Dedicated Codec Outputs With Identical Cores . . . 88
Sharing Codec Inputs With Dedicated Codec Outputs With Non-identical
Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Verifying the DFT IP at RTL Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Generating Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Generating Verilog Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

8. Pipelined Scan Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Configuring Pipelined Scan Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Adding Pipelines Before and After MUX From the Top-Level . . . . . . . . . . . . . . . . . .95

9. Advanced DFT Architecture Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Multiple Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Defining Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Defining the Usage of a Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Defining the Encoding of a Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Internal Pins Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Core Wrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Dedicated Core Wrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Shared Core Wrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Compressing Wrapper Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
IEEE 1500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

10. Limitations of the TestMAX Manager Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Unsupported RTL Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

A. Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Flow From TestMAX Manager to Synthesis, Generating Patterns, and Simulating
Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
TestMAX ATPG for DRC and ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Formal Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

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Supported GenSys Commands and Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

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About This User Guide

The TestMAX Manager User Guide describes the process for inserting compressed scan
and self-test logic into a design. You can synthesize your design and then generate test
patterns for these designs with the Synopsys® TestMAX™ ATPG tool.
This preface includes the following sections:
• New in This Release
• Related Products, Publications, and Trademarks
• Conventions
• Customer Support

New in This Release

Information about new features, enhancements, and changes, known limitations, and
resolved Synopsys Technical Action Requests (STARs) is available in the TestMAX
Manager Release Notes on the SolvNetPlus site.

Related Products, Publications, and Trademarks

For additional information about the TestMAX Manager tool, see the documentation on the
Synopsys SolvNetPlus support site at the following address:
https://solvnetplus.synopsys.com
You might also want to see the documentation for the following related Synopsys products:
• TestMAX DFT
• TestMAX XLBIST
• TestMAX SMS
• TestMAX Access
• Design Compiler®
• GenSys®

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About This User Guide
Conventions

Conventions
The following conventions are used in Synopsys documentation.

Convention Description

Courier Indicates syntax, such as write_file.

Courier italic Indicates a user-defined value in syntax, such as

write_file design_list

Courier bold Indicates user input—text you type verbatim—in examples, such
as
prompt> write_file top

Purple • Within an example, indicates information of special interest.

• Within a command-syntax section, indicates a default, such as
include_enclosing = true | false

[] Denotes optional arguments in syntax, such as

write_file [-format fmt]

... Indicates that arguments can be repeated as many times as

needed, such as
pin1 pin2 ... pinN.

| Indicates a choice among alternatives, such as

low | medium | high

\ Indicates a continuation of a command line.

/ Indicates levels of directory structure.

Bold Indicates a graphical user interface (GUI) element that has an

action associated with it.

Edit > Copy Indicates a path to a menu command, such as opening the Edit
menu and choosing Copy.

Ctrl+C Indicates a keyboard combination, such as holding down the Ctrl

key and pressing C.

Customer Support
Customer support is available through SolvNetPlus.

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About This User Guide
Customer Support

Accessing SolvNetPlus
The SolvNetPlus site includes a knowledge base of technical articles and answers to
frequently asked questions about Synopsys tools. The SolvNetPlus site also gives you
access to a wide range of Synopsys online services including software downloads,
documentation, and technical support.
To access the SolvNetPlus site, go to the following address:
https://solvnetplus.synopsys.com
If prompted, enter your user name and password. If you do not have a Synopsys user
name and password, follow the instructions to sign up for an account.
If you need help using the SolvNetPlus site, click REGISTRATION HELP in the top-right
menu bar.

Contacting Customer Support

To contact Customer Support, go to https://solvnetplus.synopsys.com.

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1
Understanding Synopsys TestMAX™ Manager
The Synopsys TestMAX™ Manager tool provides a common interface for DFT
implementation capabilities. Inserting DFT features at the RTL stage accelerates the
validation of DFT with the design and it provides faster turnaround time before the physical
design stage.
The tool generates the RTL for compression technologies such as DFTMAX and DFTMAX
Ultra compression, and self-test logic such as XLBIST and MBIST. The tool also supports
on-chip clocking (OCC), shift power control (SPC), and core wrapping logic. The tool then
connects the generated RTL to the functional RTL.
It provides lint checks, connectivity checks, and rule checks in addition to those performed
by the TestMAX Advisor and TestMAX ATPG tools. You can perform verification at the
RTL level because the tool can generate testbenches that can be simulated. The tool also
generates constraints for downstream processes.
This chapter includes the following topics:
• TestMAX Manager Design Flow
• Licensing

TestMAX Manager Design Flow

The main flow takes the RTL and generates the DFT IP and protocol files. The TestMAX
Manager tool generates new Verilog files with the DFT IP instantiated in the RTL files,
which is taken into synthesis. You can use the constraints generated from the tool to
synthesize the design in the Design Compiler or Fusion Compiler tool, connect the
scan chains created by the synthesis tools to the DFT compression IP, and then write
out the scan-inserted netlist. The DFT IP present in the RTL helps improve congestion
optimization and timing closure.

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Chapter 1: Understanding Synopsys TestMAX™ Manager
TestMAX Manager Design Flow

Figure 1 Basic TestMAX Manager Design Flow

You can use the following commands in the design flow:

For information about getting started with the TestMAX Manager tool, see Configuring the
TestMAX Manager Tool.
• create_lib - Sets up the libraries.

• set_top_module - Reads the design.

• check_dft - Checks the RTL design for lint and scan readiness.

• plan_dft - Generates the memory grouping information. For more information about
using the plan_dft command, refer to the TestMAX SMS User Guide.

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Chapter 1: Understanding Synopsys TestMAX™ Manager
TestMAX Manager Design Flow

• modify_rtl - (Optional) Modifies the RTL design.

• generate_dft - Generates the DFT IP based on the constraints and the specified
configuration.
• connect_dft - Connects the DFT IP to the RTL.

• validate_dft - Performs lint and rule checking on the IP and the connections of
the IP to the RTL. It performs structural and connectivity verification of memory BIST
components and infrastructure. It also performs simulation-based checks to validate
the complete memory BIST system.

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Chapter 1: Understanding Synopsys TestMAX™ Manager
TestMAX Manager Design Flow

The following figure shows the overall TestMAX Manager design flow:

Figure 2 Overall TestMAX Manager Design Flow

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Chapter 1: Understanding Synopsys TestMAX™ Manager
Licensing

The following are the steps for the TestMAX Manager design flow:
1. Set up the libraries.
2. Read the design and handle black boxes.
3. Check the RTL design for lint and scan readiness.
4. Set up DFT constraints and generate DFT structures.
5. Connect and insert the DFT structures into the RTL.
6. Ensure the connections and the IP RTL are correct.
7. Export the SPF, CTL, constraints, and SDC.
The synthesized netlist and the protocol files are imported to the TestMAX ATPG tool for
DRC and pattern generation. The patterns generated can then be verified in a simulator
such as the Verilog Compiler and Simulator® tool.

Licensing
You need the Test-Platform-RTL license to invoke the tool. A copy of the Test-
Platform-RTL license is checked out upon invocation and cannot be released until you
exit the tool.
Additionally, the following product licenses are required to use the TestMAX Manager tool:
• TestMAX Advisor – Licenses from this product are checked out when you execute the
plan_dft, check_dft, or validate_dft commands.

• TestMAX SMS – Licenses from this product are checked out and required when you
enable the Memory BIST flow.
• TestMAX XLBIST – Licenses from this product are checked out and required when you
enable the XLBIST flow.
• TestMAX Access – Licenses from this product are checked out and required when you
enable the hierarchical flow when using SMS or XLBIST.
• TestMAX DFT – Licenses from this product are checked out when you enable
DFTMAX, DFTMAX Ultra, or core wrapping.
• TestMAX ATPG – Licenses from this product are checked out during RTL validation
and pattern porting.
• VCS and VCS MX – Enables BIST simulation.

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Licensing

Note:
The TestMAX Manager tool supports a single thread only. Multicore is not
enabled in the TestMAX Manager tool. Therefore, the tool checks out one
Test-Platform-RTL license.

Set the following license variables during the invocation of the tool:
• setenv SNPSLMD_LICENSE_FILE - Specifies the license server hosting the Test-
Platform-RTL license.

• setenv SPYGLASS_ENABLE_LICENSE_QUEUE 1 - Enables queuing for SpyGlass. You

can override the default values using this variable. The values are set to 24000 and 10
respectively in the default setup file.
• setenv EMBEDIT_LICENSE_WAIT TRUE | 1 - Enables the licensing queue for
EmbedIT tools.
• setenv SNPSLMD_QUEUE true - Enable the environment variable to adjust the
SNPS_MAX_WAITTIME <> and SNPS_MAX_WAITTIME timeouts.

• setenv SNPS_MAX_WAITTIME - Specifies the maximum wait time for the first key
license that you require.
• setenv SNPS_MAX_QUEUETIME - Specifies the maximum wait time for checking out
subsequent licenses in the same shell.

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2
Working With the TestMAX Manager Tool
You can access the TestMAX Manager tool using a command-line interface called
dft_shell.
Using Tcl, you can extend the dft_shell command set by writing reusable procedures and
scripts. For more information, see the Using Tcl With Synopsys Tools manual.
• To start the command-line interface, see Using the User Interface.
• To exit the tool, use the exit or quit command.
This chapter includes the following topics:
• Configuring the TestMAX Manager Tool
• Using the User Interface

Configuring the TestMAX Manager Tool

To use the TestMAX Manager tool as an interface for the DFT implementation capabilities,
perform the following steps:
• Install the TestMAX Manager tool.
To perform the installation, see the TestMAX Tools Installation Guide.
• Set the SNPSLMD_LICENSE_FILE environment variable to the license server hosting the
Test-Platform-RTL license.

• Run the dft_shell invocation command to invoke the tool.

The dft_output.txt log file is generated in the current working directory when you run the
tool.

Using the User Interface

The command-line interface allows you to enter the commands at the command line
prompt.

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Chapter 2: Working With the TestMAX Manager Tool
Using the User Interface

Before you start the TestMAX Manager tool, ensure that the path to the bin directory is
included in the $PATH environment variable.
To start the TestMAX Manager tool, enter the tool invocation command at the Linux shell.
% dft_shell
If you specify the command with the -file filename option, it executes the specified script
file.
At startup, the dft_shell command performs the following tasks:
• Displays the program header and the dft_shell tool prompt.
• Executes any script files or commands specified by the -file options.
Running the TestMAX Manager tool generates the following files in the current directory:
• dft_command.log – List of commands executed
• dft_output.txt – Log file that captures the commands and output

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3
Preparing the Design
The TestMAX Manager tool uses a design library to store the design and its associated
library information. This chapter describes how to create a design library and how to
prepare and save the design.
This chapter includes the following topics:
• Defining the Search Path
• Setting Up Libraries
• Reading the RTL Design
• Prerequisite to Modifying a RTL
• Modifying the RTL
• Validating the Modified Connections
• Preventing the Creation of Intermediate Hierarchy Objects in the RTL
• Example: Preparing the Design
• Overview of Basic DFT Configuration
• Passing Options to TestMAX Advisor Using Template-based Flow
• Overview of RTL Test Point Analysis
• Checking the Design for Scan Readiness
• Creating the Test Protocol

Defining the Search Path

The TestMAX Manager tool uses a search path to look for files that are specified with a
relative path or no path.
To specify the search path, use the set_app_var command to set the search_path
application variable to the list of directories in the order of precedence. When the
tool looks for a file, it starts searching starting with the first directory specified in the
search_path variable and uses the first matching file it finds.

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Chapter 3: Preparing the Design
Setting Up Libraries

Use either of the following commands with the search_path variable:

• set_app_var - The following example adds the REFLIBS and NLIBS directories using
a relative path for the tool to search for files:
dft_shell> set search_path [concat . $env(ILANE_LIB_PATH)
${search_path}]

• lappend - Use the lappend command to add your directories to the default search
path, which is the directory from which you invoked the tool. For example,
dft_shell> lappend search_path <library path>

Setting Up Libraries
A cell library (or lib_cell library) contains basic leaf-level blocks such as standard
logic cells and I/O pads. This type of library is used only as a reference library for design
libraries. It does not have design-specific data, a reference library list, or lower-level
libraries.
Use the create_lib command to create a design library, which enables the tool to read a
netlist, a mixed design, or to read the design memories.
You can optionally specify reference libraries. The reference libraries contain the leaf-
level blocks such as standard cells and hard macros (memories, I/O pads, and so on). To
specify the reference library list when you create the design library, use the -ref_libs
option. For more information, see Specifying a Design Library’s Reference Libraries.
The following script shows a typical library setup:
dft_shell> # Specify a list of technology files
dft_shell> set TECH_FILE
dft_shell> # Specify a list of reference libraries, excluding the
temporary files
dft_shell> set REFERENCE_LIBRARIES NDM_reference_files
dft_shell> # Specify the design library
dft_shell> set DESIGN_LIBRARY "DESIGN_LIB"

dft_shell> # Create the library using the reference libraries

dft_shell> create_lib ${DESIGN_LIBRARY} -technology ${TECH_FILE} \
-ref_libs ${REFERENCE_LIBRARIES}

Reading the RTL Design

You can read designs with only RTL, netlist or a mixed design which has RTL and netlist.
The tool can read RTL designs in SystemVerilog or Verilog format.

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Reading the RTL Design

The TestMAX Manager tool must read the design libraries as reference libraries that
are built using the create_lib command, when the netlist information or memories are
present.
Note:
The TestMAX Manager tool does not allow any modifications to the files with the
VHDL format.
Use the analyze and elaborate commands followed by the set_top_module command
to read the RTL design.
The analyze command automatically creates HDL template libraries on disk based on
the name of the library provided by the -hdl_library option. The elaborate command
builds the module specified without linking the rest of the design. This allows multiple
elaborate commands to be run before performing the single linking of the entire design.
The top-level module must be one of the modules that is elaborated.
In the TestMAX Manager tool, the RTL files are read in, using the following command:
analyze -format sverilog | verilog rtl_file_path

Linking the design and setting the top-level module is done using the set_top_module
command. The top-level module must be a module that was previously elaborated with the
elaborate command. The set_top_module command sets the specified module to be
the top-level design, links the entire design, and creates a single block to be used for the
remainder of the design flow.
Set the top module of each of these files using the set_top_module <top_module_name>
command after using the elaborate <module_name> command as shown in the following
example:
dft_shell> set_top_module CGC
dft_shell> analyze -format sverilog ./third_party_occ.v
dft_shell> elaborate third_party_occ
dft_shell> set_top_module third_party_occ
dft_shell> analyze -format verilog ./CGC.v
dft_shell> elaborate CGC

The following example is an output of the analyze command to read RTL files:
analyze -format verilog [list \
SRC/des_a.v \
SRC/des_b.v ]
Running PRESTO HDLC
Searching for ./SRC/des_a.v
Searching for ./SRC/des_b.v
Compiling source file ./SRC/des_a.v
Compiling source file ./SRC/des_b.v
Presto compilation completed successfully.

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Prerequisite to Modifying a RTL

Elapsed = 00:00:00.02, CPU = 00:00:00.01

1

To populate the read design and elaborate options from the internal data structure, enable
the -adv_design_read_options in the following command:
dft_shell> set_testmax_configuration -adv_design_read_options on | off

The default is on.

Reading System Verilog Files and Designs Containing Multiple

HDL Files and Libraries
When you use VCS command-line options with the analyze, the tool automatically
resolves references for instantiated designs by searching the referenced designs in the
specified libraries and then loading these referenced designs.
To read designs containing many HDL source files and libraries, specify the -vcs option
with the analyze command. You must enclose the VCS command-line options in double
quotation marks.
For example,
dft_shell> analyze -vcs "-verilog -y mylibdir1 +libext+.v -v myfile1 \
+incdir+myincludedir1 -f mycmdfile2" top.v
dft_shell> elaborate ${DESIGN_NAME}
dft_shell> set_top_module ${DESIGN_NAME}

To read SystemVerilog files with a specified file extension and Verilog files in a single
analyze command, use the -vcs "+systemverilogext+ext" option. The files must not
contain any Verilog 2001 styles.
For example, the following command analyzes SystemVerilog files with the .sv file
extension and Verilog files:
dft_shell> analyze -format verilog -vcs "-f F +systemverilogext+.sv"
dft_shell> elaborate ${DESIGN_NAME}
dft_shell> set_top_module ${DESIGN_NAME}

Prerequisite to Modifying a RTL

Before you modify RTL using the create_port and connect_net commands, use
the setup_rtl_flow command in the TestMAX Manager tool. The setup_rtl_flow
command allows the tool to recognize any new ports or nets created by the create_port
or connect_net commands in the tool. The new ports or nets are added to the generated
RTL when the connect_dft or modify_rtl command is used.

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Modifying the RTL

Note:
Ensure that ports are available before you define the scan signals. If the ports
do not exist in the design, use the setup_rtl_flow command and then create
ports using the create_port or the create_port_bus command.
The following example shows how to create ports and buses:
dft_shell> setup_rtl_flow
1
dft_shell> create_port WrapperClock -dir in 1
dft_shell> create_port_bus \SI[5:0] -create_port
1

See Also
• Modifying the RTL

Modifying the RTL

The modify_rtl command enables RTL modifications, such as creating or removing
a point-to-point connection, adding instances, ports, uniquifying modules, and inserting
third-party IP from the TestMAX Manager tool. It generates the RTL for the last active
design unless you select the top design before the generation of RTL by using the
select_design command.

The modify_rtl command also supports post insertion modification. It changes the RTL
only and does not change other files such as SpyGlass connectivity constraints files. To
make changes to any other files apart from the RTL, you should manually update the files.
You can use the following RTL editing commands directly in the dft shell or in the RTL
editing script file that is specified in the modify_rtl -file option:
• load_rtl — Reads the new RTL required for the RTL edit.

• add_instance — Creates a new cell in the RTL.

• add_port — Creates new scalar port in the RTL.

• add_connection — Connects pins across the hierarchy in the RTL.

• delete_connection — Disconnects pins across the hierarchy in the RTL.

• copy_connection — Copies the connection from one driver to another driver.

• uniquify_instance — Creates a new reference module for a cell in the RTL.

• set_port_naming_style — Controls newly punched port names in generated RTL.

• set_rtl_parameter — Sets a parameter value for an instance.

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Modifying the RTL

• create_design — Create one or more new modules in a design.

• delete_instance — Deletes one or more cells in RTL.

• delete_port — Deletes one or more ports in RTL.

To use the RTL editing commands directly in the dft shell, enable the following app option:
dft_shell> set_app_options -name dft.shell_rtl_edit <true|false>
It is recommended to use the output directory option when writing out modified RTLs:
modify_rtl -validate_conns on -output_directory <out_dir>

Syntax:
dft_shell> modify_rtl \
-file rtl_modification_tcl_file
{
add_connection -instance inst1 \
-pin p1 [-lsb driver_lsb] [-msb driver_msb]
add_connection -port p1 \
-tieoff {1'b0}
[-name netname] [-auto_uniquify]
delete_connection -instance inst1 \
-pin p1 -instance inst2 -pin p2
add_port -name port_name -direction <IN|OUT|INOUT> \
-lsb <lsb_val> -msb <msb_val>
add_instance -name instance name/hiername \
-master master name [-auto_uniquify]
set_parameter -instance <instance name> \
-name <param-name> -value <param-value>
uniquify_instance –name <instance name/hiername> \
-master <new master name>
select_design <design name>
load_rtl <rtl_file_name/path>
load_rtl -enableSV <rtl_file_name/path>
copy_connection -current_driver_inst <inst name> \
-current_driver_pin <pin/port name> \
-new_driver_inst <driver_name> \
-new_driver_pin <pin name> \
[-new_sink_inst <inst name> \
-new_sink_pin<pin/port name>]
set_default_port_name \
-hierarchical_port_name
Expr(#si,#sp,#di,#dp,#sd,#dd,#netname,#xyz)
new_design <designname>
}
[-load_gui on | off ]\
[-output_directory rtl_out_dir]\
[-allow_post_dft_modifications]\

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Modifying the RTL

[-update_design_db on | off]\
[-stop_untouched_hierarchy on | off]

where
• -load_gui on|off— Invokes RTL modifier GUI mode. Default is off.

• -file rtl_modification_tcl_file — Specifies a file containing RTL edits. This file

must be a Tcl file with the RTL editing commands.
• -output_directory rtl_out_dir — Writes the modified RTL file in the specified
directory. If this option is not provided, the RTL is written in the default output/Verilog
directory.
• -allow_post_dft_modifications — Allows minor modifications of the RTL file after
using the connect_dft command.
• -update_design_db on|off — Allows the update of the TestMAX Manager internal
database and design library after RTL editing.
If the -update_design_db option is on, the design library is updated with the RTL.
If the -update_design_db option is off, only the RTL is updated.
• -stop_untouched_hierarchy on|off — Specify this option to identify the design
hierarchies that are not modified by the operations specified in the modify_rtl
command.
Default is off.
The tool automatically detects the hierarchies that are not needed for the modification
and passes that information to the design load. Therefore, the tool takes lesser time to
run than a full design read.
Consider the following configuration changes that you must perform when using the
modify_rtl command:

• If the file specified with the load_rtl command has an include file, you must pass the
directory containing the include file as follows:
load_rtl +incdir./testmax/SRC ./des_unit.DFTTOPIP_0.v

• The GenSys default hierarchy separator is double colon (::) . However, the hierarchy
separator used in the TestMAX Manager tool is back slash (/). To change the hierarchy
separator from :: to /, use the set_hierarchy_seperator / command.
Note:
All the options and arguments of a GenSys command might not be applicable
to the TestMAX family of tools. For more information about the commands and

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Chapter 3: Preparing the Design
Validating the Modified Connections

options that are supported in the TestMAX tools, see TestMAX Manager Tool
Commands.

Validating the Modified Connections

To validate the connectivity of the connections that are done using the modify_rtl
command, enable the -validate_conns on|off option.
The following example shows how to validate the connections:
dft_shell>modify_rtl -file connections.tcl -validate_conns on
where the connections.tcl is a Tcl file that contains the list of connections that are added or
deleted.
When the connections are modified, the constraints required for the modified connections
are automatically generated and saved in the modify_rtl_validate_conns_constraints.sgdc
file. These are validated against the modified RTL.

Preventing the Creation of Intermediate Hierarchy Objects in the

RTL
To prevent the creation of intermediate hierarchy objects such as ports, connections, or
cells in the intermediate hierarchy in the RTL, use the -enable_hier_create_port off
option. Default is on.
If the DFT insertion is in a separate hierarchy, the DFT insertion assumes that the
hierarchies are black-boxed automatically and the modifications to the hierarchies
are not expected. Therefore, the connect_dft might fail if you do not add the
-enable_hier_create_port off option to the setup_rtl_flow.

The following example shows how to create ports and buses:

dft_shell> setup_rtl_flow -enable_hier_create_port off
1
dft_shell> create_port P1
dft_shell> create_port P2 -cell I1/I2/I3
1

In this example, the top-level port P1 is added and the hierarchical port P2 is ignored.

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Chapter 3: Preparing the Design
Example: Preparing the Design

Example: Preparing the Design

Use the following example to prepare a design:
lappend search_path .
analyze -format verilog ./SRC/third_party_occ.v
elaborate third_party_occ
set_top_module third_party_occ
analyze -format verilog ./SRC/CGC.v
elaborate CGC
set_top_module CGC
analyze -format verilog ./SRC/mux.v
elaborate mux
set_top_module mux
##analyze functional RTL
set design des_unit
analyze -format verilog ./output/Verilog/des_unit_new.v
analyze -format verilog [list \
./SRC/des_a.v \
./SRC/des_b.v \
./SRC/des_c.v \
./SRC/des_ctl.v \
./SRC/des_d.v \
./SRC/des_decrypt.v \
./SRC/des_encrypt.v \
./des_unit_single_DFTTopIP_1.v\
./des_unit_single_DFTTopIP_0.v\ ]
elaborate $design
set_top_module $design
setup_rtl_flow
##insert and connect third-party IP using modify_rtl command
modify_rtl -load_gui on -file ./connect_third_party_ip.tcl \
-output_directory modified_output_rtl
exit

Contents of the connect_third_party_ip.tcl file:

add_connection -instance {u_pll_1} -pin pll_clk_1 \
-instance {third_party_occ_0} -pin fast_clk
add_connection -instance {U_DFT_TOP_IP_0} -pin lbist_mode \
-instance {clk_sel_mux} -pin sel
add_connection -instance {occ_ctrl} -pin lbist_slow_clk_en_0 \
-instance {slow_clk_mux} -pin in1
add_connection -instance {third_party_occ_0} -pin slow_clock_en \
-instance {slow_clk_mux} -pin in0
add_connection -instance {U_DFT_TOP_IP_0} -pin lbist_mode \
-instance {slow_clk_mux} -pin sel
add_connection -instance {occ_ctrl} -pin lbist_fast_clk_en_0 \
-instance {fast_clk_mux} -pin in1
add_connection -instance {third_party_occ_0} -pin fast_clock_en \

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Example: Preparing the Design

-instance {fast_clk_mux} -pin in0

add_connection -instance {U_DFT_TOP_IP_0} -pin lbist_mode \
-instance {fast_clk_mux} -pin sel
add_connection -instance {occ_ctrl} -pin lbist_clk_sel_0 \
-instance {clk_sel_mux} -pin in1
add_connection -instance {third_party_occ_0} -pin clk_mux_sel \
-instance {clk_sel_mux} -pin in0
add_connection -instance {U_DFT_TOP_IP_0} \
-pin lbist_mode -instance {clk_sel_mux} -pin sel
add_connection -instance {slow_clk_mux} \
-pin out -instance {slow_clk_CGC} -pin en
add_connection -instance {fast_clk_mux} \
-pin out -instance {fast_clk_CGC} -pin en
add_connection -instance {slow_clk_CGC} -pin test_en -tieoff 0x0
add_connection -instance {fast_clk_CGC} -pin test_en -tieoff 0x0
add_connection -instance {u_pll_1} -pin pll_clk_1 \
-instance {fast_clk_CGC} -pin clkin
add_connection -port ate_clk -instance {slow_clk_CGC} -pin clkin
add_connection -instance {fast_clk_CGC} \
-pin clkout -instance {clk_out_mux} -pin in0
add_connection -instance {slow_clk_CGC} -pin clkout \
-instance {clk_out_mux} -pin in1
add_connection -instance {clk_sel_mux} -pin out \
-instance {clk_out_mux} -pin sel

Output from the modify_rtl command when the run is successful:

dft_shell> modify_rtl -load_gui on -file ./connect_third_party_ip.tcl \
-output_directory modified_output_rtl
Information: Generating RTL modifier input source list
file ./rtl_modifier_sources.f
Invoking RTL modifier...
RTL modifier run started
Information: RTL modifier design read complete.
Information: RTL modifier run completed successfully.
Information: Modified RTL with DFT IP generated
at /
mypath/TestMAX/third_party_IP/modify_rtl_des_unit/modified_output_rtl
directory.
RTL modifier Log Directory:
/mypath/TestMAX/third_party_IP/modify_rtl_des_unit/rtl_modifier_log/
RTL modifier
LogFile : /
mypath/TestMAX/third_party_IP/modify_rtl_des_unit/rtl_modifier_log/gensys
.log
Begin building search trees for block WORK.nlib:third_party_occ.design
Done building search trees for block WORK.nlib:third_party_occ.design
(time 0s)
Begin building search trees for block WORK.nlib:mux.design Done building
search trees for block WORK.nlib:mux.design (time 0s)
Begin building search trees for block WORK.nlib:CGC.design Done building

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Chapter 3: Preparing the Design
Overview of Basic DFT Configuration

search trees for block WORK.nlib:CGC.design (time 0s)

RTL design modified successfully
1

Overview of Basic DFT Configuration

This topic shows basic DFT configuration tasks that are common to most DFT scan
insertion flows.
The definition of a basic DFT flow varies. You could insert MBIST and do not need to
enable scan or scan compression and it is still a DFT flow.
This section includes the following topics:
• Configuring DFT in the TestMAX Manager Tool
• Defining the Scan Signals
• Defining Test Clocks
• Isolating Ports
• Specifying a Location for the DFT Logic Insertion

Configuring DFT in the TestMAX Manager Tool

The TestMAX Manager tool supports DFT logic solutions that enable you to implement test
logic. The following table describes the various DFT logic that can be inserted and how to
enable and configure it. You must enable the client using the set_dft_configuration
command as it is not automatically inferred. After the client is enabled, you must configure
it with the respective command as no default is assumed.

DFT logic Commands to enable and configure

Basic Scan set_dft_configuration -scan enable

DFTMAX compression set_dft_configuration -scan enable \

-scan_compression enable
set_scan_compression_configuration

DFTMAX Ultra set_dft_configuration -scan enable \

compression -scan_compression enable
set_scan_compression_configuration \
-streaming true -clock clock_name

XLBIST set_dft_configuration -logicbist enable

set_logicbist_configuration

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DFT logic Commands to enable and configure

Core wrapping set_dft_configuration -wrapper enable

(dedicated) set_wrapper_configuration
set_dft_signal
set_boundary_cell

User-defined mode define_test_mode

set_dft_signal -type TestMode

On-chip clocking set_dft_configuration \

-clock_controller enable
set_dft_signal
set_dft_clock_controller
set_scan_path

Pipeline scan data set_dft_configuration \

-scan_data_pipeline enable
set_pipeline_scan_data_configuration

Reset Controller set_dft_asynchronous_controller \

-async [list rst_st_1 rst_st_2 vl_sms_WRSTN ] \

-cell_name rst_ctrl \
-ateclock ate_clk \
-cycles_per_asynch $occ_chain_len \
-chain_count 1 \
-test_mode_port core_occ_test_mode_local

Note:
Enable XLBIST and OCC to configure the reset controller.
For more information about asynchronous reset controller, refer to
the TestMAX XLBIST User Guide.

Shift power control set_dft_signal -view spec -type TestControl \

(SPC) -port SPC_DISABLE

set_scan_compression_configuration \
-shift_power_groups true \
-shift_power_chain_length <> \
-shift_power_chain_ratio <> \
-shift_power_disable <>

TestMAX SMS set_dft_configuration -mbist enable

set_mbist_configuration

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DFT logic Commands to enable and configure

TestMAX Access/ set_dft_configuration

AIT/SERVER/TAP [-scan enable | disable]
[-bsd enable | disable]
[-ait enable | disable]
[-hsio enable | disable]
[-wrapper enable | disable]
[-clock_controller enable | disable]
[-scan_compression enable | disable]
[-pipeline_scan_data enable | disable]
[-logicbist enable | disable]
[-mbist enable | disable]
[-dft_access enable| disable|enable_mbist|
enable_lbist | disable_mbist|disable_lbist]
[-ieee_1500 enable| disable]

IEEE 1149.1 TAP/BSD set_bsd_configuration -bsd enable | tap_only

set_bsd_configuration

IEEE500 set_dft_configuration -ieee_1500 enable

Defining the Scan Signals

To define the DFT-related signals on ports or pins in your design, use the set_dft_signal
command.
Use the -view option to configure the DFT view. A view is typically specified in scan
specification commands, such as set_dft_signal. When configuring scan synthesis, the
tool uses a combination of the two views. To define existing signals that are used in test
mode, use the existing DFT view. To define the DFT structure that you want to insert, use
the specification view.
You can also use the set_dft_signal -connect_to command to specify the source-to-
pin signal connections.
• -view existing_dft

Example 1 Describing an existing signal network

dft_shell> set_dft_signal -view existing_dft -type ScanClock \
-port CLK -timing {45 55}

The existing DFT view is descriptive and describes an existing signal network. For
example, an existing functional clock signal that is also used as a scan clock in test
mode.
• -view spec

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The specification view is prescriptive and describes action that must be taken during
DFT insertion. It indicates that the signal network or connection does not yet exist, and
the insert_dft command must create it. For example, a scan-enable signal network
that must be routed to all scannable flip-flops during the insertion of DFT.

Example 2 Configuring the specification view

dft_shell> set_dft_signal -view spec -port SI -type ScanDataIn

dft_shell> set_dft_signal -view spec -port SO -type ScanDataOut

Defining Test Clocks

dft_shell> set_dft_signal -view existing_dft -type ScanClock \
-port CLK -timing {45 55}

By default, connections are made to ports. However, to make connections to an internal

pin, such as a pad cell or a clock buffer output, you can specify them with the hookup_pin
option.
For example,
dft_shell> set_dft_signal -view existing_dft -type ScanClock \
-port CLK -timing {45 55}
dft_shell> set_dft_signal -view spec -type ScanClock -port CLK \
-hookup_pin UCLKBUF/Z

Note:
The second specification shows the scan clock as an internal pin. The pin
inherits the waveform of the port signal specified with it.
Use the -map_to option of the set_dft_signal command for clocks (including
TCK, WRCK, and WRSTN signals) but not for the test mode signals, or other
pins and ports.

Identifying Weighted Clock Groups for XLBIST

The check_dft command performs a clock analysis and reports the clock matrix. The
generated report includes the clock matrix that can be used to define the weighted clock
grouping for XLBIST in the TestMAX Manager tool.
The following flow describes how to identify weighted clock groups for XLBIST:
1. Define the test clock.
2. Run the check_dft command.

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3. The report generated includes the clock matrix that can be used to define the weighted
clock grouping for XLBIST in the TestMAX Manager tool.
4. Define clock weights by using the clock matrix advice.
For more information about how to configure weighted clock groups, refer to Example:
Configuring Weighted Clocks.

Example: Configuring Weighted Clocks

This topic lists examples that describe how to configure weighted clock groups.
To understand the configuration flow, refer Identifying Weighted Clock Groups for XLBIST

Example 3 Defining test clocks

dft_shell> set_dft_signal -type PLLClock -port vl_sms_WRCK \
-view existing -timing [list 45 55] \
-test_mode all_dft -usage occ
dft_shell> set_dft_signal -type PLLClock -port clk_noc_i \
-view existing -timing [list 45 55] \
-test_mode all_dft -usage occ
#Internal OCC controller clock source
dft_shell> set_dft_signal -type PLLClock \
-hookup_pin u_pll_gen/pll_clk_1 \
-view spec -timing [list 45 55] -test_mode all_dft \
-usage occ
dft_shell> set_dft_signal -type PLLClock \
-hookup_pin u_pll_gen/pll_clk_2 -view spec \
-timing [list 45 55] -test_mode all_dft -usage occ
dft_shell> set_dft_signal -type PLLClock \
-hookup_pin u_pll_gen/pll_clk_4 -view spec \
-timing [list 45 55] -test_mode all_dft -usage occ
dft_shell> set_dft_signal -type wrp_clock -port vl_sms_WRCK

Example 4 The check_dft command report

Information: Clock domain groups
-----------------------------------------------------------------
# Non-interacting and non-intersecting clock domain groups
rank # of flip-flops # of domains domains
in group in group in group
-----------------------------------------------------------------
1 1359 (50.20%) 1 clk1000_i
2 865 (31.95%) 1 u_pll_gen/pll_clk_2
3 483 (17.84%) 3 vl_sms_WRCK,
u_pll_gen/pll_clk_4,
clk_noc_i

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Example 5 Configuring clock weights based on the generated report

dft_shell> set_logicbist_configuration \
-occ_clock_weights \
[list [list 17 clk_noc_i u_pll_gen/pll_clk_4]\
[list 10 vl_sms_WRCK]\
[list 31 u_pll_gen/pll_clk_2]\
[list 50 u_pll_gen/pll_clk_1]]

Clocks are defined and grouped as suggested in the table. The only exception is the
vl_sms_WRCK, which is reported as groupable in the report but defined separately
in the clock weights specification. The reason is that the vl_sms_WRCK clock is used
for dedicated wrapper cells and the relationship of vl_sms_WRCK with other clocks is
available when core wrapping is executed, after the synthesis step. Therefore, you must
maintain the clock that is used to drive the dedicated wrapper cells in a separate group
when defining the clock weights.

Isolating Ports
You can isolate specific ports by adding a safe mux before or after the ports in the RTL to
control the propogation of unknown or X values by configuring the port isolation.
Use the following example to use the test_mode port for safe control:
dft_shell> set_dft_signal -type IsolationControl \
-port test_mode \
-view spec \
-active_state 1 \
-test_mode all_dft

Use the following example to isolate the vl_sms_dm0 and vl_sms_dm1 ports and define
the test_mode control signal for default isolation.
dft_shell> set_dft_port_isolation \
-safe_value_1_ports {vl_sms_dm0 \ vl_sms_dm1} \
-iso_control test_mode

Specifying a Location for the DFT Logic Insertion

By default, TestMAX Manager places all the DFT logic at the top-level of the current
design. If you require alternate insertion locations, you can use the set_dft_location
command.
dft_shell> set_dft_location dft_hier_name -include test_logic_types

where dft_hier_name must be a hierarchical instance that already exists and is not a
library cell, black box, or CTL model. If the specified instance does not exist, the command
is ignored.

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Passing Options to TestMAX Advisor Using Template-based Flow

By default, all DFT logic is placed within the specified instance. If you want certain
test logic to be within the instance, you must use the -include option of the
set_dft_location command.

For example, the set_dft_location my_cell -include {CODEC} command places

codec components within the my_cell instance.
The set_dft_location -include {TAP SERVER} instance_name command moves the
TAP and SERVER into the my_cell instance.
Note:
To specify the location to insert OCC, use the set_dft_clock_controller
command.
For more information about specifying the location to insert OCC, refer to
Configuring the OCC Controller.
The valid DFT logic types are:
• CODEC - This type includes the compressor and decompressor (codec) logic inserted by
the tool for compressed scan, serialized compressed scan, and streaming compressed
scan modes.
• WRAPPER - This type includes core wrapping cells and wrapper mode logic configured
by the set_wrapper_configuration command.
• TAP - This type includes the IEEE Std 1149.1 TAP controller logic inserted when the
set_dft_configuration -bsd enable command is used.

• SERVER - This type includes the server logic that controls the TestMAX SMS and
TestMAX Access components when the set_dft_configuration -dft_access
enable command is used.

Passing Options to TestMAX Advisor Using Template-based Flow

Sometimes when using the System Verilog as the RTL, the constructs require special
handling which is not passed automatically onto SpyGlass or when running additional non-
default rule sets, you need to pass information to TestMAX Advisor.
You can provide additional options for the check_dft, connect_dft, validate_dft
commands and TestMAX Advisor commands by using the template-based flow.
set_testmax_configuration -user_opt_file options_filename

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The options file can include the following TestMAX Advisor commands:
• read_file

• set_option

• set_goal_option

• set_parameter

Example options file:

set_option v /u/path/concatenated.v
set_option enableSV no
set_gensys_options -instance_threshold 100000

Note:
To enable the DesignWare flow in the TestMAX Manager tool, use the
set_option dw yes option.

For more information about DesignWare Components, refer to Reading

Synopsys DesignWare Components in SpyGlass.
You can use the template-based flow to run RTL test point analysis. For more information,
see Overview of RTL Test Point Analysis.

Overview of RTL Test Point Analysis

Test points are points in the design where the DFTMAX tool inserts logic to improve the
testability of the design. The tool can automatically determine where to insert test points to
improve test coverage and reduce pattern count.
This section includes the following topics:
• Running RTL Test Point Analysis
• Comparison of the set_testability_configuration Command Options

Running RTL Test Point Analysis

To perform RTL test point analysis, use the template-based flow in the TestMAX Manager
tool.
You must first pass the options to TestMAX Advisor using the following command:
dft_shell> set_testmax_configuration -user_opt_file user_option_file_name

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The user_option_file_name file contains the test point analysis rules. These rules are
used by the TestMAX Advisor commands such as check_dft and validate_dft -check
connectivity

The report containing the list of test points is written to the following directory: spg_config/
design_name/dft_shell_goal/spyglass_reports/dft_dsm.
The file name is random_pattern_dc_testpoints.rpt, regardless of the rule run.

Example 6 TestMAX Manager script

dft_shell> set_testmax_configuration -user_opt_file ./rtl_tp_analysis.tcl

rtl_tp_analysis.tcl file contains the following data:

#random_resistant
set_goal_option addrules { Info_random_resistance }
set_parameter dft_rrf_tp_count 20
set_parameter dft_pattern_count 1000
set_parameter dft_rrf_tp_effort_level high
set_parameter dft_rrf_tp_thread_count 8
#untestable_logic
set_goal_option addrules { TA_10 }
#self_gating
set_goal_option addrules { Info_self_gating_logic }
#x_blocking (same as check_dft -xd)
set_goal_option addrules { Info_x_sources }
set_parameter dft_ignore_x_sources UIO_MCP_FP_CL_HN_MD
#multicycle_paths
set_goal_option addrules { Atspeed_05 }
set_parameter dsm_enable_mcp_fp_on_celldefine_boundary on

After running the check_dft command, the TestMAX Advisor file,

spg_check_dft_config.prj , has a user options section that contains the options specified in
the rtl_tp_analysis.tcl file.
#user_options
set_goal_option addrules { Info_random_resistance }
set_parameter dft_rrf_tp_count 20...

The test points to be inserted are reported in the random_pattern_dc_testpoints.rpt file in

the spg_check_dft_config/dft_shell_goal/spyglass_reports/dft_dsm directory.
For more information about the TestMAX DFT commands and options, see the TestMAX
DFT User Guide.
If you are using X-density and want to generate the test points, use the following setting:
dft_shell> set_parameter dsm_report_x_source_in_dc_report on

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You can also prevent a test point by setting the following option:
no_test_point -name module_name | instance_list [-fanin_logic]
[-fanout_logic]

• -name module_name | instance_list - Required. Specifies the name of the module

or the list of instances that cannot be considered for suggesting test points.
• -fanin_logic - Optional. Specifies the fanin logic that cannot be considered for
suggesting test points.
• -fanout_logic - Optional. Specifies the fanout logic that cannot be considered for
suggesting test points.
The -fanin_logic and -fanout_logic options can be specified together.
For more information on the X-density and random-resistant analysis algorithm, its
parameters, and other information on test points, see the TestMAX Advisor Rules
Reference Guide documentation.

Comparison of the set_testability_configuration Command

Options
The following table describes the mapping between the
set_testability_configuration options in the TestMAX DFT tool and the
corresponding TestMAX Advisor commands.

Options in TestMAX DFT Commands in TestMAX Advisor

-target random_resistant set_goal_option addrules

{ Info_random_resistance }

-target untestable_logic set_goal_option addrules { TA_10 }

-target x_blocking set_goal_option addrules

{ Info_x_sources }
set_parameter dft_ignore_x_sources
UIO_MCP_FP_CL_HN_MD

-target multicycle_paths set_goal_option addrules

{ Atspeed_05 } set_parameter
dsm_enable_mcp_fp_on_celldefine_bou
ndary on

-target self_gating set_goal_option addrules

{ Info_self_gating_logic }

-random_pattern_count N set_parameter dft_pattern_count N

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Options in TestMAX DFT Commands in TestMAX Advisor

-effort <high | low | medium> set_parameter

dft_rrf_tp_effort_level high | low
| medium

-max_test_points N set_parameter dft_dc_tp_count N

-test_points_per_scan_cell R set_parameter
dft_dc_tp_register_sharing_ratio R

-target untestable_logic \ set_parameter dft_ta_tp_count N

-max_test_points N

-target random_resistant \ set_parameter dft_rrf_tp_count N

-max_test_points N

Checking the Design for Scan Readiness

The check_dft command analyzes the design for registers in the RTL that can easily be
replaced with scan equivalent registers during logic synthesis, or in a post-synthesis step.
The command can also check if the RTL is lint-clean.
Scan readiness checks for the following:
• Test clock control in test mode for all registers
• Making asynchronous pins (set and reset) inactive in test mode for all registers
Based on the scan readiness of the design, the command also gives an early estimate of
the stuck-at coverage and a detailed audit report of the coverage.
Internally, the tool launches the TestMAX Advisor tool with a goal set to dft/
dft_scan_ready.

To check the design for scan readiness use the following command syntax:
check_dft [-check lint|dft|all] [-load_gui on|off|run].

lint - Checks RTL for lint

dft - Checks RTL for scan readiness

all - Default value. Checks RTL for scan readiness and lint

-load_gui on|off|run - Specify the on option to launch the TestMAX Advisor GUI
to help debug issues. Otherwise, TestMAX Advisor runs in batch mode and generates
reports. The on setting launches the GUI to analyze results from a previous run.
The run option loads the TestMAX Advisor GUI and runs the check to analyze.

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Example output showing coverage from check_dft:

-------------------------------------------------------------------------
Results Summary:
-------------------------------------------------------------------------
Total Flip flop count: 968
Scannable Flip flop count: 968
Total combinational reconvergent paths to clock pins of flip-flop
: 0
Total combinational reconvergent paths to asynchronous pins of
flip-flops : 0
Total sequential reconvergent paths to asynchronous pins of flip-flops
: 0
Stuck-at fault coverage = 99.5%
Stuck-at test coverage = 99.7%
Percentage of scannable flops = 100.0%
-------------------------------------------------------------------------

Example showing the GUI:

dft_shell> check_dft -load_gui on

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Creating the Test Protocol

By default, the TestMAX Advisor tool assumes the designs are read as SystemVerilog.
If you have non-SystemVerilog files that use SystemVerilog constructs, you might see
STX_VE_481 violations. To resolve these violations, use the following configuration file:
set_testmax_configuration -user_opt_file my.txt
where the my.txt file contains set_option enableSV off.
The check_dft command creates the following files and directories:
• spg_check_dft_sources.f - List of all the RTL source files
• spg_check_dft_constraints.sgdc - TestMAX Advisor constraints such as clocks, async,
and testmode
• spg_check_dft_config.prj - File required by the TestMAX Advisor tool to read the
source, .sgdc files, and other setup-like type of violation reports and to set that the
defined goals to run
• spg_check_dft_config/
Directory contains the following files:
◦ Report of stuck-at coverage numbers
spg_check_dft_config/<design_name>/dft_shell_goal/spyglass_reports/dft/
dftCoverage.rpt
◦ List of non-scan cells
spg_check_dft_config/<design_name>/dft_shell_goal/spyglass_reports/dft/
no_scan.rpt
spg_check_dft_config/<design_name>/dft_shell_goal/spyglass_reports/
moresimple.rpt
◦ List of total scan flops, flops per IP, scan, and non scan cells in the total design
spg_check_dft_config/<TOP_DESIGN_NAME>/dft_shell_goal/spyglass_reports/dft/
dft_data/dft_data_01.csv

Creating the Test Protocol

The create_test_protocol command creates a test protocol for the current design
based on user specifications issued before running this command. The specifications
are made using commands such as set_dft_signal. The create_test_protocol
command also checks whether the user-specified values are consistent with each other. If
they are not consistent, it issues an error and does not generate a protocol. The command

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identifies information such as the time period of clocks, active values of scan enable,
resets, test mode signals, and so on.
After defining the DFT signals, create a test protocol using the create_test_protocol
command. If an existing protocol needs to be read in, use the read_test_protocol
-section test_setup command instead.

For example,
dft_shell> create_test_protocol
Information: Starting test protocol creation. (DFT-3219)
...reading user specified clock signals...
Information: Identified system/test clock port "clk_st" ( 45.0, 55.0).
(DFT-3265)
...reading user specified asynchronous signals...
1

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4
The TestMAX Manager DFT Insertion Flow
This chapter describes the TestMAX Manager DFT insertion flow.
This chapter includes of the following topics:
• Generating the DFT IP
• Fusion Compiler In-Compile Flow
• Connecting DFT IP to RTL
• Connecting DFT IP to the Netlist
• Validating the Connections Made Within the IP to the RTL
• Identifying Existing Ports When Integrating the Core-Level to the SoC-Level
• Writing Out the Test Protocol and Test Model
• Writing the Constraints File

Generating the DFT IP

The generate_dft command generates IP RTL files containing DFT logic such as
compressors, decompressors, control registers, and serializers. The tool names these files
automatically, and writes the files in the current directory.
The following IPs and features are supported for generation:
• DFTMAX
• DFTMAX Ultra
• XLBIST
• On-chip clocking
• IEEE 1500
• SPC

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Generating the DFT IP

• Core wrapping
• Pipeline scan data
Additionally, the generate_dft command generates files required for the instantiation
and connection of the DFT IP at the required level of design hierarchy in the RTL. It also
generates files required for validation.
During the execution of this command, you can preview the result of the DFT constraint
set.
After running, the command displays information messages that show the following:
• Configuration of the generated IP architectures
• DFT signals used
• Location of the DFT IP generated files and their file names
The generate_dft command creates the IP. For DFTMAX, the following files are
generated:
• <design_name>_DFTTopIP_0.v — Verilog file for the DFT IP
• rtl_modifier_sources.f — File for the connect_dft command to modify the RTL to add
MUXs and so on
• rtl_modifier_connection_commands.t — List of source files for the connect_dft
command
• rtl_modifier_gate_design.tlib — Primitive format library file
• spg_validate_dft_constraints.sgdc — Connectivity and rule check instructions for the
validate_dft command. This file is modified by the connect_dft command as it is
used in the validate_dft step.
The command also prints the implemented connections, as shown in the following
example:
generate_dft
Client Status
--------- ---------
Scan Enable
Wrapper Disable
Logicbist Disable
Mbist Disable
Dft Access Disable
Scan_compression Enable
Testability Disable
Pipe_line_scan_data Disable
Clock_controller Disable
ieee_1500 Disable

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Generating the DFT IP

- Partition: 'default_partition'
Information: Architecting DFT Scan IP with '4' scan chains in mode 'scan'
Information: Architecting Streaming DFT Compressor IP with '4' inputs /
'4' outputs / '80' internal chains in mode 'scan_comp'
ScanDataIn:
Mode: scan
"si0" -> U_DFT_TOP_IP_0/si[0]
"si1" -> U_DFT_TOP_IP_0/si[1]
"si2" -> U_DFT_TOP_IP_0/si[2]
"si3" -> U_DFT_TOP_IP_0/si[3]
Mode: scan_comp
"si0" -> U_DFT_TOP_IP_0/si[0
"si1" -> U_DFT_TOP_IP_0/si[1]
"si2" -> U_DFT_TOP_IP_0/si[2]
"si3" -> U_DFT_TOP_IP_0/si[3]
ScanDataOut:
Mode: scan
"so0" -> U_DFT_TOP_IP_0/so[0]
"so1" -> U_DFT_TOP_IP_0/so[1]
"so2" -> U_DFT_TOP_IP_0/so[2]
"so3" -> U_DFT_TOP_IP_0/so[3]TestMode:
"TM" -> U_DFT_TOP_IP_0/TM[0]ScanEnable:
"SE" -> U_DFT_TOP_IP_0/test_se Codec clocks:
"clk_st" -> U_DFT_TOP_IP_0/decompClk
"clk_st" -> U_DFT_TOP_IP_0/comprClk
Test Mode Controller Ports
--------------------------
test_mode: "TM"
Test Mode Controller Index (MSB --> LSB)
----------------------------------------
"TM"
Control signal value - Test Mode
--------------------------------
0 scan - InternalTest
1 scan_comp - InternalTest

Note:
For DFTMAX SEQ, use the dft.separate_codec_ip_files application
option to generate separate files for compressor, decompressor, and self-test
controller for each codec. The following files are created when you use the set
app_option -dft.separate_codec_ip_files command:

• des_unit_DFTTopIP_*_compressor.v
• des_unit_DFTTopIP_*_decompressor.v
• des_unit_DFTTopIP_*_selftestcontroller.v

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Fusion Compiler In-Compile Flow

Fusion Compiler In-Compile Flow

The in-compile flow is the recommended DFT flow for the Fusion Compiler tool when it
is used to synthesize and optimize the TestMAX Manager-inserted DFT, where DFT IP is
inserted into the RTL. The in-compile flow optimizes the location of DFT operations within
the stages of the compile_fusion command.
The in-compile flow provides the flexibility to use the preview_dft command at the gate
level. In addition, you can perform a second set of test DRC checks after the insert_dft
command. During the final compile step (compile_fusion -from initial_place),
the tool accounts for scan reordering during placement if the SCANDEF information is
available.
The constraints generated by the write_dft_constraints command are split into the
following scripts:
• A script to be read before the initial synthesis with the compile_fusion command, to
define the settings that must be applied after elaboration.
• A script to be read after the logic_opto stage of the compile_fusion command,
where the remaining constraints must be applied.
Currently, the file must be split manually.
To generate two constraint files, set the dft.new_in_compile_constraints application
option to true. The application option is not enabled by default. Use the following
command to enable the application option:
set_app_options -as_user_default -list {dft.new_in_compile_constraints
true}

The write_dft_constraints -out filename command generates the following

constraint files for the Fusion Compiler tool:
• filename.synth_fc.tcl - Synthesis constraints file
• filename.dft_fc.tcl - DFT Constraints file

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Fusion Compiler In-Compile Flow

Figure 3 In-Compile Flow

Synthesis specifications FunctionalRTL

set_scan_element false
specifications
set_wrapper_configuration \
-reuse_threshold compile_fusion \
-to logic_opto

DFTspecifications

create_test_protocol
dft_drc -test_mode all_dft
run_test_point_analysis
preview_dft
insert_dft
dft_drc -test_mode test_mode

compile_fusion \
-from initial_place \
-to initial_opto

dft_drc -test_mode test_mode

The in-compile flow helps to align the output from the TestMAX Manager tool with the
latest Fusion Compiler reference methodology flow.
The support for the in-compile DFT flow helps to align the output from the TestMAX
Manager tool with the latest Fusion Compiler reference flow, where the following variables
to point to the constraint files from the TestMAX Manager tool:
• $TCL_DFT_PRE_IN_COMPILE_SETUP_FILE - The settings before compile are set

• $TCL_DFT_SETUP_FILE - The in-compile settings are set

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Connecting DFT IP to RTL

Connecting DFT IP to RTL

Use the connect_dft command to instantiate the generated DFT IP RTL into your design
RTL, connect the DFT IP, and generate the combined RTL that includes RTL and DFT
RTL. The connect_dft command produces updated files in the output/Verilog directory,
which contains the original source file content and the modified content. The modified files
retain the original RTL name.
The connect_dft command adds the DFT IP RTL to the source RTL. The command uses
the rtl_modifier_connection_commands.tcl and the rtl_modifier_sources.f file written out by
the generate_dft command. Check the rtl_modifier_log/gensys.log, for more information
about the errors during connect_dft.
The connect_dft -port_diff on|off command creates a report for the newly added
ports in different modified modules. The report file is named as port_diff.rpt and it is
created inside the report directory.
The connect_dft command generates the following files:
• output/Verilog directory — for the modified RTL with the DFT IP instantiated
• output/Verilog/spyglass.f — Used by the validate_dft command that has Spyglass-
specific design read options. This file contains options such as +define, +incdir, and
Spyglass-specific options such as -stop, -top, and so on.
• output/Verilog/sources.f — File contains the RTL file list with no tool specific options.
This file is used by SpyGlass for the validate_dft command through the spyglass.f
file which has Spyglass-specific design read options in it. Use the sources.f file if you
have your own simulation or the synthesis tool and need only the modified file list.
• output/Verilog/sources_synth.f — Files contain additional design read options such as
+define, +incdir, and so on.
• output/Verilog/sources_sim.f — File contains additional design read options such as
+define, +incdir, and so on.
Note:
If you have a design read set-up for simulation or synthesis and need
modified file list only, then replace the old file list withsources.f.
• output/stub — Directory for the modified RTL with only the input/output information as
<design_name>.v. It also has files such as the spyglass.f file that points to this stub
design file.
• port_diff.rpt — A report for all the newly added ports in different modified modules.

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The default is off.

• Log — Log file and report directory from the connect_dft command. For example,
rtl_modifier_log/gensys.log.
Use the following command to specify whether to add a prefix to the modified modules and
the prefix value:
dft_shell> set_testmax_configuration -add_module_prefix <prefix>
[-change_file_names <on/off>]

Consider the following usage while configuring the change_file_names argument:

• The change_file_names argument can only be used with the
set_testmax_configuration -add_module_prefix command option.

• When the change_file_names argument is set to on, the tool renames the modified
files with prefix from the add_module_prefix option, except the file containing the top-
module.

Checking Unsupported Constructs in the Input RTL

An audit report checks whether there are any unsupported Verilog constructs in the input
RTL. This report is for information purposes only. An audit report enables you to know that
if there are modifications to the unsupported constructs, the TestMAX Manager tool might
not be able to do the modifications properly.
Use the connect_dft -audit_rtl on|off command to enable or disable the generation
of an audit report. When set to on, the command generates the rtl_modifier_log/
rtl_audit.rpt file.
The default is off.
The following unsupported constructs are listed in the audit report:
• Array of interface
• Parameterized array of interface
• Glue logic in an interface
• Task and function inside SV interfaces
• Nested module
• Type parameter

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Connecting DFT IP to the Netlist

After you generate an audit report, run the connect_dft command to instantiate the
generated DFT IP RTL into your design RTL, connect the DFT IP, and generate the
combined RTL that includes RTL and DFT RTL.

Defining the Format of SpyGlass Design Constraints

To define the format of the SpyGlass Design Constraints (SGDC) constraints, use the
dft.testmax_scan_enable_shift_only_constraint application option when defining
the ScanEnable signal.
Set the application option to true in the following command to define the format of the
SGDC constraints:
dft_shell> set_app_options -name \
dft.testmax_scan_enable_shift_only_constraint <true/false>

Default is false.
• When the application option is false, the SGDC constraints are written in the
-invertInCapture mode.
• When the application option is true, the SGDC constraints are written in following
format :
◦ If the scan enable signal type is defined as -view spec, the SGDC constraints are
written in -invertInCapture mode.
◦ If the scan enable signal type is defined as -view existing_dft, the SGDC
constraints are written in the -scanshift mode.
◦ If the scan enable signal type has both the views, the SGDC constraints are written
in the -scanshift mode.

Connecting DFT IP to the Netlist

To read a netlist or a mixed design, you must set applications options for the connect_dft
command to make the required connections. You must set the application options in the
user options file that is specified with the set_testmax_configuration command.
dft_shell> set_app_options -as_user_default \
-name dft.testmax_force_tlib_file_generation \
-value true
dft_shell> set_app_options -as_user_default \
-name dft.testmax_force_design_file_generation \
-value true

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The reference libraries that use the NDM format are treated as black boxes during the
check_dft command. To prevent this, you can generate the design file and the design
library file by setting the application options in the TestMAX Manager tool.
However, the tool does not generate a top-level edited netlist with instantiated DFT IP
by using this flow. The netlist can be written out using the write_verilog -hier all
command.

Connecting DFT IP to Netlist Using TestMAX Manager With

DFTMAX Compression
The following example shows how to connect DFT IP in the TestMAX Manager tool with
DFTMAX compression.

dft_shell> analyze -format verilog [list SRC/top.v ]

dft_shell> elaborate top
dft_shell> set_top_module top
dft_shell> # DFT Signals
dft_shell> # Clock
dft_shell> set_dft_signal -type MasterClock -port clk \
-timing [list 45 55]
dft_shell> # Scan-in , Scan-out, Scan-enable, Test Mode
dft_shell> set_dft_signal -type ScanDataIn -port si1 \
-view spec
dft_shell> set_dft_signal -type ScanDataOut -port so1 \
-view spec
dft_shell> set_dft_signal -type ScanEnable -port SE \
-view spec
dft_shell> set_dft_signal -type TestMode \
-port TM \
-view spec
dft_shell> # Scan configuration for DFTMAX
dft_shell> set_dft_configuration -scan enable \
-scan_compression enable
dft_shell> set_scan_configuration -chain 12
dft_shell> set_scan_compression_configuration \
-chain_count 80 \
-input 8 -output 8 \
-streaming false
dft_shell> create_test_protocol
dft_shell> check_dft
dft_shell> generate_dft
dft_shell> connect_dft
dft_shell> validate_dft -check connectivity
dft_shell> # Write Test Protocol files
dft_shell> write_test_protocol -o top.scan.spf \
-test_mode Internal_scan

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dft_shell> write_test_protocol -o top.comp.spf \

-test_mode ScanCompression_mode
dft_shell> # Write Synthesis constraints
dft_shell> write_dft_constraints -output constr_for_dc.tcl
dft_shell> exit

Validating the Connections Made Within the IP to the RTL

The validate_dft command validates the generated constraints for connections and
rules.
You can also specify an option to perform lint checks on the generated IP.
• -check connectivity | lint | lint_ip

◦ connectivity - Performs connectivity checks for connections and rules. Performs

rule checks on the DFT IP and checks connections between IP and design.
◦ lint - Performs lint checks on the generated IP and Gensys connections.

◦ lint_ip - Performs lint checks on the generated IP.

• -load_gui on|off|run

Specify on to launch the SpyGlass GUI to help debug issues, otherwise SpyGlass runs
in batch mode and generates reports.
• -verbose

Specify this option to generate verbose output during the connectivity check.
For example, here is the output for validate_dft -check lint -load_gui

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Identifying Existing Ports When Integrating the Core-Level to the SoC-Level

The -check connectivity option of the validate_dft command runs SpyGlass with the
spg_validate_dft_config.prj project and the dft/dft_test_connection goal.

The -check lint option of the validate_dft command runs SpyGlass with the
spg_validate_dft_config.prj project and the lint/lint_rtl goal.

Identifying Existing Ports When Integrating the Core-Level to the

SoC-Level
When integrating the core-level with the SoC-level, you can enable the TestMAX Manager
tool to identify the port connections existing at the lower level. The tool recognizes the
existing ports and does not create any ports at the lower hierarchies as the connections
already exist.
If port connections exist at the lower-level and the connectivity is not defined, the fabric at
the top-level creates new pins in the lower hierarchies instead of reusing the existing ones
at the core boundary.
You can specify the port connections existing at the lower level by using the
set_attribute -name dft_scan_through_pin attribute. The tool recognizes the
existing connections at the top-level and the SOC fabric does not need to create new test
mode ports or pins in different hierarchies.

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Writing Out the Test Protocol and Test Model

The following example describes how to specify the port connections existing at the lower-
level:
Consider that there are three hierarchies core, subsystem, and top. Use the following
example, if you have an existing one to one mapping of test mode ports from the
subsystem to the core and do not want the SoC fabric to add new ports to the subsystem
hierarchy when integrating the core-level to the SoC-level.

Example 7 Identifying lower-level port connections

##specifying existing Test Mode connection from core to SS

dft_shell> set_attribute -name dft_scan_through_pin \
-objects [get_pins u_subsystem1/u1/TM1] \
-value u_subsystem1/TM1_ss_intf
##specifying existing Test Mode connection from core to SS
dft_shell> set_attribute -name dft_scan_through_pin \
-objects [get_pins u_subsystem1/u1/TM2] \
-value u_subsystem1/TM2_ss_intf
##specifying existing scan enable connection from core to SS
dft_shell> set_attribute -name dft_scan_through_pin \
-objects [get_pins u_subsystem1/u1/SE] \
-value u_subsystem1/SE_ss_intf

Writing Out the Test Protocol and Test Model

You can write out various files using the write_test_protocol and write_test_model
commands.
The write_test_protocol command writes out the test protocol file (SPF) for the test
mode specified. This file is used by the TestMAX ATPG tool during its run_drc command.
Write out the test protocol file after the generate_dft command.
You can use the following command for writing the protocol file from the TestMAX Manager
tool:
dft_shell> write_test_protocol -o output_protocol_file_name \
-test_mode test_mode_name

The following example writes out the SPF file in internal-scan mode called INTERNAL:
dft_shell> write_test_protocol -o des_unit.is.spf \
-test_mode INTERNAL

The following example writes out the SPF in compression mode called CODEC:
dft_shell> write_test_protocol -o des_unit.sc.spf \
-test_mode CODEC

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The test_mode_name specified in the write_test_protocol command must be

previously defined with the define_test_mode command.
dft_shell> write_test_protocol -o ./spf/des_unit.is.spf \
-test_mode scan
Information: Writing protocol for test mode scan in ./spf/des_unit.is.spf
(DFT-3001)
1
dft_shell>
write_test_protocol -o ./spf/des_unit.sc.spf \
-test_mode scan_comp
Information: Writing protocol for test mode scan_comp
in ./spf/des_unit.sc.spf (DFT-3001)
1

The write_test_model command writes out the CTL file.

dft_shell> write_test_model -output ./des_unit_new.ctl

Writing the Constraints File

The write_dft_constraints command writes out the constraints that you source in
Design Compiler or Fusion Compiler for synthesis. It also writes the constraints for formal
verification to constrain the scan portion to be inactive and the SDC file for timing analysis.
dft_shell> write_dft_constraints -output constr_for_dc.tcl

Information: Formality constraints file 'constr_for_dc.tcl.fm.tcl'

generated successfully.
File with same name already exists, overwriting that file
Information: SDC constraints file 'constr_for_dc.tcl.sdc.tcl' generated
successfully.

Synthesis of DFT IP and Scan Insertion

Functional RTL, including the DFT IP-inserted RTL, and DFT IPs are read into the
synthesis tool, and an elaboration is done.
Constraints written out by the TestMAX Manager tool are sourced in the synthesis tool.
The DFT constraints file has compile options for the scan configuration to exclude DFT
elements from scan insertion (for example, DFT IP and OCC).
The internal pins flow is used for scan insertion. The output of the DFT IP (din) is defined
as scan input, and the input of DFT IP (dout) is defined as the scan output.
Clock definitions are also specified at internal hookup points.

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Compression, IEEE 1500, and OCC insertions are disabled during synthesis because
these are already defined in the RTL.
The following example shows a Design Compiler synthesis script:
# Read and Elaborate Functional RTL and DFT IPs
current_design $top_module
link
uniquify
source ../dftip_rtl_gen/dftmax_constraints.tcl
create_test_protocol
compile -scan
dft_drc
preview_dft -test_wrappers all
insert_dft
write -f verilog -hier -o ./for_tmax.v

The netlist generated after synthesis and scan insertion can be used for TestMAX ATPG
DRC and ATPG runs.
Note:
If you use the compile_ultra command for synthesis, use the
-no_autoungroup option.

Generating SDC Constraints

The write_dft_constraints command does not write the SDC constraints file
used in Design Compiler and PrimeTime and the Formality constraints. Use the
write_test_timing_constraint command with the -test_mode option to generate
SDC constraints.
Command syntax:
dft_shell> write_test_timing_constraints -mode {shift | capture | any} \
-testmode {defined | undefined} \
-OCC {any | bypass | active} \
-output filename

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Table 1 write_test_timing_constraints Command Options

Option Description

-mode {shift|capture|any} Constrains the timing analysis on the scan-enable

signal with the set_case_analysis command. The
signal value is 0 for shift mode,1 for the capture mode.
The default value for the -mode is any, where the
set_case_analysis commands with 0 and 1 signals
appear and are commented out.
When you choose a value for the -mode, the
corresponding set_case_analysis command becomes
uncommented. The active_state of the scan_enable
signal corresponding to the shift mode appears as
commented out, above the set_case_analysis
commands.

-OCC { any|bypass|active} Use only when the capture mode is set. This argument
allows to choose if we want to constraint the timing
analysis with case analysis for pll_bypass signal. The
default value is any, where the two case analysis on
pll_bypass signal appear by default, but are commented
out. When you choose the bypass or activ OCC options
the corresponding case analysis become uncommented.
The active_state of the pll_bypass signal corresponding
to OCC bypass appears as commented out above the
set_case_analysis commands.

-testmode {defined|undefined} Constrains the timing analysis with set_case_analysis

commands for TestMode type signal which
allows to choose the test mode. The value of the
set_case_analysis command depends on the mode
that is set using the current_test_mode command. The
default value is undefined where set_case_analysis
commands, on the signal which allows to choose the
test mode is commented out. When the customer
chooses a -testmode option, the corresponding
set_case_analysis commands is uncommented. When
the set_case_analysis command is uncommented, all
testmode type signals appear automatically such that the
SDC script is generated for test timing analysis.

All of these options control the generation of SDC in shift mode or capture mode with or
without OCC.

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5
Hierarchical Flows
The hierarchical flows in the TestMAX Manager tool enable the hierarchical adaptive scan
flows for DFTMAX or DFTMAX Ultra and provide hierarchical support when there are
cores and SMS cores. This chapter explains how to run the hierarchical adaptive scan
flows when there are DFTMAX and DFTMAX Ultra cores.
For more information about the hierarchical support for cores with SMS-inserted
components, see the TestMAX SMS User Guide. See the TestMAX Access User Guide for
information about XLBIST-inserted cores.
This chapter includes of the following topics:
• Hierarchical Adaptive Scan Synthesis (HASS) flow
• Integrating the HASS Flows of Compressed Scan Cores
• Integrating the Hybrid Flow at the Top Level
• Performing Top Level Hybrid Integration With Partitions
• Using Multiple Test Modes in Hierarchical Flows
• Connecting the Shift Power Control Disable Signal to the Core Block
• Limitations of the Integration of Hierarchical Flows With the TestMAX Manager Tool

Hierarchical Adaptive Scan Synthesis (HASS) flow

In the hierarchical adaptive scan synthesis (HASS) flow, scan compression logic is placed
at the block level. Cores with the scan compression logic are integrated by connecting to a
fabric that targets different predefined test modes of the cores. These cores are treated as
hard cores. Each core must have CTL test model information so that the tool can perform
top-level integration.
This approach helps reduce the routing congestion prevalent in multimillion gate
designs. Ensure that you connect and manage the DFT ports of the existing cores during
integration. You can reuse the core-level ATPG patterns and port them from the core to the
higher level without regenerating the patterns.

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Integrating the HASS Flows of Compressed Scan Cores

The hybrid flow is an extension of the HASS flow that provides additional support for
compressed scan insertion for user-defined logic.
Note:
The TestMAX Manager tool cannot perform core level insertion of scan or other
IP without codec. Therefore, you must insert compression in the flows.

Integrating the HASS Flows of Compressed Scan Cores

To enable the HASS flow at the top level, use the following commands:
• The set_dft_configuration -scan_compression enable command enables scan
compression.
• The set_scan_compression_configuration -integration_only true command
enables the HASS flow.

Integrating the Hybrid Flow at the Top Level

To enable the hybrid flow at the top level, use the following commands:
• set_dft_configuration -scan_compression enable - Enables scan compression.

• set_scan_compression_configuration -hybrid true - Enables the hybrid flow.

After you enable the hybrid flow, configure the hybrid flow integration by using the
following commands:
• Specify the total top-level scan chain count.
set_scan_configuration -chain_count

• Specify the number of compressed scan chains for the new top-level codec.
set_scan_compression_configuration -chain_count

or
• Specify the maximum compressed scan chain length.
set_scan_compression_configuration -max_length

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Performing Top Level Hybrid Integration With Partitions

Performing Top Level Hybrid Integration With Partitions

By default, hybrid integration creates a single codec for all scan logic except the existing
compressed scan cores. You can use the DFT partition feature to create multiple codecs
at the top level. This can help reduce routing congestion.
You can use the define_dft_partition command to define an additional partition and
specify the cells and designs to be placed in that partition. All cores and logic not explicitly
assigned to a user-defined partition remain in the default partition, named default_partition.

Using Multiple Test Modes in Hierarchical Flows

When you invoke DFTMAX or DFTMAX Ultra compression, by default, the tool creates
two test operating modes: a standard (uncompressed) scan mode and a compressed scan
mode. To create a larger set of test modes, use the define_test_mode command. The
tool creates logic to support each defined mode.
In a hierarchical flow that performs core integration, each lower level core can have
multiple test modes. By default, the tool groups the identically-named modes that are at
the top-level and are in different cores, and selects those core level modes as a single
mode at the top level. If the modes have different names, they are grouped by usage and
then combined into name combinations.
You can override the default name-based association of core level test modes. This
process is known as test mode scheduling. To schedule a test mode, use the -target
option of the define_test_mode command:
dft_shell> define_test_mode test_mode_name \
-target {core1:mode1 [core2:mode2 ...] \
[current_design_name]}

The -target option specifies a list of core and test-mode pairs to use for the top-level test
mode being defined. Each pair consists of a core instance name and a core test-mode
name separated by a colon (:). In compressed scan flows, the list can also contain the
name of the current design to specify that the top-level logic should be active and tested.

Connecting the Shift Power Control Disable Signal to the Core

Block
To connect the shift power control (SPC) disable signal to the core block in the TestMAX
Manager hierarchical flow, use the -usage spc option.
The following example connects the top level spc_disable signal to the core level u1/
spc_disable and u2/spc_disable signals.

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dft_shell> set_dft_signal -type TestControl -port spc_disable \

-view spec -active_state 1 -test_mode all_dft \
-connect_to [list u1/spc_disable u2/spc_disable] \
-usage spc

Limitations of the Integration of Hierarchical Flows With the

TestMAX Manager Tool
The following limitations apply to the integration of hierarchical flows with the TestMAX
Manager tool:
• The tool does not detect the logic type for DFTMAX Ultra automatically.
• The tool does not support DFTMAX Ultra Planner.

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6
On-Chip Clocking (OCC)
On-chip clocking (OCC) support is common to basic-scan and fast-sequential scan
ATPG and compressed scan environments. OCC flows use the DFT-inserted OCC clock
controller.
This chapter includes of the following topics:
• Clock Type Definitions
• OCC Controller Structure and Operation
• Specifying the DFT-Inserted On-Chip Clock Controller
• On-Chip Clock Flow
Note:
TestMAX Manager does not support the insertion of OCC at the top level in
hierarchical -integration (HASS) flow.

Clock Type Definitions

The following are the clock type definitions:
• Reference clock - The frequency reference to the phase-locked loop (PLL). It must be
maintained as a constantly pulsing and free-running oscillator or the circuitry will lose
synchronization.
• PLL clock - The output of the PLL. It is also a free-running source that runs at a
constant frequency that might or might not be the same as the reference clock.
• ATE clock - Shifts the scan chain, typically more slowly than a reference clock. This
signal must already exist, or you must manually add this signal (port) when inserting
the OCC. The period for this clock is determined by the dft.test_default_period
application option. Usually the ATE clock is not used as a reference clock, but it must
be treated as a free-running oscillator so that it does not capture predictable data while
the OCC controller generates at-speed clock pulses. The ATE clock is called a dual
clock signal when the same port drives both the ATE clock and the reference clock.
Use the ATE clock when OCC insertion is happening, when no OCC present we have
to only use the Scan_Clock declaration.

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Chapter 6: On-Chip Clocking (OCC)
OCC Controller Structure and Operation

Note:
When you use the ATE_CLOCK definition in absence of OCC and try to use
that clock for ULTRA CODEC it will not connect. Therefore, in the absence
of an OCC, use the Scan_Clock definition.
• Internal clock - The OCC controller is responsible for gating and selecting between
the PLL and ATE clocks, thus creating the internal clock signal to satisfy ATPG
requirements.
• External clock - A primary clock input of a design that directly clocks flip-flops.
The following image describes the OCC flow :

OCC Controller Structure and Operation

This section describes the OCC controller types and operation.

OCC Controller Signal Operation

The reference clock is always free-running. It is used as a frequency reference input to the
PLL.
The PLL clocks are free-running clock outputs from the on-chip clock generator. They can
be divided, shaped, or multiplied before entering the OCC. They are used for the launch
and capture of internal scannable elements when enabled by the OCC.
The ATE clock shifts the scan chain. Each OCC might have its own ATE clock.
The OCC controller serves as an interface between the on-chip clock generator and
internal scan chains. This logic typically contains clock multiplexing logic that allows
internal clocks to switch from a slow ATE clock during shift to a fast PLL clock during
capture.

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OCC Controller Structure and Operation

Internal clocks are outputs of the OCC control logic driving the scan cells. Each internal
clock is controlled or enabled by the clock chain and is connected to the sequential
elements within the design.
The OCC bypass signal allows the ATE clock signal to connect directly to the internal clock
signals, thus bypassing the PLL clocks.
The ScanEnable signal enables switching between the ATE shift clock and the PLL clock
signals. ScanEnable must be inactive during every capture procedure.
The OCC TestMode signal must be asserted in order for the clock controller to operate.
The OCC reset signal is asserted during test setup to reset the OCC controller flip-flops to
their initial states.

Clock Chain Operation

The clock chain provides a mechanism to select clock for each pattern in ATPG. It is
implemented as a scan chain segment of one or more scan cells. Clock selection values
are loaded into the clock chain as part of the regular scan load process.
A clock chain operates as follows:
• During scan shift, the clock chain shifts in new values when clocked by a scan clock.
The clock chain can be clocked by either the rising or falling clock edge, depending on
what best fits into the overall DFT architecture.
• During scan capture, the clock chain holds its value. The value scanned into the clock
chain must be scanned out and undisturbed after the capture. The clock controller
inserted by the TestMAX Manager tool meets this requirement.
The clock chains for DFTMAX can be an uncompressed or external scan chain or
embedded as a segment within a compressed scan chain.
For DFTMAX Ultra compressed scan designs, the clock chain must be an uncompressed
(external) scan chain.
Clock chains of the same type (compressed or external) can be concatenated.
Compressed clock chains are concatenated into a single chain and placed inside the
compressor where a regular single chain would be placed.
In the DFT-inserted OCC controller flow, the tool inserts a clock chain block that is
separate from the OCC controller block. See SolvNetPlus article 034274, DFT-inserted
OCC Controller Data Sheet for more information about the logic structure and operation of
the DFT-inserted OCC controller.

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Chapter 6: On-Chip Clocking (OCC)
OCC Controller Structure and Operation

Enabling On-Chip Clocking Support

The DFT-inserted OCC controller and clock chain generated by TestMAX Manager makes
the control signal connections and modifies the clock signal connections as needed.
The following is the command to insert an OCC controller:
dft_shell> set_dft_configuration -clock_controller enable

Inserting an On-Chip Clock Controller at the Top Level

To connect the top level OCC signals to the core block use the -connect_to option for
HASS and hybrid flows.
In the following configuration example, pll_bypass or pll_reset signal, that is declared first
is used to connect the top-level OCCs. The top-level OCC pll_bypass signal connects to
the core u1/pll_bypass signal:

dft_shell> set_dft_signal -type pll_bypass -port pll_bypass_top \

-view spec -active_state 1 -test_mode all
dft_shell> set_dft_signal -type pll_bypass -port pll_bypass_core1 \
-view spec -active_state 1 \
-test_mode all -connect_to [list u1/pll_bypass]
dft_shell> set_dft_signal -type pll_bypass -port pll_bypass_core2 \
-view spec -active_state 1 \
-test_mode all -connect_to [list u2/pll_bypass]

To connect the top-level OCC signals to the core block, use the -connect_to option for
HASS and hybrid flows.

Retaining the Delay Information

If there is a maximum rise in the input delays relative to a different clock or a different edge
of the same clock, the old delay information is updated to the new delay information.
To retain the previous delay information, add the -add_delay option during the
configuration of the input and output delays. The following example shows how to retain
the delay information:

Example 8 Configuring input delay

dft_shell> set_input_delay 2 \
-add_delay \
-clock refclkin [get_ports {vl_srv_bihr_run}] \
-max

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Example 9 Configuring output delay

dft_shell> set_output_delay 2 \
-add_delay \
-clock refclkin [get_ports {vl_srv_efuse_active}] \
-min

The -add_delay option uses the largest delay for maximum constraint and the smallest
delay for minimum constraint.
If you do not add the -add_delay option, the new delay information overwrites the old
delay information.

Specifying the DFT-Inserted On-Chip Clock Controller

The PLL clock is expected to already be connected in the design. The TestMAX Manager
tool disconnects this PLL clock at the hookup location and inserts the recently synthesized
clock controller at this location.

Defining Clocks
You need to define the reference, PLL, and ATE clocks by using the set_dft_signal
command.

Reference Clocks
Reference clock signals are always defined in the existing DFT view. The generate_dft
command does not connect them because they are functional signals rather than test
signals. The only effect of defining them is that they are defined in the test protocol for use
by the TestMAX ATPG tool DRC check. For some cases, a reference clock signal is not
needed.
The following example shows how to define a PLL reference clock:
dft_shell> set_dft_signal -view existing_dft \
-type RefClock -port refclk1 \
-period 10 -timing [list 3 8]

Note the following, when defining a reference clock:

• If the reference clock period is an integer divisor of the test default period, then patterns
can be written in a variety of formats, including STIL, STIL99, and WGL.
• If the reference clock is not an integer divisor to the test default period, the only format
that can be written in a completely correct way is STIL. Other formats, including the

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STIL99 format, cannot include the reference clock pulses and a warning is printed,
indicating that these pulses must be added back to the patterns manually.
• Do not define a reference clock period or timings with resolution finer than 1 ps. The
TestMAX ATPG tool cannot work with finer timing resolutions.

ATE Clocks
The following example shows how to define the signal behavior of the ATE-provided clock
required for shifting scan elements:
dft_shell> set_dft_signal -view existing_dft \
-type ATEClock \
-port ATEclk \
-timing [list 45 55]

By default, the TestMAX Manager tool makes the ATE clock connection at the source port
specified by the -view existing_dft signal definition. To specify a hookup pin to be
used for the clock connection, use the -hookup_pin option in a subsequent -view spec
scan clock signal definition.
For example,
dft_shell> set_dft_signal -view spec \
-type ATEClock \
-port ATEclk \
-hookup_pin PAD_ateclk/Z

You can use the same clock port as both the ATE clock and PLL reference clock.
Note:
You must not use the ATE clocks to drive the clock of scanned flip-flops. The
ATE clock is pulsed after the ScanEnable signal is de-asserted, which is
required to synchronize the ScanEnable signal.

PLL-Generated Clocks
For the TestMAX Manager tool to correctly insert the OCC, you must define the PLL-
generated clocks as well as the point at which they are generated. The following examples
show how to define a set of launch and capture clocks for internal scannable elements
controlled by the OCC controller:

dft_shell> set_dft_signal -view existing_dft \

-type PLLClock \
-hookup_pin PLL/pllclk1
dft_shell> set_dft_signal -view existing_dft \
-type PLLClock -hookup_pin PLL/pllclk2
dft_shell> set_dft_signal -view existing_dft \
-type PLLClock -hookup_pin PLL/pllclk3

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The PLL clocks are free running. The OCC controller is placed between the PLL clock and
the scan flip-flops.

Internal Clocks
To provide the correct clock period of internal clocks that are generated from OCC, insert
the period in the set_dft_signal -type PLLClock command.
The following example shows how to configure the clock period of internal clocks, thus
overriding the default :
dft_shell> set_dft_signal -type PLLClock \
-hookup_pin u_pll_gen/pll_clk_2 \
-view spec -period 8 -timing [list 4 5] \
-test_mode all_dft -usage occ

The generated SDC file has the new values.

Defining Global Signals

You must identify the top level interface signals that control the OCC controller. This
includes the PLL bypass, PLL reset, and scan enable signals. You must also define a
dedicated test mode signal that activates the OCC controller logic. In the OCC controller
insertion flow, these signals are defined with the -view spec option because they are
implemented and connected by the generate_dft command.
The following example shows how to define a set of OCC controller interface signals for
the design example:
dft_shell> set_dft_signal -view spec -type pll_reset -port pll_reset
dft_shell> set_dft_signal -view spec -type pll_bypass -port pll_bypass
dft_shell> set_dft_signal -view spec -type ScanEnable -port SE
dft_shell> set_dft_signal -view spec -type TestMode -usage occ \
-port TM_OCC

The test mode signal must be a dedicated signal for the OCC controller. It must be active
in all test modes and inactive in mission mode. It cannot be shared with the test mode
signals that are used for other purposes, such as test mode selection. In the internal pins
flow, you can specify internal hookup pins for these OCC control signals by using the
-hookup_pin option of the set_dft_signal command. However, you cannot specify
internal hookup pins for ATE clocks or reference clocks.

Configuring the OCC Controller

To specify where to insert a DFT-inserted OCC controller, use the
set_dft_clock_controller command.

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The following syntax shows how to configure an OCC:

dft_shell> set_dft_clock_controller -cell_name cell_name \
-ateclock clock_name \
-test_mode_port port_name] \
-enable_signal \
-pllclocks ordered_list \
[-chain_count integer] \
[-cycles_per_clock integer]

Example 10 Inserting an OCC controller that controls three clocks

dft_shell> set_dft_clock_controller -cell_name occ_int\
-ateclock {ATEclk} \
-test_mode_port {occ_test_mode} \
-pllclocks {pll/pllclk1 pll/pllclk2 pll/pllclk3} \
-cycles_per_clock 2

To insert multiple OCC controllers, use multiple set_dft_clock_controller commands.

Example 11 Disabling the OCC clock in shift and capture

dft_shell> set_dft_clock_controller -cell_name occ_ctrl \
-ateclock ate_clk -pllclocks {pll_1/pll_clk} \
-test_mode occ_test_mode \
-chain_count 2 -cycles_per_clock 5 \
-enable_signal OCC_EN_1

On-Chip Clock Controller Configuration Options

The following table lists the OCC configuration options and its descriptions:

Option Description

-cell_name (Mandatory) Specifies the hierarchical name of the

clock controller cell.

-ateclock (Mandatory) Specifies the ATE clock (port) you want

to connect to the OCC controller. The specified port
must exist and must be predefined as a ateclock
using the set_dft_signal command.
Note:
You cannot specify multiple ate clocks for each
controller.

-test_mode_port (Optional) Specifies the test-mode port used to

enable the clock controller. Use this option if you
have multiple test mode ports and you want to use
a specific port to enable the clock controller. The
specified port must be defined as a test mode signal
using the set_dft_signal command.

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Option Description

-enable_signal Specifies the signal that disables the OCC controller.

-pllclocks ordered_list (Required for asynchronous OCC controllers.)

Specifies the ordered list of PLL output clock pins to
control for asynchronous OCC controllers.
You must predefine the pins as -type pllclock
-usage occ using the set_dft_signal command.

-chain_count (Optional) Specifies the number of clock chains. The

default number of clock chains is one.

-cycles_per_clock (Optional) Specifies the maximum number of

capture cycles per clock. You must specify a
value of 2 through 10. The default number of
cycles per clock is 2. Capture cycles are cycles
during capture when capture clocks are pulsed.
Typically, for at-speed transition testing, there are
2 capture cycles, where one is used for launching
a transition and the other for capturing the effect of
that transition.

Generating Synchronised Output Pulses

Phase-locked loop (PLL) clocks are asynchronous to each other and does not produce
synchronized output pulses even if the PLL clocks at its inputs are synchronized. In order
to improve the coverage between two synchronous clock domains and the at-speed
test reliability and to reduce the test vector, you can use the OCC controller to produce
synchronized output pulses.
Ensure that the following conditions are met to produce synchronized output clock pulses:
• Clocks produced by a single OCC controller can be synchronized to each other. One
OCC controller cannot produce clock pulses synchronized to those from any other
OCC controller, even if the input clocks to each of them are synchronized.
• The rising edges of the synchronized clocks must be simultaneous and clock tree
balancing must be precise enough to allow flip-flops clocked by them to transfer data in
both directions without hold time violations. This requirement applies to the clock trees
at the outputs of the OCC controller. At the inputs of the OCC controller, the clock trees
do not have to be this precisely balanced, because data transfer between different
clocks uses a posedge-to-negedge or a negedge-to-posedge path.
• The clocks must have fixed frequency ratios. The slowest clock for each OCC
controller is called the 1X clock. The other synchronized clocks may be 1X, 2X (twice

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the frequency, one-half the period of the 1X clock) or 4X (four times the frequency,
one-quarter the period of the 1X clock). At the 1X clock’s rising edge, all clocks
synchronized to it must also have rising edges.
The default timing that is written into the STIL Protocol Format (SPF) or (CTL) file by
write_test_protocol or by write_test_model are as follows:

• 1X clocks: period 20 ns, rising edge 0 ns, falling edge 10 ns

• 2X clocks: period 10 ns, rising edge 0 ns, falling edge 5 ns
• 4X clocks: period 5 ns, rising edge 0 ns, falling edge 2.5 ns
The default timing that is written into the STIL Protocol Format (SPF) or (CTL) file by
write_test_protocol or by write_test_model is:

Enabling the Synchronised Clock Controller

Use the following command to enable synchronised clock controller:
dft_shell> set_dft_clock_controller \
-1x_clocks list_of_pins \
-2x_clocks list_of_pins \
-4x_clocks list_of_pins

When a synchronized OCC controller is defined by this command, the defining the
-1x_clocks option is mandatory. The first clock in -1x_clocks list is used as the
synchronization master clock, whose rising edge determines when the OCC controller
starts to count pulses. The -2x_clocks and -4x_clocks options. All other options of the
set_dft_clock_controller command are used in the same way for either the insertion
of a synchronous or asynchronous OCC controller.
Note:
Do not mix the use of –pllclocks and synchronized clocks with the same
set_dft_clock_controller command. This can result in bad scan chain
architecture. When some PLL clocks are asynchronous, use a separate
set_dft_clock_controller command with the –pllclocks option.

To configure the internal clock periods with a user-defined value, use the
test_sync_occ_1x_period application option. The following example describes how to
define application options:
dft_shell> set_app_options -as_user_default \
-name dft.test_sync_occ_1x_period -value 40.0

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Configuring the Clock Chain

By default, the clock chain is constructed as follows:
• In scan compression modes, the clock chain registers exist on their external chains.
• In standard scan modes, the clock chains can be combined with other chains to form
scan chains.
You can use the set_scan_path command with the -class occ option to define a
particular structure. Specify the cell name of an OCC controller to reference its clock
chain.
For example, to create an external clock chain for two OCC controllers:
dft_shell> set_dft_clock_controller -cell_name BLK1/OCC1 ...
dft_shell> set_dft_clock_controller -cell_name BLK2/OCC2 ...
dft_shell> set_scan_path OCC_CHAIN -class occ \
-include_elements {BLK1/OCC1 BLK2/OCC2} \
-scan_data_in SI_OCC -scan_data_out SO_OCC

Handling Long Clock Chains

The default is to create a single clock chain. However, if you have many clocks to control,
the clock chain might become longer than other scan chains. To split the clock control bits
up across multiple clock chains, use the -chain_count option:
dft_shell> set_dft_clock_controller -cell_name BIG_OCC -chain_count 2 \
-pll_clocks {(many clocks)} ...

In set_scan_path specifications, the OCC controller cell name references all clock chains
for that OCC controller. To reference individual clock chains, append an index number
using the colon (:) character:

dft_shell> set_dft_clock_controller -cell_name BIG_OCC -chain_count 2 \

-pll_clocks {(many clocks)} ...
dft_shell> set_scan_path OCC_CHAIN1 -class occ \
-include_elements {BIG_OCC:0} \
-scan_data_in SI_OCC1 -scan_data_out SO_OCC1
dft_shell> set_scan_path OCC_CHAIN2 -class occ \
-include_elements {BIG_OCC:1} \
-scan_data_in SI_OCC2 -scan_data_out SO_OCC2

Configuring the Clock-Chain Clock Connection

By default, the clock-chain clock connection shares the first functional clock output of the
OCC controller. This places the clock chain in both the PLL and ATE clock paths.

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To use a dedicated clock-chain clock connection from the OCC controller design, set the
following application option:
dft_shell> set_app_options \
-name dft.test_dedicated_clock_chain_clock \
-value true

This creates a dedicated OCC controller clock output for the clock chain that places it in
the ATE clock path only, which prevents it from affecting the high-speed PLL clock path.
The following image shows the shared clock-chain connection and dedicated clock-chain
connection. In both cases, you should consider how the clock-chain clock connection
interacts with clock tree synthesis (CTS).

Defining Integrated Clock-Gating Cell

When theTestMAX Manager tool inserts clock-gating cells as a part of the DFT logic, this
variable constrains the insertion process to use the specified library cell to gate any clock
signal that has a return-to-zero (RTZ) waveform. The name must match an available cell in
the target libraries, and this cell must be an integrated clock-gating cell.

Example 12 Defining the integrated clock-gating cell to use for implementing return-to-zero
clock gating in the DFT logic
dft_shell> set_app_options -as_user_default \
-name dft.test_icg_p_ref_for_dft \
-name dft.test_icg_n_ref_for_dft \
-value CGLPPSX16_RVT

Specify the cell name without the library name. If the library name is included,
the specification is ignored without warning or error. The cell specified by the
dft.test_icg_p_ref_for_dft variable is used for the initial logic construction only. After
the insertion of clock-gating cells, subsequent design optimizations can resize the cell, if
the library cell attributes allow.

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Use the -name dft.test_icg_n_ref_for_dft application option to enable the DFTMAX

SEQ and the XLBIST clock gating cell to use the negative level ICG instead of latched
gates and AND gates.
The TestMAX Manager tool uses the combinational gates to gate clock signals if the
dft.test_icg_p_ref_for_dft variable is not set.

On-Chip Clock Flow

This topic describes how to insert the OCC and clock chain at RTL with TestMAX
Manager.
Enable the On-Chip Clocking Support
dft_shell> set_dft_configuration -clock_controller enable

Define OCC Signals

dft_shell> set_dft_signal -type ScanDataIn -port OCC_si
dft_shell> set_dft_signal -type ScanDataOut -port OCC_so
dft_shell> set_dft_signal -type ScanEnable -port test_se
dft_shell> set_dft_signal -type ScanClock \
-port ate_clk -timing [list 45 55]

dft_shell> set_dft_signal -type RefClock -port reflck1

-timing [list 45 55] -view existing
dft_shell> set_dft_signal -type MasterClock -hookup pll/pllclk1
-usage occ
dft_shell> set_dft_signal -type MasterClock -hookup pll/pllclk2 \
-usage occ
dft_shell> set_dft_signal -type MasterClock -hookup pll/pllclk3 \
-usage occ
dft_shell> set_dft_signal -type testmode -port occ_test_mode -usage occ
dft_shell> set_dft_signal -type pll_bypass -port pll_bypass
dft_shell> set_dft_signal -type pll_reset -port pll_reset
dft_shell> set_dft_signal -type ScanEnable -port test_se

Configure the OCC controller

dft_shell> set_app_options \
-as_user_default -list \
{dft.test_dedicated_clock_chain_clock true}

dft_shell> set_dft_clock_controller \
-cell_name occ_ctrl \
-ateclock ate_clk \
-pllclocks { pll/pllclk1 pll/pllclk2 pll/pllclk3 } \
-test_mode_port occ_test_mode \
-cycles_per_clock 2 \

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-chain_count 1

Configuring the clock chain

dft_shell> set_scan_path occ_chain \
-scan_data_in OCC_SI \
-scan_data_out OCC_SO \
-include_elements {occ_ctrl} \
-class occ

Creating test_protocol
dft_shell> create_test_protocol

Checking design for lint and scan readiness

dft_shell> check_dft

Writing out protocol files

dft_shell> write_test_protocol -out ./results/protocol.spf

Writing constraints files

dft_shell> write_dft_constraints -output ./results/constr_for_dc.tcl

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7
TestMAX Manager-Based DFTMAX/DFTMAX
Ultra Compression Insertion
DFTMAX and DFTMAX Ultra scan compression provide scan data compression
technology to lower the cost of testing larger designs. The scan compression technology
reduces manufacturing test costs by delivering a significant test data and test time
reduction with very low silicon area overhead. DFTMAX and DFTMAX Ultra enable scan
compression in the TestMAX Manager tool, which can then be synthesized and taken to
TestMAX ATPG for test pattern generation.
For details about the DFTMAX and DFTMAX Ultra compression architecture and
decompressor and compressor operation, see the TestMAX DFT User Guide.
This chapter includes of the following topics:
• Configuring DFTMAX Compression
• Configuring DFTMAX Ultra Compression
• Sharing Codec Scan I/O Pins
• Verifying the DFT IP at RTL Level

Configuring DFTMAX Compression

To enable and configure DFTMAX compression, use the following commands:

dft_shell> set_dft_configuration -scan enable

dft_shell> set_dft_configuration -scan_compression enable
dft_shell> set_scan_compression_configuration \
-inputs num_scanins \
-outputs num_scanouts \
-chain_count num_chains | -max_length chain_length \
-test_mode mode_name \
-exclude_elements exclude_list

The -inputs and -outputs options are required. There must be enough scan-in and
scan-out signals defined to satisfy the specification.

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Configuring DFTMAX Compression

If you are using user-defined test modes, specify the mode that you must configure
with the -test_mode option. You must define the test mode previously using the
define_test_mode <mode_name> -usage scan_compression command.

The -chain_count and the -max_length options are mutually exclusive. These options
apply to the compression architecture as follows:

By default, the command creates and configures a mode named ScanCompression_mode.

If you are using user-defined test modes, specify the mode to configure with the
define_test_mode <mode_name> -usage_scan_compression option.

If you are also implementing a standard scan mode, these compressed chains might be
used as the base chains to create other modes.
If the number of pins is insufficient, the tool displays the following error message:
Error: Architecting of Load/Unload compressor failed with the given set
of parameters
Information: Skipping dft rtl generation.
Error: 0

Scan Compression and On-Chip Clocking Controllers

On-chip clocking (OCC) controllers allow on-chip clock sources to be used for at-speed
capture during device testing. In an OCC controller flow, the clock chain is a special scan
segment that provides control over the at-speed capture pulse sequence generated by the
OCC controller.
In the DFTMAX scan compression flow, the clock chain is external (uncompressed). This
is different from the default flow in DFTMAX when using DFT Compiler, which puts the
OCC clock chain between the decompressor and the compressor.

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Defining External Clock Chains

External clock chains are uncompressed and exist outside the codec.

To define the external clock chain, use the set_scan_path command. This command
allows you to specify the scan-in and the scan-out of the OCC clock chain.
For example,
dft_shell> set_dft_configuration -clock_controller enable
dft_shell> set_dft_signal -view spec -type ScanDataIn -port occ_si

dft_shell> set_dft_signal -view spec -type ScanDataOut -port occ_so

dft_shell> set_dft_clock_controller -cell_name occ_ctrl
dft_shell> set_scan_path occ1 -class occ \
-include_elements {occ_ctrl} \
-scan_data_in occ_si \
-scan_data_out occ_so \
-test_mode all

The -class occ option indicates that the scan path specification defines a clock chain.
Use the -include_elements option to allow the tool, to change the order of elements or
use the -ordered_elements option to use only the specified order. The -test_mode all
option is required. You can also define multiple external clock chain.
The shift power control chain (SPC) chain is an external (uncompressed) chain outside
the DFTMAX codec. When scan-in completes, the SPC registers contain the group mask
values for the next pattern.
You either concatenate or separate SPC and OCC chains to reduce power or optimize
chain length in your flow.

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Use the following command to specify separate OCC chain:

dft_shell> set_scan_path occ_chain -scan_data_in Si \
-scan_data_out So -include {occ_ctrl} -class occ

Use the following command to specify separate SPC chains:

dft_shell> set_scan_path spc_chain -scan_data_in si \
-scan_data_out so -class spc

For more information about using separate and concatenated SPC and OCC chains, refer
the TestMAX DFT User Guide.
Note:
Compressor pipeline is not supported.

Configuring DFTMAX Ultra Compression

To enable and configure DFTMAX Ultra compression, include the -streaming true
option with the set_scan_compression_configuration command.
dft_shell> set_dft_configuration -scan enable
dft_shell> set_dft_configuration -scan_compression enable
dft_shell> set_scan_compression_configuration \
-streaming true\
-inputs num_scanins \
-outputs num_scanouts \
-chain_count num_chains | -max_length chain_length \
-clock codec_clock \
[-test_mode mode_name]

The -inputs and -outputs options are required. There must be enough scan-in and
scan-out signals defined to satisfy the specification.
The -chain_count and -max_length options are mutually exclusive; only one is required.
The -clock option specifies which clock to use for the streaming codec. If you do
not specify the -clock option, the following error appears during the generate_dft
command:
Error: Missing codec clock specifications

By default, the command creates and configures a mode named ScanCompression_mode.

If you are using user-defined test modes, you must specify the mode to configure with the
-test_mode option.

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Configuring DFTMAX Ultra Compression

The configuration options apply to the following compression architecture:

DFTMAX Ultra compression architecture has additional lock-up latches stage at the output
of compressor.
DFTMAX Ultra compression automatically computes the input and output shift register
lengths that are optimal for the number of scan inputs and outputs and the number of
compressed scan chains.

Configuring Multiple Input/Output

You can configure a multiple input/output (I/O) using the TestMAX Manager tool in
DFTMAX Ultra. Use this feature to implement an architecture, outside of the DFTMAX
Ultra block. This architecture that uses bandwidth throttling to create patterns for multiple I/
O configurations.
On-chip clocking (OCC) controllers allow on-chip clock sources to be used for at-speed
capture during device testing. For more information about configuring OCC in Multiple
I/O configuration, refer to Scan Compression and On-Chip Clocking Controllers in the
TestMAX DFT User Guide.

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Configuring DFTMAX Ultra Compression

The advantage of configuring multiple I/Os in a single DFTMAX Ultra IP is that the area
overhead is less as the same codec can be configured with multiple I/Os. Thus providing
a single codec solution. For big designs, you can configure a maximum of 3000 internal
scan chains.
The following figure describes the configuration of DFTMAX Ultra Codec with two scan in/
two scan out and one scan in / one scan out respectively.

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Figure 4 Multiple I/O Configuration

Note:
Only the DFTMAX Ultra flow without partitions is supported.

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See Also
• Scan Compression and On-Chip Clocking Controllers

Defining Multiple Configurations in the TestMAX Manager Tool

Use the following syntax to configure multiple I/O in the tool:
dft_shell> set_scan_compression_configuration -streaming true \
-multi_configurations [list <Value1> <Value2> <Value3>] \
-configuration_ports [list cfg1 cfg2]

The following is a description of the arguments used in the syntax:

• Values are a factor of the DFTMAX Ultra codec I/O (default I/O configuration). You can
specify a maximum of three configurations excluding the default I/O configuration.
• Specify configuration ports signals as test control.
An example of the multiple I/O configuration is as follows:
dft_shell> set_dft_signal -type TestControl -port [list cfg1 cfg2]
dft_shell> set_scan_compression_configuration -chain_count 100 \
-input 10 -output 10
-streaming true -clock clk_st
dft_shell> set_scan_compression_configuration -streaming true \
-multi_configuration [list 5 2 1] \
-configuration_ports [list cfg1 cfg2]

To view the multiple I/O configuration, use the report_dft -scan_compression

command. The output is as follows:
Report : Scan Compression Configuration
TEST MODE: all_dft
VIEW : Specification
--------------------------------------------------------------
xtolerance High
Inputs 10
Outputs 10
Chain Count 100
Configuration Ports cfg1 cfg2
Multi Configuration 5 2 1
Maximum Chain Length Unspecified
Serialize disable
Shift Power Groups False
Clock mixing: No mix
Insert terminal lockup: False

Note:
During the configuration. the codec is assumed to be symmetrical and has a
balanced configuration of I/Os.

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Defining Multiple Configurations in TestMAX ATPG

To configure multiple I/Os in ATPG, specify the modes available in DRC and then use the
multi configuration mode.
The following syntax describes how to specify modes in DRC:
dft_shell> set_drc –multi_config_mode <mode number>

The mode number argument defines the mode to run, one mode at a time.
The syntax for the multiple I/O configuration is:
dft_shell> set_atpg -streaming_multi_config_mode

If you use the -streaming_multi_config_mode option, ATPG terminates early when it

reaches the best trade off patterns and fault coverage for that particular mode . If you do
not use this option, ATPG runs to complete the fault coverage using the mode selected
during DRC.
The following example describes the multiple I/O configuration in ATPG mode:
set_drc -multi_config_mode 3
run_drc ultra_10_5_2_1_ascan.spf
set_atpg –streaming_multi_config_mode
run_atpg –auto
write_faults mode3.rpt -all -replace
write_patterns mode3.stil -format stil -replace
;
set_drc -multi_config_mode 2
run_drc ultra_10_5_2_1_ascan.spf
set_atpg –streaming_multi_config_mode
read_faults mode3.rpt -retain_code
run_atpg –auto
write_faults mode2.rpt -all -replace
write_patterns mode2.stil -format stil -replace
;
drc –force
set_drc -multi_config_mode 1
run_drc ultra_10_5_2_1_ascan.spf
set_atpg –streaming_multi_config_mode
read_faults mode2.rpt -retain_code
run_atpg –auto
write_faults mode1.rpt -all -replace
write_patterns mode1.stil -format stil -replace
;
drc –force
run_drc ultra_10_5_2_1_ascan.spf
set_atpg –streaming_multi_config_mode
read_faults mode1.rpt -retain_code
run_atpg –auto

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write_faults run0.rpt -all -replace

write_patterns run0.stil -format stil -replace

Note:
The write_patterns command will write only the patterns generated only for
the last ATPG run. Write patterns for each mode and save the fault list (to be
read back while retaining their code).

Using On-Chip Clock Controllers With DFTMAX Ultra

Compression
DFTMAX Ultra requires that the clock chains of OCC controllers be uncompressed so that
the control bits are directly controllable without conflict by ATPG.
To define an external clock chain, use the -scan_data_in and -scan_data_out options
of the set_scan_path command to specify the input and output ports of the external
chain:
dft_shell> set_dft_clock_controller -cell_name BLK/OCC ...
dft_shell> set_scan_path OCC_CHAIN -class occ \
-include_elements {BLK/OCC} \
-scan_data_in SI_OCC -scan_data_out SO_OCC

For details about defining external clock chains, see Configuring the Clock Chain on
page 72.

Reducing Scan Shift Power Using Shift Power Groups

During scan shift, there is significant toggle activity in the scan chains. At high scan shift
frequencies, this can result in higher-than-desired shift power consumption.
Use the shift power groups to reduce power consumption during scan shift in DFTMAX
and DFTMAX Ultra compressed scan modes.
For more information about configuring SPC in multiple I/O configuration, refer to the
TestMAX DFT User Guide.

Sharing Codec Scan I/O Pins

DFTMAX compression provides design testability with reduced scan pin count
requirements.
The tool normally requires each codec to have dedicated scan-in and scan-out pin
connections. For large designs with many blocks and many separate codecs, the scan pin
requirements could be challenging for pin-limited designs.

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Sharing Codec Scan I/O Pins

The following image displays the dedicated and shared codec I/O connections:

Specifying the I/O Sharing Configuration

Use the -shared_inputs, -shared_outputs, and -integration_only configuration
options of the following command to share codec scan I/O pins:
dft_shell> set_scan_compression_configuration

.The following examples describes how to define the I/O sharing configuration:
dft_shell> set_scan_compression_configuration \
-shared_inputs M \
-shared_outputs N \
-integration_only true

The value M specifies the size of the set of shared scan-in pins used for all codec input
connections. The value N specifies the size of the set of shared scan-out pins used for all
codec output connections.

Codec I/O Sharing With Identical Cores

The following example shows the core-level and top-level scripts:
dft_shell> analyze -format verilog ./des_unit_single.v
dft_shell> elaborate des_unit_single
dft_shell> set_top_module des_unit_single
current_design des_unit_single
link
##############################################
# Specify the dft signals #######
##############################################
dft_shell> set_dft_signal -type ScanDataIn -port scan_in[0:9]
dft_shell> set_dft_signal -type ScanDataOut -port scan_out[0:9]
dft_shell> set_dft_signal -type ScanEnable -port scan_en
dft_shell> set_dft_signal -type ScanClock -port clk_st \

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-timing [list 45 55] \

-view exist
dft_shell> set_dft_signal -view spec \
-port scan_compression_mode -type TestMode
dft_shell> set_dft_signal -view existing_dft -port test_mode \
-type Constant -active_state 1 -test_mode all
#######define test modes
dft_shell> define_test_mode is_mode
-encoding "scan_compression_mode 0" -usage scan
dft_shell> define_test_mode sc_mode \
-encoding "scan_compression_mode 1" \
-usage scan_compression
##############################################################
# DFTMAX COMPRESSION
##############################################################
dft_shell> set_dft_configuration -scan_compression enable
dft_shell> #internal scan
dft_shell> set_scan_configuration -test_mode is_mode -chain_count 3
dft_shell> #compression mode
dft_shell> set_scan_compression_configuration \
-chain_count 100 -inputs 10 \
-outputs 10 -test_mode sc_mode -modes 4
dft_shell> create_test_protocol
dft_shell> generate_dft
dft_shell> connect_dft
dft_shell> write_test_protocol -o ./des_unit_single.is.spf -test_mode
is_mode
dft_shell> write_test_protocol -o ./des_unit_single.sc.spf -test_mode
sc_mode
dft_shell> write_test_model -o ./des_unit_single.ctl
####################################################################
#Level 1
dft_shell> analyze -format verilog ./des_unit_single_DFTTopIP_0.v
dft_shell> analyze -format verilog ./dus_3x.v
dft_shell> elaborate dus_3x
dft_shell> set_top_module dus_3x
dft_shell> current_design dus_3x
dft_shell> read_test_model ./des_unit_single.ctl
dft_shell> link
##############################################
# Specify the dft signals #######
##############################################
dft_shell> set_dft_signal -type ScanDataIn -port scan_in[0:14]
dft_shell> set_dft_signal -type ScanDataOut -port scan_out[0:14]
dft_shell> set_dft_signal -type ScanEnable -port scan_en
dft_shell> set_dft_signal -type ScanClock \
-port dus_0_clk_st -timing [list 45 55] \
-view exist
dft_shell> set_dft_signal -type ScanClock \
-port dus_1_clk_st -timing [list 45 55] \
-view exist
dft_shell> set_dft_signal -type ScanClock \
-port dus_2_clk_st -timing [list 45 55] \

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-view exist
dft_shell> set_dft_signal -view spec
-port scan_compression_mode -type TestMode
dft_shell> set_dft_signal -view existing_dft -port test_mode \
-type Constant \
-active_state 1 -test_mode all
#######define test modes
dft_shell> define_test_mode is_mode -encoding "scan_compression_mode 0" \
-usage scan -target \
{dus_0 is_mode dus_1 is_mode dus_2 is_mode}
dft_shell> define_test_mode sc_mode -encoding "scan_compression_mode 1" \
-usage scan_compression \
-target {dus_0 sc_mode dus_1 sc_mode dus_2 sc_mode}
##############################################################
# DFTMAX COMPRESSION
##############################################################
dft_shell> set_dft_configuration -scan_compression enable
dft_shell> #internal scan
dft_shell> set_scan_configuration -test_mode is_mode -chain_count 9
dft_shell> #compression mode
dft_shell> set_scan_compression_configuration -integration_only true \
-shared_input 15 -shared_output 15 \
-test_mode sc_mode
dft_shell> create_test_protocol
dft_shell> generate_dft
dft_shell> connect_dft
dft_shell> write_test_protocol -o ./dus_3x.is.spf -test_mode is_mode
dft_shell> write_test_protocol -o ./dus_3x.sc.spf -test_mode sc_mode
dft_shell> write_test_model -o ./dus_3x.ctl

Sharing Codec Inputs With Dedicated Codec Outputs With

Identical Cores
To enable dedicated codec outputs with identical cores, ensure that all cores are identical
in a single group.
The value N specified with the -shared_output option is the full, unshared value (the sum
of all shared codec output widths).The following example shows the core-level and top-
level scripts:
dft_shell> #Level 0 \
#Core 0 scan compression configuration
dft_shell> set_scan_compression_configuration \
-chain_count 150 -inputs 6 -outputs 9
dft_shell> #Core 1 scan compression configuration
dft_shell> set_scan_compression_configuration \
-chain_count 150 -inputs 6 -outputs 9
####################################################################
#Level 1 scan compression configuration
dft_shell> set_scan_compression_configuration \

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-integration_only true \
-shared_input 6 -shared_output 18

Sharing Codec Inputs With Dedicated Codec Outputs With

Non-identical Cores
The TestMAX Manager tool supports shared scan-in with dedicated scan-outs for non-
identical codecs.
The non-identical codec must have the same number of scan inputs and scan outputs but
can have a different internal chain counts.
You must specify the -virtual_chain_count V option of the
set_scan_compression_configuration command. The value V is the maximum value
of the chain count of the cores in scan compression mode.
For example,
#Level 0
#Core 0 scan compression configuration
set_scan_compression_configuration -chain_count 150 -inputs 6 -outputs 9
#Core 1 scan compression configuration
set_scan_compression_configuration -chain_count 100 \
-inputs 6 -outputs 9 -virtual_chain_count 150
####################################################################
#Level 1 scan compression configuration
set_scan_compression_configuration -integration_only true \
-shared_input 6 -shared_output 18

Verifying the DFT IP at RTL Level

RTL testbench enables you to verify the functionality of the DFT IP at RTL level, before the
synthesis and the scan chain generation.
To verify the IP, generate a Verilog testbench and a VCS simulation. The simulation
verifies the following:
• DFT IP (RTL and gate Level)
• Top Level connections
• Protocol
Use the following flow to generate the RTL testbench:
1. Compute the test patterns based on the same modeling objects used for the IP
generation
2. Append the test patterns to the existing test protocol of the specified test mode

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3. Generate a STIL file.

4. Run MaxTestBench to generate the final Verilog testbench in serial only simulation
mode.

Figure 5 Flow for generating RTL testbench

Note:
See Limitations of the TestMAX Manager Tool for the features that are not
supported for RTL testbench.

Generating Test Patterns

Test patterns are generated automatically when you run the generate_dft command.
The following patterns are created for DFTMAX:
• Full observe pattern
• X-tolerance pattern
• Full random pattern
The following patterns are created for DFTMAX Ultra:
• Initialization pattern
• Full observe pattern
• Full random pattern
DFTMAX IP with SPC and DFTMAX ULTRA IP with SPC are supported by adding an
additional test pattern (or updating the initialization pattern) that fills all `1’ the SPC chain

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The following is an example of full observe pattern for multiple scan channels setup:

"pattern 0" : Call "pattern_counter_load" {

"si7" = 0101 \r28 0 ;
}
Call "occ_load" {
"si7" = \r8 0 ;
}
Call "jtag_reseed_setup" {
}
Call "reseed_load" {
"si0" = N01 \r16 0 N01 \r16 0 N01 \r16 0 ;
"si1" = \r57 0 ;
"si2" = \r57 0 ;
"si3" = \r21 0 1 \r18 0 1 \r9 0 1000010;
"si4" = 1 \r18 0 1 \r37 0 ;
"si5" = \r12 0 1 \r44 0 ;
"si6" = \r32 0 1 \r7 0 1 \r16 0 ;
"si7" = 001 \r18 0 1 \r17 0 11 \r16 0 ;
}
Call "reseed_load" {
"si0" = N \r5 0 1 \r12 0 N \r5 0 1 \r12 0 N100001 \r12 0 ;
"si1" = \r38 0 111 \r16 0 ;
"si2" = \r57 0 ;
"si3" = \r21 0 1 \r18 0 1 \r16 0 ;
"si4" = 1 \r18 0 1 \r37 0 ;
"si5" = \r57 0 ;
"si6" = \r40 0 1 \r16 0 ;
"si7" = 001 \r18 0 1 \r17 0 11 \r16 0 ;
}
Call "load_unload" {
"cnt_xlbist" := 140;
}
Call "misr_unload" {
"so0" = HLLLHH \r5 L HLHHL;
"so1" = HLLLHLLHLHHHLLLH;
"so2" = HH \r6 L HHLHHLHL;
"so3" = HLLHHLHHLHLHHLHH;
"so4" = HLLHLHLLLL \r6 H ;
"so5" = LHHHH \r8 L HHL;
}

Generating Verilog Testbench

Use the write_testbench command to generate the testbench.
write_testbench -output <tb_ name> \
-test_mode xlbist [-verbose]

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<tb_ name> is a mandatory argument that defines the base name of the Verilog testbench.
Two files are generated: <tb_ name>.v and <tb_ name>.dat.
The -verbose is an optional. The argument enables the verbose mode that displays the
STIL file name and the MaxTestBench run that generates the Verilog testbench.
The following example shows the generation of the Verilog testbench:
write_testbench -output dftshell_tb -test_mode \
ScanCompression_mode -verbose
Start creating RTL test patterns for mode ScanCompression_mode
Detected DFTMAX design with 1 partition/s
#3 test patterns were generated for partition nbr 0
Information: Generating STIL file
rtl_testbench_ScanCompression_mode.stil
Invoking stil2verilog...
stil2verilog rtl_testbench_ScanCompression_mode.stil dftshell_tb
-config ./maxtb_cfg.tcl -replace -ser_only2
STIL2VERILOG
Version R-2020.09-DEV-20200624 for linux64 - Jun 24, 2020
maxtb> Parsingcommand line...
maxtb> Info: SerialOnly2 format Verilog test bench is enabled by default.
(I-013)
maxtb> Reading configuration file "./maxtb_cfg.tcl".
maxtb> Configuration file correctly read.
maxtb> Checking for feature license...
maxtb> Parsing STIL file "rtl_testbench_ScanCompression_mode.stil" ...
maxtb> STIL file successfully interpreted (PatternExec:
"ScanCompression_mode").
maxtb> Total test patterns to process 3
maxtb> Warning: Detected Serial Only test patterns, the generated
testbench can only be run in serial simulation mode (W-030)
maxtb> Generating verilog test bench for serial load mode only. Parallel
load mode parameters will be ignored.
maxtb> Test data file "dftshell_tb.dat" generated successfully.
maxtb> Test bench file "dftshell_tb.v" generated successfully.
maxtb> Warning (W-030) occurred 1 time.
maxtb> Info (I-013) occurred 1 time.
maxtb> Memory usage: 9.54 Mbytes. CPU usage: 0.046 seconds.
maxtb> End.
Information: Testbench file 'dftshell_tb.v' generated successfully.

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8
Pipelined Scan Data
You can use the pipelined scan data feature to resolve delay problems associated with
long routes in compressed scan logic. Pipelined scan data is not limited to compressed
scan chain logic, it can be applied to internal_scan or uncompressed modes as well.
The following image displays the pipeline scan architecture:

To use pipelines in hierarchical flows you must have the same number of stages from
the scan into the decompressor inputs. For example, if you have one core with one pipe
and another core with two pipes you must add a balancing pipe stage to the first core. If
the requirement is to add five pipes at the top, then add three shared pipes in addition to
the five pipes. Therefore, after balancing all the pipelines of cores, you can use a shared
pipeline to meet the pipeline requirement of the top.
The pipeline stages for DFTMAX Ultra are as folllows:
• StreamingPipelineStages
• ExternalCyclesPerShift
• SerializerInputPipelineStages
• SerializerOutputPipelineStages

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Configuring Pipelined Scan Data

Configuring Pipelined Scan Data

To configure pipelined scan data, use the following commands:
dft_shell> set_dft_configuration -pipeline_scan_data enable
dft_shell> set_pipeline_scan_data_configuration \
-head_pipeline_clock clock_name \
-tail_pipeline_clock clock_name \
-head_pipeline_stages integer \
-tail_pipeline_stages integer \
-head_scan_flop false|true \
-tail_scan_flop true|false

You must use the set_dft_configuration -pipeline_scan_data enable command

before setting the pipeline configuration, otherwise, the tool generates an error.
If you are using a head or a tail pipeline, you must specify the clock to be used for the
pipeline scan flip-flop. If you do not specify the option, the tool generates the following
DFT-1015 error.
Error: The pipeline stage and the pipeline clock are required to enable
DFT tail pipelining (DFT-1015)

To view the pipeline specification report, use the report_dft -pipeline command:
dft_shell> report_dft -pipeline
Report : Pipeline Specification
Design : des_unit
Version: R-2020.09-SP6-DEV
Date : Mon May 31 16:24:41 2021
****************************************

Head Clock Name u_pll_1/pll_clk_1

Tail ClockName u_pll_1/pll_clk_1
Head Pipeline Stage 2
Tail Pipeline Stage 2
1

The polarity of lockup latches can change based on pipeline register clock.
Clock polarity of pipeline flops can be controlled using the following application option :
set_app_options \
-as_user_default \
-list {dft.put_negedge_head_pipeline_flops true|false}

During the generate_dft command, messages display the number of stages.

For example,
# Pipeline Clock
set_dft_signal -view existing -port clk1 \

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Adding Pipelines Before and After MUX From the Top-Level

-type ScanClock-timing [list 45 55]

set_pipeline_scan_data_configuration \
-head_pipeline_clock clk1 \
-tail_pipeline_clock clk1 \
-head_pipeline_stages 3 \
-tail_pipeline_stages 1
Accepted Pipeline configuration specification.
...
generate_dft
...
Information: Architecting Shared Head Pipeline with '3' stages
Information: Architecting Shared Tail Pipeline with '1' stages
...
Head Pipeline Clock:
"clk1" -> U_DFT_TOP_IP_0/h_pclkTail Pipeline Clock:
"clk1" -> U_DFT_TOP_IP_0/t_pclk

The test protocol file for Internal scan mode does not have any information related to the
pipeline register because it is not needed for this mode.
In the test protocol file, the compressor structures for compressed scan modes has the
following entry in the SPF for pipeline registers:
LoadPipelineStages - Indicates the number of head pipeline stages
UnloadPipelineStages - Indicates the number of tail pipeline stages

For example,
CompressorStructures {
Compressor "U_decompressor_ScanCompression_mode" {
LoadPipelineStages 3;
ModeGroup mode_group;
LoadGroup load_group;
…
Compressor "U_compressor_ScanCompression_mode" {
UnloadPipelineStages 1;
ModeGroup mode_group;
UnloadGroup unload_group;
UnloadModeGroup unload_mode_group0 unload_mode_group1;

Adding Pipelines Before and After MUX From the Top-Level

When the fabric MUX is used with the pipelined scan data feature, the tool adds pipeline
stages to meet the total top-level pipeline depth. Pipeline registers added along the shared
scan data path are called shared pipeline registers, and pipeline registers added along the
scan data path to a single codec are called dedicated pipeline registers.

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Figure 6 Pipelined Scan Data When the Fabric MUX is Used

Shared pipeline registers

Dedicated pipeline registers

By default, the tool adds an optimal number of shared pipeline registers as possible to
minimize cell count, and it uses dedicated pipeline registers only to balance cores of
differing depths. Figure 6 represents the shared pipeline registers when fabric MUX is
used.
In some cases, such as to adjust layout characteristics, you might want to change
the allocation of shared and dedicated pipeline registers. To do this, you can use the
-head_shared_pipeline_stages and -tail_shared_pipeline_stages options of the
set_pipeline_scan_data_configuration command:
set_pipeline_scan_data_configuration \
-head_pipeline_stages total_depth \
-tail_pipeline_stages total_depth \
-head_shared_pipeline_stages shared_depth \
-tail_shared_pipeline_stages shared_depth

The tool uses the specified number of shared pipeline registers along the shared scan
path, then it uses dedicated pipeline registers as needed for the remaining stages to meet
the total pipeline depth target. Figure 7 shows the previous example with a single shared
head and tail pipeline stage.

Figure 7 Using a Reduced Number of Shared Pipeline Register Stages

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Adding Pipelines Before and After MUX From the Top-Level

You can locate the codec from anywhere in the full chip. When you perform high speed
scan shifting, long routing lines are created depending on the location of the codec.
Therefore, pipeline stages are needed either before or after the fabric accordingly.
You can add the pipeline before and after MUX from the top-level. Use the
-head_shared_pipeline_stages and -tail_shared_pipeline_stages command
options for sharing pipelines before and after the fabric MUX.
Use the following example to configure the pipelines accordingly:
dft_shell> set_pipeline_scan_data_configuration \
-head_pipeline_stages 3 \
-head_pipeline_clock clk_st \
-tail_pipeline_stages 3 \
-tail_pipeline_clock clk_st \
-head_shared_pipeline_stages 1 \
-tail_shared_pipeline_stages 1 \
-head_scan_flop true \
-tail_scan_flop true

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9
Advanced DFT Architecture Methodology
This chapter describes the advanced DFT architecture, related methodology, and
processes in the following topics:
• Multiple Test Modes
• Defining Test Modes
• Defining the Usage of a Test Mode
• Defining the Encoding of a Test Mode
• Internal Pins Flow
• Core Wrapping
• Dedicated Core Wrapping
• Shared Core Wrapping
• Compressing Wrapper Chains
• IEEE 1500

Multiple Test Modes

You can reconfigure the scan chains in your design to suit various test requirements by
defining different modes of operation called test modes. Each test mode is activated by
asserting one or more test mode signals according to a particular test mode encoding.
Different test modes can have different scan-in and scan-out pin counts and can also have
independent sets of scan-in and scan-out pins.

Defining Test Modes

To define a test mode, use the define_test_mode command.
Each test mode must have a unique name that is used to refer to the test mode
in subsequent DFT commands or reports. The default standard scan test mode is
internal_scan.

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Defining the Usage of a Test Mode

You can either configure the default mode and define additional modes or you can create a
new set of named modes without using the default test mode.

Defining the Usage of a Test Mode

By default, a test mode represents a standard scan test mode of operation. To specify how
to use a test mode, define the -usage option of the define_test_mode command. The
valid keywords for this option are:
• scan - The traditional standard scan mode operation is the default if the -usage option
is not specified. The scan chains are driven directly by top-level scan-in ports and they
drive, in turn, top-level scan-out ports. This mode is used for testing all logic internal to
the core.
• scan_compression -The compressed scan mode of operation provided by the
DFTMAX compression. In this mode, the internal scan chains are driven by
combinational scan data decompressors and the scan chains drive the combinational
scan data compressors. This mode is used for testing all logic internal to the core with
reduced test data volume and test application time.
• streaming_compression - The compressed scan mode of operation provided by
DFTMAX Ultra compression. In this mode, the internal scan chains are driven by shift
register scan data decompressors and the scan chains drive the shift register scan
data compressors. This mode is used to test all logic that is internal to the core with
significantly reduced test data volume and test application time.
• wrp_if - This mode is an inward-facing uncompressed scan mode. The wrapper chain
is placed in the INTEST mode of operation. Both wrapper chains and internal core
chains are active.
• wrp_of - The outward facing or EXTEST mode of wrapper operation. This mode is
used for testing all logic external to the design. Wrappers are enabled and configured
to drive and capture data outside of the design. In this mode the internal chains are
disabled.
• wrp_of scan_compression - This mode is used for inserting a codec for the EXTEST
test mode.
Use the write_test_model -test_mode wrp_of command to create an EXTEST netlist.

Defining the Encoding of a Test Mode

Each test mode is activated by asserting one or more test mode signals according to a
particular encoding associated with that test mode. To declare these test mode signals,
use the set_dft_signal -type TestMode command.

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Internal Pins Flow

Internal Pins Flow

This topic describes the usage of internal pins to define signals. Advanced DFT
architectures with no straightforward path to a port might require some DFT signals to
connect to an internal pin. In such a case you can use the internal pins flow to define such
signals.
The following command is used to enable the internal pins flow:
dft_shell> set_dft_drc_configuration -internal_pins enable

If the internal pins flow is not enabled an error occurs when using this flow.
The option -hookup_pin can be used to hookup internal pins using the set_dft_signal
command.
When defining DFT signals, define each internal pins signal by using the -hookup_pin
option without -port option.
dft_shell> set_dft_signal -view spec -type TestMode \
-hookup_pin U_TEST_CTRL/TM_OUT[1]

dft_shell> set_dft_signal -view spec -type TestMode \

-hookup_pin U_TEST_CTRL/TM_OUT[0]

Core Wrapping
A core should always be wrapped to test core logic separately from top-level logic. A
wrapped core has a wrapper chain that allows the core to be isolated from the surrounding
logic. A wrapper chain is composed of wrapper cells inserted between the I/O ports and
the core logic of the design.
The TestMAX Manager tool supports the following core wrapping flows:
• Dedicated core wrapping
• Shared core wrapping
Core wrapping is primarily intended to wrap core data ports. The following ports are
excluded from wrapping:
• Functional and test clock ports
• Asynchronous set or reset signal ports
• Scan-input, scan-output, scan-enable, and other global test signal ports

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Core Wrapping

• Wrapper signal ports

• Any port with a constant test signal value defined
The wrapper chain operates in one of four modes - inactive, inward-facing, outward-facing,
or safe.
When core wrapping is enabled, the following core wrapping test modes are created by
default:
• wrp_if

• wrp_of

The following table lists the supported and unsupported options for the
set_wrapper_configuration command:

Supported Options Unsupported Options

reuse_threshold hier_wrapping

chain_count mix_with_scan_cell

test_mode use_system_clock_for_dedicated_wrp_cells

mix_cells gate_cells

depth_threshold add_wrapper_cells_to_power_domain

input_wrapper_cells partition

output_wrapper_cells ded_hier_path

scan_cells ded_hier_wrap_clock

safe_state feedthrough_chains

hold_mux_for_shared_wrapper_cells

To avoid a wrapper cell from being inserted on a port, you can use the
set_boundary_cell -type none -port command. To configure port-specific wrapper
settings, use the following command:
dft_shell> set_boundary_cell -class wrapper \
-ports [list port1 port 2] \
-type none

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The following table lists the supported and unsupported options for set_boundary_cell:

Supported Options Unsupported Options

class pins

type

port

location

instance

shift_clk

reuse_threshold

exclude

add_shared_wrapper_cell_only

For more information about the command and options used for core wrapping, refer to
Synthesis Manpages.

Dedicated Core Wrapping

Use the following command to enable dedicated core wrapping:
set_wrapper_configuration -reuse_threshold -1.

The value of the -reuse_threshold option to enable dedicated core wrapping is -1.
If you need to have a different wrapper shift signal for the input and output cells, you must
use the commands:
dft_shell> set_dft_signal -type input_wrp_shift \
-port input_wrapper_shift_signal \
-view specset_dft_signal -type output_wrp_shift \
-port output_wrapper_shift_signal \
-view spec

Here is an example script for dedicated core wrapping:

dft_shell> set_dft_configuration -wrapper enable
dft_shell> set_dft_signal -view spec \
-type wrp_shift -port my_wrp_shift
dft_shell> set_dft_signal -view exist -type wrp_clock -port wclk \
-timing [list 45 55] -test_mode all_dft
dft_shell> set_wrapper_configuration \

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-class core_wrapper -reuse_threshold -1

dft_shell> set_wrapper_configuration -chain_count 4
dft_shell> set_scan_configuration -chain 12 -test_mode wrp_if
dft_shell> set_boundary_cell -ports -type none -port i_rdata

Shared Core Wrapping

The TestMAX Manager tool supports the maximized reuse core wrapping flow to share
I/O registers that are connected to I/O ports through the combinational logic. Functional
registers are used as wrapper cells. The shared core wrapping reduces the area and
timing impact that might occur due to dedicated core wrapping.
The tool does not insert wrapper cells at the RTL level. The synthesis tools insert all
wrapper cells during scan synthesis. The tool generates the DFT top IP that contains the
DFT wrapper IP. During generate_dft, the commands and options that are required
for using the existing functional I/O registers for shared wrapper cells are added to the
constraint files written out during write_dft_constraints.
The TestMAX Manager tool supports core wrapping with DFTMAX, DFTMAX Ultra,
DFTMAX with XLBIST, DFTMAX Ultra with XLBIST configurations, and in XLBIST mode.
Use the following command to enable shared core wrapping:
dft_shell>set_wrapper_configuration -reuse_threshold <threshold_value>

The value of reuse_threshold in the set_wrapper_configuration command must be

greater than or equal to 0. For example:
dft_shell>set_wrapper_configuration -reuse_threshold 5

To specify the number of wrapper chains that the codec must support in the scan
compression mode, use the following command:
dft_shell>set_wrapper_configuration \
-chain_count <N>\
-test_mode Scan_compression_mode

M is the number of wrapper short chains that the codec should support in the scan
compression mode.
The tool specifies N/2 input and N/2 output wrapper chains automatically. For most
designs, the input wrapper chain count is not equal to the output wrapper chain count.
To specify the input and the output wrapper chain counts separately, use the following
command.
dft_shell> set_wrapper_configuration -input_chain_count <N1>
-output_chain_count <N2> -test_mode sccomp

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N1 is the number of input wrapper chains and N2 is the number of output wrapper chains.
To specify the number of wrapper chains to insert when implementing a XLBIST codec,
use the following configuration:
dft_shell> set_wrapper_configuration \
-chain_count <X>\
-test_mode {wrp_of_extest_mode_name}

dft_shell> set_wrapper_configuration \
-chain_count <Y> \
-test_mode {XLBIST_test_mode_name}

X is the number of wrapper chains to insert in the extest mode (wrp_of). Y is the number of
wrapper short chains to insert in the codec in the XLBIST mode, and Y>=X>0.
Note:
In a scenario where XLBIST and scan compression modes exist the wrapper
chain count for scan compression mode is considered.
The following set_wrapper_configuration options are not supported for the XLBIST-
only shared wrapper configuration:
• mix_cells
• mix_with_scan_cells
• safe_state
• max_length

Compressing Wrapper Chains

This topic describes how to compress wrapper chains by inserting a dedicated codec for
EXTEST mode.
The EXTEST test mode provides dedicated access to wrapper chains. You specify the
EXTEST test mode using the wrp_of option. Furthermore, to insert a dedicated codec for
the EXTEST test mode, you use the wrp_of scan_compression option.
Note the following prerequisites to compress wrapper chains:
• To make sure that the different scan chains are correctly routed through the two
specified codecs, the INTEST mode wrapper chain count and the EXTEST mode
compression internal chain count should be the same.
• In the RTL flow, codec stump channels are used to build the stump chains for other
modes. This results to an order dependency on set_scan_compression commands.

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The codec with the highest internal chain count is specified first in the INTEST mode
codec. This order dependency does not exist for the combination of Fusion Compiler
and general multi mode.

Figure 8 EXTEST Codec Implementation

To enable the EXTEST codec in the Fusion Compiler tool, use the following application
option:
dft_shell> set_app_options -as_user_default\
–name dft.scan.enable_general_multimode_support
-value true

Define the dedicated inputs/outputs for wrapper:

dft_shell> set_dft_signal -view existing -type ScanDataIn
-port wrp_si[${i}] -test_mode [list wrp_of my_wrp_of]
dft_shell> set_dft_signal -view existing -type ScanDataOut
-port wrp_so[${i}] -test_mode [list wrp_of my_wrp_of]

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The following example shows how to define the EXTEST codec to the
compressed_wrp_of test mode.
dft_shell> define_test_mode compressed_wrp_of \
-usage {wrp_of scan_compression} \
-encoding [list TM1 1 TM2 0 TM3 1]

The following example describes the EXTEST codec wrapper configuration for the
compressed_wrp_of test mode.
dft_shell> set_wrapper_configuration -reuse_threshold -1
dft_shell> set_wrapper_configuration -chain_count $ext_sc \
-test_mode [list compressed_wrp_of]
dft_shell> set_wrapper_configuration -chain_count $wrp_channel_count \
-test_mode [list wrp_of]

The following example describes the EXTEST codec configuration:

dft_shell> set_scan_compression_configuration \
-input 2 \
-output 2 \
-chain_count $ext_sc \
-shift_power_groups true \
-shift_power_chain_length 10 \
-shift_power_disable SPC_DISABLE \
-shift_power_clock vl_sms_WRCK \
-test_mode [list my_wrp_of]
dft_shell> set_wrapper_configuration -chain_count $ext_sc \
-test_mode [list sccomp]

You can further include the compression_wrp_of test mode in the OCC chain and define
inputs and outputs for the compressed_wrp_of test mode by using the following example:
dft_shell> set_scan_path my_occ_chain \
-include_elements [list core_occ_ctrl_upper \
core_occ_ctrl_local rst_ctrl] \
-test_mode [list sccomp scan wrp_if compressed_wrp_of]

dft_shell> for {set i 0} {$i < $wrp_channel_count } {incr i} {

set_dft_signal -view existing
-type ScanDataIn
-port wrp_si[${i}]
-test_mode [list wrp_of compressed_wrp_of]
set_dft_signal -view existing
-type ScanDataOut
-port wrp_so[${i}]
-test_mode [list wrp_of compressed_wrp_of]

Note:
Use the following command write_test_protocol -test_mode my_wrp_of
-out ../outputs/des_unit.my_wrp_of.spf to write out the protocol file for
the EXTEST test mode.

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IEEE 1500

The following output displays when you run the generate_dft.log command for the
EXTEST codec configuration:
Information: Architecting DFT Extest Wrapper IP with '2' wrapper chains
in mode 'wrp_of'
Information: Architecting Streaming DFT Compressor IP with '7' inputs /
'7' outputs / '80' internal chains in mode 'sccomp'
Information: Architecting '2' Input Wrapper Chains / '2' Output Wrapper
Chains / '76' Scan Chains
Information: Architecting DFT Compressor IP with '2' inputs / '2'
outputs / '4' internal chains in mode 'my_wrp_of'
Information: Compressor will have 100% x-tolerance
Information: shift power control length is '10'
Information: Architecting DFT XLBist Compressor IP with '80' internal
chains in mode 'xlbist'
Information: Architecting '2' Input Wrapper Chains / '2' Output Wrapper
Chains / '76' Scan Chains

IEEE 1500
Using IEEE 1500 test-mode control logic provides a standard interface for test mode
control. You can use the IEEE 1500 insertion feature to add this IEEE 1500 test mode
control logic.
To use a DFT-inserted IEEE 1500 controller for test-mode control at the core level, first
enable 1500 insertion with the set_dft_configuration command and then define the
DFT signals:
dft_shell> set_dft_configuration -ieee_1500 enable

dft_shell> set_dft_signal -view spec -type WSI -port port

dft_shell> set_dft_signal -view spec -type WRSTN -port port -active_state

0

dft_shell> set_dft_signal -view spec -type WRCK -port port

dft_shell> set_dft_signal -view spec -type CaptureWR -port port

dft_shell> set_dft_signal -view spec -type ShiftWR -port port

dft_shell> set_dft_signal -view spec -type UpdateWR -port port
dft_shell> set_dft_signal -view spec -type SelectWIR -port port
dft_shell> set_dft_signal -view spec -type WSO -port port

The width of the instruction register can be defined using the following command:
dft_shell> set_ieee_1500_configuration -wir_width 4

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When you define your DFT signals, do not define the following test-mode signals, that are
driven by the test-mode core data register (TMCDR) bits instead:
• Test-mode signals for multiple test-mode selection
• On-chip clocking (OCC) controller test-mode signals and PLL bypass signals

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10
Limitations of the TestMAX Manager Tool
This chapter provides the list of limitations of the TestMAX Manager tool.
The TestMAX Manager tool does not consist of a GUI interface.
The following features are not supported:
• Retiming registers
• Pipeline scan enable
• Compressor pipeline
• Insertion of OCC at the top-level in hierarchical adaptive scan synthesis (HASS) flow
• DFT/MBIST IP insertion inside the VHDL modules
• Hierarchical core wrapping
Dedicated wrapper insertion is supported at any level that does not have a generate
block as a part of the hierarchical path. It is not supported below any generate
hierarchy in the RTL.
Limitations of the internal hookup pin in the set_dft_signal command:
• Instance pins inside generate hierarchy are not supported as hook-up pins.
• Complex ports such as multi-dimensional ports, interface ports, array of interface, or
structure ports are not supported, for the set_dft_signal command or for hook-up
pins in the following scenarios:
◦ Generate block
◦ Nested parameterized interface
◦ Task and functions inside parametrized interface
◦ Structure within interfaces
◦ Nested array of interfaces
• Escaped instance or port names are not supported as set_dft_signal or hook-up
pins.

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Unsupported RTL Constructs

The following features are not supported for generating Verilog testbench:
• Shift power controller supported with SPC disabled
• DFTMAX ULTRA XTOL patterns
• Scan fabric

Unsupported RTL Constructs

The following Verilog constructs are not supported:
• Local define or undef
The following module is an example of the local define module in a RTL construct:
define M1 5 // original macro value
module mod1
input P1 [`M1:0] // macro value 5
…
endmodule

`undef P
`define P 7 // change in macro value

module mod2
input P1 [`M1:0] // macro value 7
…
endmodule

• Gate primitives, such as bufand bufif1

• Analog Verliog
• Port size specification in module port list
The following example defines how a port size is specified in a module: module abc
( in1[1:0] , out1);

• Name clash between block level parameter and module level parameter
The following SystemVerilog constructs are not supported:
• Array of interface
• Complex ports such as multi-dimensional ports, interface, array of interface, or
structure ports are not supported in the test path for wrapper or OCC insertion. The
complex ports are also not supported in the test path for internal hook-up pin or the
set_dft_signal port.

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Unsupported RTL Constructs

• Parameterized Interface
Flow might not work if there are multiple instantiations of same interface with different
parameter values.
• Partially connected structure port and signal
The following example describes a partially connected structure port in a RTL
construct:
// struct declaration
typedef struct packed {
logic [OCP3_DATA_MSB:0] sdata;
logic [1:0] sresp;
} ocp3_sdata_t;

module test ( …)

// struct ports
output ocp3_sdata_t ocp3_sdata;
output ocp3_sdata_t ocp3_sdata1;

…..

assign ocp3_sdata = {SData, SResp}; // bus splitting of struct port

connections

u0 mid (
.data (SData),
.resp (SResp),
.sdata (ocp3_sdata1)

……
endmodule

• Generic SystemVerilog interfaces

A module that is instantiated multiple times with different interface modports are not
supported.
• Shortreal and real types
• External modules
The following example describes an external module in a RTL construct:

module extern4(in1, in2, out1, out2);

input [5:0] in1, in2;
output [7:0] out1;
output [14:0] out2;
extern module leaf(in1, in2, out1, out2);
leaf I1(.*);

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module leaf(.*);
input [5:0] in1, in2;
output [7:0] out1;
output [14:0] out2;
bot1 #(5, 7) I1(in1, in2, out1);
bot2 #(5, 14) I2(in1, in2, out2);
extern module bot1 #(parameter p1 = 8,
parameter p2 = 19)
(input signed [p1:0] in1, inputsigned [p1:0] in2,output
signed[p2:0] out1);
extern module bot2 #(parameter p1 = 8,
parameter p2 = 19)
(input signed [p1:0] in1, input
signed [p1:0] in2,
output signed [p2:0] out1);

module bot1(.*);
assign out1 = in1 & in2;
endmodule

module bot2(.*);
assign out1 = in1 * in2;
endmodule
endmodule
endmodule

• Nested module
The following example describes a nested module in a RTL construct:

module instan2 #(parameter p1 = 6, parameter p2 = 15)

(input signed [p1-1 : 0] in1,
input signed [p1-1 : 0] in2,
output signed [p2-1 : 0] out1);
wire [p2-1 :0] w1;
nested_mod1 I1();

module nested_mod1;
nested_mod2 #(p1, p2) I1(in1, in2, w1);
nested_mod2 #(p1, p2) I2(w1, w1, out1);

module nested_mod2 #(parameter p1 = 6,

parameter p2 = 15)
(input signed [p1-1 : 0] in1,
input signed [p1-1 : 0] in2,
output signed [p2-1 : 0] out1);
out1 = in1 * in2;
endmodule
endmodule
endmodule

• Glue logic interface

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The following example represents a glue logic interface in a RTL construct:

interface intf #(parameter BUS_WIDTH = 8,DATA

= 2)(input logic [0:BUS_WIDTH-1] data[DATA-1:0]);
logic [BUS_WIDTH-1:0] buffer[DATA-1:0];
logic [BUS_WIDTH-1:0] sum;
int count;

always @*
for(count = 0; count < DATA; count++)
buffer[count] = data[count];

initial
sum = '0;
endinterface

module instance4 #(parameter WIDTH1 = 2,WIDTH2 =

32)(input clk, input logic [0:WIDTH2-1]
data[WIDTH1-1:0], output [0:WIDTH2-1] sum);

int count;
intf #(WIDTH2,WIDTH1)inst(data);

always @(posedge clk)

begin
for(count = 0;count < WIDTH1; count++)
inst.sum = inst.sum + inst.data[count];
end

assign sum = inst.sum;

endmodule

• Type parameters
The following example represents type parameters in RTL construct:

extern module bot1(a, b, c);

extern module bot2 #(parameter p1 = 8, parameter typeTP = logic

[17:0])
(input [p1:0] a, input [p1:0] b,
output TP c);

module extern2(input [5:0] in1, input [5:0] in2,

output [9:0] out1, output [14:0] out2);
bot1 I1(in1, in2, out1);
bot2 #(5, logic [14:0]) I2(in1, in2, out2);
endmodule

module bot1(.*);
input [5:0] a, b;

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output [9:0] c;
assign c = a + b;
endmodule

module bot2(.*);
assign c = a * b;
endmodule

• Nested SystemVerilog interface(interface within an interface)

• Virtual SystemVerilog interface
The following example represents a nested SystemVerilog interface in a RTL construct:

module testbench(intf.tb tb_if);

virtual interface intf.tb local_if; //
virtual interface.
....
task read(virtual interface intf.tb l_if)
// As argument to task ....
initial
begin
Local_if = tb_if; // initializing virtual interface.
Local_if.cb.read <= 1; //writing to synchronous signal
read
read(Local_if); // passing interface to task.
end
endmodule

• Task and function inside SystemVerilog

The following example represents a task and functions inside a SystemVerilog in a RTL
construct:

interface intf_AB (input bit clk);

logic ack;
logic ready;
logic send;
logic [31:0] data;

task send_data (input logic send_signal,

input logic [31:0] data_bus);
... // actual task definition
endtask

... // rest of the interface definition here

endinterface

module moduleA (interface xyz);

...
xyz.send_data(send);

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...
endmodule

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A
Appendix
This appendix includes of the following topics:
• Flow From TestMAX Manager to Synthesis, Generating Patterns, and Simulating
Patterns
• TestMAX ATPG for DRC and ATPG
• Simulation
• Formal Verification
• Supported GenSys Commands and Options

Flow From TestMAX Manager to Synthesis, Generating Patterns,

and Simulating Patterns
This section explains the synthesis of DFT IP from the TestMAX Manager tool, DRC and
ATPG using the TestMAX ATPG tool with a scan-inserted netlist, and the simulation of
generated scan vectors.
The TestMAX Manager tool can write out the functional RTL with DFT IP. Along with the
updated RTL, the TestMAX Manager tool can also write out the SPF (protocol file) and
scan constraints for synthesis.

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TestMAX ATPG for DRC and ATPG

TestMAX ATPG for DRC and ATPG

The TestMAX ATPG tool is used for DRC in different test modes and subsequent pattern
generation.
The design netlist used in the TestMAX ATPG tool is the output netlist from synthesis and
scan insertion. The protocol file (SPF) comes from the TestMAX Manager tool.
The following is a template TestMAX ATPG command script to run DRC and ATPG:
read_netlist Verilog_libraries
read_netlist for_tmax.v
run_build
run_drc protocol_file_from_testmax_manager
set_atpg -verbose
set_atpg -min_ateclock_cycles number_of_ate_clock_cycles
add_faults -all
run_atpg -auto
run_sim
write_patterns serial_pattern_name -format stil \
-replace -compress gzip -serial
write_patterns parallel_pattern_name -format stil -replace \
-compress gzip -parallel -unified_stil_flow
write_testbench -input serial_pattern_name \

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Simulation

-output serial_verilog_testbench_name -replace

write_testbench -input parallel_pattern_name \
-output parallel_verilog_testbench_names -replace

Simulation
VCS simulation can be done using the scan vectors and Verilog testbench written out from
the TestMAX ATPG tool.
The following are the VCS commands to run serial and parallel simulations in zero-delay
mode (no timing):
## Serial Simulation
vcs -R -full64 -v ./for_tmax.v \
serial_testbench_name vcs_simulation_libraries \
-o simv_serial_stuck_stil_zd -Mdir=csrc_serial_stuck_stil_zd \
override_timescale=1ns/100ps \
+delay_mode_zero +tetramax +define+tetramax_serial \
-Marchive=512 +libext+.v\
-l serial_simulation_logfile_name
## Parallel Simulation
vcs -R -full64 -v ./for_tmax.v \
parallel_testbench_name vcs_simualtion_libraries \
-o simv_parallel_stuck_stil_zd -Mdir=csrc_parallel_stuck_stil_zd \
override_timescale=1ns/100ps \
+delay_mode_zero +tetramax +define+tetramax_parallel \
-Marchive=512 +libext+.v \
-l parallel_simulation_logfile_name

Formal Verification
To check the functional equivalence between your RTL with the DFT-inserted and
the instantiated RTL, use the formal verification constraint files generated by the
write_dft_constraints command with your formal verification tool. This formal
verification constraints file contains the constraints to put your design in Functional mode.
You still need to define the do not verify constraints if you have test-specific scan out ports
and so on to ensure your design is functionally equivalent.

Supported GenSys Commands and Options

This topic shows examples of GenSys commands and options that are supported in the
TestMAX Manager tool.
• set_default_port_name — Controls newly punched port names in generated RTL.

• set_parameter_instance — Sets a parameter value for an instance.

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Supported GenSys Commands and Options

• select_design — Selects a particular design(module).

• new_design — Creates a new design.

The following example shows the supported command and options to add connections to
ports and instances by using theadd_connection command:
add_connection -instance <inst/hierinst> -pin <p1> [-lsb <lsb>]
[-msb <msb>]\
-instance <inst/hierinst> -pin <p2> [-lsb <lsb>] [-msb <msb>]
[-name <netname>][-auto_uniquify]
add_connection -instance <inst/hierinst> -pin <p1> [-lsb <lsb>]
[-msb <msb>]\
-port <p2> [-lsb <lsb>] [-msb <msb>] [-name <netname>]
[-auto_uniquify]
add_connection -port <p1> [-lsb <lsb>] [-msb <msb>]\
-port <p2> [-lsb <lsb>] [-msb <msb>] [-name <netname>]
[-auto_uniquify]
add_connection -instance <inst/hierinst> -pin <p1> -tieoff {1'b0}
[-name <netname>] [-auto_uniquify]
add_connection -port <p1> -tieoff {1'b0} [-name <netname>]

The following example shows the supported commands and options to delete ports and
instances using the delete_connection command:
delete_connection -instance <inst1> -pin <p1> -instance <inst2> -pin <p2>
delete_connection -instance <inst1> -pin <p1> -port <p2>
delete_connection -port <p1> -port <p2>

The following example shows how to add an instance:

add_instance -name <instance name/hiername> -master <master name>
[-auto_uniquify]

The following example show how to add a port:

add_port -name scalar_port_name -direction <IN|OUT|INOUT>
add_port -name bus_port_name –direction <IN|OUT|INOUT> -lsb lsb_val -msb
msb_val

The following example shows how to uniquify an instance:

uniquify_instance –name <inst/hierinst> –master <new master name>

The following example shows how to select a design:

select_design –name <design name>

The following example shows how to read third-party IP RTL:

load_rtl <rtl_file_name/path>
load_rtl –enableSV <rtl_file_name/path>

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Supported GenSys Commands and Options

The following example shows how to copy a connection:

copy_connection -current_driver_inst <inst>
-current_driver_pin <pin/port> -new_driver_inst <inst> \
-new_driver_pin <pin/port> [-new_sink_inst <inst>
-new_sink_pin <pin/port>]

The following example shows how to create a new design:

new design <desname>

The following example shows how to define a port:

set_default_port_name -hierarchical_port_name
Expr(#si,#sp,#di,#dp,#sd,#dd,#netname,#xyz)

For more information about the commands, options and arguments, see GenSys Tcl
Commands Reference Guide.

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