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TMS570LS0432, TMS570LS0332
SPNS186B – OCTOBER 2012 – REVISED JUNE 2015

TMS570LS0x32 16- and 32-Bit RISC Flash Microcontroller

1 Device Overview

1.1
1
Features
• High-Performance Automotive-Grade • Multiple Communication Interfaces
Microcontroller for Safety-Critical Applications – Two CAN Controllers (DCANs)
– Dual CPUs Running in Lockstep • DCAN1 - 32 Mailboxes With Parity
– ECC on Flash and RAM Interfaces Protection
– Built-In Self-Test for CPU and On-Chip RAMs • DCAN2 - 16 Mailboxes With Parity
– Error Signaling Module With Error Pin Protection
– Voltage and Clock Monitoring • Compliant to CAN Protocol Version 2.0B
• ARM® Cortex®-R4 32-Bit RISC CPU – Multibuffered Serial Peripheral Interface
– Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline (MibSPI) Module
– 8-Region Memory Protection Unit (MPU) • 128 Words With Parity Protection
– Open Architecture With Third-Party Support – Two Standard Serial Peripheral Interface (SPI)
• Operating Conditions Modules
– 80-MHz System Clock – UART (SCI) Interface With Local Interconnect
Network (LIN 2.1) Interface Support
– Core Supply Voltage (VCC): 1.2-V Nominal
• Next Generation High-End Timer (N2HET) Module
– I/O Supply Voltage (VCCIO): 3.3-V Nominal
– Up to 19 Programmable Pins
– ADC Supply Voltage (VCCAD): 3.3-V Nominal
– 128-Word Instruction RAM With Parity
• Integrated Memory Protection
– Up to 384KB of Program Flash With ECC – Includes Hardware Angle Generator
– 32KB of RAM With ECC – Dedicated High-End Timer Transfer Unit (HTU)
– 16KB of Flash for Emulated EEPROM With With MPU
ECC • Enhanced Quadrature Encoder Pulse (eQEP)
• Hercules™ Common Platform Architecture Module
– Consistent Memory Map Across Family – Motor Position Encoder Interface
– Real-Time Interrupt (RTI) Timer (OS Timer) • 12-Bit Multibuffered Analog-to-Digital Converter
– 96-Channel Vectored Interrupt Module (VIM) (ADC) Module
– 2-Channel Cyclic Redundancy Checker (CRC) – 16 Channels
• Frequency-Modulated Phase-Locked Loop – 64 Result Buffers With Parity Protection
(FMPLL) With Built-In Slip Detector • Up to 45 General-Purpose Input/Output (GPIO)
• IEEE 1149.1 JTAG Boundary Scan and ARM Pins
CoreSight™ Components – 8 Dedicated Interrupt-Capable GPIO Pins
• Advanced JTAG Security Module (AJSM) • Package
– 100-Pin Quad Flatpack (PZ) [Green]

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS570LS0432, TMS570LS0332
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1.2 Applications
• Braking Systems (ABS and ESC) • Active Driver Assistance Systems
• Electric Power Steering (EPS) • Aerospace and Avionics
• Electric Pump Control • Railway Communications
• Battery-Management Systems • Off-road Vehicles

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1.3 Description
The TMS570LS0432/0332 device is a high-performance automotive-grade microcontroller for safety
systems. The safety architecture includes dual CPUs in lockstep, CPU and Memory BIST logic, ECC on
both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral
I/Os.
The TMS570LS0432/0332 device integrates the ARM Cortex-R4 CPU. The CPU offers an efficient
1.66 DMIPS/MHz, and has configurations that can run up to 80 MHz, providing up to 132 DMIPS. The
device supports the big-endian (BE32) format.
The TMS570LS0432/0332 device has 384KB and 256KB of integrated flash (respectively) and 32KB of
data RAM. Both the flash and RAM have single-bit error correction and double-bit error detection. The
flash memory on this device is a nonvolatile, electrically erasable, and programmable memory
implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (the same
level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates
with a system clock frequency of 80 MHz. The SRAM supports single-cycle read and write accesses in
byte, halfword, word, and double-word modes throughout the supported frequency range.
The TMS570LS0432/0332 device features peripherals for real-time control-based applications, including a
Next Generation High-End Timer (N2HET) timing coprocessor with up to 19 I/O terminals and a 12-bit
Analog-to-Digital Converter (ADC) supporting 16 inputs in the 100-pin package.
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a small instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs,
capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer
Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory.
A Memory Protection Unit (MPU) is built into the HTU.
The Enhanced Quadrature Encoder Pulse (eQEP) module is used for direct interface with a linear or
rotary incremental encoder to get position, direction, and speed information from a rotating machine as
used in high-performance motion and position-control systems.
The device has a 12-bit-resolution MibADC with 16 channels and 64 words of parity-protected buffer RAM.
The MibADC channels can be converted individually or can be grouped by software for sequential
conversion sequences. There are three separate groupings. Each sequence can be converted once when
triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when
compatibility with older devices or faster conversion time is desired.
The device has multiple communication interfaces: one MibSPI, two SPIs, one UART/LIN, and two
DCANs. The SPI provides a convenient method of serial high-speed communications between similar
shift-register type devices. The UART/LIN supports the Local Interconnect standard 2.1 and can be used
as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports
the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster communication protocol that
efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The
DCAN is ideal for applications operating in noisy and harsh environments (for example, automotive and
industrial applications) that require reliable serial communication or multiplexed wiring.
The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external
frequency reference to a higher frequency for internal use. The FMPLL provides one of the five possible
clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the
available clock sources and the device clock domains.
The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous
external clock on the ECLK pin. The ECLK frequency is a user-programmable ratio of the peripheral
interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of
the device operating frequency.

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The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt is
generated or the external nERROR pin is toggled when a fault is detected. The nERROR pin can be
monitored externally as an indicator of a fault condition in the microcontroller.
The I/O Multiplexing and Control Module (IOMM) allows the configuration of the input/output pins to
support alternate functions. See Table 4-17 for a list of the pins that support multiple functions on this
device.
With integrated safety features and a wide choice of communication and control peripherals, the
TMS570LS0432/0332 device is an ideal solution for real-time control applications with safety-critical
requirements.

Device Information (1)

PART NUMBER PACKAGE BODY SIZE
TMS570LS0432PZ LQFP (100) 14.00 mm × 14.00 mm
TMS570LS0332PZ LQFP (100) 14.00 mm × 14.00 mm
(1) For more information, see Section 9, Mechanical Packaging and Orderable Information.

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1.4 Functional Block Diagram

Figure 1-1 shows a functional block diagram of the device.

nTRST
TMS
DAP TCK
AJSM with RTCK
ICEPick
CCM-R4 Debug
TDI
TDO
Gasket

N2HET
VCCP Flash 128 Words N2HET[31:28, 26, 24:22, 20:16,
(A) 14, 12, 10, 8, 6, 4, 2, 0]
FLTP1 384KB Cortex-R4 with Parity
FLTP2 with ECC with MPU nRST
Cortex-R4
8 regions nPORRST
with MPU SYS TEST
RAM 8 regions ECLK
32KB GIOA[7:0]/INT[7:0]
with ECC GIO

HTU STC LINRX

LBIST
LIN LINTX
2 Regions
8 DCP MiBSPI1 MIBSPI1SIMO
with MPU 8 Transfer MIBSPI1SOMI
Groups MIBSPI1CLK
128 Buffers MIBSPI1nCS[3:0]
with Parity MIBSPI1nENA
BRIDGE
SPI2SIMO
SPI2SOMI
SPI2 SPI2CLK
SPI2nCS[0]
SCR
SPI3SIMO
SPI3SOMI
SPI3 SPI3CLK
SPI3nCS[3:0]
Peripheral
16KB CRC R4 Bridge
SPI3nENA
Flash for 2 Channel Slave I/F DCAN1
EEPROM PCR CAN1RX
32 Messages CAN1TX
w/ECC with Parity
OSCIN OSC DCAN2
OSCOUT
Kelvin_GND
PLL 16 Messages CAN2RX
CAN2TX
VCCPLL Clock RTI with Parity
VSSPLL Monitor
nERROR ESM VIM MiBADC ADIN[21, 20, 17, 16, 11:0]
96 Channel 64 Words ADEVT
VCCAD / ADREFHI
with Parity with Parity VSSAD / ADREFLO

IOMM DCC eQEP

eQEPA
eQEPB
eQEPS
eQEPI

A. The TMS570LS0332 device only supports 256KB Flash with ECC.

Figure 1-1. Functional Block Diagram

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Table of Contents
1 Device Overview ......................................... 1 6.9 Flash Memory ....................................... 50
1.1 Features .............................................. 1 6.10 Flash Program and Erase Timings for Program
1.2 Applications ........................................... 2 Flash ................................................ 52
1.3 Description ............................................ 3 6.11 Flash Program and Erase Timings for Data Flash .. 52
1.4 Functional Block Diagram ............................ 5 6.12 Tightly Coupled RAM Interface Module ............. 53
2 Revision History ......................................... 7 6.13 Parity Protection for Accesses to peripheral RAMs . 53
3 Device Comparison ..................................... 8 6.14 On-Chip SRAM Initialization and Testing ........... 54
4 Terminal Configuration and Functions ............. 9 6.15 Vectored Interrupt Manager ......................... 56
4.1 PZ QFP Package Pinout (100-Pin) ................... 9 6.16 Real-Time Interrupt Module ......................... 58
4.2 .................................
Terminal Functions 10 6.17 Error Signaling Module .............................. 59
4.3 Output Multiplexing and Control ..................... 16 6.18 Reset / Abort / Error Sources ....................... 63
4.4 Special Multiplexed Options ......................... 17 6.19 Digital Windowed Watchdog ........................ 64
5 Specifications .......................................... 18 6.20 Debug Subsystem ................................... 65
5.1 Absolute Maximum Ratings ......................... 18 7 Peripheral Information and Electrical
Specifications ........................................... 70
5.2 ESD Ratings ........................................ 18
7.1 Peripheral Legend................................... 70
5.3 Power-On Hours (POH) ............................. 18
7.2 Multibuffered 12-Bit Analog-to-Digital Converter .... 70
5.4 Recommended Operating Conditions ............... 19
7.3 General-Purpose Input/Output ...................... 78
5.5 Switching Characteristics Over Recommended
Operating Conditions for Clock Domains ........... 19 7.4 Enhanced High-End Timer (N2HET) ................ 79
5.6 Wait States Required ............................... 20 7.5 Controller Area Network (DCAN).................... 82
5.7 Power Consumption ................................ 21 7.6 Local Interconnect Network Interface (LIN) ......... 83
5.8 Thermal Resistance Characteristics for PZ ......... 22 7.7 Multibuffered / Standard Serial Peripheral Interface 84
5.9 Input/Output Electrical Characteristics .............. 22 7.8 Enhanced Quadrature Encoder (eQEP) ............ 94
5.10 Output Buffer Drive Strengths ...................... 23 8 Device and Documentation Support ............... 96
5.11 Input Timings ........................................ 24 8.1 Device Support ...................................... 96
5.12 Output Timings ...................................... 25 8.2 Documentation Support ............................. 99
6 System Information and Electrical 8.3 Related Links ........................................ 99
Specifications ........................................... 27 8.4 Community Resources .............................. 99
6.1 Voltage Monitor Characteristics ..................... 27 8.5 Trademarks.......................................... 99
6.2 Power Sequencing and Power-On Reset ........... 28 8.6 Electrostatic Discharge Caution ..................... 99
6.3 Warm Reset (nRST)................................. 30 8.7 Glossary ............................................. 99
6.4 ARM Cortex-R4 CPU Information ................... 31 8.8 Device Identification Code Register ............... 100
6.5 Clocks ............................................... 35 8.9 Die Identification Registers ....................... 100
6.6 Clock Monitoring .................................... 41 8.10 Module Certifications............................... 101
6.7 Glitch Filters ......................................... 43 9 Mechanical Packaging and Orderable
6.8 Device Memory Map ................................ 44 Addendum .............................................. 106
9.1 Packaging Information ............................. 106

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2 Revision History
Scope: Applicable updates to the Hercules™ TMS570 MCU device family, specifically relating to the
TMS570LS0432 devices, which are now in the production data (PD) stage of development have been
incorporated.

Changes from April 30, 2014 to June 30, 2015 (from A Revision (April 2014) to B Revision) Page

• Updated/Changed section title to "Device Overview" ........................................................................... 1

• Added Section 1.3 (Description): Added paragraph describing IOMM ....................................................... 4
• Section 1.3 (Description): Added the Device Information table ................................................................. 4
• Figure 1-1 (Functional Block Diagram): Added flash footnote .................................................................. 5
• Added Section 3, Device Comparison ............................................................................................. 8
• Section 5 (Specifications): Updated/Changed section title .................................................................... 18
• Section 5.2 (ESD Ratings): Added section ...................................................................................... 18
• Section 5.3 (Power-On Hours (POH)): Added table (new) .................................................................... 18
• Table 5-4 (Selectable 8mA/2mA Control): Clarified impact of SPI2PC9 register on drive strength of SPI2SOMI
pin in footnote ........................................................................................................................ 23
• Section 6.4.1 (Summary of ARM Cortex-R4 CPU Features): Added Quantity of Breakpoints and Watchpoints ...... 31
• Section 6.20.3 (JTAG Identification Code): Added a table showing JTAG ID code for each silicon revision. .......... 65
• Table 7-7 (MibADC Operating Characteristics ): Added missing footnote for ZSET 10-/12-bit modes. ................... 74
• Section 7.7.1 (Features [MibSPI]): Updated/Changed size of SPI baud clock generator from "8-bit" to "11-bit"....... 84
• Section 8 (Device and Documentation Support): Updated/Changed section outline structure ........................... 96
• Section 8.1 (Device Support): Added section (new) ............................................................................ 96
• Section 8.1.1 (Development Support, Hardware Development Tools): Updated/Changed the JTAG-based
emulators specified ................................................................................................................. 96
• Section 8.1.2 (Device Nomenclature): Updated/Changed section title ....................................................... 97
• Section 8.1.2: Deleted the support tool development (TMDX/TMDS) references .......................................... 97
• Section 8.8 (Device Identification Code Register): Added silicon revision B device identification code ............... 100
• Section 8.9 (Die Identification Registers): Updated/Changed the DIEIDL and DIEIDH to point to the original
registers at location 0xFFFFFF7C and 0xFFFFFF80 ........................................................................ 100

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3 Device Comparison
Table 3-1 lists the features of the TMS570LS0432/0332 devices.

Table 3-1. TMS570LS0432/0332 Device Comparison (1) (2)

FEATURES DEVICES
Generic Part (3)
TMS570LS1227ZWT TMS570LS0714ZWT TMS570LS0714PGE TMS570LS0714PZ TMS570LS0432PZ (3) TMS570LS0332PZ TMS570LS0232PZ
Number
Package 337 BGA 337 BGA 144 QFP 100 QFP 100 QFP 100 QFP 100 QFP
CPU ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4 ARM Cortex-R4 ARM Cortex-R4
Frequency (MHz) 180 180 160 100 80 80 80
Flash (KB) 1280 768 768 768 384 256 128
RAM (KB) 192 128 128 128 32 32 32
Data Flash
64 64 64 64 16 16 16
[EEPROM] (KB)
EMAC 10/100 – – – – – –
FlexRay 2-ch – – – – – –
CAN 3 3 3 2 2 2 2
MibADC
2 (24ch) 2 (24ch) 2 (24ch) 2 (16ch) 1 (16ch) 1 (16ch) 1 (16ch)
12-bit (Ch)
N2HET (Ch) 2 (44) 2 (44) 2 (40) 2 (21) 1 (19) 1 (19) 1 (19)
ePWM Channels 14 14 14 8 – – –
eCAP Channels 6 6 6 4 0 0 0
eQEP Channels 2 2 2 1 1 1 1
MibSPI (CS) 3 (6 + 6 + 4) 3 (6 + 6 + 4) 3 (5 + 6 + 4) 2 (5 + 1) 1 (4) 1 (4) 1 (4)
SPI (CS) 2 (2 + 1) 2 (2 + 1) 1 (1) 1 (1) 2 2 2
SCI (LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 1 (with LIN) 1 (with LIN) 1 (with LIN) 1 (with LIN)
I2C 1 1 1 – – – –

(4) 101 (with 16 101 (with 16 64 (with 10 45 (with 9 45 (with 8 45 (with 9 45 (with 8
GPIO (INT)
interrupt capable) interrupt capable) interrupt capable) interrupt capable) interrupt capable) interrupt capable) interrupt capable)
EMIF 16-bit data – – – – – –
ETM (Trace) – – – – – – –
RTP/DMM – – – – – – –
Operating
–40ºC to 125ºC –40ºC to 125ºC –40ºC to 125ºC –40ºC to 125ºC –40ºC to 125ºC –40ºC to 125ºC –40ºC to 125ºC
Temperature
Core Supply (V) 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V
I/O Supply (V) 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V

(1) For additional device variants, see www.ti.com/tms570

(2) This table reflects the maximum configuration for each peripheral. Some functions are multiplexed and not all pins are available at the
same time.
(3) Superset device
(4) Total number of pins that can be used as general-purpose input or output when not used as part of a peripheral.

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4 Terminal Configuration and Functions

4.1 PZ QFP Package Pinout (100-Pin)
Figure 4-1 shows the 100-pin PZ QFP package pinout.

73 MIBSPI1nCS[0]

MIBSPI1nENA

MIBSPI1SIMO
MIBSPI1SOMI
MIBSPI1C LK

N2HET[024]
SPI2SOMI
SPI2SIMO
N2HET[8]

ADIN[11]
SPI2CLK

CAN1RX
CAN1T X

ADIN[8]
ADIN[6]
ADIN[5]
ADIN[4]

ADIN[3]
ADIN[2]
ADEVT
VCCIO
TMS

VCC
VSS

VSS
75
74

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50 ADIN[10]
nTRST 76
49 ADIN[1]
TDI 77
48 ADIN[9]
TDO 78
47
79 VSSAD/ADREFLO
TCK 46 VCCAD/ADREFHI
RTCK 80
45 ADIN[21]
nRST 81
44 ADIN[20]
nERROR 82
43 ADIN[7]
N2HET[10] 83
42 ADIN[0]
ECLK 84
41 ADIN[17]
VCCIO 85
40 ADIN[16]
VSS 86
39 MIBSPI1nCS[3]
VSS 87
38 SPI3nCS[0]
VCC 88
37 SPI3nENA
N2HET[12] 89 SPI3CLK
36
N2HET[14] 90
35 SPI3SIMO
CAN2TX 91
34 SPI3SOMI
CAN2RX 92
33 VSS
MIBSPI1nCS[1] 93
32 VCC
LINRX 94
31 nPORRST
LINTX 95
30 VCC
VCCP 96
29 VSS
N2HET[16] 97
28 VCCIO
N2HET[18] 98
27 MIBSPI1nCS[2]
VCC 99
26 N2HET[6]
VSS 100
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
FLTP 1

VCCIO

TEST
N2HET[4]
GIOA[3]
GIOA[4]
GIOA[5]
N2HET[022]
GIOA[6]
VC C
OSCIN
KELVIN_GN D

VC C
GIOA[0]
GIOA[1]

GIOA[2]
FLTP2

VSS

VSS
GIOA[7]
N2HET[0]

N2HET[2]
OSCOUT

SPI2nCS[0]
VSS

Figure 4-1. PZ QFP Package Pinout (100-Pin)

Note: Pins can have multiplexed functions. Only the default function is depicted in Figure 4-1.

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4.2 Terminal Functions

Table 4-1 through Table 4-16 identify the external signal names, the associated pin numbers along with
the mechanical package designator, the pin type (Input, Output, I/O, Power, or Ground), whether the pin
has any internal pullup/pulldown, whether the pin can be configured as a GPIO, and a functional pin
description.

NOTE
In the Terminal Functions table below, the "Reset Pull State" is the state of the pull applied to
the terminal while nPORRST is low and immediately after nPORRST goes High. The default
pull direction may change when software configures the pin for an alternate function. The
"Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given
terminal by the IOMM control registers.

All I/O signals except nRST are configured as inputs while nPORRST is low and
immediately after nPORRST goes High. While nPORRST is low, the input buffers
are disabled, and the output buffers are disabled with the default pulls enabled.

All output-only signals have the output buffer disabled and the default pull enabled
while nPORRST is low, and are configured as outputs with the pulls disabled
immediately after nPORRST goes High.

4.2.1 High-End Timer (N2HET)

Table 4-1. High-End Timer (N2HET)

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION
TYPE PULL
SIGNAL NAME 100
STATE
PZ
N2HET[0] 19 I/O Pulldown Programmable, Timer input capture or output compare. The
20 µA N2HET applicable terminals can be programmed
N2HET[2] 22
as general-purpose input/output (GPIO).
N2HET[4] 25 Each terminal has a suppression filter with a
N2HET[6] 26 programmable duration.

N2HET[8] 74
N2HET[10] 83
N2HET[12] 89
N2HET[14] 90
N2HET[16] 97
MIBSPI1nCS[1]/EQEPS/ 93
N2HET[17]
N2HET[18] 98
MIBSPI1nCS[2]/N2HET[20]/ 27
N2HET[19]
MIBSPI1nCS[2]/N2HET[20]/ 27
N2HET[19]
N2HET[22] 11
N2HET[24] 64
MIBSPI1nCS[3]/N2HET[26] 39
ADEVT/N2HET[28] 58
GIOA[7]/N2HET[29] 18
MIBSPI1nENA/N2HET[23]/ 68
N2HET[30]
GIOA[6]/SPI2nCS[1]/N2HET[31] 12

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4.2.2 Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 4-2. Enhanced Quadrature Encoder Pulse Modules (eQEP)

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION
TYPE PULL
SIGNAL NAME 100
STATE
PZ
SPI3CLK/EQEPA 36 Input Pullup Fixed 20 µA Enhanced QEP Input A
SPI3nENA/EQEPB 37 Input Enhanced QEP Input B
SPI3nCS[0]/EQEPI 38 I/O Enhanced QEP Index
MIBSPI1nCS[1]/EQEPS/N2HET 93 I/O Enhanced QEP Strobe
[17]

4.2.3 General-Purpose Input/Output (GPIO)

Table 4-3. General-Purpose Input/Output (GPIO)

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION
TYPE PULL
SIGNAL NAME 100
STATE
PZ
GIOA[0]/SPI3nCS[3] 1 I/O Pulldown Programmable, General-purpose input/output
20 µA All GPIO terminals can generate interrupts to the
GIOA[1]/SPI3nCS[2] 2
CPU on rising/falling/both edges.
GIOA[2]/SPI3nCS[1] 5
GIOA[3]/SPI2nCS[3] 8
GIOA[4]/SPI2nCS[2] 9
GIOA[5]/EXTCLKIN 10
GIOA[6]/SPI2nCS[1]/N2HET[31] 12
GIOA[7]/N2HET[29] 18

4.2.4 Controller Area Network Interface Modules (DCAN1, DCAN2)

Table 4-4. Controller Area Network Interface Modules (DCAN1, DCAN2)

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION
TYPE PULL
SIGNAL NAME 100
STATE
PZ
CAN1RX 63 I/O Pullup Programmable, CAN1 Receive, or general-purpose I/O (GPIO)
20 µA
CAN1TX 62 CAN1 Transmit, or GPIO
CAN2RX 92 CAN2 Receive, or GPIO
CAN2TX 91 CAN2 Transmit, or GPIO

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4.2.5 Multibuffered Serial Peripheral Interface (MibSPI1)

Table 4-5. Multibuffered Serial Peripheral Interface (MibSPI1)

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION
TYPE PULL
SIGNAL NAME 100
STATE
PZ
MIBSPI1CLK 67 I/O Pullup Programmable, MibSPI1 Serial Clock, or GPIO
20 µA
MIBSPI1nCS[0] 73 MibSPI1 Chip Select, or GPIO
MIBSPI1nCS[1]/EQEPS/N2HET 93
[17]
MIBSPI1nCS[2]/N2HET[20]/N2 27
HET[19]
MIBSPI1nCS[3]/N2HET[26] 39
MIBSPI1nENA/N2HET[23]/N2H 68 MibSPI1 Enable, or GPIO
ET[30]
MIBSPI1SIMO 65 MibSPI1 Slave-In-Master-Out, or GPIO
MIBSPI1SOMI 66 MibSPI1 Slave-Out-Master-In, or GPIO

4.2.6 Standard Serial Peripheral Interface (SPI2)

Table 4-6. Standard Serial Peripheral Interface (SPI2)

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION
TYPE PULL
SIGNAL NAME 100
STATE
PZ
SPI2CLK 71 I/O Pullup Programmable, SPI2 Serial Clock, or GPIO
20 µA
SPI2nCS[0] 23 SPI2 Chip Select, or GPIO
GIOA[6]/SPI2nCS[1]/N2HET[31] 12
GIOA[4]/SPI2nCS[2] 9
GIOA[3]/SPI2nCS[3] 8
SPI2SIMO 70 SPI2 Slave-In-Master-Out, or GPIO
SPI2SOMI 69 SPI2 Slave-Out-Master-In, or GPIO
The drive strengths for the SPI2CLK, SPI2SIMO, and SPI2SOMI signals are selected individually by configuring the respective SRS bits of
the SPIPC9 register fo SPI2.
SRS = 0 for 8-mA drive (fast). This is the default mode as the SRS bits in the SPIPC9 register default to 0.
SRS = 1 for 2-mA drive (slow)
SPI3CLK/EQEPA 36 I/O Pullup Programmable, SPI3 Serial Clock, or GPIO
20 µA
SPI3nCS[0]/EQEPI 38 SPI3 Chip Select, or GPIO
GIOA[2]/SPI3nCS[1] 5
GIOA[1]/SPI3nCS[2] 2
GIOA[0]/SPI3nCS[3] 1
SPI3nENA/EQEPB 37 SPI3 Enable, or GPIO
SPI3SIMO 35 SPI3 Slave-In-Master-Out, or GPIO
SPI3SOMI 34 SPI3 Slave-Out-Master-In, or GPIO

4.2.7 Local Interconnect Network Controller (LIN)

Table 4-7. Local Interconnect Network Controller (LIN)

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION
TYPE PULL
SIGNAL NAME 100
STATE
PZ
LINRX 94 I/O Pullup Programmable, LIN Receive, or GPIO
20 µA
LINTX 95 LIN Transmit, or GPIO

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4.2.8 Multibuffered Analog-to-Digital Converter (MibADC)

Table 4-8. Multibuffered Analog-to-Digital Converter (MibADC)

TERMINAL SIGNAL TYPE RESET PULL TYPE DESCRIPTION
PULL
SIGNAL NAME 100
STATE
PZ
ADEVT/N2HET[28] 58 I/O Pullup Programmable, ADC event trigger or GPIO
20 µA
ADIN[0] 42 Input N/A None Analog inputs
ADIN[1] 49
ADIN[2] 51
ADIN[3] 52
ADIN[4] 54
ADIN[5] 55
ADIN[6] 56
ADIN[7] 43
ADIN[8] 57
ADIN[9] 48
ADIN[10] 50
ADIN[11] 53
ADIN[16] 40
ADIN[17] 41
ADIN[20] 44
ADIN[21] 45
VCCAD/ADREFHI 46 Input/Power N/A None ADC high reference level/ADC operating supply
VSSAD/ADREFLO 47 Input/Ground N/A None ADC low reference level/ADC supply ground

4.2.9 System Module

Table 4-9. System Module

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION
TYPE PULL
SIGNAL NAME 100
STATE
PZ
ECLK 84 I/O Pulldown Programmable, External prescaled clock output, or GPIO.
20 µA
GIOA[5]/EXTCLKIN 10 Input Pulldown 20 µA External Clock In
nPORRST 31 Input Pulldown 100 µA Power-on reset, cold reset External power supply
monitor circuitry must drive nPORRST low when
any of the supplies to the microcontroller fall out
of the specified range. This terminal has a glitch
filter.
nRST 81 I/O Pullup 100 µA The external circuitry can assert a system reset
by driving nRST low. To ensure that an external
reset is not arbitrarily generated, TI recommends
that an external pullup resistor is connected to
this terminal. This terminal has a glitch filter.

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4.2.10 Error Signaling Module (ESM)

Table 4-10. Error Signaling Module (ESM)

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION
TYPE PULL
SIGNAL NAME 100
STATE
PZ
nERROR 82 I/O Pulldown 20 µA ESM error signal. Indicates error of high severity.

4.2.11 Main Oscillator

Table 4-11. Main Oscillator

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION
TYPE PULL
SIGNAL NAME 100
STATE
PZ
OSCIN 14 Input N/A None From external crystal/resonator, or external clock
input
OSCOUT 16 Output N/A None To external crystal/resonator
KELVIN_GND 15 Input N/A None Dedicated ground for oscillator

4.2.12 Test/Debug Interface

Table 4-12. Test/Debug Interface

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION
TYPE PULL
SIGNAL NAME 100
STATE
PZ
nTRST 76 Input Pulldown Fixed, 100 µA JTAG test hardware reset
RTCK 80 Output N/A None JTAG return test clock
TCK 79 Input Pulldown Fixed, 100 µA JTAG test clock
TDI 77 I/O Pullup Fixed, 100 µA JTAG test data in
TDO 78 Output Fixed, None JTAG test data out
100-µA
Pulldown
TMS 75 I/O Pullup Fixed, 100 µA JTAG test select
TEST 24 I/O Pulldown Fixed, 100 µA Test enable. This terminal must be connected to
ground directly or through a pulldown resistor.

4.2.13 Flash

Table 4-13. Flash

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION
TYPE PULL
SIGNAL NAME 100
STATE
PZ
FLTP1 3 Input N/A None Flash test pins. For proper operation this terminal
must connect only to a test pad or not be
FLTP2 4 Input N/A None
connected at all [no connect (NC)].
The test pad must not be exposed in the final
product where it might be subjected to an ESD
event.
VCCP 96 3.3-V N/A None Flash external pump voltage (3.3 V). This
Power terminal is required for both flash read and flash
program and erase operations.

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4.2.14 Core Supply

Table 4-14. Core Supply

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION
TYPE PULL
SIGNAL NAME 100
STATE
PZ
VCC 13 1.2-V N/A None Digital logic and RAM supply
Power
VCC 21
VCC 30
VCC 32
VCC 61
VCC 88
VCC 99

4.2.15 I/O Supply

Table 4-15. I/O Supply

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION
TYPE PULL
SIGNAL NAME 100
STATE
PZ
VCCIO 6 3.3-V N/A None I/O supply
Power
VCCIO 28
VCCIO 60
VCCIO 85

4.2.16 Core and I/O Supply Ground Reference

Table 4-16. Core and I/O Supply Ground Reference

TERMINAL SIGNAL RESET PULL TYPE DESCRIPTION
TYPE PULL
SIGNAL NAME 100
STATE
PZ
VSS 7 Ground N/A None Device Ground Reference. This is a single
ground reference for all supplies except for the
VSS 17
ADC supply.
VSS 20
VSS 29
VSS 33
VSS 59
VSS 72
VSS 86
VSS 87
VSS 100

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4.3 Output Multiplexing and Control

Output multiplexing will be used in the device. The multiplexing is used to allow development of additional
package and feature combinations as well as to maintain pinout compatibility with the marketing device
family.
In all cases indicated as multiplexed, the output buffers are multiplexed.

4.3.1 Notes on Output Multiplexing

Table 4-17 shows the output signal multiplexing and control signals for selecting the desired functionality
for each pin.
• The pins default to the signal defined by the DEFAULT FUNCTION column in Table 4-17
• The CONTROL 1, CONTROL 2, and CONTROL 3 columns indicate the multiplexing control register and the bit
that must be set in order to select the corresponding functionality to be output on any particular pin.
For example, consider the multiplexing on pin 18, shown in Table 4-18 .

Table 4-17. Output Mux Options

DEFAULT
100 PZ PIN CONTROL 1 OPTION2 CONTROL 2 OPTION 3 CONTROL 3
FUNCTION
1 GIOA[0] PINMMR0[8] SPI3nCS[3] PINMMR0[9] – –
2 GIOA[1] PINMMR1[0] SPI3nCS[2] PINMMR1[1] – –
5 GIOA[2] PINMMR1[8] SPI3nCS[1] PINMMR1[9] – –
8 GIOA[3] PINMMR1[16] SPI2nCS[3] PINMMR1[17] – –
9 GIOA[4] PINMMR1[24] SPI2nCS[2] PINMMR1[25] – –
10 GIOA[5] PINMMR2[0] EXTCLKIN PINMMR2[1] – –
12 GIOA[6] PINMMR2[8] SPI2nCS[1] PINMMR2[9] N2HET[31] PINMMR2[10]
18 GIOA[7] PINMMR2[16] N2HET[29] PINMMR2[17] – –
93 MIBSPI1nCS[1] PINMMR6[8] EQEPS PINMMR6[9] N2HET[17] PINMMR6[10]
27 MIBSPI1nCS[2] PINMMR3[0] N2HET[20] PINMMR3[1] N2HET[19] PINMMR3[2]
39 MIBSPI1nCS[3] PINMMR4[8] N2HET[26] PINMMR4[9] – –
68 MIBSPI1nENA PINMMR5[8] N2HET[23] PINMMR5[9] N2HET[30] PINMMR5[10]
36 SPI3CLK PINMMR3[16] EQEPA PINMMR3[17] – –
38 SPI3nCS[0] PINMMR4[0] EQEPI PINMMR4[1] – –
37 SPI3nENA PINMMR3[24] EQEPB PINMMR3[25] – –
58 ADEVT PINMMR4[16] N2HET[28] PINMMR4[17] – –

Table 4-18. Muxing Example

100 PZ PIN DEFAULT CONTROL 1 OPTION2 CONTROL 2 OPTION 3 CONTROL 3
FUNCTION
18 GIOA[7] PINMMR2[16] N2HET[29] PINMMR2[17] – –

• When GIOA[7] is configured as an output pin in the GPIO module control register, then the programmed output
level appears on pin 18 by default. The PINMMR2[16] bit is set by default to indicate that the GIOA[7] signal is
selected to be output.
• If the application must output the N2HET[29] signal on pin 18, it must clear PINMMR2[16] and set PINMMR2[17].
• The pin is connected as input to both the GPIO and N2HET modules. That is, there is no input multiplexing on this
pin.

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4.3.2 General Rules for Multiplexing Control Registers

• The PINMMR control registers can only be written in privileged mode. A write in a nonprivileged mode will
generate an error response.
• If the application writes all 0s to any PINMMR control register, then the default functions are selected for the
affected pins.
• Each byte in a PINMMR control register is used to select the functionality for a given pin. If the application sets
more than 1 bit within a byte for any pin, then the default function is selected for this pin.
• Some bits within the PINMMR registers could be associated with internal pads that are not brought out in the 100-
pin package. As a result, bits marked reserved should not be written as 1.

4.4 Special Multiplexed Options

Special controls are implemented to affect particular functions on this microcontroller. These controls are
described in this section.

4.4.1 Filtering for eQEP Inputs

4.4.1.1 eQEPA Input

• When PINMMR8[0] = 1, the eQEPA input is double-synchronized using VCLK.
• When PINMMR8[0] = 0 and PINMMR8[1] = 1, the eQEPA input is double-synchronized and then qualified through
a fixed 6-bit counter using VCLK.
• PINMMR8[0] = 0 and PINMMR8[1] = 0 is an illegal combination and behavior defaults to PINMMR8[0] = 1.

4.4.1.2 eQEPB Input

• When PINMMR8[8] = 1, the eQEPB input is double-synchronized using VCLK.
• When PINMMR8[8] = 0 and PINMMR8[9] = 1, the eQEPB input is double-synchronized and then qualified through
a fixed 6-bit counter using VCLK.
• PINMMR8[8] = 0 and PINMMR8[9] = 0 is an illegal combination and behavior defaults to PINMMR8[8] = 1.

4.4.1.3 eQEPI Input

• When PINMMR8[16] = 1, the eQEPI input is double-synchronized using VCLK.
• When PINMMR8[16] = 0 and PINMMR8[17] = 1, the eQEPI input is double-synchronized and then qualified
through a fixed 6-bit counter using VCLK.
• PINMMR8[16] = 0 and PINMMR8[17] = 0 is an illegal combination and behavior defaults to PINMMR8[16] = 1.

4.4.1.4 eQEPS Input

• When PINMMR8[24] = 1, the eQEPS input is double-synchronized using VCLK.
• When PINMMR8[24] = 0 and PINMMR8[25] = 1, the eQEPS input is double-synchronized and then qualified
through a fixed 6-bit counter using VCLK.
• PINMMR8[24] = 0 and PINMMR8[25] = 0 is an illegal combination and behavior defaults to PINMMR8[24] = 1.

4.4.2 N2HET PIN_nDISABLE Input Port

• When PINMMR9[0] = 1, GIOA[5] is connected directly to N2HET PIN_nDISABLE input of the N2HET module.
• When PINMMR9[0] = 0 and PINMMR9[1] = 1, EQEPERR is inverted and double-synchronized using VCLK before
connecting directly to the N2HET PIN_nDISABLE input of the N2HET module.
• PINMMR9[0] = 0 and PINMMR9[1] = 0 is an illegal combination and behavior defaults to PINMMR9[0] = 1.

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5 Specifications

5.1 Absolute Maximum Ratings (1)

Over Operating Free-Air Temperature Range
MIN MAX UNIT
VCC (2) –0.3 1.43
Supply voltage VCCIO, VCCP (2) –0.3 4.6 V
VCCAD –0.3 3.6
All input pins –0.3 4.6
Input voltage V
ADC input pins –0.3 4.6
IIK (VI < 0 or VI > VCCIO)
–20 20
All pins, except ADIN[21:20,17:16,11:0]
Input clamp current IIK (VI < 0 or VI > VCCAD) mA
–10 10
ADIN[21:20,17:16,11:0]
Total –40 40
Operating free-air
–40 125 °C
temperature, TA
Operating junction
–40 150 °C
temperature, TJ
Latch-up performance I-test, All I/O pins –100 100 mA
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated
grounds.

5.2 ESD Ratings

VALUE UNIT
Human Body Model (HBM), per AEC Q100-002 (1) ±2 kV
Electrostatic discharge (ESD) All pins except corner pins ±500 V
V(ESD) Charged Device Model (CDM),
performance:
per AEC Q100-011 Corner pins (1, 25, 26, 50, 51, 75,
±750 V
76, 100)
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS‑001 specification.

5.3 Power-On Hours (POH) (1) (2)

JUNCTION
NOMINAL CORE VOLTAGE (VCC) LIFETIME POH
TEMPERATURE (Tj)
1.2 105ºC 100K
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms
and conditions for TI semiconductor products.
(2) To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table. To convert to
equivalent POH for a specific temperature profile, see the Calculating Equivalent Power-on-Hours for Hercules Safety MCUs Application
Report (SPNA207).

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5.4 Recommended Operating Conditions (1)

MIN NOM MAX UNIT
VCC Digital logic supply voltage (Core) 1.14 1.2 1.32 V
VCCIO Digital logic supply voltage (I/O) 3 3.3 3.6 V
VCCAD / VADREFHI MibADC supply voltage / A-to-D high-voltage reference source 3 3.3 3.6 V
VCCP Flash pump supply voltage 3 3.3 3.6 V
VSS Digital logic supply ground 0 V
VSSAD / VADREFLO MibADC supply ground / A-to-D low-voltage reference source –0.1 0.1 V
VSLEW Maximum positive slew rate for VCCIO, VCCAD and VCCP supplies 1 V/µs
TA Operating free-air temperature –40 125 °C
TJ Operating junction temperature (2) –40 150 °C
(1) All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD
(2) Reliability data is based upon a temperature profile that is equivalent to 100,000 power-on hours at 105°C junction temperature.

5.5 Switching Characteristics Over Recommended Operating Conditions for Clock Domains

Table 5-1. Clock Domains Timing Specifications

PARAMETER CONDITIONS MIN MAX UNIT
fHCLK HCLK - System clock frequency 80 MHz
GCLK - CPU clock frequency (ratio fGCLK : fHCLK =
fGCLK fHCLK MHz
1:1)
fVCLK VCLK - Primary peripheral clock frequency 80 MHz
fVCLK2 VCLK2 - Secondary peripheral clock frequency 80 MHz
VCLKA1 - Primary asynchronous peripheral clock
fVCLKA1 80 MHz
frequency
fRTICLK RTICLK - clock frequency fVCLK MHz

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5.6 Wait States Required

The TCM RAM can support program and data fetches at full CPU speed without any address or data wait states
required. There are no registers which need to be programmed for RAM wait states.
The TCM flash can support zero address and data wait states up to a CPU speed of 45 MHz in nonpipelined
mode.The flash supports a maximum CPU clock speed of 80 MHz in pipelined mode with no address wait states
and one data wait state.
The proper wait states should be set in the register fields Address Setup Wait State Enable (ASWSTEN
0xFFF87000[4]), Random Wait states (RWAIT 0xFFF87000[11:8]), and Emulation Wait states (EWAIT
0xFFF872B8[19:16]) as shown in Figure 5-1.

Flash Address Wait States

ASWSTEN 0
0MHz 80MHz

Main Memory Data Wait States (Bank 0)

RWAIT 0 1
0MHz 45MHz 80MHz

EEPROM Emulation Memory Wait States (Bank 7)

EWAIT 1 2 3
0MHz 50MHz 67MHz 80MHz

Figure 5-1. Wait States Scheme

The flash wrapper defaults to nonpipelined mode with address wait states disabled, ASWSTEN=0; the main
memory random-read data wait state, RWAIT=1; and the emulation memory random-read wait states, EWAIT=1.

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5.7 Power Consumption

Over Recommended Operating Conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fHCLK = 80 MHz
VCC digital supply current (operating mode) fVCLK = 80 MHz, 135 (1)
Flash in pipelined
ICC mode, VCCmax mA
LBIST clock rate = (2) (3)
VCC digital supply current (LBIST mode) 145
45 MHz
PBIST ROM clock (2) (3)
VCC digital supply current (PBIST mode) 135
frequency = 80 MHz
ICCREFHI ADREFHI supply current (operating mode) ADREFHImax 3 mA
ICCAD VCCAD supply current (operating mode) VCCADmax
ICCIO VCCIO digital supply current (operating mode) No DC load, VCCmax 45 (4) mA
ICCP VCCP pump supply current Read mode
Read from one bank
ICCP, and program or
3.3-V supply current 65 (4) mA
ICCIO,ICCAD erase another,
VCCPmax
(1) The maximum ICC, value can be derated
• linearly with voltage
• by 0.76 mA/MHz for lower operating frequency when fHCLK= fVCLK
• for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.
60 - 0.001 e0.026 TJK
(2) The maximum ICC, value can be derated
• linearly with voltage
• for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.
60 - 0.001 e0.026 TJK
(3) LBIST and PBIST currents are for a short duration, typically less than 10 ms. They are usually ignored for thermal calculations for the
device and the voltage regulator
(4) Maximum current requirement of the three combined supplies

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5.8 Thermal Resistance Characteristics for PZ

Table 5-2 shows the thermal resistance characteristics for the PQFP - PZ mechanical packages.

Table 5-2. Thermal Resistance Characteristics

(S-PQFP Package) [PZ]
PARAMETER °C/W
RθJA 48
RθJC 5

5.9 Input/Output Electrical Characteristics (1)

Over Recommended Operating Conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vhys Input hysteresis All inputs 180 mV
(2)
VIL Low-level input voltage All inputs –0.3 0.8 V
VIH High-level input voltage All inputs (2) 2 VCCIO + 0.3 V
IOL = IOLmax 0.2 VCCIO
VOL Low-level output voltage IOL = 50 µA, V
standard output 0.2
mode
IOH = IOHmax 0.8 VCCIO
VOH High-level output voltage IOH = 50 µA, V
standard output VCCIO - 0.3
mode
VI < VSSIO - 0.3 or VI
IIC Input clamp current (I/O pins) –3.5 3.5 mA
> VCCIO + 0.3
IIH 20-µA pulldown VI = VCCIO 5 40
IIH 100-µA pulldown VI = VCCIO 40 195
IIL 20-µA pullup VI = VSS –40 –5
II Input current (I/O pins) µA
IIL 100-µA pullup VI = VSS –195 –40
No pullup or
All other pins –1 1
pulldown
CI Input capacitance 2 pF
CO Output capacitance 3 pF
(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.
(2) This does not apply to the nPORRST pin.

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5.10 Output Buffer Drive Strengths

Table 5-3. Output Buffer Drive Strengths

LOW-LEVEL OUTPUT CURRENT,
IOL for VI=VOLmax
or SIGNALS
HIGH-LEVEL OUTPUT CURRENT,
IOH for VI=VOHmin

EQEPI, EQEPS,
8 mA TMS, TDI, TDO, RTCK,
nERROR

TEST,
4 mA MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK, SPI3CLK, SPI3SIMO, SPI3SOMI,
nRST

AD1EVT,
CAN1RX, CAN1TX, CAN2RX, CAN2TX,
GIOA[0-7],

2 mA zero-dominant LINRX, LINTX,

MIBSPI1nCS[0-3], MIBSPI1nENA
N2HET[0], N2HET[2], N2HET[4], N2HET[6], N2HET[8], N2HET[10], N2HET[12], N2HET[14],
N2HET[16], N2HET[18], N2HET[22], N2HET[24],
SPI2nCS[0-3], SPI3nENA, SPI3nCS[0]

ECLK,
selectable 8 mA/ 2 mA SPI2CLK, SPI2SIMO, SPI2SOMI
The default output buffer drive strength is 8 mA for these signals.

Table 5-4. Selectable 8 mA/ 2 mA Control

SIGNAL CONTROL BIT ADDRESS 8 mA 2 mA
ECLK SYSPC10[0] 0xFFFF FF78 0 1
SPI2CLK SPI2PC9[9] 0xFFF7 F668 0 1
SPI2SIMO SPI2PC9[10] 0xFFF7 F668 0 1
SPI2SOMI SPI2PC9[11] (1) 0xFFF7 F668 0 1
(1) Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these 2 bits
differ, SPI2PC9[11] determines the drive strength.

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5.11 Input Timings

t pw
VCCIO
Input V IH VIH

VIL V IL
0

Figure 5-2. TTL-Level Inputs

Table 5-5. Timing Requirements for Inputs (1)

MIN MAX UNIT
(2)
tpw Input minimum pulse width tc(VCLK) + 10 ns
(1) tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK)
(2) The timing shown in Figure 5-2 is only valid for pin used in GIO mode.

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5.12 Output Timings

Table 5-6. Switching Characteristics for Output Timings versus Load Capacitance (CL)
PARAMETER MIN MAX UNIT
CL = 15 pF 2.5
CL = 50 pF 4
Rise time, tr
CL = 100 pF 7.2
CL = 150 pF 12.5
8-mA pins ns
CL = 15 pF 2.5
CL = 50 pF 4
Fall time, tf
CL = 100 pF 7.2
CL = 150 pF 12.5
CL = 15 pF 5.6
CL = 50 pF 10.4
Rise time, tr
CL = 100 pF 16.8
CL = 150 pF 23.2
4-mA pins ns
CL = 15 pF 5.6
CL= 50 pF 10.4
Fall time, tf
CL = 100 pF 16.8
CL = 150 pF 23.2
CL = 15 pF 8
CL = 50 pF 15
Rise time, tr
CL = 100 pF 23
CL = 150 pF 33
2-mA-z pins ns
CL = 15 pF 8
CL = 50 pF 15
Fall time, tf
CL = 100 pF 23
CL = 150 pF 33
CL = 15 pF 2.5
CL = 50 pF 4
Rise time, tr
CL = 100 pF 7.2
CL = 150 pF 12.5
8-mA mode
CL = 15 pF 2.5
CL = 50 pF 4
Fall time, tf
CL = 100 pF 7.2
Selectable 8-mA/ 2-mA-z CL = 150 pF 12.5
ns
pins CL = 15 pF 8
CL = 50 pF 15
Rise time, tr
CL = 100 pF 23
CL = 150 pF 33
2-mA-z mode
CL = 15 pF 8
CL = 50 pF 15
Fall time, tf
CL = 100 pF 23
CL = 150 pF 33

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tr tf
VCCIO
Output V OH VOH

VOL VOL
0

Figure 5-3. CMOS-Level Outputs

Table 5-7. Timing Requirements for Outputs (1)

PARAMETER MIN MAX UNIT
Delay between low-to-high, or high-to-low transition of general-purpose output
td(parallel_out) signals that can be configured by an application in parallel, for example, all signals in 5 ns
a GIOA port, or all N2HET signals.
(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check
Table 5-3 for output buffer drive strength information on each signal.

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6 System Information and Electrical Specifications

6.1 Voltage Monitor Characteristics
A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the
requirement for a specific sequence when powering up the core and I/O voltage supplies.

6.1.1 Important Considerations

• The voltage monitor does not eliminate the need of a voltage supervisor circuit to ensure that the
device is held in reset when the voltage supplies are out of range.
• The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other
supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a
source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and
VCCP supplies.

6.1.2 Voltage Monitor Operation

The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good
I/O signal (PGIO) on the device. During power up or power down, the PGMCU and PGIO are driven low
when the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and
PGMCU being low isolates the core logic as well as the I/O controls during the power up or power down of
the supplies. This allows the core and I/O supplies to be powered up or down in any order.
When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When
the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output
pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device
enters a low power mode.
The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.2.3.1 for the timing
information on this glitch filter.

Table 6-1. Voltage Monitoring Specifications

PARAMETER MIN TYP MAX UNIT
VCC low - VCC level below this
0.75 0.9 1.13
threshold is detected as too low.
VCC high - VCC level above this
Voltage monitoring 1.40 1.7 2.1
VMON threshold is detected as too high. V
thresholds
VCCIO low - VCCIO level below
this threshold is detected as too 1.85 2.4 2.9
low.

6.1.3 Supply Filtering

The VMON has the capability to filter glitches on the VCC and VCCIO supplies.
Table 6-2 shows the characteristics of the supply filtering. Glitches in the supply larger than the maximum
specification cannot be filtered.

Table 6-2. VMON Supply Glitch Filtering Capability

PARAMETER MIN MAX UNIT
Width of glitch on VCC that can be filtered 250 1000 ns
Width of glitch on VCCIO that can be filtered 250 1000 ns

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6.2 Power Sequencing and Power-On Reset

6.2.1 Power-Up Sequence

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-
up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (for more details,
see Table 6-4), core voltage rising above the minimum core supply threshold, and the release of power-on
reset. The high-frequency oscillator will start up first and its amplitude will grow to an acceptable level. The
oscillator start-up time is dependent on the type of oscillator and is provided by the oscillator vendor. The
different supplies to the device can be powered up in any order.
During power up, the device goes through the sequential phases listed in Table 6-3.

Table 6-3. Power-Up Phases

Oscillator start-up and validity check 1032 oscillator cycles
eFuse autoload 1160 oscillator cycles
Flash pump power up 688 oscillator cycles
Flash bank power up 617 oscillator cycles
Total 3497 oscillator cycles

The CPU reset is released at the end of this sequence and fetches the first instruction from address
0x00000000.

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6.2.2 Power-Down Sequence

The different supplies to the device can be powered down in any order.

6.2.3 Power-On Reset: nPORRST

This reset must be asserted by an external circuitry whenever the I/O or core supplies are outside the
recommended range. This signal has a glitch filter on it. It also has an internal pulldown.

6.2.3.1 nPORRST Electrical and Timing Requirements

Table 6-4. Electrical Requirements for nPORRST

NO. PARAMETER MIN MAX UNIT
VCC low supply level when nPORRST must be active during power
VCCPORL 0.5 V
up
VCC high supply level when nPORRST must remain active during
VCCPORH 1.14 V
power up and become active during power down
VCCIO / VCCP low supply level when nPORRST must be active
VCCIOPORL 1.1 V
during power up
VCCIO / VCCP high supply level when nPORRST must remain active
VCCIOPORH 3.0 V
during power up and become active during power down
VIL(PORRST) Low-level input voltage of nPORRST VCCIO > 2.5 V 0.2 * VCCIO V
Low-level input voltage of nPORRST VCCIO < 2.5 V 0.5 V
Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL
3 tsu(PORRST) 0 ms
during power up
6 th(PORRST) Hold time, nPORRST active after VCC > VCCPORH 1 ms
Setup time, nPORRST active before VCC < VCCPORH during power
7 tsu(PORRST) 2 µs
down
8 th(PORRST) Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH 1 ms
9 th(PORRST) Hold time, nPORRST active after VCC < VCCPORL 0 ms
Filter time nPORRST pin;
tf(nPORRST) Pulses less than MIN will be filtered out, pulses greater than MAX 475 2000 ns
will generate a reset.

3.3 V VCCIOPORH
VCCIOPORH VCCIO / VCCP
8

1.2 V VCCPORH
VCCPORH VCC
7
6
6
VCCIOPORL 7 VCCIOPORL
VCCPORL VCCPORL
VCC (1.2 V)
VCCIO / VCCP(3.3 V) 3 9
VIL(PORRST) VIL VIL VIL VIL(PORRST)
nPORRST
NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing.

Figure 6-1. nPORRST Timing Diagram

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6.3 Warm Reset (nRST)

This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset
condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the
output buffer is implemented as an open drain (drives low only). To ensure an external reset is not
arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. It also has an internal pullup

6.3.1 Causes of Warm Reset

Table 6-5. Causes of Warm Reset

DEVICE EVENT SYSTEM STATUS FLAG
Power-up reset Exception Status Register, bit 15
Oscillator fail Global Status Register, bit 0
PLL slip Global Status Register, bits 8 and 9
Watchdog exception / Debugger reset Exception Status Register, bit 13
CPU Reset (driven by the CPU STC) Exception Status Register, bit 5
Software reset Exception Status Register, bit 4
External reset Exception Status Register, bit 3

6.3.2 nRST Timing Requirements

Table 6-6. nRST Timing Requirements

MIN MAX UNIT
Valid time, nRST active after nPORRST inactive 2256tc(OSC) (1)
tv(RST) ns
Valid time, nRST active (all other system reset conditions) 32tc(VCLK)
Filter time nRST pin;
tf(nRST) Pulses less than MIN will be filtered out, pulses greater than MAX will 475 2000 ns
generate a reset
(1) Assumes the oscillator has started up and stabilized before nPORRST is released.

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6.4 ARM Cortex-R4 CPU Information

6.4.1 Summary of ARM Cortex-R4 CPU Features

The features of the ARM Cortex-R4 CPU include:
• An integer unit with integral Embedded ICE-RT logic.
• High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)
for Level two (L2) master and slave interfaces.
• Dynamic branch prediction with a global history buffer, and a 4-entry return stack
• Low interrupt latency.
• Nonmaskable interrupt.
• A Harvard Level one (L1) memory system with:
– Tightly Coupled Memory (TCM) interfaces with support for error correction or parity checking
memories
– ARMv7-R architecture Memory Protection Unit (MPU) with 8 regions
• Dual core logic for fault detection in safety-critical applications.
• An L2 memory interface:
– Single 64-bit master AXI interface
– 64-bit slave AXI interface to TCM RAM blocks
• A debug interface to a CoreSight Debug Access Port (DAP).
• Six Hardware Breakpoints
• Two Watchpoints
• A Perfomance Monitoring Unit (PMU)
• A Vectored Interrupt Controller (VIC) port.
For more information on the ARM Cortex-R4 CPU, see www.arm.com.

6.4.2 ARM Cortex-R4 CPU Features Enabled by Software

The following CPU features are disabled on reset and must be enabled by the application if required.
• ECC On Tightly Coupled Memory (TCM) Accesses
• Hardware Vectored Interrupt (VIC) Port
• Memory Protection Unit (MPU)

6.4.3 Dual Core Implementation

The device has two Cortex-R4 cores, where the output signals of both CPUs are compared in the CCM-
R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by 2 clock
cycles as shown in Figure 6-3.
The CPUs have a diverse CPU placement given by following requirements:
• Different orientation; for example, CPU1 = "north" orientation, CPU2 = "flip west" orientation
• Dedicated guard ring for each CPU

North Flip West

F
F

Figure 6-2. Dual - CPU Orientation

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6.4.4 Duplicate clock tree after GCLK

The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the 2nd CPU
running at the same frequency and in phase to the clock of CPU1. See Figure 6-3.

6.4.5 ARM Cortex-R4 CPU Compare Module (CCM) for Safety

This device has two ARM Cortex-R4 CPU cores, where the output signals of both CPUs are compared in
the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in
a different way as shown in Figure 6-3.

Output + Control

CCM-R4
2 cycle delay
CCM-R4 compare
CPU1CLK compare error

CPU 1 CPU 2

2 cycle delay

CPU2CLK

Input + Control

Figure 6-3. Dual Core Implementation

To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of
both CPUs before the registers are used, including function calls where the register values are pushed
onto the stack.

6.4.6 CPU Self-Test

The CPU STC (Self-Test Controller) is used to test the two Cortex-R4 CPU Cores using the Deterministic
Logic BIST Controller as the test engine.
The main features of the self-test controller are:
• Ability to divide the complete test run into independent test intervals
• Capable of running the complete test or running a few intervals at a time
• Ability to continue from the last executed interval (test set) or to restart from the beginning (first test
set)
• Complete isolation of the self-tested CPU core from the rest of the system during the self-test run
• Ability to capture the failure interval number
• Timeout counter for the CPU self-test run as a fail-safe feature

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6.4.6.1 Application Sequence for CPU Self-Test

1. Configure clock domain frequencies.
2. Select the number of test intervals to be run.
3. Configure the timeout period for the self-test run.
4. Save the CPU state if required
5. Enable self-test.
6. Wait for CPU reset.
7. In the reset handler, read CPU self-test status to identify any failures.
8. Retrieve CPU state if required.
For more information, see the TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller Technical
Reference Manual (SPNU517).

6.4.6.2 CPU Self-Test Clock Configuration

The maximum clock rate for the self-test is 45 MHz. The STCCLK is divided down from the CPU clock,
when necessary. This divider is configured by the STCCLKDIV register at address 0xFFFFE108.

6.4.6.3 CPU Self-Test Coverage

Table 6-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test
cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.

Table 6-7. CPU Self-Test Coverage

INTERVALS TEST COVERAGE, % TEST CYCLES
0 0 0
1 60.06 1365
2 68.71 2730
3 73.35 4095
4 76.57 5460
5 78.7 6825
6 80.4 8190
7 81.76 9555
8 82.94 10920
9 83.84 12285
10 84.58 13650
11 85.31 15015
12 85.9 16380
13 86.59 17745
14 87.17 19110
15 87.67 20475
16 88.11 21840
17 88.53 23205
18 88.93 24570
19 89.26 25935
20 89.56 27300
21 89.86 28665
22 90.1 30030
23 90.36 31395
24 90.62 32760

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Table 6-7. CPU Self-Test Coverage (continued)

INTERVALS TEST COVERAGE, % TEST CYCLES
25 90.86 34125
26 91.06 35490

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6.5 Clocks

6.5.1 Clock Sources

The table below lists the available clock sources on the device. Each of the clock sources can be enabled
or disabled using the CSDISx registers in the system module. The clock source number in the table
corresponds to the control bit in the CSDISx register for that clock source.
The table also shows the default state of each clock source.

Table 6-8. Available Clock Sources

CLOCK
SOURCE NAME DESCRIPTION DEFAULT STATE
NO.
0 OSCIN Main Oscillator Enabled
1 PLL1 Output From PLL1 Disabled
2 Reserved Reserved Disabled
3 EXTCLKIN1 External Clock Input #1 Disabled
4 CLK80K Low-Frequency Output of Internal Reference Oscillator Enabled
5 CLK10M High-Frequency Output of Internal Reference Oscillator Enabled
6 Reserved Reserved Disabled
7 Reserved Reserved Disabled

6.5.1.1 Main Oscillator

The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors
across the external OSCIN and OSCOUT pins as shown in Figure 6-4. The oscillator is a single stage
inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test
measurement and low power modes.
TI strongly encourages each customer to submit samples of the device to the resonator/crystal
vendors for validation. The vendors are equipped to determine what load capacitors will best tune
their resonator/crystal to the microcontroller device for optimum start-up and operation over
temperature/voltage extremes.
An external oscillator source can be used by connecting a 3.3 V clock signal to the OSCIN pin and leaving
the OSCOUT pin unconnected (open) as shown in Figure 6-4.

(see Note B)
OSCIN Kelvin_GND OSCOUT OSCIN OSCOUT
C1 C2
External
(see Note A) Clock Signal
(toggling 0 V to 3.3 V)

Crystal

(a) (b)

Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor.

Note B: Kelvin_GND should not be connected to any other GND.

Figure 6-4. Recommended Crystal/Clock Connection

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6.5.1.1.1 Timing Requirements for Main Oscillator

Table 6-9. Timing Requirements for Main Oscillator

PARAMETER MIN TYP MAX UNIT
tc(OSC) Cycle time, OSCIN (when using a sine-wave input) 50 200 ns
tc(OSC_SQR) Cycle time, OSCIN, (when input to the OSCIN is a square
50 200 ns
wave )
tw(OSCIL) Pulse duration, OSCIN low (when input to the OSCIN is a
15 ns
square wave)
tw(OSCIH) Pulse duration, OSCIN high (when input to the OSCIN is a
15 ns
square wave)

6.5.1.2 Low-Power Oscillator

The Low-Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO.

6.5.1.2.1 Features
The main features of the LPO are:
• Supplies a clock at extremely low power for power-saving modes. This is connected as clock source #
4 of the Global Clock Module.
• Supplies a high-frequency clock for nontiming-critical systems. This is connected as clock source # 5
of the Global Clock Module.
• Provides a comparison clock for the crystal oscillator failure detection circuit.

BIAS_EN

LFEN CLK80K

LF_TRIM

Low-Power
HFEN CLK10M
Oscillator
HF_TRIM CLK10M_VALID

nPORRST

Figure 6-5. LPO Block Diagram

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Figure 6-5 shows a block diagram of the internal reference oscillator. This is an LPO and provides two
clock sources: one nominally 80 kHz and one nominally 10 MHz.

6.5.1.2.2 LPO Electrical and Timing Specifications

Table 6-10. LPO Specifications

PARAMETER MIN TYP MAX UNIT
Oscillator fail frequency - lower threshold, using
1.375 2.4 4.875
untrimmed LPO output
Clock Detection MHz
Oscillator fail frequency - higher threshold, using
22 38.4 78
untrimmed LPO output
Untrimmed frequency 5.5 9 19.5 MHz
Trimmed frequency 8 9.6 11 MHz
LPO - HF oscillator
(fHFLPO) Start-up time from STANDBY (LPO BIAS_EN High for
10 µs
at least 900 µs)
Cold start-up time 900 µs
Untrimmed frequency 36 85 180 kHz
LPO - LF oscillator Start-up time from STANDBY (LPO BIAS_EN High for
100 µs
(fLFLPO) at least 900 µs)
Cold start-up time 2000 µs

6.5.1.3 Phase Locked Loop (PLL) Clock Modules

The PLL is used to multiply the input frequency to some higher frequency.
The main features of the PLL are:
• Frequency modulation can be optionally superimposed on the synthesized frequency of PLL.
• Configurable frequency multipliers and dividers.
• Built-in PLL Slip monitoring circuit.
• Option to reset the device on a PLL slip detection.

6.5.1.3.1 Block Diagram

Figure 6-6 shows a high-level block diagram of the PLL macro on this microcontroller.

OSCIN /NR INTCLK VCOCLK /OD post_ODCLK /R PLLCLK

PLL
/1 to /64 /1 to /8 /1 to /32

/NF fPLLCLK = (fOSCIN / NR) * NF / (OD * R)

/1 to /256

Figure 6-6. PLL Block Diagram

6.5.1.3.2 PLL Timing Specifications

Table 6-11. PLL Timing Specifications

PARAMETER MIN MAX UNIT
fINTCLK PLL1 Reference Clock frequency 1 20 MHz
fpost_ODCLK Post-ODCLK – PLL1 Post-divider input clock frequency 400 MHz
fVCOCLK VCOCLK – PLL1 Output Divider (OD) input clock frequency 150 550 MHz

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6.5.2 Clock Domains

6.5.2.1 Clock Domain Descriptions

Table 6-12 lists the device clock domains and their default clock sources. The table also shows the
system module control register that is used to select an available clock source for each clock domain.

Table 6-12. Clock Domain Descriptions

CLOCK SOURCE
CLOCK DOMAIN DEFAULT CLOCK
SELECTION DESCRIPTION
NAME SOURCE
REGISTER
HCLK OSCIN GHVSRC • Is disabled through the CDDISx registers bit 1
• Always the same frequency as HCLK
• In phase with HCLK
• Is disabled separately from HCLK through the CDDISx registers
GCLK OSCIN GHVSRC bit 0
• Can be divided by 1 up to 8 when running CPU self-test
(LBIST) using the CLKDIV field of the STCCLKDIV register at
address 0xFFFFE108
• Always the same frequency as GCLK
• 2 cycles delayed from GCLK
GCLK2 OSCIN GHVSRC • Is disabled along with GCLK
• Gets divided by the same divider setting as that for GCLK when
running CPU self-test (LBIST)
• Divided down from HCLK
• Can be HCLK/1, HCLK/2, ... or HCLK/16
VCLK OSCIN GHVSRC • Is disabled separately from HCLK through the CDDISx registers
bit 2
• Can be disabled separately for eQEP using CDDISx registers
bit 9
• Divided down from HCLK
• Can be HCLK/1, HCLK/2, ... or HCLK/16
VCLK2 OSCIN GHVSRC • Frequency must be an integer multiple of VCLK frequency
• Is disabled separately from HCLK through the CDDISx registers
bit 3
• Defaults to VCLK as the source
VCLKA1 VCLK VCLKASRC • Frequency can be as fast as HCLK frequency
• Is disabled through the CDDISx registers bit 4
• Defaults to VCLK as the source
• If a clock source other than VCLK is selected for RTICLK, then
the RTICLK frequency must be less than or equal to VCLK/3
RTICLK VCLK RCLKSRC
– Application can ensure this by programming the RTI1DIV
field of the RCLKSRC register, if necessary
• Is disabled through the CDDISx registers bit 6

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6.5.2.2 Mapping of Clock Domains to Device Modules

Each clock domain has a dedicated functionality as shown in the figure below.

GCM

0
OSCIN GCLK,GCLK2 (to CPU)
FMzPLL
/1 ...64 X1 ...256 /1 ...8 /1 ...32 * 1 HCLK (to SYSTEM)

80 kHz 4 VCLK (to System and

/1 ...16
Low Power Peripheral Modules)
Oscillator 10 MHz 5 /1 ...16 VCLK (to N2HET)
3
EXTCLKIN

*The frequency at this node must not

exceed the maximum HCLK frequency
0

1
3
AVCLK1 (to DCAN1, 2)
4

5
VCLK

0
1
3 /1,2,4, or 8

4
5 RTICLK (to RTI+DWWD)

VCLK
CDDISx.9

AVCLK1 VCLK

VCLK2 VCLK2

/1,2 HRP
/1,2 ...1024 /1,2 ...256 /2,3 ...224 /1,2 ...32 /1 ...64
...65536

HET TU eQEP
Phase_ LRP
Prop_seg
seg2
SPI LIN /20...27
Baud Rate ADCLK ECLK
Baud Rate
Phase_seg1
SPIx,MibSPIx LIN MibADC External Clock High Loop
Resolution Clock
CAN Baud Rate
N2HET
DCAN1, 2

Figure 6-7. Device Clock Domains

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6.5.3 Clock Test Mode

The TMS570 platform architecture defines a special mode that allows various clock signals to be brought
out on to the ECLK pin and N2HET[2] device outputs. This mode is called the Clock Test mode. It is very
useful for debugging purposes and can be configured through the CLKTEST register in the system
module.

Table 6-13. Clock Test Mode Options

CLKTEST[3-0] SIGNAL ON ECLK CLKTEST[11-8] SIGNAL ON N2HET[2]
0000 Oscillator 0000 Oscillator Valid Status
Main PLL free-running clock output
0001 0001 Main PLL Valid status
(PLLCLK)
0010 Reserved 0010 Reserved
0011 Reserved 0011 Reserved
0100 CLK80K 0100 Reserved
0101 CLK10M 0101 CLK10M Valid status
0110 Reserved 0110 Reserved
0111 Reserved 0111 Reserved
1000 GCLK 1000 CLK80K
1001 RTI Base 1001 Oscillator Valid status
1010 Reserved 1010 Oscillator Valid status
1011 VCLKA1 1011 Oscillator Valid status
1100 Reserved 1100 Oscillator Valid status
1101 Reserved 1101 Oscillator Valid status
1110 Reserved 1110 Oscillator Valid status
1111 Flash HD Pump Oscillator 1111 Oscillator Valid status

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6.6 Clock Monitoring

The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal low-
power oscillator (LPO).
The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO).
The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN
frequency falls out of a frequency window, the CLKDET flags this condition in the global status register
(GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp
mode clock).
The valid OSCIN frequency range is defined as: fHFLPO / 4 < fOSCIN < fHFLPO * 4.

6.6.1 Clock Monitor Timings

For more information on LPO and Clock detection, refer to Table 6-10.

lower upper
fail pass fail
threshold threshold

1.375 4.875 22 78 f[MHz]

Figure 6-8. LPO and Clock Detection, Untrimmed HFLPO

6.6.2 External Clock (ECLK) Output Functionality

The ECLK pin can be configured to output a prescaled clock signal indicative of an internal device clock.
This output can be externally monitored as a safety diagnostic.

6.6.3 Dual Clock Comparator

The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by
counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of
spec, an error signal is generated. For example, the DCC can be configured to use CLK10M as the
reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration
allows the DCC to monitor the PLL output clock when VCLK is using the PLL output as its source.

6.6.3.1 Features
• Takes two different clock sources as input to two independent counter blocks.
• One of the clock sources is the known-good, or reference clock; the second clock source is the "clock under test."
• Each counter block is programmable with initial, or seed values.
• The counter blocks start counting down from their seed values at the same time; a mismatch from the expected
frequency for the clock under test generates an error signal which is used to interrupt the CPU.

6.6.3.2 Mapping of DCC Clock Source Inputs

Table 6-14. DCC Counter 0 Clock Sources

TEST MODE CLOCK SOURCE [3:0] CLOCK NAME
Others Oscillator (OSCIN)
0 0x5 High-frequency LPO
0xA Test clock (TCK)
1 X VCLK

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Table 6-15. DCC Counter 1 Clock Sources

TEST MODE KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME
Others – N2HET[31]
Main PLL free-running clock
0x0
output
0x1 n/a
0x2 Low-frequency LPO
0 0xA 0x3 High-frequency LPO
0x4 Flash HD pump oscillator
0x5 EXTCLKIN
0x6 n/a
0x7 Ring oscillator
0x8 - 0xF VCLK
1 X X HCLK

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6.7 Glitch Filters

A glitch filter is present on the following signals.

Table 6-16. Glitch Filter Timing Specifications

PIN PARAMETER MIN MAX UNIT
ns
Filter time nPORRST pin;
nPORRST tf(nPORRST) 475 2000
pulses less than MIN will be filtered out, pulses greater than
MAX will generate a reset (1)
ns
Filter time nRST pin;
nRST tf(nRST) 475 2000
pulses less than MIN will be filtered out, pulses greater than
MAX will generate a reset
ns
Filter time TEST pin;
TEST tf(TEST) 475 2000
pulses less than MIN will be filtered out, pulses greater than
MAX will pass through
(1) The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump,
I/O pins, and so forth) without also generating a valid reset signal to the CPU.

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6.8 Device Memory Map

6.8.1 Memory Map Diagram

Figure 6-9 shows the device memory map.

0xFFFFFFFF
SYSTEM Modules
0xFFF80000
Peripherals - Frame 1
0xFFF7FFFF
0xFF000000 CRC
0xFE000000
RESERVED
0xFCFFFFFF
Peripherals - Frame 2
0xFC000000
RESERVED
0xF07FFFFF

Flash Module Bus2 Interface

(Flash ECC, OTP andEEPROM accesses)

0xF0000000

RESERVED

0x2005FFFF
Flash (384KB) (Mirrored Image)
0x20000000
RESERVED
0x08407FFF
RAM - ECC
0x08400000
RESERVED
0x08007FFF
RAM (32KB)
0x08000000
RESERVED
0x0005FFFF
Flash (384KB)
0x00000000

Figure 6-9. TMS570LS0432 Memory Map

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0xFFFFFFFF
SYSTEM Modules
0xFFF80000
Peripherals - Frame 1
0xFFF7FFFF
0xFF000000 CRC
0xFE000000
RESERVED
0xFCFFFFFF
Peripherals - Frame 2
0xFC000000
RESERVED
0xF07FFFFF

Flash Module Bus2 Interface

(Flash ECC, OTP andEEPROM accesses)

0xF0000000

RESERVED

0x2003FFFF
Flash (256KB) (Mirrored Image)
0x20000000
RESERVED
0x08407FFF
RAM - ECC
0x08400000
RESERVED
0x08007FFF
RAM (32KB)
0x08000000
RESERVED
0x0003FFFF
Flash (256KB)
0x00000000

Figure 6-10. TMS570LS0332 Memory Map

The Flash memory in all configurations is mirrored to support ECC logic testing. The base address of the
mirrored Flash image is 0x2000 0000.

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6.8.2 Memory Map Table

See Figure 1-1 for a block diagram showing the device interconnects.

Table 6-17. Device Memory Map

ADDRESS RANGE RESPONSE FOR ACCESS TO
FRAME CHIP FRAME ACTUAL
MODULE NAME UNIMPLEMENTED LOCATIONS IN
SELECT START END SIZE SIZE
FRAME
Memories tightly coupled to the ARM Cortex-R4 CPU
TCM Flash CS0 0x0000_0000 0x00FF_FFFF 16MB 384KB (1)
TCM RAM + RAM
CSRAM0 0x0800_0000 0x0BFF_3FFF 64MB 32KB
ECC Abort
Flash mirror
Mirrored Flash 0x2000_0000 0x20FF_FFFF 16MB 384KB (1)
frame
Flash Module Bus2 Interface
Customer OTP,
0xF000_0000 0xF000_07FF 2KB
TCM Flash Banks
64KB
Customer OTP,
0xF000_E000 0xF000_E3FF 1KB
EEPROM Bank
Customer
OTP–ECC, TCM 0xF004_0000 0xF004_00FF 256B
Flash Banks
8KB
Customer
OTP–ECC, 0xF004_1C00 0xF004_1C7F 128B
EEPROM Bank
TI OTP, TCM
0xF008_0000 0xF008_07FF 2KB
Flash Banks
64KB Abort
TI OTP, EEPROM
0xF008_E000 0xF008_E3FF 1KB
Bank
TI OTP–ECC,
0xF00C_0000 0xF00C_00FF 256B
TCM Flash Banks
8KB
TI OTP–ECC,
0xF00C_1C00 0xF00C_1C7F 128B
EEPROM Bank
EEPROM
0xF010_0000 0xF010_07FF 256KB 2KB
Bank–ECC
EEPROM Bank 0xF020_0000 0xF020_3FFF 2MB 16KB
Flash Data Space
0xF040_0000 0xF040_DFFF 1MB 48KB
ECC
Cyclic Redundancy Checker (CRC) Module Registers
CRC CRC frame 0xFE00_0000 0xFEFF_FFFF 16MB 512B Accesses above 0x200 generate abort.
Peripheral Memories
MIBSPI1 RAM PCS[7] 0xFF0E_0000 0xFF0F_FFFF 128KB 2KB Abort for accesses above 2KB
Wrap around for accesses to
unimplemented address offsets lower
DCAN2 RAM PCS[14] 0xFF1C_0000 0xFF1D_FFFF 128KB 2KB
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
Wrap around for accesses to
unimplemented address offsets lower
DCAN1 RAM PCS[15] 0xFF1E_0000 0xFF1F_FFFF 128KB 2KB
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
Wrap around for accesses to
MIBADC RAM 8KB unimplemented address offsets lower
than 0x1FFF.
PCS[31] 0xFF3E_0000 0xFF3F_FFFF 128KB Look-up table for ADC wrapper. Starts
at offset 0x2000 ans ends at 0x217F.
MIBADC Look-Up
384 bytes Wrap around for accesses between
Table
offsets 0x180 and 0x3FFF. Aborts
generated for accesses beyond 0x4000

(1) The TMS570LS0332 device has only 256KB of flash.

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Table 6-17. Device Memory Map (continued)

ADDRESS RANGE RESPONSE FOR ACCESS TO
FRAME CHIP FRAME ACTUAL
MODULE NAME UNIMPLEMENTED LOCATIONS IN
SELECT START END SIZE SIZE
FRAME
Wrap around for accesses to
unimplemented address offsets lower
N2HET RAM PCS[35] 0xFF46_0000 0xFF47_FFFF 128KB 16KB
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
HTU RAM PCS[39] 0xFF4E_0000 0xFF4F_FFFF 128KB 1KB Abort
Debug Components
CoreSight Debug Reads return zeros, writes have no
CSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KB
ROM effect
Reads return zeros, writes have no
Cortex-R4 Debug CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB
effect
Peripheral Control Registers
Reads return zeros, writes have no
HTU PS[22] 0xFFF7_A400 0xFFF7_A4FF 256B 256B
effect
Reads return zeros, writes have no
N2HET PS[17] 0xFFF7_B800 0xFFF7_B8FF 256B 256B
effect
Reads return zeros, writes have no
GIO PS[16] 0xFFF7_BC00 0xFFF7_BCFF 256B 256B
effect
Reads return zeros, writes have no
MIBADC PS[15] 0xFFF7_C000 0xFFF7_C1FF 512B 512B
effect
Reads return zeros, writes have no
DCAN1 PS[8] 0xFFF7_DC00 0xFFF7_DDFF 512B 512B
effect
Reads return zeros, writes have no
DCAN2 PS[8] 0xFFF7_DE00 0xFFF7_DFFF 512B 512B
effect
Reads return zeros, writes have no
LIN PS[6] 0xFFF7_E400 0xFFF7_E4FF 256B 256B
effect
Reads return zeros, writes have no
MibSPI1 PS[2] 0xFFF7_F400 0xFFF7_F5FF 512B 512B
effect
Reads return zeros, writes have no
SPI2 PS[2] 0xFFF7_F600 0xFFF7_F7FF 512B 512B
effect
Reads return zeros, writes have no
SPI3 PS[1] 0xFFF7_F800 0xFFF7_F9FF 512B 512B
effect
Reads return zeros, writes have no
EQEP PS[25] 0xFFF7_9900 0xFFF7_99FF 256B 256B
effect
Reads return zeros, writes have no
EQEP (Mirrored) PS2[25] 0xFCF7_9900 0xFCF7_99FF 256B 256B
effect
System Modules Control Registers and Memories
Wrap around for accesses to
unimplemented address offsets lower
VIM RAM PPCS2 0xFFF8_2000 0xFFF8_2FFF 4KB 1KB
than 0x3FF. Accesses beyond 0x3FF
will be ignored.
Flash Wrapper PPCS7 0xFFF8_7000 0xFFF8_7FFF 4KB 4KB Abort
eFuse Farm
PPCS12 0xFFF8_C000 0xFFF8_CFFF 4KB 4KB Abort
Controller
Reads return zeros, writes have no
PCR registers PPS0 0xFFFF_E000 0xFFFF_E0FF 256B 256B
effect
System Module -
Reads return zeros, writes have no
Frame 2 (see PPS0 0xFFFF_E100 0xFFFF_E1FF 256B 256B
effect
device TRM)
Reads return zeros, writes have no
PBIST PPS1 0xFFFF_E400 0xFFFF_E5FF 512B 512B
effect
Reads return zeros, writes have no
STC PPS1 0xFFFF_E600 0xFFFF_E6FF 256B 256B
effect
IOMM
Generates address error interrupt if
Multiplexing PPS2 0xFFFF_EA00 0xFFFF_EBFF 512B 512B
enabled.
control module

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Table 6-17. Device Memory Map (continued)

ADDRESS RANGE RESPONSE FOR ACCESS TO
FRAME CHIP FRAME ACTUAL
MODULE NAME UNIMPLEMENTED LOCATIONS IN
SELECT START END SIZE SIZE
FRAME
Reads return zeros, writes have no
DCC PPS3 0xFFFF_EC00 0xFFFF_ECFF 256B 256B
effect
Reads return zeros, writes have no
ESM PPS5 0xFFFF_F500 0xFFFF_F5FF 256B 256B
effect
Reads return zeros, writes have no
CCMR4 PPS5 0xFFFF_F600 0xFFFF_F6FF 256B 256B
effect
Reads return zeros, writes have no
RAM ECC even PPS6 0xFFFF_F800 0xFFFF_F8FF 256B 256B
effect
Reads return zeros, writes have no
RAM ECC odd PPS6 0xFFFF_F900 0xFFFF_F9FF 256B 256B
effect
Reads return zeros, writes have no
RTI + DWWD PPS7 0xFFFF_FC00 0xFFFF_FCFF 256B 256B
effect
Reads return zeros, writes have no
VIM Parity PPS7 0xFFFF_FD00 0xFFFF_FDFF 256B 256B
effect
Reads return zeros, writes have no
VIM PPS7 0xFFFF_FE00 0xFFFF_FEFF 256B 256B
effect
System Module -
Reads return zeros, writes have no
Frame 1 (see PPS7 0xFFFF_FF00 0xFFFF_FFFF 256B 256B
effect
device TRM)

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6.8.3 Master/Slave Access Privileges

The table below lists the access permissions for each bus master on the device. A bus master is a module
that can initiate a read or a write transaction on the device.
Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed
in the "MASTERS" column can access that slave module.

Table 6-18. Master / Slave Access Matrix

SLAVES ON MAIN SCR
Peripheral Control
Registers, All
Flash Module Bus2
MASTERS ACCESS MODE Non-CPU Accesses Peripheral
Interface:
to Program Flash CRC Memories, And All
OTP, ECC, EEPROM
and CPU Data RAM System Module
Bank
Control Registers
And Memories
CPU READ User/Privilege Yes Yes Yes Yes
CPU WRITE User/Privilege No Yes Yes Yes
HTU Privilege No Yes Yes Yes

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6.9 Flash Memory

6.9.1 Flash Memory Configuration

Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a
customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense
amplifiers, and control logic.
Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical
construction constraints.
Flash Pump: A charge pump which generates all the voltages required for reading, programming, or
erasing the flash banks.
Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.

Table 6-19. Flash Memory Banks and Sectors

SECTOR
MEMORY ARRAYS (or BANKS) SEGMENT LOW ADDRESS HIGH ADDRESS
NO.
0 8KB 0x0000_0000 0x0000_1FFF
1 8KB 0x0000_2000 0x0000_3FFF
2 8KB 0x0000_4000 0x0000_5FFF
3 8KB 0x0000_6000 0x0000_7FFF
4 8KB 0x0000_8000 0x0000_9FFF
5 8KB 0x0000_A000 0x0000_BFFF
6 8KB 0x0000_C000 0x0000_DFFF
BANK0 (384KB) (1) 7 8KB 0x0000_E000 0x0000_FFFF
8 8KB 0x0001_0000 0x0001_1FFF
9 8KB 0x0001_2000 0x0001_3FFF
10 8KB 0x0001_4000 0x0001_5FFF
11 8KB 0x0001_6000 0x0001_7FFF
12 32KB 0x0001_8000 0x0001_FFFF
13 128KB 0x0002_0000 0x0003_FFFF
14 (2) 128KB 0x0004_0000 0x0005_FFFF
0 4KB 0xF020_0000 0xF020_0FFF
1 4KB 0xF020_1000 0xF020_1FFF
BANK7 (16KB) for EEPROM emulation (3) (4)
2 4KB 0xF020_2000 0xF020_2FFF
3 4KB 0xF020_3000 0xF020_3FFF
(1) This Flash bank is 144-bit wide with ECC support.
(2) Sector 14 is not accessible or included in the TMS570LS0332 configuration.
(3) Flash bank7 is an FLEE bank and can be programmed while executing code from flash bank0. It is 72-bit wide with ECC support.
(4) Code execution is not allowed from flash bank7.

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6.9.2 Main Features of Flash Module

• Support for multiple flash banks for program and/or data storage
• Simultaneous read access on a bank while performing program or erase operation on any other bank
• Integrated state machines to automate flash erase and program operations
• Software interface for flash program and erase operations
• Pipelined mode operation to improve instruction access interface bandwidth
• Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4 CPU
– Error address is captured for host system debugging
• Support for a rich set of diagnostic features

6.9.3 ECC Protection for Flash Accesses

All accesses to the program flash memory are protected by Single Error Correction Double Error Detection
(SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of
instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on
the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is
corrected and flagged by the CPU, while a multibit error is only flagged. The CPU signals an ECC error
through its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting
the "X" bit of the Performance Monitor Control Register, c9.
MRC p15,#0,r1,c9,c12,#0 ;Enabling Event monitor states
ORR r1, r1, #0x00000010
MCR p15,#0,r1,c9,c12,#0 ;Set 4th bit (‘X’) of PMNC register
MRC p15,#0,r1,c9,c12,#0

The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM
and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC
checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN
bits of the System Control coprocessor's Auxiliary Control Register, c1.
MRC p15, #0, r1, c1, c0, #1
ORR r1, r1, #0x0e000000 ;Enable ECC checking for ATCM and BTCMs
DMB
MCR p15, #0, r1, c1, c0, #1

6.9.4 Flash Access Speeds

For information on flash memory access speeds and the relevant wait states required, see Section 5.6.

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6.10 Flash Program and Erase Timings for Program Flash

Table 6-20. Timing Specifications for Program Flash

PARAMETER MIN NOM MAX UNIT
tprog (144bit) Wide Word (144 bit) programming time 40 300 µs
-40°C to 125°C 4
tprog (Total) 384KByte programming time (1) 0°C to 60°C, for first s
1 2
25 cycles
-40°C to 125°C 0.30 4 s
terase Sector/Bank erase time (2) 0°C to 60°C, for first
16 100 ms
25 cycles
Write/erase cycles with 15 year Data Retention
twec -40°C to 125°C 1000 cycles
requirement
(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes
programming 144 bits at a time at the maximum specified operating frequency.
(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase
a sector.

6.11 Flash Program and Erase Timings for Data Flash

Table 6-21. Timing Specifications for Data Flash

PARAMETER MIN NOM MAX UNIT
tprog (72 bit) Wide Word (72 bit) programming time 47 300 µs
–40°C to 125°C 330
tprog (Total) 16KB programming time (1) 0°C to 60°C, for first ms
100 165
25 cycles
–40°C to 125°C 0.200 8 s
terase Sector/Bank erase time (2) 0°C to 60°C, for first
14 100 ms
25 cycles
Write/erase cycles with 15 year Data Retention
twec –40°C to 125°C 100000 cycles
requirement
(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes
programming 72 bits at a time at the maximum specified operating frequency.
(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase
a sector.

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6.12 Tightly Coupled RAM Interface Module

Figure 6-11 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4 CPU.
VBUSP I/F PMT I/F
36 Bit
Upper 32 bits data & 3636 Bit
Bit
wide
wide
Cortex-R4 4 ECC bits wideRAM
RAM
RAM
EVEN Address
TCM BUS TCRAM
B0
TCM Interface 1 36 Bit
64 Bit data bus 3636 Bit
Bit
wide
wide
wide
RAM
Lower 32 bits data & RAM
RAM
4 ECC bits

36 Bit
Upper 32 bits data & 3636 Bit
Bit
wide
B1 wide
wideRAM
ODD Address 4 ECC bits
TCM RAM
RAM
TCM BUS
TCRAM
64 Bit data bus Interface 2 36 Bit
3636 Bit
Bit
wide
wide
wideRAM
Lower 32 bits data & RAM
RAM
4 ECC bits

VBUSP I/F PMT I/F

Figure 6-11. TCRAM Block Diagram

6.12.1 Features
The features of the Tightly Coupled RAM (TCRAM) module are:
• Acts as slave to the BTCM interface of the Cortex-R4 CPU
• Supports CPU's internal ECC scheme by providing 64-bit data and 8-bit ECC code
• Monitors CPU Event Bus and generates single-bit or multibit error interrupts
• Stores addresses for single-bit and multibit errors
• Provides CPU address bus integrity checking by supporting parity checking on the address bus
• Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
• Provides enhanced safety for the RAM addressing by implementing two 36-bit wide byte-interleaved RAM banks
and generating independent RAM access control signals to the two banks
• Supports auto-initialization of the RAM banks along with the ECC bits
• No support for bit-wise RAM accesses

6.12.2 TCRAMW ECC Support

The TCRAMW passes on the ECC code for each data read by the Cortex-R4 CPU from the RAM. It also
stores the CPU's ECC port contents in the ECC RAM when the CPU does a write to the RAM. The
TCRAMW monitors the CPU's event bus and provides registers for indicating single-bit and multibit errors
and also for identifying the address that caused the single-bit or multibit error. The event signaling and the
ECC checking for the RAM accesses must be enabled inside the CPU.
For more information see the device Technical Reference Manual.

6.13 Parity Protection for Accesses to peripheral RAMs

Accesses to some peripheral RAMs are protected by odd/even parity checking. During a read access the
parity is calculated based on the data read from the peripheral RAM and compared with the good parity
value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates
a parity error signal that is mapped to the Error Signaling Module. The module also captures the
peripheral RAM address that caused the parity error.

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The parity protection for peripheral RAMs is not enabled by default and must be enabled by the
application. Each individual peripheral contains control registers to enable the parity protection for
accesses to its RAM.

NOTE
The CPU read access gets the actual data from the peripheral. The application can choose
to generate an interrupt whenever a peripheral RAM parity error is detected.

6.14 On-Chip SRAM Initialization and Testing

6.14.1 On-Chip SRAM Self-Test Using PBIST

6.14.1.1 Features
• Extensive instruction set to support various memory test algorithms
• ROM-based algorithms allow the application to run TI production-level memory tests
• Independent testing of all on-chip SRAM

6.14.1.2 PBIST RAM Groups

Table 6-22. PBIST RAM Grouping

TEST PATTERN (ALGORITHM)
MARCH 13N (1) MARCH 13N (1)
TRIPLE READ TRIPLE READ
TWO PORT SINGLE PORT
MEMORY RAM GROUP TEST CLOCK MEM TYPE SLOW READ FAST READ
(CYCLES) (CYCLES)
ALGO MASK ALGO MASK ALGO MASK ALGO MASK
0x1 0x2 0x4 0x8
PBIST_ROM 1 ROM CLK ROM X X
STC_ROM 2 ROM CLK ROM X X
DCAN1 3 VCLK Dual Port 12720
DCAN2 4 VCLK Dual Port 6480
RAM 6 HCLK Single Port 133160
MIBSPI1 7 VCLK Dual Port 33440
VIM 10 VCLK Dual Port 12560
MIBADC 11 VCLK Dual Port 4200
N2HET1 13 VCLK Dual Port 25440
HTU1 14 VCLK Dual Port 6480
(1) There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for
application testing.

The PBIST ROM clock can be divided down from HCLK. The divider is selected by programming the
ROM_DIV field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.

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6.14.2 On-Chip SRAM Auto Initialization

This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware
Initialization mechanism in the System module. This hardware mechanism allows an application to
program the memory arrays with error detection capability to a known state based on their error detection
scheme (odd/even parity or ECC).
The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects
the memories that are to be initialized.
For more information on these registers refer to the device Technical Reference Manual.
The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in
Table 6-23.

Table 6-23. Memory Initialization

ADDRESS RANGE MSINENA REGISTER
CONNECTING MODULE
BASE ADDRESS ENDING ADDRESS BIT NO. (1)
RAM 0x08000000 0x08007FFF 0
MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF 7 (2)
DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6
DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 5
MIBADC RAM 0xFF3E0000 0xFF3FFFFF 8
N2HET RAM 0xFF460000 0xFF47FFFF 3
HTU RAM 0xFF4E0000 0xFF4FFFFF 4
VIM RAM 0xFFF82000 0xFFF82FFF 2
(1) Unassigned register bits are reserved.
(2) The MibSPI1 module performs an initialization of the transmit and receive RAMs as soon as the module is brought out of reset using the
SPI Global Control Register 0 (SPIGCR0). This is independent of whether the application chooses to initialize the MibSPI1 RAMs using
the system module auto-initialization method.

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6.15 Vectored Interrupt Manager

The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the
many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow
of program execution. Normally, these events require a timely response from the central processing unit
(CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to
an interrupt service routine (ISR).

6.15.1 VIM Features

The VIM module has the following features:
• Supports 96 interrupt channels.
– Provides programmable priority and enable for interrupt request lines.
• Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.
• Provides two software dispatch mechanisms when the CPU VIC port is not used.
– Index interrupt
– Register vectored interrupt
• Parity protected vector interrupt table against soft errors.

6.15.2 Interrupt Request Assignments

Table 6-24. Interrupt Request Assignments

DEFAULT VIM
MODULES INTERRUPT SOURCES INTERRUPT
CHANNEL
ESM ESM High level interrupt (NMI) 0
Reserved Reserved 1
RTI RTI compare interrupt 0 2
RTI RTI compare interrupt 1 3
RTI RTI compare interrupt 2 4
RTI RTI compare interrupt 3 5
RTI RTI overflow interrupt 0 6
RTI RTI overflow interrupt 1 7
Reserved Reserved 8
GIO GIO interrupt A 9
N2HET N2HET level 0 interrupt 10
HTU HTU level 0 interrupt 11
MIBSPI1 MIBSPI1 level 0 interrupt 12
LIN LIN level 0 interrupt 13
MIBADC MIBADC event group interrupt 14
MIBADC MIBADC sw group 1 interrupt 15
DCAN1 DCAN1 level 0 interrupt 16
SPI2 SPI2 level 0 interrupt 17
Reserved Reserved 18
Reserved Reserved 19
ESM ESM Low level interrupt 20
SYSTEM Software interrupt (SSI) 21
CPU PMU interrupt 22
GIO GIO interrupt B 23
N2HET N2HET level 1 interrupt 24
HTU HTU level 1 interrupt 25

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Table 6-24. Interrupt Request Assignments (continued)

DEFAULT VIM
MODULES INTERRUPT SOURCES INTERRUPT
CHANNEL
MIBSPI1 MIBSPI1 level 1 interrupt 26
LIN LIN level 1 interrupt 27
MIBADC MIBADC sw group 2 interrupt 28
DCAN1 DCAN1 level 1 interrupt 29
SPI2 SPI2 level 1 interrupt 30
MIBADC MIBADC magnitude compare interrupt 31
Reserved Reserved 32-34
DCAN2 DCAN2 level 0 interrupt 35
Reserved Reserved 36
SPI3 SPI3 level 0 interrupt 37
SPI3 SPI3 level 1 interrupt 38
Reserved Reserved 39-41
DCAN2 DCAN2 level 1 interrupt 42
Reserved Reserved 43-60
FMC FSM_DONE interrupt 61
Reserved Reserved 62-79
HWAG HWA_INT_REQ_H 80
Reserved Reserved 81
DCC DCC done interrupt 82
Reserved Reserved 83
eQEPINTn eQEP Interrupt 84
PBIST PBIST Done Interrupt 85
Reserved Reserved 86-87
HWAG HWA_INT_REQ_L 88
Reserved Reserved 89-95

NOTE
Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR
entry; therefore only request channels 0..94 can be used and are offset by 1 address in the
VIM RAM.

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6.16 Real-Time Interrupt Module

The real-time interrupt (RTI) module provides timer functionality for operating systems and for
benchmarking code. The RTI module can incorporate several counters that define the timebases needed
for scheduling an operating system.
The timers also allow you to benchmark certain areas of code by reading the values of the counters at the
beginning and the end of the desired code range and calculating the difference between the values.

6.16.1 Features
The RTI module has the following features:
• Two independent 64 bit counter blocks
• Four configurable compares for generating operating system ticks. Each event can be driven by either
counter block 0 or counter block 1.
• Fast enabling/disabling of events
• Two time-stamp (capture) functions for system or peripheral interrupts, one for each counter block

6.16.2 Block Diagrams

Figure 6-12 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI
module. Both the counter blocks are identical.

31 0
Compare
OVLINTx
up counter
RTICPUCx
31 0 31 0
Up counter = Free running counter To Compare
RTICLK RTIUCx RTIFRCx Unit

31 0 31 0
Capture Capture
up counter free running counter
RTICAUCx RTICAFRCx

CAP event source 0 External

CAP event source 1 control

Figure 6-12. Counter Block Diagram

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Figure 6-13 shows a typical high-level block diagram for one of the four compares inside the RTI module.
Each of the four compares are identical.

31 0
Update
compare
RTIUDCPy

+
31 0
Compare
RTICOMPy
From counter
block 0 =
From counter INTy
block 1
Compare
control

Figure 6-13. Compare Block Diagram

6.16.3 Clock Source Options

The RTI module uses the RTICLK clock domain for generating the RTI time bases.
The application can select the clock source for the RTICLK by configuring the RCLKSRC register in the
System module at address 0xFFFFFF50. The default source for RTICLK is VCLK.
For more information, on the clock sources see Table 6-8 and Table 6-12.

6.17 Error Signaling Module

The Error Signaling Module (ESM) manages the various error conditions on the TMS570 microcontroller.
The error condition is handled based on a fixed severity level assigned to it. Any severe error condition
can be configured to drive a low level on a dedicated device terminal called nERROR. This can be used
as an indicator to an external monitor circuit to put the system into a safe state.

6.17.1 Features
The features of the Error Signaling Module are:
• 128 interrupt/error channels are supported, divided into 3 different groups
– 64 channels with maskable interrupt and configurable error pin behavior
– 32 error channels with nonmaskable interrupt and predefined error pin behavior
– 32 channels with predefined error pin behavior only
• Error pin to signal severe device failure
• Configurable timebase for error signal
• Error forcing capability

6.17.2 ESM Channel Assignments

The Error Signaling Module (ESM) integrates all the device error conditions and groups them in the order
of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest
severity. The device response to each error is determined by the severity group it is connected to.
Table 6-26 shows the channel assignment for each group.

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Table 6-25. ESM Groups

INFLUENCE ON
ERROR GROUP INTERRUPT CHARACTERISTICS
ERROR PIN
Group1 Maskable, low or high priority Configurable
Group2 Nonmaskable, high priority Fixed
Group3 No interrupt generated Fixed

Table 6-26. ESM Channel Assignments

ERROR SOURCES GROUP CHANNELS
Reserved Group1 0
Reserved Group1 1
Reserved Group1 2
Reserved Group1 3
Reserved Group1 4
Reserved Group1 5
FMC - correctable error: bus1 and bus2 interfaces (does not include accesses to
Group1 6
EEPROM bank)
N2HET - parity Group1 7
HTU - parity Group1 8
HTU - MPU Group1 9
PLL - Slip Group1 10
Clock Monitor - interrupt Group1 11
Reserved Group1 12
Reserved Group1 13
Reserved Group1 14
VIM RAM - parity Group1 15
Reserved Group1 16
MibSPI1 - parity Group1 17
Reserved Group1 18
MibADC - parity Group1 19
Reserved Group1 20
DCAN1 - parity Group1 21
Reserved Group1 22
DCAN2 - parity Group1 23
Reserved Group1 24
Reserved Group1 25
RAM even bank (B0TCM) - correctable error Group1 26
CPU - self-test Group1 27
RAM odd bank (B1TCM) - correctable error Group1 28
Reserved Group1 29
DCC - error Group1 30
CCM-R4 - self-test Group1 31
Reserved Group1 32
Reserved Group1 33
Reserved Group1 34
FMC - correctable error (EEPROM bank access) Group1 35
FMC - uncorrectable error (EEPROM bank access) Group1 36
IOMM - Mux configuration error Group1 37
Reserved Group1 38

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Table 6-26. ESM Channel Assignments (continued)

ERROR SOURCES GROUP CHANNELS
Reserved Group1 39
eFuse farm – this error signal is generated whenever any bit in the eFuse farm
error status register is set. The application can choose to generate and interrupt Group1 40
whenever this bit is set in order to service any eFuse farm error condition.
eFuse farm - self test error. It is not necessary to generate a separate interrupt
Group1 41
when this bit gets set.
Reserved Group1 42
Reserved Group1 43
Reserved Group1 44
Reserved Group1 45
Reserved Group1 46
Reserved Group1 47
Reserved Group1 48
Reserved Group1 49
Reserved Group1 50
Reserved Group1 51
Reserved Group1 52
Reserved Group1 53
Reserved Group1 54
Reserved Group1 55
Reserved Group1 56
Reserved Group1 57
Reserved Group1 58
Reserved Group1 59
Reserved Group1 60
Reserved Group1 61
Reserved Group1 62
Reserved Group1 63
Reserved Group2 0
Reserved Group2 1
CCMR4 - compare Group2 2
Reserved Group2 3
FMC - uncorrectable error (address parity on bus1 accesses) Group2 4
Reserved Group2 5
RAM even bank (B0TCM) - uncorrectable error Group2 6
Reserved Group2 7
RAM odd bank (B1TCM) - uncorrectable error Group2 8
Reserved Group2 9
RAM even bank (B0TCM) - address bus parity error Group2 10
Reserved Group2 11
RAM odd bank (B1TCM) - address bus parity error Group2 12
Reserved Group2 13
Reserved Group2 14
Reserved Group2 15
TCM - ECC live lock detect Group2 16
Reserved Group2 17
Reserved Group2 18
Reserved Group2 19

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Table 6-26. ESM Channel Assignments (continued)

ERROR SOURCES GROUP CHANNELS
Reserved Group2 20
Reserved Group2 21
Reserved Group2 22
Reserved Group2 23
RTI_WWD_NMI Group2 24
Reserved Group2 25
Reserved Group2 26
Reserved Group2 27
Reserved Group2 28
Reserved Group2 29
Reserved Group2 30
Reserved Group2 31
Reserved Group3 0
eFuse Farm - autoload error Group3 1
Reserved Group3 2
RAM even bank (B0TCM) - ECC uncorrectable error Group3 3
Reserved Group3 4
RAM odd bank (B1TCM) - ECC uncorrectable error Group3 5
Reserved Group3 6
FMC - uncorrectable error: bus1 and bus2 interfaces (does not include address
Group3 7
parity error and errors on accesses to EEPROM bank)
Reserved Group3 8
Reserved Group3 9
Reserved Group3 10
Reserved Group3 11
Reserved Group3 12
Reserved Group3 13
Reserved Group3 14
Reserved Group3 15
Reserved Group3 16
Reserved Group3 17
Reserved Group3 18
Reserved Group3 19
Reserved Group3 20
Reserved Group3 21
Reserved Group3 22
Reserved Group3 23
Reserved Group3 24
Reserved Group3 25
Reserved Group3 26
Reserved Group3 27
Reserved Group3 28
Reserved Group3 29
Reserved Group3 30
Reserved Group3 31

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6.18 Reset / Abort / Error Sources

Table 6-27. Reset/Abort/Error Sources

ESM HOOKUP
ERROR SOURCE SYSTEM MODE ERROR RESPONSE
GROUP.CHANNEL
CPU TRANSACTIONS
Precise write error (NCNB/Strongly Ordered) User/Privilege Precise Abort (CPU) n/a
Precise read error (NCB/Device or Normal) User/Privilege Precise Abort (CPU) n/a
Imprecise write error (NCB/Device or Normal) User/Privilege Imprecise Abort (CPU) n/a
Undefined Instruction Trap
Illegal instruction User/Privilege n/a
(CPU) (1)
MPU access violation User/Privilege Abort (CPU) n/a
SRAM
B0 TCM (even) ECC single error (correctable) User/Privilege ESM 1.26
Abort (CPU), ESM →
B0 TCM (even) ECC double error (noncorrectable) User/Privilege 3.3
nERROR
B0 TCM (even) uncorrectable error (that is, redundant
User/Privilege ESM → NMI → nERROR 2.6
address decode)
B0 TCM (even) address bus parity error User/Privilege ESM → NMI → nERROR 2.10
B1 TCM (odd) ECC single error (correctable) User/Privilege ESM 1.28
Abort (CPU), ESM →
B1 TCM (odd) ECC double error (noncorrectable) User/Privilege 3.5
nERROR
B1 TCM (odd) uncorrectable error (that is, redundant
User/Privilege ESM → NMI → nERROR 2.8
address decode)
B1 TCM (odd) address bus parity error User/Privilege ESM → NMI → nERROR 2.12
FLASH WITH CPU BASED ECC
FMC correctable error - Bus1 and Bus2 interfaces (does
User/Privilege ESM 1.6
not include accesses to EEPROM bank)
FMC uncorrectable error - Bus1 accesses Abort (CPU), ESM →
User/Privilege 3.7
(does not include address parity error) nERROR
FMC uncorrectable error - Bus2 accesses
(does not include address parity error and EEPROM bank User/Privilege ESM → nERROR 3.7
accesses)
FMC uncorrectable error - address parity error on Bus1
User/Privilege ESM → NMI → nERROR 2.4
accesses
FMC correctable error - Accesses to EEPROM bank User/Privilege ESM 1.35
FMC uncorrectable error - Accesses to EEPROM bank User/Privilege ESM 1.36
HIGH-END TIMER TRANSFER UNIT (HTU)
NCNB (Strongly Ordered) transaction with slave error
User/Privilege Interrupt → VIM n/a
response
External imprecise error (Illegal transaction with ok
User/Privilege Interrupt → VIM n/a
response)
Memory access permission violation User/Privilege ESM 1.9
Memory parity error User/Privilege ESM 1.8
N2HET
Memory parity error User/Privilege ESM 1.7
MIBSPI
MibSPI1 memory parity error User/Privilege ESM 1.17
MIBADC
MibADC Memory parity error User/Privilege ESM 1.19
DCAN
DCAN1 memory parity error User/Privilege ESM 1.21

(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage
of the CPU.
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Table 6-27. Reset/Abort/Error Sources (continued)

ESM HOOKUP
ERROR SOURCE SYSTEM MODE ERROR RESPONSE
GROUP.CHANNEL
DCAN2 memory parity error User/Privilege ESM 1.23
PLL
PLL slip error User/Privilege ESM 1.10
CLOCK MONITOR
Clock monitor interrupt User/Privilege ESM 1.11
DCC
DCC error User/Privilege ESM 1.30
CCM-R4
Self test failure User/Privilege ESM 1.31
Compare failure User/Privilege ESM → NMI → nERROR 2.2
VIM
Memory parity error User/Privilege ESM 1.15
VOLTAGE MONITOR
VMON out of voltage range n/a Reset n/a
CPU SELF-TEST (LBIST)
CPU Self-test (LBIST) error User/Privilege ESM 1.27
PIN MULTIPLEXING CONTROL
Mux configuration error User/Privilege ESM 1.37
eFuse CONTROLLER
eFuse Controller Autoload error User/Privilege ESM → nERROR 3.1
eFuse Controller - Any bit set in the error status register User/Privilege ESM 1.40
eFuse Controller self-test error User/Privilege ESM 1.41
WINDOWED WATCHDOG
WWD Nonmaskable Interrupt exception n/a ESM => NMI => nERROR 2.24
ERRORS REFLECTED IN THE SYSESR REGISTER
Power-Up Reset n/a Reset n/a
Oscillator fail / PLL slip (2) n/a Reset n/a
Watchdog exception n/a Reset n/a
CPU Reset (driven by the CPU STC) n/a Reset n/a
Software Reset n/a Reset n/a
External Reset n/a Reset n/a
(2) Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.

6.19 Digital Windowed Watchdog

This device includes a digital windowed watchdog (DWWD) module that protects against runaway code
execution.
The DWWD module allows the application to configure the time window within which the DWWD module
expects the application to service the watchdog. A watchdog violation occurs if the application services the
watchdog outside of this window, or fails to service the watchdog at all. The application can choose to
generate a system reset or a nonmaskable interrupt to the CPU in case of a watchdog violation.
The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog
can only be disabled upon a system reset.

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6.20 Debug Subsystem

6.20.1 Block Diagram

The device contains an ICEPICK module to allow JTAG access to the scan chains (see Figure 6-14).

Boundary Scan I/F Boundary Scan

TRST BSR/BSDL Debug
TMS ROM1
TCK
RTCK Debug APB
TDI
TDO Secondary Tap 0
DAP
APB slave
ICEPICK_C

Cortex
R4

Secondary Tap 2
AJSM

Test Tap 0
eFuse Farm

Figure 6-14. Debug Subsystem Block Diagram

6.20.2 Debug Components Memory Map

Table 6-28. Debug Components Memory Map

FRAME CHIP FRAME ADDRESS RANGE FRAME ACTUAL RESPONSE FOR ACCESS TO
MODULE NAME
SELECT START END SIZE SIZE UNIMPLEMENTED LOCATIONS IN FRAME

CoreSight Debug
CSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KB Reads return zeros, writes have no effect
ROM
Cortex-R4 Debug CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB Reads return zeros, writes have no effect

6.20.3 JTAG Identification Code

The JTAG ID code for this device is the same as the device ICEPick Identification Code.

Table 6-29. JTAG Identification Code

SILICON REVISION IDENTIFICATION CODE
Initial Silicon 0x0B97102F
Revision A 0x1B97102F
Revision B 0x2B97102F

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6.20.4 Debug ROM

The Debug ROM stores the location of the components on the Debug APB bus:

Table 6-30. Debug ROM table

ADDRESS DESCRIPTION VALUE
0x000 Pointer to Cortex-R4 0x0000 1003
0x001 Reserved 0x0000 2002
0x002 Reserved 0x0000 3002
0x003 Reserved 0x0000 4002
0x004 End of table 0x0000 0000

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6.20.5 JTAG Scan Interface Timings

Table 6-31. JTAG Scan Interface Timing (1)

NO. PARAMETER MIN MAX UNIT
fTCK TCK frequency (at HCLKmax) 12 MHz
fRTCK RTCK frequency (at TCKmax and HCLKmax) 10 MHz
1 td(TCK -RTCK) Delay time, TCK to RTCK 24 ns
2 tsu(TDI/TMS - RTCKr) Setup time, TDI, TMS before RTCK rise (RTCKr) 26 ns
3 th(RTCKr -TDI/TMS) Hold time, TDI, TMS after RTCKr 0 ns
4 th(RTCKr -TDO) Hold time, TDO after RTCKf 0 ns
5 td(TCKf -TDO) Delay time, TDO valid after RTCK fall (RTCKf) 12 ns
(1) Timings for TDO are specified for a maximum of 50 pF load on TDO

TCK

RTCK

1 1

TMS
TDI
2
3

TDO

4
5

Figure 6-15. JTAG Timing

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6.20.6 Advanced JTAG Security Module

This device includes a an Advanced JTAG Security Module (AJSM). which provides maximum security to
the memory content of the device by allowing users to secure the device after programming.

Flash Module Output

OTP Contents
(example)
H L H L ... H L L H
Unlock By Scan ...
Register

Internal Tie-Offs L L H H H H L L
(example only)

UNLOCK
128-bit comparator

Internal Tie-Offs H L L H H L L H
(example only)
Figure 6-16. AJSM Unlock

The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP
address 0xF0000000.The OTP contents are XOR-ed with the "Unlock By Scan" register contents. The
outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this
combinational logic is compared against a secret hard-wired 128-bit value. A match results in the
UNLOCK signal being asserted, so that the device is now unsecure.
A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. Changing
a 0 to 1 is not possible because the visible unlock code is stored in the One Time Programmable (OTP)
flash region. Also, changing all the 128 bits to zeros is not a valid condition and will permanently secure
the device.
Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By
Scan" register of the AJSM module. The value to be scanned is such that the XOR of the OTP contents
and the Unlock-By-Scan register contents results in the original visible unlock code.
The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).
A secure device only permits JTAG accesses to the AJSM scan chain through the Secondary Tap # 2 of
the ICEPick module. All other secondary taps, test taps and the boundary scan interface are not
accessible in this state.

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6.20.7 Boundary Scan Chain

The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary
scan chain is connected to the Boundary Scan Interface of the ICEPICK module.

Device Pins (conceptual)

TRST TDI
IC E P ICK

TMS Boundary Scan Interface

Boundary
TCK Scan TDO
RTCK
TDI
TDO BSDL

Figure 6-17. Boundary Scan Implementation (Conceptual Diagram)

Data is serially shifted into all boundary-scan buffers through TDI, and out through TDO.

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7 Peripheral Information and Electrical Specifications

7.1 Peripheral Legend

Table 7-1. Peripheral Legend

ABBREVIATION FULL NAME
MibADC Multibuffered Analog-to-Digital Converter
CCM-R4 CPU Compare Module – Cortex-R4
CRC Cyclic Redundancy Check
DCAN Controller Area Network
DCC Dual Clock Comparator
ESM Error Signaling Module
GIO General-Purpose Input/Output
HTU High-End Timer Transfer Unit
LIN Local Interconnect Network
MibSPI Multibuffered Serial Peripheral Interface
N2HET Platform High-End Timer
RTI Real-Time Interrupt Module
SCI Serial Communications Interface
SPI Serial Peripheral Interface
VIM Vectored Interrupt Manager
eQEP Enhanced Quadrature Encoder Pulse

7.2 Multibuffered 12-Bit Analog-to-Digital Converter

The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that
enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could
be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given
with respect to ADREFLO unless otherwise noted.

Table 7-2. MibADC Overview

DESCRIPTION VALUE
Resolution 12 bits
Monotonic Assured
Output conversion code 00h to FFFh [00 for VAI ≤ ADREFLO; FFF for VAI ≥ ADREFHI]

7.2.1 Features
• 12-bit resolution
• ADREFHI and ADREFLO pins (high and low reference voltages)
• Total Sample/Hold/Convert time: 600 ns Typical Minimum at 30 MHz ADCLK
• One memory region per conversion group is available (event, group 1, group 2)
• Allocation of channels to conversion groups is completely programmable
• Memory regions are serviced by interrupt
• Programmable interrupt threshold counter is available for each group
• Programmable magnitude threshold interrupt for each group for any one channel
• Option to read either 8-, or 10-, or 12-bit values from memory regions
• Single or continuous conversion modes
• Embedded self-test
• Embedded calibration logic
• Enhanced power-down mode
– Optional feature to automatically power down ADC core when no conversion is in progress

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• External event pin (ADEVT) programmable as general-purpose I/O

7.2.2 Event Trigger Options

The ADC module supports three conversion groups: Event Group, Group1, and Group2. Each of these
three groups can be configured to be hardware event-triggered. In that case, the application can select
from among eight event sources to be the trigger for the conversions of a group.

7.2.2.1 MIBADC Event Trigger Hookup

Table 7-3. MIBADC Event Trigger Hookup

SOURCE SELECT BITS
EVENT NUMBER For G1, G2, or EVENT TRIGGER
(G1SRC[2:0], G2SRC[2:0], or EVSRC[2:0])
1 000 ADEVT
2 001 N2HET[8]
3 010 N2HET[10]
4 011 RTI compare 0 interrupt
5 100 N2HET[12]
6 101 N2HET[14]
7 110 N2HET[17]
8 111 N2HET[19]

NOTE
For ADEVT, N2HET trigger sources, the connection to the MibADC module trigger input is
made from the output side of the input buffer. This way, a trigger condition can be generated
either by configuring the function as output onto the pad, or by driving the function from an
external trigger source as input. If the mux controller module is used to select different
functionality instead of ADEVT or N2HET[x], care must be taken to disable these signals
from triggering conversions; there is no multiplexing on input connections.

NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.

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7.2.3 ADC Electrical and Timing Specifications

Table 7-4. MibADC Recommended Operating Conditions

PARAMETER MIN MAX UNIT
ADREFHI A-to-D high-voltage reference source ADREFLO VCCAD V
ADREFLO A-to-D low-voltage reference source VSSAD ADREFHI V
VAI Analog input voltage ADREFLO ADREFHI V
Analog input clamp current
IAIC –2 2 mA
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)

Table 7-5. MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions (1)
PARAMETER DESCRIPTION/CONDITIONS MIN TYP MAX UNIT
Analog input mux on-
Rmux See Figure 7-1 95 250 Ω
resistance
ADC sample switch on-
Rsamp See Figure 7-1 60 250 Ω
resistance
Cmux Input mux capacitance See Figure 7-1 7 16 pF
Csamp ADC sample capacitance See Figure 7-1 8 13 pF
VSSAD < VIN < VSSAD + 100 mV –300 –1 200
Analog off-state input VSSAD + 100 mV < VIN < VCCAD -
IAIL VCCAD = 3.6 V MAX –200 –0.3 200 nA
leakage current 200 mV
VCCAD - 200 mV < VIN < VCCAD –200 1 500
VSSAD < VIN < VSSAD + 100 mV –8 2
VSSAD + 100 mV < VIN < VCCAD -
IAOSB Analog on-state input bias VCCAD = 3.6 V MAX –4 2 µA
200 mV
VCCAD - 200 mV < VIN < VCCAD –4 12
IADREFHI ADREFHI input current ADREFHI = VCCAD, ADREFLO = VSSAD 3 mA
(2)
Normal operating mode mA
ICCAD Static supply current
ADC core in power-down mode 5 µA
n
(1) 1 LSB = (ADREFHI – ADREFLO)/ 2 where n = 10 in 10-bit mode and 12 in 12-bit mode
(2) See Section 5.7.

Rext Pin Smux Rmux

VS1
23*IAIL
Cext
On-State
Leakage
Rext Pin Smux Rmux
VS2
IAIL
Cext IAIL IAIL
Off-State
Leakages

Rext Pin Smux Rmux Ssamp Rsamp

VS24
IAIL Csamp
Cmux
Cext IAIL IAIL

Figure 7-1. MibADC Input Equivalent Circuit

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Table 7-6. MibADC Timing Specifications

PARAMETER MIN NOM MAX UNIT
tc(ADCLK) (1) Cycle time, MibADC clock 33 ns
td(SH) (2) Delay time, sample and hold time 200 ns
Delay time from ADC power on until first input can be
td(PU-ADV) 1 µs
sampled
12-BIT MODE
td(C) Delay time, conversion time 400 ns
(3)
td(SHC) Delay time, total sample/hold and conversion time 600 ns
10-BIT MODE
td(C) Delay time, conversion time 330 ns
td(SHC) (3) Delay time, total sample/hold and conversion time 530 ns
(1) The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits
4:0.
(2) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each
conversion group. The sample time must be determined by accounting for the external impedance connected to the input channel as
well as the internal impedance of the ADC.
(3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors for
example, the prescale settings.

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Table 7-7. MibADC Operating Characteristics Over Full Ranges of Recommended Operating Conditions
PARAMETER DESCRIPTION/CONDITIONS MIN TYP MAX UNIT
Conversion range
over which
CR specified ADREFHI - ADREFLO 3 3.6 V
accuracy is
maintained
With ADC
1
Calibration
10-bit mode
Without ADC
Difference between the first ideal 2
Calibration
ZSET Offset Error transition (from code 000h to 001h) and LSB (1)
the actual transition With ADC
2
Calibration
12-bit mode
Without ADC
4
Calibration
Difference between the last ideal 10-bit mode 2
FSET Gain Error transition (from code FFEh to FFFh) LSB
and the actual transition minus offset. 12-bit mode 3
Difference between the actual step 10-bit mode ± 1.5
Differential
EDNL width and the ideal value. LSB
nonlinearity error 12-bit mode ±2
(See Figure 7-2)
Maximum deviation from the best 10-bit mode ±2
straight line through the MibADC.
Integral
EINL MibADC transfer characteristics, LSB
nonlinearity error 12-bit mode ±2
excluding the quantization error.
(See Figure 7-3)
With ADC
±2
Calibration
10-bit mode
Without ADC
Maximum value of the difference ±4
Total unadjusted Calibration
ETOT between an analog value and the ideal LSB
error With ADC
midstep value. (See Figure 7-4) ±4
Calibration
12-bit mode
Without ADC
±7
Calibration
(1) 1 LSB = (ADREFHI – ADREFLO)/ 2n where n = 10 in 10-bit mode and 12 in 12-bit mode

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7.2.4 Performance (Accuracy) Specifications

7.2.4.1 MibADC Nonlinearity Errors

The differential nonlinearity error shown in Figure 7-2 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.

0 ... 110

0 ... 101

0 ... 100
Digital Output Code

0 ... 011
Differential Linearity
1 LSB Error (–½ LSB)

0 ... 010

Differential Linearity
0 ... 001 Error (–½ LSB)
1 LSB

0 ... 000
0 1 2 3 4 5
Analog Input Value (LSB)
n
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/2 where n=10 in 10-bit mode and 12 in 12-bit mode

Figure 7-2. Differential Nonlinearity (DNL) Error

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The integral nonlinearity error shown in Figure 7-3 (sometimes referred to as linearity error) is the
deviation of the values on the actual transfer function from a straight line.

0 ... 111

0 ... 110

Ideal
0 ... 101 Transition

Actual
Digital Output Code

Transition
0 ... 100

At Transition
0 ... 011 011/100
(–½ LSB)

0 ... 010
End-Point Lin. Error

0 ... 001
At Transition
001/010 (–1/4 LSB)

0 ... 000
0 1 2 3 4 5 6 7
Analog Input Value (LSB)
n
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/2 where n=10 in 10-bit mode and 12 in 12-bit mode

Figure 7-3. Integral Nonlinearity (INL) Error

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7.2.4.2 MibADC Total Error

The absolute accuracy or total error of an MibADC as shown in Figure 7-4 is the maximum value of the
difference between an analog value and the ideal midstep value.

0 ... 111

0 ... 110

0 ... 101
Digital Output Code

0 ... 100
Total Error
At Step 0 ... 101
(–1 1/4 LSB)
0 ... 011

0 ... 010

Total Error
0 ... 001 At Step
0 ... 001 (1/2 LSB)

0 ... 000
0 1 2 3 4 5 6 7
Analog Input Value (LSB)
n
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/2 where n=10 in 10-bit mode and 12 in 12-bit mode

Figure 7-4. Absolute Accuracy (Total) Error

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7.3 General-Purpose Input/Output

The GPIO module on this device supports one port GIOA. The I/O pins are bidirectional and bit-
programmable. GIOA supports external interrupt capability.

7.3.1 Features
The GPIO module has the following features:
• Each I/O pin can be configured as:
– Input
– Output
– Open Drain
• The interrupts have the following characteristics:
– Programmable interrupt detection either on both edges or on a single edge (set in GIOINTDET)
– Programmable edge-detection polarity, either rising or falling edge (set in GIOPOL register)
– Individual interrupt flags (set in GIOFLG register)
– Individual interrupt enables, set and cleared through GIOENASET and GIOENACLR registers
respectively
– Programmable interrupt priority, set through GIOLVLSET and GIOLVLCLR registers
• Internal pullup/pulldown allows unused I/O pins to be left unconnected
For information on input and output timings see Section 5.11 and Section 5.12

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7.4 Enhanced High-End Timer (N2HET)

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,
capture or compare inputs, or general-purpose I/O.. It is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses.

7.4.1 Features
The N2HET module has the following features:
• Programmable timer for input and output timing functions
• Reduced instruction set (30 instructions) for dedicated time and angle functions
• 128 words of instruction RAM protected by parity
• User defined number of 25-bit virtual counters for timer, event counters and angle counters
• 7-bit hardware counters for each pin allow up to 32-bit resolution in conjunction with the 25-bit virtual
counters
• Up to 19 pins usable for input signal measurements or output signal generation
• Programmable suppression filter for each input pin with adjustable limiting frequency
• Low CPU overhead and interrupt load
• Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU)
• Diagnostic capabilities with different loopback mechanisms and pin status readback functionality

7.4.2 N2HET RAM Organization

The timer RAM uses 4 RAM banks, where each bank has two port access capability. This means that one
RAM address may be written while another address is read. The RAM words are 96-bits wide, which are
split into three 32-bit fields (program, control, and data).

7.4.3 Input Timing Specifications

The N2HET instructions PCNT and WCAP impose some timing constraints on the input signals.

N2HETx
3
4

Figure 7-5. N2HET Input Capture Timings

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Table 7-8. Dynamic Characteristics for the N2HET Input Capture Functionality
PARAMETER MIN (1) (2)
MAX (1) (2)
UNIT
Input signal period, PCNT or WCAP for rising edge 25
1 (hr)(lr) tc(VCLK2) + 2 2 (hr)(lr)tc(VCLK2) - 2 ns
to rising edge
Input signal period, PCNT or WCAP for falling edge
2 (hr) (lr) tc(VCLK2) + 2 225 (hr)(lr) tc(VCLK2) - 2 ns
to falling edge
Input signal high phase, PCNT or WCAP for rising
3 2(hr) tc(VCLK2) + 2 225 (hr)(lr) tc(VCLK2) - 2 ns
edge to falling edge
Input signal low phase, PCNT or WCAP for falling
4 2(hr) tc(VCLK2) + 2 225 (hr)(lr) tc(VCLK2) - 2 ns
edge to rising edge
(1) hr = High-resolution prescaler, configured using the HRPFC field of the Prescale Factor Register (HETPFR).
(2) lr = Loop-resolution prescaler, configured using the LFPRC field of the Prescale Factor Register (HETPFR).

7.4.4 N2HET Checking

7.4.4.1 Output Monitoring using Dual Clock Comparator (DCC)

N2HET[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure
the frequency of the pulse-width modulated (PWM) signal on N2HET[31].
N2HET[31] can be configured to be an internal-only channel. That is, the connection to the DCC module is
made directly from the output of the N2HET module (from the input of the output buffer).
For more information on DCC, see Section 6.6.3.

7.4.5 Disabling N2HET Outputs

Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET
module provides this capability through the "Pin Disable" input signal. This signal, when driven low,
causes the N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated.
For more details on the "N2HET Pin Disable" feature, see the device-specific Technical Reference Manual
listed in Section 8.2.1.
GIOA[5] and EQEPERR are connected to the "Pin Disable" input for N2HET. In the case of GIOA[5]
connection, this connection is made from the output of the input buffer. In the case of EQEPERR, the
EQEPERR output signal is asserted in the event of a phase error. This signal is inverted and double-
synchronized to VCLK2 for input into the N2HET PIN_nDISABLE port.
The PIN_nDISABLE port input source is selectable between the GIOA[5] and EQEPERR sources. This is
achieved through the PINMMR9[1:0] bits.

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7.4.6 High-End Timer Transfer Unit (N2HET)

A High-End Timer Transfer Unit (N2HET) can perform DMA type transactions to transfer N2HET data to or
from main memory. A Memory Protection Unit (MPU) is built into the N2HET.

7.4.6.1 Features
• CPU independent
• Master Port to access system memory
• 8 control packets supporting dual buffer configuration
• Control packet information is stored in RAM protected by parity
• Event synchronization (N2HET transfer requests)
• Supports 32- or 64-bit transactions
• Addressing modes for N2HET address (8 byte or 16 byte) and system memory address (fixed, 32-bit or 64-bit)
• One shot, circular, and auto switch buffer transfer modes
• Request lost detection

7.4.6.2 Trigger Connections

Table 7-9. N2HET Request Line Connection

MODULES REQUEST SOURCE HTU REQUEST
N2HET HTUREQ[0] HTU DCP[0]
N2HET HTUREQ[1] HTU DCP[1]
N2HET HTUREQ[2] HTU DCP[2]
N2HET HTUREQ[3] HTU DCP[3]
N2HET HTUREQ[4] HTU DCP[4]
N2HET HTUREQ[5] HTU DCP[5]
N2HET HTUREQ[6] HTU DCP[6]
N2HET HTUREQ[7] HTU DCP[7]

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7.5 Controller Area Network (DCAN)

The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication
protocol that efficiently supports distributed real-time control with robust communication rates of up to
1 Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example,
automotive and industrial fields) that require reliable serial communication or multiplexed wiring.

7.5.1 Features
Features of the DCAN module include:
• Supports CAN protocol version 2.0 part A, B
• Bit rates up to 1 Mbps
• The CAN kernel can be clocked by the oscillator for baud-rate generation.
• 32 and 16 mailboxes on DCAN1 and DCAN2, respectively
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loop-back modes for self-test operation
• Automatic bus on after Bus-Off state by a programmable 32-bit timer
• Message RAM protected by parity
• Direct access to Message RAM during test mode
• CAN RX / TX pins configurable as general-purpose I/O pins
• Message RAM Auto Initialization
For more information on the DCAN, see the device-specific Technical Reference Manual listed in
Section 8.2.1.

7.5.2 Electrical and Timing Specifications

Table 7-10. Dynamic Characteristics for the DCANx TX and RX pins

PARAMETER MIN MAX UNIT
(1)
td(CANnTX) Delay time, transmit shift register to CANnTX pin 15 ns
td(CANnRX) Delay time, CANnRX pin to receive shift register 5 ns
(1) These values do not include rise/fall times of the output buffer.

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7.6 Local Interconnect Network Interface (LIN)

The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is
an SCI. The SCI’s hardware features are augmented to achieve LIN compatibility.
The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn
to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a K-
line.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept is
single-master/multiple-slave with a message identification for multicast transmission between any network
nodes.

7.6.1 LIN Features

The following are features of the LIN module:
• Compatible to LIN 1.3, 2.0 and 2.1 protocols
• Multibuffered receive and transmit units
• Identification masks for message filtering
• Automatic Master Header Generation
– Programmable Synch Break Field
– Synch Field
– Identifier Field
• Slave Automatic Synchronization
– Synch break detection
– Optional baudrate update
– Synchronization Validation
• 231 programmable transmission rates with 7 fractional bits
• Error detection
• 2 Interrupt lines with priority encoding

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7.7 Multibuffered / Standard Serial Peripheral Interface

The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display
drivers, and ADCs.

7.7.1 Features
Both Standard and MibSPI modules have the following features:
• 16-bit shift register
• Receive buffer register
• 11-bit baud clock generator
• SPICLK can be internally generated (master mode) or received from an external clock source (slave
mode)
• Each word transferred can have a unique format
• SPI I/Os not used in the communication can be used as digital input/output signals

Table 7-11. MibSPI/SPI Default Configurations

MibSPIx/SPIx I/Os
MibSPI1 MIBSPI1SIMO[0], MIBSPI1SOMI[0], MIBSPI1CLK, MIBSPI1nCS[3:0], MIBSPI1nENA
SPI2 SPI2SIMO, SPI2SOMI, SPI2CLK, SPI2nCS[0]
SPI3 SPI3SIMO, SPI3SOMI, SPI3CLK, SPI3nENA, SPI3nCS[0]

7.7.2 MibSPI Transmit and Receive RAM Organization

The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of four parts:
a 16-bit transmit field, a 16-bit receive field, a 16-bit control field, and a 16-bit status field. The Multibuffer
RAM can be partitioned into multiple transfer group with variable number of buffers each.

7.7.3 MibSPI Transmit Trigger Events

Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event
and a trigger source can be chosen. A trigger event can be, for example, a rising edge or a permanent low
level at a selectable trigger source. Up to 15 trigger sources are available which can be used by each
transfer group. These trigger options are listed in Table 7-12.

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7.7.3.1 MIBSPI1 Event Trigger Hookup

Table 7-12. MIBSPI1 Event Trigger Hookup

EVENT NO. TGxCTRL TRIGSRC[3:0] TRIGGER
Disabled 0000 No trigger source
EVENT0 0001 GIOA[0]
EVENT1 0010 GIOA[1]
EVENT2 0011 GIOA[2]
EVENT3 0100 GIOA[3]
EVENT4 0101 GIOA[4]
EVENT5 0110 GIOA[5]
EVENT6 0111 GIOA[6]
EVENT7 1000 GIOA[7]
EVENT8 1001 N2HET[8]
EVENT9 1010 N2HET[10]
EVENT10 1011 N2HET[12]
EVENT11 1100 N2HET[14]
EVENT12 1101 N2HET[16]
EVENT13 1110 N2HET[18]
EVENT14 1111 Internal Tick counter

NOTE
For N2HET trigger sources, the connection to the MibSPI1 module trigger input is made from
the input side of the output buffer (at the N2HET module boundary). This way, a trigger
condition can be generated even if the N2HET signal is not selected to be output on the pad.

NOTE
For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin, or by driving the GIOx pin from an external trigger
source.

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7.7.4 MibSPI/SPI Master Mode I/O Timing Specifications

Table 7-13. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO
= output, and SPISOMI = input) (1) (2) (3)
NO. PARAMETER MIN MAX UNIT
1 tc(SPC)M Cycle time, SPICLK (4) 40 256tc(VCLK) ns
Pulse duration, SPICLK high (clock polarity =
tw(SPCH)M 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3
0)
2 (5) ns
Pulse duration, SPICLK low (clock polarity =
tw(SPCL)M 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3
1)
Pulse duration, SPICLK low (clock polarity =
tw(SPCL)M 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3
0)
3 (5) ns
Pulse duration, SPICLK high (clock polarity =
tw(SPCH)M 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3
1)
Delay time, SPISIMO valid before SPICLK
td(SPCH-SIMO)M 0.5tc(SPC)M – 6
low (clock polarity = 0)
4 (5) ns
Delay time, SPISIMO valid before SPICLK
td(SPCL-SIMO)M 0.5tc(SPC)M – 6
high (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK
tv(SPCL-SIMO)M 0.5tc(SPC)M – tf(SPC) – 4
low (clock polarity = 0)
5 (5) ns
Valid time, SPISIMO data valid after SPICLK
tv(SPCH-SIMO)M 0.5tc(SPC)M – tr(SPC) – 4
high (clock polarity = 1)
Setup time, SPISOMI before SPICLK low
tsu(SOMI-SPCL)M tf(SPC) + 2.2
(5)
(clock polarity = 0)
6 ns
Setup time, SPISOMI before SPICLK high
tsu(SOMI-SPCH)M tr(SPC) + 2.2
(clock polarity = 1)
Hold time, SPISOMI data valid after SPICLK
th(SPCL-SOMI)M 10
(5)
low (clock polarity = 0)
7 ns
Hold time, SPISOMI data valid after SPICLK
th(SPCH-SOMI)M 10
high (clock polarity = 1)
C2TDELAY*tc(VCLK) + 2*tc(VCLK) - (C2TDELAY+2) * tc(VCLK) - tf(SPICS) +
Setup time CS active until CSHOLD = 0
tf(SPICS) + tr(SPC) – 7 tr(SPC) + 5.5
SPICLK high (clock ns
polarity = 0) C2TDELAY*tc(VCLK) + 3*tc(VCLK) - (C2TDELAY+3) * tc(VCLK) - tf(SPICS) +
CSHOLD = 1
tf(SPICS) + tr(SPC) – 7 tr(SPC) + 5.5
8 (6) tC2TDELAY
C2TDELAY*tc(VCLK) + 2*tc(VCLK) - (C2TDELAY+2) * tc(VCLK) - tf(SPICS) +
Setup time CS active until CSHOLD = 0 tf(SPICS) + tf(SPC) – 7 tf(SPC) + 5.5
SPICLK low (clock polarity ns
= 1) C2TDELAY*tc(VCLK) + 3*tc(VCLK) - (C2TDELAY+3) * tc(VCLK) - tf(SPICS) +
CSHOLD = 1
tf(SPICS) + tf(SPC) – 7 tf(SPC) + 5.5
Hold time SPICLK low until CS inactive 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) +
ns
(6)
(clock polarity = 0) tc(VCLK) - tf(SPC) + tr(SPICS) - 7 tc(VCLK) - tf(SPC) + tr(SPICS) + 11
9 tT2CDELAY
Hold time SPICLK high until CS inactive 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) +
ns
(clock polarity = 1) tc(VCLK) - tr(SPC) + tr(SPICS) - 7 tc(VCLK) - tr(SPC) + tr(SPICS) + 11
(C2TDELAY+1) * tc(VCLK) - tf(SPICS) – ns
10 tSPIENA SPIENAn Sample point (C2TDELAY+1)*tc(VCLK)
29
11 tSPIENAW SPIENAn Sample point from write to buffer (C2TDELAY+2)*tc(VCLK) ns

(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see Table 5-6.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40 ns.
The external load on the SPICLK pin must be less than 60 pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

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1
SPICLK
(clock polarity = 0)

3
SPICLK
(clock polarity = 1)

4 5

SPISIMO Master Out Data Is Valid

SPISOMI Master In Data

Must Be Valid

Figure 7-6. SPI Master Mode External Timing (CLOCK PHASE = 0)

Write to buffer

SPICLK
(clock polarity=0)

SPICLK
(clock polarity=1)

SPISIMO Master Out Data Is Valid

8 9
SPICSn

10

11
SPIENAn

Figure 7-7. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)

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Table 7-14. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO
= output, and SPISOMI = input) (1) (2) (3)
NO. PARAMETER MIN MAX UNIT
(4)
1 tc(SPC)M Cycle time, SPICLK 40 256tc(VCLK) ns
Pulse duration, SPICLK high (clock polarity
tw(SPCH)M 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3
(5)
= 0)
2 ns
Pulse duration, SPICLK low (clock polarity
tw(SPCL)M 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3
= 1)
Pulse duration, SPICLK low (clock polarity
tw(SPCL)M 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3
(5)
= 0)
3 ns
Pulse duration, SPICLK high (clock polarity
tw(SPCH)M 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3
= 1)
Valid time, SPICLK high after SPISIMO
tv(SIMO-SPCH)M 0.5tc(SPC)M – 6
(5)
data valid (clock polarity = 0)
4 ns
Valid time, SPICLK low after SPISIMO data
tv(SIMO-SPCL)M 0.5tc(SPC)M – 6
valid (clock polarity = 1)
Valid time, SPISIMO data valid after
tv(SPCH-SIMO)M 0.5tc(SPC)M – tr(SPC) – 4
(5)
SPICLK high (clock polarity = 0)
5 ns
Valid time, SPISIMO data valid after
tv(SPCL-SIMO)M 0.5tc(SPC)M – tf(SPC) – 4
SPICLK low (clock polarity = 1)
Setup time, SPISOMI before SPICLK high
tsu(SOMI-SPCH)M tr(SPC) + 2.2
(5)
(clock polarity = 0)
6 ns
Setup time, SPISOMI before SPICLK low
tsu(SOMI-SPCL)M tf(SPC) + 2.2
(clock polarity = 1)
Valid time, SPISOMI data valid after
tv(SPCH-SOMI)M 10
(5)
SPICLK high (clock polarity = 0)
7 ns
Valid time, SPISOMI data valid after
tv(SPCL-SOMI)M 10
SPICLK low (clock polarity = 1)
0.5*tc(SPC)M + 0.5*tc(SPC)M +
CSHOLD = 0 (C2TDELAY+2) * tc(VCLK) - (C2TDELAY+2) * tc(VCLK) -
Setup time CS active until tf(SPICS) + tr(SPC) – 7 tf(SPICS) + tr(SPC) + 5.5
SPICLK high (clock polarity ns
= 0) 0.5*tc(SPC)M + 0.5*tc(SPC)M +
CSHOLD = 1 (C2TDELAY+3) * tc(VCLK) - (C2TDELAY+3) * tc(VCLK) -
(6)
tf(SPICS) + tr(SPC) – 7 tf(SPICS) + tr(SPC) + 5.5
8 tC2TDELAY
0.5*tc(SPC)M + 0.5*tc(SPC)M +
CSHOLD = 0 (C2TDELAY+2) * tc(VCLK) - (C2TDELAY+2) * tc(VCLK) -
Setup time CS active until tf(SPICS) + tf(SPC) – 7 tf(SPICS) + tf(SPC) + 5.5
SPICLK low (clock polarity ns
= 1) 0.5*tc(SPC)M + 0.5*tc(SPC)M +
CSHOLD = 1 (C2TDELAY+3) * tc(VCLK) - (C2TDELAY+3) * tc(VCLK) -
tf(SPICS) + tf(SPC) – 7 tf(SPICS) + tf(SPC) + 5.5
T2CDELAY*tc(VCLK) + T2CDELAY*tc(VCLK) +
Hold time SPICLK low until CS inactive
tc(VCLK) - tf(SPC) + tr(SPICS) - tc(VCLK) - tf(SPC) + tr(SPICS) + ns
(clock polarity = 0)
(6)
7 11
9 tT2CDELAY
T2CDELAY*tc(VCLK) + T2CDELAY*tc(VCLK) +
Hold time SPICLK high until CS inactive
tc(VCLK) - tr(SPC) + tr(SPICS) - tc(VCLK) - tr(SPC) + tr(SPICS) + ns
(clock polarity = 1)
7 11
(C2TDELAY+1)* tc(VCLK) -
10 tSPIENA SPIENAn Sample Point (C2TDELAY+1)*tc(VCLK) ns
tf(SPICS) – 29
11 tSPIENAW SPIENAn Sample point from write to buffer (C2TDELAY+2)*tc(VCLK) ns
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see the Table 5-6.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40 ns.
The external load on the SPICLK pin must be less than 60 pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

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SPICLK
(clock polarity = 0)
2

SPICLK
(clock polarity = 1)

4 5

SPISIMO Master Out Data Is Valid Data Valid

6 7

Master In Data
SPISOMI Must Be Valid

Figure 7-8. SPI Master Mode External Timing (CLOCK PHASE = 1)

Write to buffer

SPICLK
(clock polarity=0)

SPICLK
(clock polarity=1)

SPISIMO Master Out Data Is Valid

8 9
SPICSn

10

11
SPIENAn

Figure 7-9. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)

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7.7.5 SPI Slave Mode I/O Timings

Table 7-15. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO =
input, and SPISOMI = output) (1) (2) (3) (4)
NO. PARAMETER MIN MAX UNIT
1 tc(SPC)S Cycle time, SPICLK (5) 40 ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 14
2 (6) ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 14
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 14
3 (6) ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 14
td(SPCH-SOMI)S Delay time, SPISOMI valid after SPICLK high (clock polarity = 0) trf(SOMI) + 20
4 (6) ns
td(SPCL-SOMI)S Delay time, SPISOMI valid after SPICLK low (clock polarity = 1) trf(SOMI) + 20
Hold time, SPISOMI data valid after SPICLK high (clock polarity
th(SPCH-SOMI)S 2
(6)
=0)
5 ns
Hold time, SPISOMI data valid after SPICLK low (clock polarity
th(SPCL-SOMI)S 2
=1)
tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 4
6 (6) ns
tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 4
Hold time, SPISIMO data valid after SPICLK low (clock polarity
th(SPCL-SIMO)S 2
(6)
= 0)
7 ns
Hold time, SPISIMO data valid after S PICLK high (clock polarity
th(SPCH-SIMO)S 2
= 1)
Delay time, SPIENAn high after last SPICLK low (clock polarity 2.5tc(VCLK)+tr(ENA
td(SPCL-SENAH)S 1.5tc(VCLK)
= 0) n)+ 22
8 ns
Delay time, SPIENAn high after last SPICLK high (clock polarity 2.5tc(VCLK)+
td(SPCH-SENAH)S 1.5tc(VCLK)
= 1) tr(ENAn) + 22
Delay time, SPIENAn low after SPICSn low (if new data has tc(VCLK)+tf(ENAn)+
9 td(SCSL-SENAL)S tf(ENAn) ns
been written to the SPI buffer) 27
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 5-6.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40 ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

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1
SPICLK
(clock polarity = 0)

3
SPICLK
(clock polarity = 1)

5
4

SPISOMI SPISOMI Data Is Valid

SPISIMO SPISIMO Data

Must Be Valid

Figure 7-10. SPI Slave Mode External Timing (CLOCK PHASE = 0)

SPICLK
(clock polarity=0)

SPICLK
(clock polarity=1)

SPIENAn
9
SPICSn

Figure 7-11. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)

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Table 7-16. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO =
input, and SPISOMI = output) (1) (2) (3) (4)
NO. PARAMETER MIN MAX UNIT
1 tc(SPC)S Cycle time, SPICLK (5) 40 ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 14
2 (6) ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 14
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 14
3 (6) ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 14
td(SOMI-SPCL)S Dealy time, SPISOMI data valid after SPICLK low (clock
trf(SOMI) + 20
(6)
polarity = 0)
4 ns
td(SOMI-SPCH)S Delay time, SPISOMI data valid after SPICLK high (clock
trf(SOMI) + 20
polarity = 1)
Hold time, SPISOMI data valid after SPICLK high (clock
th(SPCL-SOMI)S 2
(6)
polarity =0)
5 ns
Hold time, SPISOMI data valid after SPICLK low (clock polarity
th(SPCH-SOMI)S 2
=1)
tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 4
6 (6) ns
tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 4
High time, SPISIMO data valid after SPICLK high (clock
tv(SPCH-SIMO)S 2
(6)
polarity = 0)
7 ns
High time, SPISIMO data valid after SPICLK low (clock polarity
tv(SPCL-SIMO)S 2
= 1)
Delay time, SPIENAn high after last SPICLK high (clock
td(SPCH-SENAH)S 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) + 22
polarity = 0)
8 ns
Delay time, SPIENAn high after last SPICLK low (clock polarity
td(SPCL-SENAH)S 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn) + 22
= 1)
Delay time, SPIENAn low after SPICSn low (if new data has
9 td(SCSL-SENAL)S tf(ENAn) tc(VCLK)+tf(ENAn)+ 27 ns
been written to the SPI buffer)
Delay time, SOMI valid after SPICSn low (if new data has been
10 td(SCSL-SOMI)S tc(VCLK) 2tc(VCLK)+trf(SOMI)+ 28 ns
written to the SPI buffer)

(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 5-6.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40 ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

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SPICLK
(clock polarity = 0)
2

SPICLK
(clock polarity = 1)
5
4

SPISOMI SPISOMI Data Is Valid

SPISIMO SPISIMO Data

Must Be Valid

Figure 7-12. SPI Slave Mode External Timing (CLOCK PHASE = 1)

SPICLK
(clock polarity=0)

SPICLK
(clock polarity=1)

SPIENAn
9
SPICSn

10
SPISOMI Slave Out Data Is Valid

Figure 7-13. SPI Slave Mode Enable Timing (CLOCK PHASE = 1)

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7.8 Enhanced Quadrature Encoder (eQEP)

Figure 7-14 shows the eQEP module interconnections on the device.

VBUSP Interface
EQEPA
EQEPB

EQEPENCLK EQEP EQEPI

CDDISx.9
EQEP VCLK EQEPIO
VCLK
CLK Module
ACK EQEPIOE
CLKSTOP_REQ GATE
SYS_nRST I/O
EQEPS
EQEPSO
MUX
VIM EQEPINTn
EQEPSOE
CTRL

nEQEPERR
NHET _SYNC EQEPERR
nDIS

GIOA[5]

VCLK2
NHETnDIS_SEL

Figure 7-14. eQEP Module Interconnections

7.8.1 Clock Enable Control for eQEPx Modules

The device level control of the eQEP clock is accomplished through the enable/disable of the VCLK clock
domain for eQEP only. This is realized using bit 9 of the CLKDDIS register. The eQEP clock source is
enabled by default.

7.8.2 Using eQEPx Phase Error

The eQEP module sets the EQEPERR signal output whenever a phase error is detected in its inputs
EQEPxA and EQEPxB. This error signal from both the eQEP modules is input to the connection selection
multiplexor. As shown in Figure 7-14, the output of this selection multiplexor is inverted and connected to
the N2HET module. This connection allows the application to define the response to a phase error
indicated by the eQEP modules.

7.8.3 Input Connections to eQEPx Modules

The input connections to each of the eQEP modules can be selected between a double-VCLK-
synchronized input or a double-VCLK-synchronized and filtered input, as shown in Table 7-17.

Table 7-17. Device-Level Input Synchronization

CONTROL FOR DOUBLE-SYNCHRONIZED CONTROL FOR DOUBLE-SYNCHRONIZED
INPUT SIGNAL
CONNECTION TO eQEPx AND FILTERED CONNECTION TO eQEPx
eQEPA PINMMR8[0] = 1 PINMMR8[0] = 0 and PINMMR8[1] = 1
eQEPB PINMMR8[8] = 1 PINMMR8[8] = 0 and PINMMR8[9] = 1
eQEPI PINMMR8[16] = 1 PINMMR8[16] = 0 and PINMMR8[17] = 1
eQEPS PINMMR8[24] = 1 PINMMR8[24] = 0 and PINMMR8[25] = 1

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7.8.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing

Table 7-18. eQEPx Timing Requirements

PARAMETER TEST CONDITIONS MIN MAX UNIT
Synchronous 2 tc(VCLK) cycles
tw(QEPP) QEP input period
Synchronous, with input filter 2 tc(VCLK) + filter width cycles
Synchronous 2 tc(VCLK) cycles
tw(INDEXH) QEP Index Input High Time
Synchronous, with input filter 2 tc(VCLK) + filter width cycles
Synchronous 2 tc(VCLK) cycles
tw(INDEXL) QEP Index Input Low Time
Synchronous, with input filter 2 tc(VCLK) + filter width cycles
tw(STROBH Synchronous 2 tc(VCLK) cycles
QEP Strobe Input High Time
) Synchronous, with input filter 2 tc(VCLK) + filter width cycles
tw(STROBL Synchronous 2 tc(VCLK) cycles
QEP Strobe Input Low Time
) Synchronous, with input filter 2 tc(VCLK) + filter width cycles

Table 7-19. eQEPx Switching Characteristics

PARAMETER MIN MAX UNIT
td(CNTR)xin Delay time, external clock to counter increment 4 tc(VCLK) cycles
td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 6 tc(VCLK) cycles

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8 Device and Documentation Support

8.1 Device Support

8.1.1 Development Support

Texas Instruments (TI) offers an extensive line of development tools for the Hercules™ Safety generation
of MCUs, including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of Hercules™-based applications:
Software Development Tools
• Code Composer Studio™ Integrated Development Environment (IDE)
– C/C++ Compiler
– Code generation tools
– Assembler/Linker
– Cycle Accurate Simulator
• Application algorithms
• Sample applications code
Hardware Development Tools
• Development and evaluation boards
• JTAG-based emulators - XDS100™v2, XDS200, XDS560™ v2 emulator
• Flash programming tools
• Power supply
• Documentation and cables

8.1.1.1 Getting Started

This section gives a brief overview of the steps to take when first developing for a TMS570 MCU device.
For more detail on each of these steps, see the following:
• Initialization of the TMS570LS043x, TMS570LS033x and RM42L432 Hercules ARM Cortex-R4
Microcontrollers (SPNA163)
• Compatibility Considerations: Migrating FromTMS570LS31x/21x or TMS570LS12x/11x to
TMS570LS04x/03x Safety Microcontrollers (SPNA175)

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8.1.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
devices. Each commercial family member has one of three prefixes: TMX, TMP, or TMS. These prefixes
represent evolutionary stages of product development from engineering prototypes (TMX) through fully
qualified production devices (TMS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical specifications.
TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and
reliability verification.
TMS Fully-qualified production device.

TMX and TMP devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.

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Figure 8-1 illustrates the numbering and symbol nomenclature for the TMS570LS0432/0332.

Full Part # TMS 570 LS 04 3 2 B PZ Q Q1 R

Orderable Part # TMS 570 04 3 2 B PZ Q Q1 R

Prefix: TM
TMS = Fully Qualified
TMP = Prototype
TMX = Samples

Core Technology:
570 = Cortex-R4
Cortex R4

Architecture:
LS = Lockstep CPUs
(not included in orderable part #)

Flash Memory Size:

04 = 384KB
03 = 256KB

RAM MemorySize:
3 = 32KB

Peripheral Set:

Die Revision:
Blank = Initial Die
A = Die Revision A
B = Die Revision B

Package Type:
PZ = 100-Pin Package

Temperature Range:
Q = –40oC to 125oC

Quality Designator:
Q1 = Automotive

Shipping Options:
R = Tape and Reel

Figure 8-1. Device Numbering Conventions

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8.2 Documentation Support

8.2.1 Related Documentation from Texas Instruments

The following documents describe the TMS570LS0432/0332 microcontroller.
SPNU517 TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual details the
integration, the environment, the functional description, and the programming models for each
peripheral and subsystem in the device.
SPNZ197 TMS570LS0x32 Microcontroller Silicon Revision A, Silicon Errata describes the usage notes and
known exceptions to the functional specifications for the device silicon revision(s).
SPNZ226 TMS570LS0x32 Microcontroller Silicon Revision B, Silicon Errata describes the usage notes and
known exceptions to the functional specifications for the device silicon revision(s).
SPNA207 Calculating Equivalent Power-on-Hours for Hercules™ Safety MCUs details how to use the
spreadsheet to calculate the aging effect of temperature on Texas Instruments Hercules Safety MCUs.

8.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 8-1. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
TMS570LS0432 Click here Click here Click here Click here Click here
TMS570LS0332 Click here Click here Click here Click here Click here

8.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among
engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve
problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers
get started with Embedded Processors from Texas Instruments and to foster innovation and growth of
general knowledge about the hardware and software surrounding these devices.

8.5 Trademarks
Hercules, Code Composer Studio, XDS100, XDS560, E2E are trademarks of Texas Instruments.
CoreSight is a trademark of ARM Limited.
ARM, Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere.
All rights reserved.
All other trademarks are the property of their respective owners.

8.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

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8.8 Device Identification Code Register

The device identification code register identifies several aspects of the device including the silicon version.
The details of the device identification code register are shown in Table 8-2. The device identification code
register value for this device is:
• Rev 0 = 0x8048AD05
• Rev A = 0x8048AD0D
• Rev B = 0x8048AD15

Figure 8-2. Device ID Bit Allocation Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP-15 UNIQUE ID TECH
R-1 R-00000000100100 R-0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I/O
PERIPH RAM
TECH VOLT FLASH ECC VERSION 1 0 1
PARITY ECC
AGE
R-101 R-0 R-1 R-10 R-1 R-00001 R-1 R-0 R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8-2. Device ID Bit Allocation Register Field Descriptions

BIT FIELD VALUE DESCRIPTION
31 CP15 Indicates the presence of coprocessor 15
1 CP15 present
30-17 UNIQUE ID 100100
Silicon version (revision) bits.
This bit field holds a unique number for a dedicated device configuration (die).
16-13 TECH Process technology on which the device is manufactured.
0101 F021
12 I/O VOLTAGE I/O voltage of the device.
0 I/O are 3.3v
11 PERIPHERAL Peripheral Parity
PARITY
1 Parity on peripheral memories
10-9 FLASH ECC Flash ECC
10 Program memory with ECC
8 RAM ECC Indicates if RAM memory ECC is present.
1 ECC implemented
7-3 REVISION 0 Revision of the Device.
2-0 FAMILY ID 101 The platform family ID is always 0b101

8.9 Die Identification Registers

The two die ID registers at addresses 0xFFFFFF7C and 0xFFFFFF80 form a 64-bit die id with the
information as shown in Table 8-3.

Table 8-3. Die-ID Registers

ITEM NO. OF BITS BIT LOCATION
X Coord. on Wafer 12 0xFFFFFF7C[11:0]
Y Coord. on Wafer 12 0xFFFFFF7C[23:12]
Wafer # 8 0xFFFFFF7C[31:24]
Lot # 24 0xFFFFFF80[23:0]
Reserved 8 0xFFFFFF80[31:24]

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8.10 Module Certifications

The following communications modules have received certification of adherence to a standard.

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8.10.1 DCAN Certification

Figure 8-3. DCAN Certification

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8.10.2 LIN Certifications

8.10.2.1 LIN Master Mode

Figure 8-4. LIN Certification - Master Mode

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8.10.2.2 LIN Slave Mode - Fixed Baud Rate

Figure 8-5. LIN Certification - Slave Mode - Fixed Baud Rate

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8.10.2.3 LIN Slave Mode - Adaptive Baud Rate

Figure 8-6. LIN Certification - Slave Mode - Adaptive Baud Rate

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9 Mechanical Packaging and Orderable Addendum

9.1 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TMS5700332BPZQQ1 ACTIVE LQFP PZ 100 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 TMS570LS
& no Sb/Br) 0332BPZQQ1
TMS5700432BPZQQ1 ACTIVE LQFP PZ 100 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 TMS570LS
& no Sb/Br) 0432BPZQQ1
TMS5700432BPZQQ1R ACTIVE LQFP PZ 100 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 TMS570LS
& no Sb/Br) 0432BPZQQ1

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 5-Mar-2017

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 MECHANICAL DATA

MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK

0,27
0,50 0,08 M
0,17
75 51

76 50

100 26 0,13 NOM

1 25
12,00 TYP Gage Plane
14,20
SQ
13,80
16,20 0,25
SQ 0,05 MIN 0°– 7°
15,80

1,45 0,75
1,35 0,45

Seating Plane

1,60 MAX 0,08

4040149 /B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

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