CAN-PCIe/402

PCI Express® Board with up to 4 CAN Interfaces

Single Lane PCIe Board with Altera® CAN Data Management
FPGA for up to 4x CAN The independent CAN nets according to
• 1x, 2x or 4x CAN interfaces according to ISO 11898-1 are driven by the esdACC (esd
ISO 11898-2 Advanced CAN Core) implemented in the
• Bus mastering and local data management Altera FPGA. The FPGA supports bus
by FPGA mastering (first-party DMA) to transfer data
to the host memory. This results in a
• PCIe® interface according to PCI Express reduction of overall latency on servicing I/O
Specification R1.0a transactions in particular at higher data rates
• Selectable CAN termination on board and a reduced host CPU load.
CAN-PCIe/402-2
• Supports MSI (Message Signaled (C.2045.04)
Interrupts) Due to the usage of MSI (Message Signaled
Wide Choice of Hardware Designs Interrupts) the CAN-PCIe/402 can be
Wide Range of Operating System Support The CAN-PCIe/402 is a PC board designed operated for example in Hypervisor
and Advanced CAN Diagnostic for the PCIe bus that features one, two environments.
• Drivers and higher layer protocols for (CANPCIe/402-2) or four (CAN-PCIe/402- The CAN-PCIe/402 provides high resolution
Windows®, Linux®, VxWorks®, QNX®, RTX, 4/2Slot) electrically isolated CAN High- hardware timestamps.
RTX64 and others Speed interfaces according to ISO 11898-2.
• CANopen®, J1939 and ARINC 825 protocol The CAN-PCIe/402-4/2Slot comes with two Software Support1
libraries are available CAN interfaces via a separate slot bracket. CAN layer 2 (NTCAN-API) software drivers
These product versions are also available are available for Windows, Linux, VxWorks,
• esd Advanced CAN Core (esdACC) QNX, RTX and RTX64.
technology without electrical isolation.
The CANopen software package is available
In the CAN-PCIe402-B4/1Slot version all for Windows, Linux, RTX, VxWorks and
Variety of Product Designs QNX.
four CAN interfaces are connected via one
• Product versions available with or without 37-pin DSUB connector.
electrical isolation Drivers for other operating systems are
Equipped with up to two CAN interfaces the
• Low profile version for 1xCAN or 2xCAN board is available as low profile versions available on request.
• 4x CAN via 1x DSUB37 connector (CAN-PCIe/402-1-LP and -LP2).

Adapter Board CAN-PCIe/402-Slot2 (electrical isolation optional)

10-pin
CAN4 post connector
CAN-adapter board
CAN3

Optional Ribbon PCIe

CAN-PCIe/402-B4 only Electrical
Cable
CAN Core Card Edge
Isolation with Timestamp
Connector
DSUB9
CiA pinning
CAN Core
4x CAN Interface with Timestamp

esdACC
CAN2
CAN1 CAN Core
with Timestamp

Optional Optional
CAN Core
Electrical Electrical with Timestamp
Isolation Isolation
DSUB9
DSUB37 CiA pinning
CiA pinning

Standard Version CAN-PCIe/402-2 (electrical isolation optional)

Technical Specifications:
PCI Express Interface: Order Information:
PCIe port PCI Express Spec. R1.0a, Link width 1x Hardware Order No.
CAN-PCIe/402-1 1x CAN (CAN 1 only) C.2045.02
CAN:
CAN-PCIe/402-1-D as C.2045.02 but without electr. isolation C.2045.03
Interface 1x, 2x or 4x CAN high-speed interfaces according to CAN-PCIe/402-2 2x CAN (CAN 1, CAN2) C.2045.04
ISO 11898-2, bit rate up to 1 Mbit/s, with or without electrical CAN-PCIe/402-2-D as C.2045.04 but without electr. isolation C.2045.05
isolation CAN-PCIe/402-4/2Slot 4x CAN (C.2045.04, C.2045.10) C.2045.06
CAN controller esdACC in EP4CGX Altera FPGA, acc. to ISO 11898-1 CAN-PCIe/402-4/2Slot-D as C.2045.06 but without electr. isolation C.2045.07
(CAN 2.0 A/B) CAN-PCIe/402-B4/1 Slot 4x CAN via 1x DSUB37, 1 Slot C.2045.08
CAN-PCIe/402-Slot2 Adapter board, CAN 3,4, cable C.2045.10
General: CAN-PCIe/402-Slot2-D as C.2045.10 but without electr. isolation C.2045.11
Ambient temp. 0 °C ... +75 °C CAN-PCIe/402-1-LP Low profile version, CAN 1 C.2045.32
CAN-PCIe/402-1-LP-2 Low profile version, CAN 2 C.2045.34
Rel. humidity Max. 90 % (non-condensing)
CAN layer 2 drivers for Windows and Linux are included in delivery.
Power suppy 3.3 V: 2x CAN IMAX = 280 mA,
4x CAN IMAX = 290 mA Software Support1
12 V: 2x CAN IMAX = 180 mA,
4x CAN IMAX = 230 mA Additional CAN layer 2 object licences including CD-ROM:
CAN-DRV-LCD QNX C.1101.32
Connector PCIe: PCIe card edge connector CAN-DRV-LCD VxWorks C.1101.55
CAN: 1x 9-pin DSUB per CAN channel, CAN-DRV-LCD RTX (incl. RTX64) C.1101.35
male (all except C.2045.08), Higher CAN layer protocols including CD-ROM:
1x 37-pin DSUB, male (only C.2045.08) CANopen-LCD Windows/Linux, RTX, QNX or VxWorks C.1101.xx
Weight CAN-PCIe/402-2: 60g J1939 stack for Windows or Linux C.1130.xx
ARINC 825-LCD for Windows/Linux, RTX, QNX or VxWorks C.1140.xx
1
For detailed information about driver availability for your operating system please contact our sales team.

©2016 esd electronic system design gmbh, Hannover All data are subject to change without prior notice. CiA® and CANopen® are registered community trademarks of CAN in Automation e.V..
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esd electronic system design gmbh Phone: +49 (0) 511 3 72 98-0
Vahrenwalder Str. 207 Fax: +49 (0) 511 3 72 98-68
30165 Hannover / Germany E-mail: info@esd.eu
CAN-PCIe/402
Driven by esdACC (Advanced CAN Core)

Basic Product Features:

• CAN ISO 11898-1 protocol compatibility
• Tested and certified acc. to ISO CAN Conformance Tests
“ISO 16845:2004 Road vehicles - Controller area network (CAN) -
Conformance test plan”
• 11-bit and 29-bit CAN IDs
• Bit rates from 10 kbit/s up to 1 Mbit/s supported
• Receive buffer (64 CAN messages )
• Complete access to CAN error counters
• Programmable error warning limit
• Error code capture register
• Error interrupt for each CAN bus error
• Arbitration lost interrupt with detailed bit position
• Single-shot transmission (no re-transmission)
• Listen only mode (no acknowledge, no active error flags)
• Automatic bit rate detection (hardware supported bit rate
detection)
• Acceptance filter (4-byte code, 4-byte mask)
• Self reception mode (reception of ‘own’ messages)
• Busload measurement

Superior esdACC Features 1: Superior esdACC Features (continued) 1:

• Operating system independently programmable via esd's NTCAN- • Hardware timer to provide accurate software timeouts beyond
API operating system accuracy
• 32-bit register interface optimized for CAN needs • Bus mastering in RX direction takes the load off host CPU (needs
• Easy to program bus master capable local bus to host interface)
• Transmission and reception of CAN frames with a minimum of • Optional integration with 32-bit microcontroller to further relieve
register accesses host CPU
• RX and TX timestamping (64-bit wide, bit accurate, resolution may • Optional different sources for timestamps (e.g. IRIG-B)
vary with input clock, in any case ≤ 62.5 ns, usually 20.833 ns)
• Using FPGA technology provides the option to tailor any feature
• On hardware with IRIG-B interfaces IRIG-B time is used for to any customer's needs, including optional integration with
timestamping customer's FPGA content
• TX FIFO (16 CAN frames deep ) • The esdACC IP core has been verified on Xilinx Spartan and
• Providing the means to generate 100% busload even with Altera Cyclone FPGAs.
non-realtime operating systems
1
Availability of the Superior esdACC Features depends on the operating system. Please contact our sales
• Providing the means for real back-to-back transmission team for further information.

• Timestamped Tx FIFO (16 CAN frames deep)

• High priority
• 64 bit timestamp
• Bit time accuracy for CAN transmission
• Frame accurate abortion of transmissions with minimum delay
• e.g. for driver timeouts
• ISO11898-1 conform For further information on the esdACC IP Core please contact our
• Aborted frames in FIFO won't be blocked by low priority TX sales team.

esd electronic system design gmbh Phone: +49 (0) 511 3 72 98-0
Vahrenwalder Str. 207 Fax: +49 (0) 511 3 72 98-68
30165 Hannover / Germany E-mail: info@esd.eu