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Decoder Design for Engineers

The document describes experiments with decoders. It discusses the function of a 2-to-4 decoder and provides its truth table and VHDL code. The procedure involves opening Quartus II software, creating a new project, writing VHDL code for a 2-to-4 decoder, and filling in the truth table by observing the decoder's inputs and outputs on an FPGA board.

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162 views3 pages

Decoder Design for Engineers

The document describes experiments with decoders. It discusses the function of a 2-to-4 decoder and provides its truth table and VHDL code. The procedure involves opening Quartus II software, creating a new project, writing VHDL code for a 2-to-4 decoder, and filling in the truth table by observing the decoder's inputs and outputs on an FPGA board.

Uploaded by

AAAAALLENN
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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电⽓以2 1 孙嘉56201568

Experiment VII

Decoders & Applications

OBJECTIVES:
 Examine the function of a decoder.
 Design and test a 2-to-4 decoder with active-low outputs using VHDL/HDL.
 Design and simulate a BCD decoder design with active-high outputs in HDL.

MATERIALS:
 Quartus II sofrware 13.1 or higher.
 IBM or compatible computer with Pentium III or higher, 128 M-byte RAM or more, and 8 G-
byte Or larger hard drive.
 XC FPGA Board with Altera FPGA (Cyclone IV EP4CE6E22C8)

DISCUSSION:
The 2-to-4 decoder
Decoders are used often in computer and communication circuits. A decoder activates one of its
outputs depending on the binary number present on its input. If the number of data inputs is N, the
maximum number of outputs for a decoder is 2N since there are 2N possible combinations of inputs.
For a full decoder, there is an output for each combination of inputs. For example, a 2-to-4 decoder
has 2 data inputs and hence 2*2 = 4 outputs. A partial-decoder does not use all possible input
combinations, and so has fewer outputs. The truth table shown below describes the functionality of
the 2-to-4 decoder with active low outputs.

If we examine the truth table closely, we find that there is only one 0 in each output column. So there
is no need to use Boolean algebra or a K-map; we can get the equations by just seeing what
combination of inputs produces the 0 in each column. The equations and schematics are:

1
PROCEDURE:
1. Open Quartus II and create a new project “decodor_2_4”.
2. Create a “.vhd” file and write the gates equivalent VHDL code for a 2-to-4 decoder

3. Fill in the following truth tables for all the gates by observing the inputs/outputs on the programmed
board.

A B O0 O1 O2 O3
SW1 SW2 LED1 LED2 LED3 LED4
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0

2
Question
1.) For a 3-to-8 decoder with active high outputs and an active high enable line (EN):
a. List the truth table:

A 13 00 01 02 03

sw.SwzLED.EDU, ⽐⻅
0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

b. Write the Boolean equations:

00
' '
= A B

'

01 = A3
1

'
02 = AB
O 3 -
AB

c. Sketch the input and output timing waveforms for all input combinations.

:
02

0
3
1 0 0 0

0 0
0 1
3
0 1 0
0

0
0 0 1

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