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TPA3250
SLASE99A – DECEMBER 2015 – REVISED APRIL 2016

TPA3250 70-W Stereo, 130-W peak PurePath™ Ultra-HD Pad Down Class-D Amplifier
1 Features • EMI Compliant When Used With Recommended
•
1 Differential Analog Inputs System Design
• Total Output Power at 10%THD+N
2 Applications
– 70-W Stereo Continuous into 8 Ω in BTL
Configuration at 32 V • High End Soundbar
– 130-W Stereo Peak into 4 Ω in BTL • Mini Combo Systems
Configuration at 32 V • Blu-ray Disk™ / DVD Receivers
• Total Output Power at 1%THD+N • Active Speakers
– 60-W Stereo Continuous into 8 Ω in BTL
Configuration at 32 V
3 Description
The TPA3250 device is a high performance class-D
– 105-W Stereo Peak into 4 Ω in BTL power amplifier that enables true premium sound
Configuration at 32 V quality with class-D efficiency. It features an
• Advanced Integrated Feedback Design with High- advanced integrated feedback design and proprietary
speed Gate Driver Error Correction high-speed gate driver error correction (PurePath™
(PurePath™ Ultra-HD) Ultra-HD). This technology allows ultra low distortion
across the audio band and superior audio quality.
– Signal Bandwidth up to 100 kHz for High
With a 32V power supply the device can drive up to 2
Frequency Content From HD Sources x 130 W peak into 4-Ω load and 2 x 70 W continuous
– Ultra Low 0.005% THD+N at 1 W into 4 Ω and into 8-Ω load and features a 2 VRMS analog input
<0.01% THD+N to Clipping interface that works seamlessly with high
– 60 dB PSRR (BTL, No Input Signal) performance DACs such as TI's PCM5242. In
addition to excellent audio performance, TPA3250
– <60 µV (A-Weighted) Output Noise achieves both high power efficiency and very low
– >110 dB (A Weighted) SNR power stage idle losses below 1 W. This is achieved
• Multiple Configurations Possible: through the use of 60 mΩ MOSFETs and an
optimized gate driver scheme that achieves
– Stereo, Mono, 2.1 and 4xSE
significantly lower idle losses than typical discrete
• Click and Pop Free Startup and Stop implementations.
• 92% Efficient Class-D Operation (8 Ω)
• Wide 12-V to 36-V Supply Voltage Operation Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
• Self-Protection Design (Including Undervoltage,
Overtemperature, Clipping, and Short Circuit TPA3250 HTSSOP (44) 6.10mm x 14.00mm
Protection) With Error Reporting (1) For all available packages, see the orderable addendum at
the end of the datasheet.

Simplified Schematic Total Harmonic Distortion

T H D + N - T o ta l H a r m o n ic D is to r tio n + N o is e - %

10
TPA3250 8:
RIGHT LC
Filter

Audio TAS5630
Source LEFT 1
LC
And Control Filter
/CLIP_OTW

/RESET

/FAULT
0.1
12V
Operation Mode Select M1:M2 Power Supply
Switching Frequency Select FREQ_ADJ 36V
Master/Slave Synchronization OSC_IO
0.01

110VAC->240VAC

T A = 25qC
0.001
10m 100m 1 10 100
Po - Output Power - W
D000

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA3250
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Table of Contents
1 Features .................................................................. 1 9.2 Functional Block Diagrams ..................................... 15
2 Applications ........................................................... 1 9.3 Feature Description................................................. 17
3 Description ............................................................. 1 9.4 Device Functional Modes........................................ 17
4 Revision History..................................................... 2 10 Application and Implementation........................ 21
10.1 Application Information.......................................... 21
5 Device Comparison Table..................................... 3
10.2 Typical Applications .............................................. 21
6 Pin Configuration and Functions ......................... 3
11 Power Supply Recommendations ..................... 28
7 Specifications......................................................... 5
11.1 Power Supplies ..................................................... 28
7.1 Absolute Maximum Ratings ...................................... 5
11.2 Powering Up.......................................................... 28
7.2 ESD Ratings.............................................................. 5
11.3 Powering Down ..................................................... 29
7.3 Recommended Operating Conditions....................... 6
11.4 Thermal Design..................................................... 30
7.4 Thermal Information .................................................. 6
7.5 Electrical Characteristics........................................... 7 12 Layout................................................................... 33
12.1 Layout Guidelines ................................................. 33
7.6 Audio Characteristics (BTL) ...................................... 8
12.2 Layout Examples................................................... 34
7.7 Audio Characteristics (SE) ....................................... 9
7.8 Audio Characteristics (PBTL) ................................... 9 13 Device and Documentation Support ................. 37
7.9 Typical Characteristics, BTL Configuration............. 10 13.1 Documentation Support ........................................ 37
7.10 Typical Characteristics, SE Configuration............. 12 13.2 Community Resources.......................................... 37
7.11 Typical Characteristics, PBTL Configuration ........ 13 13.3 Trademarks ........................................................... 37
13.4 Electrostatic Discharge Caution ............................ 37
8 Parameter Measurement Information ................ 14
13.5 Glossary ................................................................ 37
9 Detailed Description ............................................ 14
9.1 Overview ................................................................. 14 14 Mechanical, Packaging, and Orderable
Information ........................................................... 37

4 Revision History
Changes from Original (December 2015) to Revision A Page

• Changed the datasheet device number From: TPS3250D2 To TPA3250 ............................................................................ 1

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5 Device Comparison Table

DEVICE NAME DESCRIPTION

TPA3251 175-W Stereo Class-D PurePath™ Ultra-HD Analog Input Audio Power Amplifier
TPA3116D2 50W Filter-Free Class-D Stereo Amplifier Family with AM Avoidance
TPA3118D2 30W Filter-Free Class-D Stereo Amplifier Family with AM Avoidance

6 Pin Configuration and Functions

The TPA3250 is available in a thermally enhanced TSSOP package.
The package type contains a PowerPad™ that is located on the bottom side of the device for thermal connection
to the PCB.

DDV Package
HTSSOP 44-Pin
(Top View)

GVDD_CD 1 44 BST_D

CLIP_OTW 2 43 BST_C

VBG 3 42 GND

FAULT 4 41 GND

RESET 5 40 OUT_D

INPUT_D 6 39 OUT_D

INPUT_C 7 38 PVDD_CD

C_START 8 37 PVDD_CD

AVDD 9 36 PVDD_CD

GND 10 35 OUT_C

GND 11 34 GND
Thermal
DVDD 12 Pad 33 GND

OSC_IOP 13 32 OUT_B

OSC_IOM 14 31 PVDD_AB

FREQ_ADJ 15 30 PVDD_AB

OC_ADJ 16 29 PVDD_AB

INPUT_A 17 28 OUT_A

INPUT_B 18 27 OUT_A

M2 19 26 GND

M1 20 25 GND

VDD 21 24 BST_B

GVDD_AB 22 23 BST_A

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Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
AVDD 9 P Internal voltage regulator, analog section
BST_A 23 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_A required.
BST_B 24 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_B required.
BST_C 43 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_C required.
BST_D 44 P HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_D required.
CLIP_OTW 2 O Clipping warning and Over-temperature warning; open drain; active low
C_START 8 O Startup ramp, requires a charging capacitor to GND
DVDD 12 P Internal voltage regulator, digital section
FAULT 4 O Shutdown signal, open drain; active low
FREQ_ADJ 15 O Oscillator frequency programming pin
10, 11, 25, 26, P
GND Ground
33, 34, 41, 42
GVDD_AB 22 P Gate-drive voltage supply; AB-side, requires 0.1 µF capacitor to GND
GVDD_CD 1 P Gate-drive voltage supply; CD-side, requires 0.1 µF capacitor to GND
INPUT_A 17 I Input signal for half bridge A
INPUT_B 18 I Input signal for half bridge B
INPUT_C 7 I Input signal for half bridge C
INPUT_D 6 I Input signal for half bridge D
M1 20 I Mode selection 1 (LSB)
M2 19 I Mode selection 2 (MSB)
OC_ADJ 16 I/O Over-Current threshold programming pin
OSC_IOM 14 I/O Oscillator synchronization interface
OSC_IOP 13 O Oscillator synchronization interface
OUT_A 27, 28 O Output, half bridge A
OUT_B 32 O Output, half bridge B
OUT_C 35 O Output, half bridge C
OUT_D 39, 40 O Output, half bridge D
PVDD_AB 29, 30, 31 P PVDD supply for half-bridge A and B
PVDD_CD 36, 37, 38 P PVDD supply for half-bridge C and D
RESET 5 I Device reset Input; active low
VDD 21 P Power supply for internal voltage regulator requires a 10-µF capacitor with a 0.1-µF capacitor to GND for decoupling.
VBG 3 P Internal voltage reference requires a 0.1-µF capacitor to GND for decoupling.
PowerPAD™ P Ground, connect to PCB copper pour. Placed on bottom side of device.

Table 1. Mode Selection Pins

MODE PINS OUTPUT
INPUT MODE DESCRIPTION
M2 M1 CONFIGURATION
0 0 2N + 1 2 × BTL Stereo BTL output configuration
0 1 2N/1N + 1 1 x BTL + 2 x SE 2.1 BTL + SE mode
1 0 2N + 1 1 x PBTL Parallelled BTL configuration. Connect INPUT_C and INPUT_D to GND.
1 1 1N +1 4 x SE Single ended output configuration

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7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
BST_X to GVDD_X (2) –0.3 50 V
VDD to GND –0.3 13.2 V
GVDD_X to GND (2) –0.3 13.2 V
Supply voltage PVDD_X to GND (2) –0.3 50 V
DVDD to GND –0.3 4.2 V
AVDD to GND –0.3 8.5 V
VBG to GND -0.3 4.2 V
(2)
OUT_X to GND –0.3 50 V
BST_X to GND (2) –0.3 62.5 V
OC_ADJ, M1, M2, OSC_IOP, OSC_IOM, FREQ_ADJ, C_START, to GND –0.3 4.2 V
Interface pins RESET, FAULT, CLIP_OTW, CLIP to GND –0.3 4.2 V
INPUT_X to GND –0.3 7 V
Continuous sink current, RESET, FAULT, CLIP_OTW, CLIP, RESET to 9 mA
GND
TJ Operating junction temperature range 0 150 °C
Tstg Storage temperature range –40 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.

7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
±2000 V
pins (1)
VESD Electrostatic discharge
Charged device model (CDM), per JEDEC specification
±500 V
JESD22-C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
PVDD_x Half-bridge supply DC supply voltage 12 32 38 V
Supply for logic regulators and gate-drive
GVDD_x DC supply voltage 10.8 12 13.2 V
circuitry
VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V
RL(BTL) 2.7 4
Output filter inductance within
RL(SE) Load impedance 1.5 3 Ω
recommended value range
RL(PBTL) 1.6 2
LOUT(BTL) 5
LOUT(SE) Output filter inductance Minimum output inductance at IOC 5 μH
LOUT(PBTL) 5
Nominal 430 450 470
PWM frame rate selectable for AM
FPWM interference avoidance; 1% Resistor AM1 475 500 525 kHz
tolerance
AM2 575 600 625
Nominal; Master mode 29.7 30 30.3
R(FREQ_ADJ) PWM frame rate programming resistor AM1; Master mode 19.8 20 20.2 kΩ
AM2; Master mode 9.9 10 10.1
CPVDD PVDD close decoupling capacitors 1.0 μF
ROC Over-current programming resistor Resistor tolerance = 5% 22 30 kΩ
ROC(LATCHED) Over-current programming resistor Resistor tolerance = 5% 47 64 kΩ
Voltage on FREQ_ADJ pin for slave
V(FREQ_ADJ) Slave mode 3.3 V
mode operation
TJ Junction temperature 0 125 °C

7.4 Thermal Information

TPA3250
THERMAL METRIC (1) DDV 44-PINS HTSSOP UNIT
JEDEC STANDARD 4 LAYER PCB
RθJA Junction-to-ambient thermal resistance 26.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 10.2 °C/W
RθJB Junction-to-board thermal resistance 6.5 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 6.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.4 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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7.5 Electrical Characteristics

PVDD_X = 32 V, GVDD_X = 12 V, VDD = 12 V, TA (Ambient temperature) = 25°C, fS = 450 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as reference
DVDD VDD = 12 V 3 3.3 3.6 V
node
Voltage regulator, only used as reference
AVDD VDD = 12 V 7.8 V
node
Operating, 50% duty cycle 40
IVDD VDD supply current mA
Idle, reset mode 13
50% duty cycle 25
IGVDD_X Gate-supply current per full-bridge mA
Reset mode 3
50% duty cycle with 10µH Output Filter Inductors 12.5 mA
IPVDD_X PVDD idle current per full bridge
Reset mode, No switching 1 mA
ANALOG INPUTS
RIN Input resistance 24 kΩ
VIN Maximum input voltage swing 7 V
IIN Maximum input current 1 mA
G Inverting voltage Gain VOUT/VIN 20 dB
OSCILLATOR
Nominal, Master Mode 2.58 2.7 2.82
fOSC(IO+) AM1, Master Mode FPWM × 6 2.85 3 3.15 MHz
AM2, Master Mode 3.45 3.6 3.75
VIH High level input voltage 1.86 V
VIL Low level input voltage 1.45 V
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS) TJ = 25°C, Includes metallization resistance, 60 100 mΩ
RDS(on)
Drain-to-source resistance, high side (HS) GVDD = 12 V 60 100 mΩ
I/O PROTECTION
Undervoltage protection limit, GVDD_x and
Vuvp,VDD,GVDD 9.5 V
VDD
(1)
Vuvp,VDD, GVDD,hyst 0.6 V
OTW Overtemperature warning, CLIP_OTW (1) 115 125 135 °C
Temperature drop needed below OTW
(1)
OTWhyst temperature for CLIP_OTW to be inactive 25 °C
after OTW event.
OTE (1) Overtemperature error 145 155 165 °C
OTE-OTW(differential)
(1) OTE-OTW differential 30 °C

(1) A reset needs to occur for FAULT to be

OTEhyst 25 °C
released following an OTE event
OLPC Overload protection counter fPWM = 450 kHz 2.3 ms
Resistor – programmable, nominal peak current in
IOC Overcurrent limit protection 14 A
1Ω load, ROCP = 22 kΩ
Resistor – programmable, peak current in 1Ω load,
IOC(LATCHED) Overcurrent limit protection 14 A
ROCP = 47kΩ
IDCspkr DC Speaker Protection Current Threshold BTL current imbalance threshold 1.5 A
Time from switching transition to flip-state induced
IOCT Overcurrent response time 150 ns
by overcurrent.
Connected when RESET is active to provide
IPD Output pulldown current of each half 3 mA
bootstrap charge. Not used in SE mode.

(1) Specified by design.

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Electrical Characteristics (continued)

PVDD_X = 32 V, GVDD_X = 12 V, VDD = 12 V, TA (Ambient temperature) = 25°C, fS = 450 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC DIGITAL SPECIFICATIONS
VIH High level input voltage 1.9 V
M1, M2, OSC_IOP, OSC_IOM, RESET
VIL Low level input voltage 0.8 V
Ilkg Input leakage current 100 μA
OTW/SHUTDOWN (FAULT)
Internal pullup resistance, CLIP_OTW to
RINT_PU 20 26 32 kΩ
DVDD, FAULT to DVDD
VOH High level output voltage Internal pullup resistor 3 3.3 3.6 V
VOL Low level output voltage IO = 4 mA 200 500 mV
Device fanout CLIP_OTW, FAULT No external pullup 30 devices

7.6 Audio Characteristics (BTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 32 V,
GVDD_X = 12 V, RL = 8 Ω, fS = 450 kHz, ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00,
AES17 + AUX-0025 measurement filters,unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 8 Ω, 10% THD+N 70
RL = 4 Ω, 10% THD+N, 3 seconds Peak
130
Power (1)
RL = 4 Ω, 10% THD+N, Single Channel, 300 W
130
seconds duration (1)
PO Power output per channel
RL = 8 Ω, 1% THD+N 60
RL = 4 Ω, 1% THD+N 40
RL = 4 Ω, 1% THD+N, 6 seconds Peak
105
Power (1)
RL = 4 Ω, 1% THD+N, Single Channe (1)l 105
THD+N Total harmonic distortion + noise 1W 0.005%
A-weighted, AES17 filter, Input Capacitor
Vn Output integrated noise 60 μV
Grounded
|VOS| Output offset voltage Inputs AC coupled to GND 20 60 mV
SNR Signal-to-noise ratio (2) 112 dB
DNR Dynamic range 112 dB
Pidle Power dissipation due to Idle losses (IPVDD_X) PO = 0, 4 channels switching (3) 0.6 W

(1) Peak Power rating using TPA3250 EVM

(2) SNR is calculated relative to 1% THD+N output level.
(3) Actual system idle losses also are affected by core losses of output inductors.

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7.7 Audio Characteristics (SE)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 32 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 15 μH, CDEM = 1 µF, MODE = 11,
AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 4 Ω, 10% THD+N 33
RL = 3 Ω, 10% THD+N 42
PO Power output per channel W
RL = 4 Ω, 1% THD+N 27
RL = 3 Ω, 1% THD+N 34
THD+N Total harmonic distortion + noise 1W 0.015%
A-weighted, AES17 filter, Input Capacitor
Vn Output integrated noise 111 μV
Grounded
(1)
SNR Signal to noise ratio A-weighted 100 dB
DNR Dynamic range A-weighted 100 dB
(2)
Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching 0.5 W

(1) SNR is calculated relative to 1% THD+N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

7.8 Audio Characteristics (PBTL)

PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 32 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, MODE = 10,
AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 8 Ω, 10% THD+N 75
RL = 4 Ω, 10% THD+N 145
RL = 3 Ω, 10% THD+N 189
PO Power output per channel W
RL = 8 Ω, 1% THD+N 60
RL = 4 Ω, 1% THD+N 115
RL = 3 Ω, 1% THD+N 150
THD+N Total harmonic distortion + noise 1W 0.015%
A-weighted, AES17 filter, Input Capacitor
Vn Output integrated noise 62 μV
Grounded
(1)
SNR Signal to noise ratio A-weighted 112 dB
DNR Dynamic range A-weighted 107 dB
(2)
Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0, 4 channels switching 0.6 W

(1) SNR is calculated relative to 1% THD+N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

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7.9 Typical Characteristics, BTL Configuration

All Measurements taken at audio frequency = 1 kHz, PVDD_X = 32 V, GVDD_X = 12 V, RL = 8 Ω, fS = 450 kHz, ROC = 22 kΩ,
TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless otherwise
noted.

T H D + N - T o ta l H a r m o n ic D is to r tio n + N o is e - %
T H D + N - T o ta l H a r m o n ic D is to r tio n + N o is e - %

10 10
5 1W T A = 25qC 1W T A = 25qC
10W 10W
2
40W 40W
1
1
0.5

0.2
0.1
0.05 0.1

0.02
0.01
0.005
0.01
0.002
0.001
0.0005
0.0003 0.001
20 100 1k 10k 20k 20 100 1k 10k 40k
f - Frequency - Hz f - Frequency - Hz
D001 D002

RL = 8 Ω P = 1W, 10W, 40W TA = 25°C RL = 8 Ω P = 1W, 10W, 40W TA = 25°C

AUX-0025 filter, 80 kHz analyzer BW

Figure 1. Total Harmonic Distortion+Noise vs Frequency Figure 2. Total Harmonic Distortion+Noise vs Frequency
T H D + N - T o ta l H a r m o n ic D is to r tio n + N o is e - %

10 125
8: 4:
8:
100
P O - O u tp u t P o w e r - W

75

0.1

50

0.01
25
THD+N = 10%
T A = 25qC T A = 25qC
0.001 0
10m 100m 1 10 100 10 15 20 25 30 35 40
Po - Output Power - W PVDD - Supply Voltage - V
D000
D003
D004

RL = 8 Ω TA = 25°C RL = 4 Ω, 8 Ω THD+N = 10% TA = 25°C

Figure 3. Total Harmonic Distortion + Noise vs Output Figure 4. Output Power vs Supply Voltage
Power
120 100
4: 4:
8: 8:
100
P O - O u tp u t P o w e r - W

80
Efficiency - %

60 10

40

20
THD+N = 1%
T A = 25qC TA = 25qC
0 1
10 15 20 25 30 35 40 10m 100m 1 10 100
PVDD - Supply Voltage - V 2 Channel Output Power - W
D005 D006
RL = 4 Ω, 8 Ω THD+N = 1% TA = 25°C RL = 4 Ω, 8 Ω THD+N = 10% TA = 25°C

Figure 5. Output Power vs Supply Voltage Figure 6. System Efficiency vs Output Power

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Typical Characteristics, BTL Configuration (continued)

All Measurements taken at audio frequency = 1 kHz, PVDD_X = 32 V, GVDD_X = 12 V, RL = 8 Ω, fS = 450 kHz, ROC = 22 kΩ,
TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00, AES17 + AUX-0025 measurement filters,unless otherwise
noted.
30 0
4: T A = 25qC 8:
8: -20 V ref = 22.627 V
25 FFT size = 16384
-40

N o is e A m p litu d e - d B
20
Power Loss - W

-60

15 -80

-100
10
-120

5
-140
TA = 25qC
0 -160
0 50 100 150 200 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 48k
2 Channel Output Power - W f - Frequency - Hz
D007 D008

RL = 4 Ω, 8 Ω THD+N = 10% TA = 25°C 8 Ω, VREF = 25.46 V (1% Output power) FFT = 16384
AUX-0025 filter, 80 kHz analyzer BW TA = 25°C

Figure 7. System Power Loss vs Output Power Figure 8. Noise Amplitude vs Frequency

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7.10 Typical Characteristics, SE Configuration

All Measurements taken at audio frequency = 1 kHz, PVDD_X = 32 V, GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ,
TA = 25°C, Output Filter: LDEM = 15 μH, CDEM = 680 nF, MODE = 11, AES17 + AUX-0025 measurement filters, unless
otherwise noted.

THD+N - Total Harmonic Distortion + Noise - %

THD+N - Total Harmonic Distortion + Noise - %

10 10
3: 1W TA = 25qC
4: 5W
15W
1 1

0.1 0.1

0.01 0.01

TA = 25qC
0.001 0.001
10m 100m 1 10 100 20 100 1k 10k 20k
Po - Output Power - W f - Frequency - Hz D010
D009
RL = 3Ω, 4Ω TA = 25°C RL = 4Ω P = 1W, 10W, 25W TA = 25°C

Figure 9. Total Harmonic Distortion+Noise vs Output Power Figure 10. Total Harmonic Distortion+Noise vs Frequency
70
THD+N - Total Harmonic Distortion + Noise - %

10 3:
1W TA = 25qC 4:
60
5W
15W
P O - O u tp u t P o w e r - W

50
1

40

0.1 30

20

0.01 10 THD+N = 10%

T A = 25qC
0
10 15 20 25 30 35 40
0.001 PVDD - Supply Voltage - V
D012
20 100 1k 10k 40k
RL = 3Ω, 4Ω THD+N = 10% TA = 25°C
f - Frequency - Hz D011
RL = 4Ω P = 1W, 10W, 25W TA = 25°C
AUX-0025 filter, 80 kHz analyzer BW
Figure 12. Output Power vs Supply Voltage
Figure 11. Total Harmonic Distortion+Noise vs Frequency
60
3:
4:
50
P O - O u tp u t P o w e r - W

40

30

20

10
THD+N = 1%
T A = 25qC
0
10 15 20 25 30 35 40
PVDD - Supply Voltage - V
D013

RL = 3Ω, 4Ω THD+N = 1% TA = 25°C

Figure 13. Output Power vs Supply Voltage

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7.11 Typical Characteristics, PBTL Configuration

All Measurements taken at audio frequency = 1kHz, PVDD_X = 32 V, GVDD_X = 12 V, RL = 4Ω, fS = 450 kHz, ROC = 22 kΩ,
TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, MODE = 10, AES17 + AUX-0025 measurement filters, unless otherwise
noted.
THD+N - Total Harmonic Distortion + Noise - %

THD+N - Total Harmonic Distortion + Noise - %

10 10
4: 5 1W TA = 25qC
8: 20W
2 75W
1
1
0.5
0.2
0.1
0.1 0.05
0.02
0.01
0.01 0.005
0.002
0.001
TA = 25qC 0.0005
0.001 0.0003
10m 100m 1 10 100 20 100 1k 10k 20k
Po - Output Power - W D014
f - Frequency - Hz D015
RL = 4Ω, 8Ω TA = 25°C RL = 4Ω P = 1W, 20W, 75W TA = 25°C

Figure 14. Total Harmonic Distortion+Noise vs Output Figure 15. Total Harmonic Distortion+Noise vs Frequency
Power
275
THD+N - Total Harmonic Distortion + Noise - %

10 3:
1W TA = 25qC 250
4:
20W 225
75W
P O - O u tp u t P o w e r - W

1 200

175

150
0.1 125

100

75
0.01
50

25 THD+N = 10%
T A = 25qC
0
0.001 10 15 20 25 30 35 40
20 100 1k 10k 40k PVDD - Supply Voltage - V
f - Frequency - Hz D016
D017

RL = 4Ω P = 1W, 20W, 75W TA = 25°C RL = 3Ω, 4Ω THD+N = 10% TA = 25°C

AUX-0025 filter, 80 kHz analyzer BW

Figure 16. Total Harmonic Distortion+Noise vs Frequency Figure 17. Output Power vs Supply Voltage
225
3:
200 4:

175
P O - O u tp u t P o w e r - W

150

125

100

75

50

25 THD+N = 1%
T A = 25qC
0
10 15 20 25 30 35 40
PVDD - Supply Voltage - V
D018

RL = 3Ω, 4Ω THD+N = 1% TA = 25°C

Figure 18. Output Power vs Supply Voltage

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8 Parameter Measurement Information

All parameters are measured according to the conditions described in the Recommended Operating Conditions,
Typical Characteristics, BTL Configuration, Typical Characteristics, SE Configuration and Typical Characteristics,
PBTL Configuration sections.
Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to
out of band noise present at the amplifier output. AES-17 + AUX-0025 pre-analyzer filters are recommended to
use for Class-D amplifier measurements. In absence of such filters, a 30-kHz low-pass filter (10 Ω + 47 nF) can
be used to reduce the out of band noise remaining on the amplifier outputs.

9 Detailed Description

9.1 Overview
To facilitate system design, the TPA3250 needs only a 12-V supply in addition to the (typical) 32-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry, AVDD and DVDD. Additionally, all circuitry requiring a floating voltage supply, that is, the high-side gate
drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
The audio signal path including gate drive and output stage is designed as identical, independent half-bridges.
For this reason, each half-bridge has separate bootstrap pins (BST_X). Power-stage supply pins (PVDD_X) and
gate drive supply pins (GVDD_X) are separate for each full bridge. Although supplied from the same 12-V
source, separating to GVDD_AB, GVDD_CD, and VDD on the printed-circuit board (PCB) by RC filters (see
application diagram for details) is recommended. These RC filters provide the recommended high-frequency
isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as
possible. In general, the physical loop with the power supply pins, decoupling capacitors and GND return path to
the device pins must be kept as short as possible and with as little area as possible to minimize induction (see
reference board documentation for additional information).
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. It is recommended to use 33-
nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient
energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully
turned on during the remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each full-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X node is
decoupled with 1-μF ceramic capacitor placed as close as possible to the supply pins. It is recommended to
follow the PCB layout of the TPA3250 reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 36-V power-
stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit, but it is recommended to release RESET after the power
supply is settled for minimum turn on audible artefacts. Moreover, the TPA3250 is fully protected against
erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-
critical within the specified range (see the Recommended Operating Conditions table of this data sheet).

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9.2 Functional Block Diagrams

/CLIP_OTW

VDD

VBG

VREG AVDD
POWER-UP
/FAULT UVP
RESET
DVDD

GND
M1

PROTECTION & I/O LOGIC

TEMP GVDD_A GVDD_C
SENSE
M2 GND
GVDD_B GVDD_D

/RESET

DIFFOC
STARTUP
CONTROL
C_START
OVER-LOAD
PROTECTION CURRENT
CB3C OC_ADJ
SENSE
OSC_IOM

OSC_IOP OSCILLATOR PVDD_X

PPSC OUT_X
FREQ_ADJ GND

GVDD_AB
PWM
ACTIVITY
DETECTOR BST_A

PVDD_AB

- PWM TIMING
INPUT_A CONTROL GATE-DRIVE OUT_A
ANALOG RECEIVER CONTROL
LOOP FILTER
+
GND

GVDD_AB

BST_B

PVDD_AB

- PWM TIMING
INPUT_B CONTROL GATE-DRIVE OUT_B
ANALOG RECEIVER CONTROL
LOOP FILTER
+
GND

GVDD_CD

BST_C

PVDD_CD

- PWM TIMING
INPUT_C CONTROL GATE-DRIVE OUT_C
ANALOG RECEIVER CONTROL
LOOP FILTER
+
GND

GVDD_CD

BST_D

PVDD_CD

- PWM TIMING
INPUT_D CONTROL GATE-DRIVE OUT_D
ANALOG RECEIVER CONTROL
LOOP FILTER
+
GND

FunctionalBlockDiagram.vsd

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Functional Block Diagrams (continued)

Capacitor for
External
System Filtering
microcontroller or &
Analog circuitry Startup/Stop

/FAULT

/CLIP_OTW

C_START
/RESET
BST_A
Oscillator OSC_IOP
Bootstrap
Synchronization OSC_IOM BST_B Capacitors

OUT_A 2nd Order

Output L-C Output
INPUT_A
ANALOG_IN_A Input DC H-Bridge 1 OUT_B Filter for
Input
Blocking each
ANALOG_IN_B
INPUT_B H-Bridge 1
Caps H-Bridge

2-CHANNEL
Hardwire PWM
Frame Adjust
H-BRIDGE
FREQ_ADJ
& Master/Slave BTL MODE
Mode

OUT_C
2nd Order
INPUT_C
ANALOG_IN_C Input DC Input Output L-C Output
Blocking INPUT_D H-Bridge 2 H-Bridge 2 OUT_D
Filter for
ANALOG_IN_D Caps each
H-Bridge

BST_C
Hardwire M1
GVDD_AB, CD
PVDD_AB, CD

Mode M2 Bootstrap
BST_D Capacitors
OC_ADJ

Control
DVDD

AVDD
VBG
GND

VDD
GND

PVDD PVDD GVDD, VDD, Hardwire

36V Power Supply DVDD & Over-
SYSTEM Decoupling AVDD Current
Power Supply
Power Limit
Decoupling
Supplies
GND
GND
GVDD (12V)/VDD (12V)
12V

VAC
*NOTE1: Logic AND in or outside microcontroller

Figure 19. System Block Diagram

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9.3 Feature Description

9.3.1 Error Reporting
The FAULT, and CLIP_OTW, pins are active-low, open-drain outputs. The function is for protection-mode
signaling to a system-control device.
Any fault resulting in device shutdown is signaled by the FAULT pin going low. Also, CLIP_OTW goes low when
the device junction temperature exceeds 125°C (see Table 2).

Table 2. Error Reporting

FAULT CLIP_OTW DESCRIPTION
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) Junction
0 0
temperature higher than 125°C (overtemperature warning)
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 125°C
0 0
(overtemperature warning)
0 1 Overload (OLP) or undervoltage (UVP). Junction temperature lower than 125°C
1 0 Junction temperature higher than 125°C (overtemperature warning)
1 1 Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)

Note that asserting either RESET low forces the FAULT signal high, independent of faults being present. TI
recommends monitoring the CLIP_OTW signal using the system microcontroller and responding to an
overtemperature warning signal by, that is, turning down the volume to prevent further heating of the device
resulting in device shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and
CLIP_OTW outputs.

9.4 Device Functional Modes

9.4.1 Device Protection System
The TPA3250 contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overload, overtemperature, and undervoltage. The TPA3250 responds to a fault by immediately
setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In situations other
than overload and overtemperature error (OTE), the device automatically recovers when the fault condition has
been removed, that is, the supply voltage has increased.
The device will function on errors, as shown in Table 3.

Table 3. Device Protection

BTL MODE PBTL MODE SE MODE
LOCAL LOCAL LOCAL
TURNS OFF TURNS OFF TURNS OFF
ERROR IN ERROR IN ERROR IN
A A A
A+B A+B
B B B
A+B+C+D
C C C
C+D C+D
D D D

Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge (non-latching,
does not assert FAULT).

9.4.1.1 Overload and Short Circuit Current Protection

TPA3250 has fast reacting current sensors with a programmable trip threshold (OC threshold) on all high-side
and low-side FETs. To prevent output current to increase beyond the programmed threshold, TPA3250 has the
option of either limiting the output current for each switching cycle (Cycle By Cycle Current Control, CB3C) or to
perform an immediate shutdown of the output in case of excess output current (Latching Shutdown). CB3C
prevents premature shutdown due to high output current transients caused by high level music transients and a

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drop of real speaker’s load impedance, and allows the output current to be limited to a maximum programmed
level. If the maximum output current persists, i.e. the power stage being overloaded with too low load impedance,
the device will shut down the affected output channel and the affected output is put in a high-impedance (Hi- Z)
state until a RESET cycle is initiated. CB3C works individually for each half bridge output. If an over current
event is triggered, CB3C performs a state flip of the half bridge output that is cleared upon beginning of next
PWM frame.

PWM_X
RISING EDGE PWM
SETS CB3C LATCH

HS PWM

LS PWM
OC EVENT RESETS
OC THRESHOLD CB3C LATCH

OUTPUT CURRENT

OCH

HS GATE-DRIVE

LS GATE-DRIVE

Figure 20. CB3C Timing Example

During CB3C an over load counter increments for each over current event and decrease for each non-over
current PWM cycle. This allows full amplitude transients into a low speaker impedance without a shutdown
protection action. In the event of a short circuit condition, the over current protection limits the output current by
the CB3C operation and eventually shut down the affected output if the overload counter reaches its maximum
value. If a latched OC operation is required such that the device shuts down the affected output immediately
upon first detected over current event, this protection mode should be selected. The over current threshold and
mode (CB3C or Latched OC) is programmed by the OC_ADJ resistor value. The OC_ADJ resistor needs to be
within its intentional value range for either CB3C operation or Latched OC operation.
I_OC

IOC_max

IOC_min
Not Defined

ROC_ADJ
CB3C, min level
R_OC, max,

Latching OC, max level

R_Latch, min,

Latching OC, min level

R_Latch, max,
CB3C, max level
R_OC, min,

Figure 21. OC Threshold versus OC_ADJ Resistor Value Example

OC_ADJ values outside specified value range for either CB3C or latched OC operation will result in minimum OC
threshold.

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Table 4. Device Protection

OC_ADJ Resistor Value Protection Mode OC Threshold
22kΩ CB3C 16.3A
24kΩ CB3C 15.1A
27kΩ CB3C 13.5A
30kΩ CB3C 12.3A
47kΩ Latched OC 16.3A
51kΩ Latched OC 15.1A
56kΩ Latched OC 13.5A
64kΩ Latched OC 12.3A

9.4.1.2 DC Speaker Protection

The output DC protection scheme protects a connected speaker from excess DC current caused by a speaker
wire accidentally shorted to chassis ground. Such a short circuit results in a DC voltage of PVDD/2 across the
speaker, which potentially can result in destructive current levels. The output DC protection detects any
unbalance of the output and input current of a BTL output, and in the event of the unbalance exceeding a
programmed threshold, the overload counter increments until its maximum value and the affected output channel
is shut down. DC Speaker Protection is disabled in PBTL and SE mode operation.

9.4.1.3 Pin-to-Pin Short Circuit Protection (PPSC)

The PPSC detection system protects the device from permanent damage in the case that a power output pin
(OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent
after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup that is, when VDD is supplied, consequently a short to either GND_X or PVDD_X after
system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on
the output, all half bridges are kept in a Hi-Z state until the short is removed; the device then continues the
startup sequence and starts switching. The detection is controlled globally by a two step sequence. The first step
ensures that there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from
OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC
filter. The typical duration is < 15 ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the
device will not react to changes applied to the RESET pin. If no shorts are present the PPSC detection passes,
and FAULT is released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL
and PBTL output configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC
detection system it is recommended not to insert a resistive load to GND_X or PVDD_X.

9.4.1.4 Overtemperature Protection OTW and OTE

TPA3250 has a two-level temperature-protection system that asserts an active-low warning signal (CLIP_OTW)
when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds
155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-
impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To clear the OTE latch,
RESET must be asserted. Thereafter, the device resumes normal operation.

9.4.1.5 Undervoltage Protection (UVP) and Power-on Reset (POR)

The UVP and POR circuits of the TPA3250 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table.
Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on
any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)
state and FAULT being asserted low. The device automatically resumes operation when all supply voltages have
increased above the UVP threshold.

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9.4.1.6 Fault Handling

If a fault situation occurs while in operation, the device acts accordingly to the fault being a global or a channel
fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut down, and
will assert FAULT low. A global fault is a latching fault and clearing FAULT and restart operation requires
resetting the device by toggling RESET. Toggling RESET should never be allowed with excessive system
temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET
(RESET high) if the OTW signal is cleared (high). A channel fault results in shutdown of the PWM activity of the
affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults being
present. TI recommends monitoring the OTW signal using the system micro controller and responding to an over
temperature warning signal by, that is, turning down the volume to prevent further heating of the device resulting
in device shutdown (OTE).

Table 5. Error Reporting

Fault/Event Global or Reporting Latched/Self Action needed
Fault/Event Output FETs
Description Channel Method Clearing to Clear
PVDD_X UVP
Increase affected
VDD UVP Voltage Fault Global FAULT pin Self Clearing HI-Z
supply voltage
AVDD UVP
Allow DVDD to
POR (DVDD UVP) Power On Reset Global FAULT pin Self Clearing HI-Z
rise
Allow BST cap to
Channel (Half
BST_X UVP Voltage Fault None Self Clearing recharge (lowside HighSide off
Bridge)
ON, VDD 12V)
Cool below OTW
OTW Thermal Warning Global OTW pin Self Clearing Normal operation
threshold
Thermal
OTE Global FAULT pin Latched Toggle RESET HI-Z
Shutdown
OLP (CB3C>1.7ms) OC Shutdown Channel FAULT pin Latched Toggle RESET HI-Z
Latched OC
(47kΩ<ROC_ADJ<68 OC Shutdown Channel FAULT pin Latched Toggle RESET HI-Z
kΩ)
CB3C Reduce signal
Flip state, cycle
(22kΩ<ROC_ADJ<30 OC Limiting Channel None Self Clearing level or remove
by cycle at fs/3
kΩ) short
No OSC_IO
Resume OSC_IO
Stuck at Fault (1) activity in Slave Global None Self Clearing HI-Z
activity
Mode

(1) Stuck at Fault occurs when input OSC_IO input signal frequency drops below minimum frequency given in the Electrical Characteristics
table of this data sheet.

9.4.1.7 Device Reset

Asserting RESET low initiates the device ramp down. The output FETs go into a Hi-Z state after the ramp down
is complete. Output pull downs are active both in SE mode and BTL mode with RESET low.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs.
Asserting reset input low removes any fault information to be signaled on the FAULT output, that is, FAULT is
forced high. A rising-edge transition on reset input allows the device to resume operation after an overload fault.
To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the falling edge of
FAULT.

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10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information

TPA3250 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1 mixed
1x BTL + 2x SE mode depending on output power conditions and system design.

10.2 Typical Applications

10.2.1 Stereo BTL Application
3R3

+12V
470uF 100nF 100nF 33nF
1 44
GVDD_AB BST_A
10µH
2 43
VDD BST_B
10nF
3 42 33nF
M1 GND 1nF
4 41 1µF
M2 GND 3R3
10µF 5 40
INPUT_A INPUT_A OUT_A
10µF 1µF
6 39 3R3
INPUT_B INPUT_B OUT_A 1nF
22k 7 38 10nF
OC_ADJ PVDD_AB 1µF
10µH
30k 8 37
FREQ_ADJ PVDD_AB 470uF
9 36
OSC_IOM PVDD_AB
10 35
PVDD
OSC_IOP OUT_B
1µF 1µF
11 34
DVDD GND
12
GND
TPA3250 GND
33 GND
13 32 1µF
GND OUT_C
1µF 14 31
AVDD PVDD_CD
10nF 10µH
15 30
C_START PVDD_CD 1µF 470uF
10µF 10nF
16 29
INPUT_C INPUT_C PVDD_CD 1nF
10µF 17 28 1µF
INPUT_D INPUT_D OUT_D 3R3
18 27
/RESET /RESET OUT_D
1µF
19 26 3R3
/FAULT /FAULT GND 1nF
100nF 20 25 10nF
VBG GND 33nF 10µH
21 24
/CLIP_OTW /CLIP_OTW BST_C
3R3 22 23
GVDD_CD BST_D
100nF
33nF

Figure 22. Typical Differential Input BTL Application

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Typical Applications (continued)

10.2.1.1 Design Requirements
For this design example, use the parameters in Table 6.

Table 6. Design Requirements, BTL Application

DESIGN PARAMETER EXAMPLE
Low Power (Pull-up) Supply 3.3 V
Mid Power Supply 12 V 12 V
High Power Supply 12 - 32 V
M2 = L
Mode Selection
M1 = L
INPUT_A = ±3.9 V (peak, max)
INPUT_B = ± 3.9V (peak, max)
Analog Inputs
INPUT_C = ±3.9 V (peak, max)
INPUT_D = ±3.9 V (peak, max)
Output Filters Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
Speaker Impedance 3-8 Ω

10.2.1.2 Detailed Design Procedures

A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audio
volume decrease or intelligent power supply nominally operating at a low rail adjusting to a higher supply rail.
The device is inverting the audio signal from input to output.
The DVDD and AVDD pins are not recommended to be used as a voltage sources for external circuitry.

10.2.1.2.1 Decoupling Capacitor Recommendations

In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 1μF that is placed on the power supply to each full-bridge. It must withstand the voltage
overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple
current created by high power output. A minimum voltage rating of 50 V is required for use with a 32V power
supply.

10.2.1.2.2 PVDD Capacitor Recommendation

The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000 μF, 50 V supports most applications.
The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speed
switching.

10.2.1.2.3 PCB Material Recommendation

FR-4 Glass Epoxy material with 2 oz. (70 μm) copper is recommended for use with the TPA3250. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance.

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10.2.1.2.4 Oscillator
The oscillator frequency can be trimmed by external control of the FREQ_ADJ pin.
To reduce interference problems while using radio receiver tuned within the AM band, the switching frequency
can be changed from nominal to lower values. These values should be chosen such that the nominal and the
lower value switching frequencies together results in the fewest cases of interference throughout the AM band.
The oscillator frequency can be selected by the value of the FREQ_ADJ resistor connected to GND in master
mode according to the description in the Recommended Operating Conditions table.
For slave mode operation, turn off the oscillator by pulling the FREQ_ADJ pin to DVDD. This configures the
OSC_I/O pins as inputs to be slaved from an external differential clock. In a master/slave system inter channel
delay is automatically setup between the switching of the audio channels, which can be illustrated by no idle
channels switching at the same time. This will not influence the audio output, but only the switch timing to
minimize noise coupling between audio channels through the power supply to optimize audio performance and to
get better operating conditions for the power supply. The inter channel delay will be setup for a slave device
depending on the polarity of the OSC_I/O connection such that a slave mode 1 is selected by connecting the
master device OSC_I/O to the slave 1 device OSC_I/O with same polarity (+ to + and - to -), and slave mode 2 is
selected with the inverse polarity (+ to - and - to +).

10.2.2 Application Curves

Relevant performance plots for TPA3250 in BTL configuration are shown in Typical Characteristics, BTL
Configuration

Table 7. Relevant Performance Plots, BTL Configuration

PLOT TITLE FIGURE NUMBER
Total Harmonic Distortion+Noise vs Frequency Figure 1
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW Figure 2
Total Harmonic Distortion + Noise vs Output Power Figure 3
Output Power vs Supply Voltage, 10% THD+N Figure 4
Output Power vs Supply Voltage, 10% THD+N Figure 6
System Efficiency vs Output Power Figure 6
System Power Loss vs Output Power Figure 7
Output Power vs Case Temperature
Noise Amplitude vs Frequency Figure 8

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10.2.3 Typical Application, Single Ended (1N) SE

TPA3250 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1 mixed
1x BTL + 2x SE mode depending on output power conditions and system design.
15µH 470uF
3R3

+12V
470uF 100nF 100nF 33nF
1 44 10nF
GVDD_AB BST_A
1nF
2 43 1µF
VDD BST_B
3 42 3R3
M1 GND 33nF
4 41
M2 GND 1µF 3R3
10µF 1nF
5 40
INPUT_A INPUT_A OUT_A 10nF
10µF 6 39
INPUT_B INPUT_B OUT_A
22k 7 38
OC_ADJ PVDD_AB 1µF 470uF
15µH
30k 8 37
FREQ_ADJ PVDD_AB 470uF
9 36
OSC_IOM PVDD_AB
10 35
PVDD
OSC_IOP OUT_B
1µF 1µF
11 34
DVDD GND
12
GND
TPA3250 GND
33 GND
13 32 1µF
GND OUT_C
1µF 14 31
AVDD PVDD_CD 470uF
470nF 15µH
15 30
C_START PVDD_CD 1µF 470uF
10µF 16 29
INPUT_C INPUT_C PVDD_CD
10µF 17 28
INPUT_D INPUT_D OUT_D 10nF
18 27 1nF
/RESET /RESET OUT_D 1µF
19 26 3R3
/FAULT /FAULT GND
100nF 20 25
VBG GND 33nF
1µF 3R3
21 24 1nF
/CLIP_OTW /CLIP_OTW BST_C
3R3 10nF
22 23
GVDD_CD BST_D
100nF
33nF
15µH 470uF

Figure 23. Typical Single Ended (1N) SE Application

10.2.3.1 Design Requirements

Refer to Stereo BTL Application for the Design Requirements.

Table 8. Design Requirements, SE Application

DESIGN PARAMETER EXAMPLE
Low Power (Pull-up) Supply 3.3 V
Mid Power Supply 1 2V 12 V
High Power Supply 12 - 32 V
M2 = H
Mode Selection
M1 = H
INPUT_A = ±3.9 V (peak, max)
INPUT_B = ±3.9 V (peak, max)
Analog Inputs
INPUT_C = ±3.9 V (peak, max)
INPUT_D = ±3.9 V (peak, max)
Output Filters Inductor-Capacitor Low Pass FIlter (15 µH + 680 nF)
Speaker Impedance 2-8Ω

10.2.3.2 Detailed Design Procedures

Refer to Stereo BTL Application for the Detailed Design Procedures.

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10.2.3.3 Application Curves

Relevant performance plots for TPA3250 in PBTL configuration are shown in Typical Characteristics, SE
Configuration

Table 9. Relevant Performance Plots, SE Configuration

PLOT TITLE FIGURE NUMBER
Total Harmonic Distortion+Noise vs Output Power Figure 9
Total Harmonic Distortion+Noise vs Frequency Figure 10
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW Figure 11
Output Power vs Supply Voltage, 10% THD+N Figure 12
Output Power vs Supply Voltage, 1% THD+N Figure 13
Output Power vs Case Temperature

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10.2.4 Typical Application, Differential (2N) PBTL

TPA3250 can be configured either in stereo BTL mode, 4 channel SE mode, mono PBTL mode, or in 2.1 mixed
1x BTL + 2x SE mode depending on output power conditions and system design.
3R3

+12V
470uF 100nF 100nF 33nF
1 44
GVDD_AB BST_A
10µH
2 43
VDD BST_B
3 42 33nF
M1 GND
4 41
M2 GND
10µF 5 40
INPUT_A INPUT_A OUT_A
10µF 6 39
INPUT_B INPUT_B OUT_A
22k 7 38 PVDD
OC_ADJ PVDD_AB 1µF
10µH
30k 8 37
FREQ_ADJ PVDD_AB 470uF
9 36 10nF
OSC_IOM PVDD_AB
10 35 1nF
OSC_IOP OUT_B 680nF
1µF 1µF
11 34 3R3
DVDD GND
12
GND
TPA3250 GND
33 680nF
3R3
13 32 1µF 1nF
GND OUT_C 10nF
1µF 14 31
AVDD PVDD_CD
10nF 10µH
15 30
C_START PVDD_CD 1µF 470uF
16 29
INPUT_C PVDD_CD GND
17 28
INPUT_D OUT_D
18 27
/RESET /RESET OUT_D
19 26
/FAULT /FAULT GND
100nF 20 25
VBG GND 33nF 10µH
21 24
/CLIP_OTW /CLIP_OTW BST_C
3R3 22 23
GVDD_CD BST_D
100nF
33nF

Figure 24. Typical Differential (2N) PBTL Application

10.2.4.1 Design Requirements

Refer to Stereo BTL Application for the Design Requirements.

Table 10. Design Requirements, PBTL Application

DESIGN PARAMETER EXAMPLE
Low Power (Pull-up) Supply 3.3 V
Mid Power Supply 12 V 12 V
High Power Supply 12 - 32 V
M2 = H
Mode Selection
M1 = L
INPUT_A = ±3.9V (peak, max)
INPUT_B = ±3.9V (peak, max)
Analog Inputs
INPUT_C = Grounded
INPUT_D = Grounded
Output Filters Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)
Speaker Impedance 2-4Ω

10.2.4.2 Detailed Design Procedures

Refer to Stereo BTL Application for the Detailed Design Procedures.

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10.2.4.3 Application Curves

Relevant performance plots for TPA3250 in PBTL configuration are shown in Typical Characteristics, PBTL
Configuration

Table 11. Relevant Performance Plots, PBTL Configuration

PLOT TITLE FIGURE NUMBER
Total Harmonic Distortion+Noise vs Output Power Figure 14
Total Harmonic Distortion+Noise vs Frequency Figure 15
Total Harmonic Distortion+Noise vs Frequency, 80kHz analyzer BW Figure 16
Output Power vs Supply Voltage, 10% THD+N Figure 17
Output Power vs Supply Voltage, 1% THD+N Figure 18
Output Power vs Case Temperature

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11 Power Supply Recommendations

11.1 Power Supplies

The TPA3250 device requires two external power supplies for proper operation. A high-voltage supply called
PVDD is required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one
mid-voltage power supply for GVDD_X and VDD is required to power the gate-drive and other internal digital and
analog portions of the device. The allowable voltage range for both the PVDD and the GVDD_X/VDD supplies
are listed in the Recommended Operating Conditions table. Ensure both the PVDD and the GVDD_X/VDD
supplies can deliver more current than listed in the Electrical Characteristics table.

11.1.1 VDD Supply

The VDD supply required from the system is used to power several portions of the device. It provides power to
internal regulators DVDD and AVDD that are used to power digital and analog sections of the device,
respectively. Proper connection, routing, and decoupling techniques are highlighted in the TPA3250 device EVM
User's Guide SLVUAG8 (as well as the Application Information section and Layout Examples section) and must
be followed as closely as possible for proper operation and performance. Deviation from the guidance offered in
the TPA3250 device EVM User's Guide, which followed the same techniques as those shown in the Application
Information section, may result in reduced performance, errant functionality, or even damage to the TPA3250
device. Some portions of the device also require a separate power supply which is a lower voltage than the VDD
supply. To simplify the power supply requirements for the system, the TPA3250 device includes integrated low-
dropout (LDO) linear regulators to create these supplies. These linear regulators are internally connected to the
VDD supply and their outputs are presented on AVDD and DVDD pins, providing a connection point for an
external bypass capacitors. It is important to note that the linear regulators integrated in the device have only
been designed to support the current requirements of the internal circuitry, and should not be used to power any
additional external circuitry. Additional loading on these pins could cause the voltage to sag and increase noise
injection, which negatively affects the performance and operation of the device.

11.1.2 GVDD_X Supply

The GVDD_X supply required from the system is used to power the gate-drives for the output H-bridges. Proper
connection, routing, and decoupling techniques are highlighted in the TPA3250 device EVM User's Guide
SLVUAG8 (as well as the Application Information section and Layout Examples section) and must be followed as
closely as possible for proper operation and performance. Deviation from the guidance offered in the TPA3250
device EVM User's Guide, which followed the same techniques as those shown in the Application Information
section, may result in reduced performance, errant functionality, or even damage to the TPA3250 device.

11.1.3 PVDD Supply

The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which
provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are
highlighted in the TPA3250 device EVM User's Guide SLVUAG8 (as well as the Application Information section
and Layout Examples section) and must be followed as closely as possible for proper operation and
performance. Due the high-voltage switching of the output stage, it is particularly important to properly decouple
the output power stages in the manner described in the TPA3250 device EVM User's Guide SLVUAG8. The lack
of proper decoupling, like that shown in the EVM User's Guide, can results in voltage spikes which can damage
the device, or cause poor audio performance and device shutdown faults.

11.2 Powering Up
The TPA3250 does not require a power-up sequence, but it is recommended to hold RESET low minimum
400ms after PVDD supply voltage is turned ON. The outputs of the H-bridges remain in a high-impedance state
until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection (UVP)
voltage threshold (see the Electrical Characteristics table of this data sheet). This allows an internal circuit to
charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output as well as
initiating a controlled ramp up sequence of the output voltage.

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Powering Up (continued)

PVDD

VDD

GVDD

tRESET delay > 400ms DVDD

/RESET

AVDD
tAVDD ramp C 100µs

/FAULT
tPrecharge C 220ms

VIN_X

OUT_X

VOUT_X

tStartup ramp

Figure 25. Startup Timing

When RESET is released to turn on TPA3250, FAULT signal will turn low and AVDD voltage regulator will be
enabled. FAULT will stay low until AVDD reaches the undervoltage protection (UVP) voltage threshold (see the
Electrical Characteristics table of this data sheet). After a precharge time to stabilize the DC voltage across the
input AC coupling capacitors, before the ramp up sequence starts.

11.3 Powering Down

The TPA3250 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a
good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks by
initiating a controlled ramp down sequence of the output voltage.

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11.4 Thermal Design

11.4.1 Thermal Performance
TPA3250 thermal performance is dependent on the thermal design of the PCB. As a result, the maximum
continuous output power attainable will be influenced by the PCB design. The continuous power rating is lower
than the peak output power capability of the device. TPA3250 peak power rating is based on the burst capability
of the device. The peak to average power ratio of TPA3250 is well suited to handle even demanding audio
playback without thermal shutdown. Thermal performance with typical audio content (burst) versus sine wave
content (continuous) should be considered when defining the thermal test requirements for the end product.

11.4.2 Thermal Performance with Continuous Output Power

It is recommended to operate TPA3250 below the OTW threshold, which in most systems will require the
average output power to be below the maximum peak output power. The maximum continuous power TPA3250
will deliver depends directly on the thermal design of the PCB and for the entire system (closed box with no air
flow, or a fanned system etc.). Thermal performance is also impacted by PVDD voltage and switching frequency.
The best configuration for a given application will often depend on the continuous output power requirements.

Table 12. Device and PCB Temperatures with 8-Ω Load, TA = 40°C
TA = 40°C, TPA3250 EVM, No Airflow. Steady State Temperatures.
Switching Device Top Maximum PCB
PVDD Continuous Power [W] Comment
Frequency Temperature Temperature
32V 450kHz 73W 10% THD 114°C 89°C
32V 450kHz 18W 1/4 of 10% THD power 87°C 71°C
32V 450kHz 9W 1/8 of 10% THD power 77°C 65°C
32V 600kHz 72W 10% THD 128°C 98°C OTW after 236 seconds
32V 600kHz 18W 1/4 of 10% THD power 105°C 84°C
32V 600kHz 9W 1/8 of 10% THD power 85°C 70°C
36V 450kHz 92W 10% THD 150°C 113°C OTW after 95 seconds
36V 450kHz 23W 1/4 of 10% THD power 111°C 87°C
36V 450kHz 11.5W 1/8 of 10% THD power 79°C 71°C
OTW after 3 seconds. Not
36V 600kHz 91W 10% THD OTE (1)
recommended.
36V 600kHz 22.5W 1/4 of 10% THD power 144°C 109°C OTW after 152 seconds
36V 600kHz 11.5W 1/8 of 10% THD power 115°C 90°C

(1) Steady state data is not available because device heats up to OTE in this condition.

Table 13. Device and PCB Temperatures with 4-Ω Load, TA = 40°C
TA = 40°C, TPA3250 EVM, No Airflow. Steady State Temperatures.
Switching Device Top Maximum PCB
PVDD Continuous Power [W] Comment
Frequency Temperature Temperature
OTW after 1 second.Not
32V 450kHz 130W 10% THD OTE
recommended.
OTW after 92 seconds. Not
32V 450kHz 32.5W 1/4 of 10% THD power 147°C 111°C
recommended.
32V 450kHz 16W 1/8 of 10% THD power 107°C 85°C
OTW after 1 second. Not
32V 600kHz 130W 10% THD OTE (1)
recommended.
OTW after 29 seconds. Not
32V 600kHz 32.5W 1/4 of 10% THD power OTE (1)
recommended.
OTW after 92 seconds. Not
32V 600kHz 16W 1/8 of 10% THD power 147°C 99°C
recommended.
OTW after 0 seconds. Not
36V 450kHz 165W 10% THD OTE (1)
recommended.
OTW after 11 seconds. Not
36V 450kHz 41W 1/4 of 10% THD power OTE (1)
recommended.

(1) Steady state data is not available because device heats up to OTE in this condition.
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Table 13. Device and PCB Temperatures with 4-Ω Load, TA = 40°C (continued)
TA = 40°C, TPA3250 EVM, No Airflow. Steady State Temperatures.
OTW after 134 seconds. Not
36V 450kHz 21W 1/8 of 10% THD power 142°C 108°C
recommended.
36V 600kHz Not recommended

11.4.3 Thermal Performance with Non-Continuous Output Power

As audio signals often have a peak to average ratio larger than one (average level below maximum peak output),
the thermal performance for audio signals can be illustrated using burst signals with different burst ratios.

Figure 26. Example of audio signal

A burst signal is characterized by the high-level to low-level ratio as well as the duration of the high level and low
level, e.g. a burst 1:4 stimuli is a single period of high level followed by 4 cycles of low level.

High level Low level

1cycle : 4cycles

Figure 27. Example of 1:4 Burst Signal

The following analysis of thermal performance for TPA3250 is made with the TPA3250 EVM surrounded by still
air (no airflow) with a controlled air temperature of 40°C. For 32-V operation the system is not thermally limited
with 8Ω load, but depending on the burst stimuli for operation at 36V some thermal limitations may occur,
depending on switching frequency and average to maximum power ratio. Low to maximum power ratio of the
burst stimuli is given in the plots as for example P1:8 which equals 1 cycle of full power followed by 8 cycles of
low power.

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130 130

120 120

110 110
Temperature (qC)

Temperature (qC)
100 100

90 90

80 80

70 70 Device Top P1:8

PCB Max P1:8
60 Device Top P1:8 Device Top P1:4 Device Top P1:2 60 Device Top P1:4
PCB Max P1:8 PCB Max P1:4 PCB Max P1:2 PCB Max P1:4
50 50
1:8 1:4 1:2 1 1:8 1:4 1:2 1
Burst Ratio (High:Low) D022 Burst Ratio (High:Low) D021
PVDD = 32V, fs = 450kHz RL = 8Ω TA = 40°C PVDD = 32V, fs = 600kHz RL = 8Ω TA = 40°C

Figure 28. Device and PCB Temperatures vs. Burst Ratio Figure 29. Device and PCB Temperatures vs. Burst Ratio

130 130

120 120

110 110
Temperature (qC)

Temperature (qC)

100 100

90 90

80 80

70 Device Top P1:8 70

PCB Max P1:8
60 Device Top P1:4 60 Device Top P1:8
PCB Max P1:4 PCB Max P1:8
50 50
1:8 1:4 1:2 1 1:8 1:4 1:2 1
Burst Ratio (High:Low) D023 Burst Ratio (High:Low) D024
PVDD = 36V, fs = 450kHz RL = 8Ω TA = 40°C PVDD = 36V, fs = 600kHz RL = 8Ω TA = 40°C

Figure 30. Device and PCB Temperatures vs. Burst Ratio Figure 31. Device and PCB Temperatures vs. Burst Ratio

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12 Layout

12.1 Layout Guidelines

• Use an unbroken ground plane to have good low impedance and inductance return path to the power supply
for power and audio signals.
• Maintain a contiguous ground plane from the ground pins to the PCB area surrounding the device for as
many of the ground pins as possible, since the ground pins are the best conductors of heat in the package.
• PCB layout, audio performance and EMI are linked closely together.
• Routing the audio input should be kept short and together with the accompanied audio source ground.
• The small bypass capacitors on the PVDD lines of the DUT be placed as close the PVDD pins as possible.
• A local ground area underneath the device is important to keep solid to minimize ground bounce.
• Orient the passive component so that the narrow end of the passive component is facing the TPA3250
device, unless the area between two pads of a passive component is large enough to allow copper to flow in
between the two pads.
• Avoid placing other heat producing components or structures near the TPA3250 device.
• Avoid cutting off the flow of heat from the TPA3250 device to the surrounding ground areas with traces or via
strings, especially on output side of device.
Netlist for this printed circuit board is generated from the schematic in Figure 32.

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12.2 Layout Examples

12.2.1 BTL Application Printed Circuit Board Layout Example

Pad to top layer ground pour Top Layer Signal Traces

Bottom Layer Signal Traces Bottom to top layer connection via

System Processor

1 44

2 43

3 42 T1
4 41

5 40

6 39

7 38

8 37

9 36

10 35

11 34

12 33 T2
13 32
10k

14 31
22k

15 30
T2
16 29

17 28

18 27

19 26

20 25

21 24

22 23

T1

A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins. Wide
traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or
traces should be blocking the current path.
C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors placed close to the pins.
D. Note T3: PowerPad™ needs to be soldered to PCB GND copper pour

Figure 32. BTL Application Printed Circuit Board - Composite

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Layout Examples (continued)

12.2.2 SE Application Printed Circuit Board Layout Example

Pad to top layer ground pour Top Layer Signal Traces

Bottom Layer Signal Traces Bottom to top layer connection via

System Processor

1 44

2 43

3 42 T1
4 41

5 40

6 39

7 38

8 37

9 36

10 35

11 34
T2
12 33

13 32
10k

14 31
22k

15 30
T2
16 29

17 28

18 27

19 26

20 25

21 24

22 23

T1

A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins. Wide
traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or
traces should be blocking the current path.
C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed close to the pins.
D. Note T3: PowerPad™ needs to be soldered to PCB GND copper pour

Figure 33. SE Application Printed Circuit Board - Composite

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Layout Examples (continued)

12.2.3 PBTL Application Printed Circuit Board Layout Example

Pad to top layer ground pour Top Layer Signal Traces

Bottom Layer Signal Traces Bottom to top layer connection via

System Processor

1 44
23

2 43

3 42 T1
4 41

5 40

6 39
Grounded for PBTL
7 38
Grounded for PBTL
8 37

9
14 36

10 35

11 34
T2
12 33

13 32

31
10k

14
22k

15 30
T2
16 29

17 28

18 27

19 26

20 25

21 24

22 23

T1

A. Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer
copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)
B. Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins. Wide
traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or
traces should be blocking the current path.
C. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed close to the pins.
D. ote T3: PowerPad™ needs to be soldered to PCB GND copper pour

Figure 34. PBTL Application Printed Circuit Board - Composite

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13 Device and Documentation Support

13.1 Documentation Support

TPA3250D2EVM User's Guide, SLVUAG8

13.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

13.3 Trademarks
PurePath, PowerPAD, E2E are trademarks of Texas Instruments.
Blu-ray Disk is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2015–2016, Texas Instruments Incorporated Submit Documentation Feedback 37

Product Folder Links: TPA3250
 PACKAGE OUTLINE
DDW0044D SCALE 1.250
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE

8.3
TYP
7.9
A PIN 1 ID
AREA 42X 0.635
44
1

14.1
13.9 2X
NOTE 3
13.335

22
23 0.27
6.2 44X
B 0.17 0.1 C
6.0 0.08 C A B
SEATING PLANE
C
(0.15) TYP

SEE DETAIL A

22 23

4.43
3.85
EXPOSED
THERMAL PAD

7.30 0.25
6.72 45 GAGE PLANE 1.2 MAX

0.75 0.15
0 -8 0.50 0.05
2X (0.6) 2X (0.13)
NOTE 5 NOTE 5 DETAIL A
TYPICAL
1 44

4223171/A 07/2016

NOTES: PowerPAD is a trademark of Texas Instruments.

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDW0044D PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE

(5.2)
NOTE 9 SOLDER MASK
(4.43) DEFINED PAD
44X (1.45) SYMM SEE DETAILS

1
44

44X (0.4)

42X (0.635)

45 (1.3)
SYMM TYP
(7.3)
(14)
NOTE 9
(R0.05) TYP

( 0.2) TYP
VIA

22 23

METAL COVERED (0.65) TYP

BY SOLDER MASK
(1.3 TYP)
(7.5)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER

SOLDER MASK METAL
OPENING SOLDER MASK
OPENING

0.05 MAX 0.05 MIN

AROUND AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE
4223171/A 07/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDW0044D PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE

(4.43)
BASED ON
44X (1.45) 0.125 THICK
STENCIL
1
44

44X (0.4)

42X (0.635)

SYMM 45 (7.3)
BASED ON
0.125 THICK
STENCIL

SEE TABLE FOR

DIFFERENT OPENINGS
22 23 FOR OTHER STENCIL
THICKNESSES
METAL COVERED SYMM
BY SOLDER MASK

(7.5)

SOLDER PASTE EXAMPLE

PAD 45:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 4.95 X 8.16
0.125 4.43 X 7.30 (SHOWN)
0.15 4.04 X 6.66
0.175 3.74 X 6.17

4223171/A 07/2016

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPA3250D2DDW ACTIVE HTSSOP DDW 44 35 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 3250

TPA3250D2DDWR ACTIVE HTSSOP DDW 44 2000 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 70 3250

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3250D2DDWR HTSSOP DDW 44 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA3250D2DDWR HTSSOP DDW 44 2000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPA3250D2DDW DDW HTSSOP 44 35 530 11.89 3600 4.9

Pack Materials-Page 3
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