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TAS5614LA
SLAS846A – MAY 2012 – REVISED MARCH 2015

TAS5614LA 150-W Stereo and 300-W Mono PurePath™ HD Digital-Input Class-D Power
Stage
1 Features 3 Description
1• PurePath™ HD Integrated Feedback Provides: The TAS5614LA device is a feature optimized class-
D power amplifier based on the TAS5614LA.
– 0.03% THD at 1 W into 4 Ω
– > 65 dB PSRR (No Input Signal) The TAS5614LA uses large MOSFETs for improved
power efficiency and a novel gate drive scheme for
– > 105 dB (A-weighted) SNR reduced losses in idle and at low output signals
• Preclipping Output for Control of a Class-G Power leading to reduced heat sink size.
Supply
The unique preclipping output signal can be used to
• Reduced Heat Sink Size due to use of 60-mΩ control a class-G power supply. This combined with
Output MOSFET With > 90% Efficiency at Full the low idle loss and high power efficiency of the
Output Power TAS5614LA leads to industry-leading levels of
• Output Power at 10%THD+N efficiency ensuring a super “green” system.
– 150-W and 4-Ω BTL Stereo Configuration The TAS5614LA uses constant voltage gain. The
– 300-W and 2-Ω in PBTL Mono Configuration internally matched gain resistors ensure a high Power
Supply Rejection Ratio giving an output voltage only
• Output Power at 1%THD+N dependent on the audio input voltage and free from
– 125-W and 4-Ω BTL Stereo Configuration any power supply artifacts.
– 65-W and 8-Ω BTL Stereo Configuration The high integration of the TAS5614LA makes the
• Click- and Pop-Free Start-up amplifier easy to use; and, using TI’s reference
• Error Reporting Self-Protected Design With UVP, schematics and PCB layouts leads to fast design in
Overtemperature, and Short-Circuit Protection time. The TAS5614LA is available in the space-
saving, surface-mount, 44-pin HTSSOP package.
• EMI Compliant When Used With Recommended
System Design Device Information(1)
• 44-Pin HTSSOP (DDV) Package for Reduced PART NUMBER PACKAGE BODY SIZE (NOM)
Board Size TAS5614LA HTSSOP (44) 14.00 mm × 6.10 mm
(1) For all available packages, see the orderable addendum at
2 Applications the end of the data sheet.
• Blu-ray™ and DVD Receivers
• High-Power Sound Bars
• Powered Subwoofer and Active Speakers
• Mini Combo Systems
Typical TAS5614LA Application Block Diagram

TASxxxx PurePath HDTM

Digital Audio
Processor
TAS
5630
TAS5614LA
DIGITAL
AUDIO
INPUT

+12V 18V-36V

PurePath HDTM
+3.3V
REG.
Class G Power Supply
Ref design

105VAC → 240VAC

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.1 Overview ................................................................. 12
2 Applications ........................................................... 1 7.2 Functional Block Diagrams ..................................... 13
3 Description ............................................................. 1 7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 19
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3 8 Application and Implementation ........................ 21
8.1 Application Information............................................ 21
6 Specifications......................................................... 4
8.2 Typical Applications ................................................ 21
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4 9 Power Supply Recommendations...................... 31
6.3 Recommended Operating Conditions....................... 5 10 Layout................................................................... 31
6.4 Thermal Information .................................................. 5 10.1 Layout Guidelines ................................................. 31
6.5 Electrical Characteristics........................................... 6 10.2 Layout Example .................................................... 33
6.6 Audio Specification Stereo (BTL).............................. 7 11 Device and Documentation Support ................. 35
6.7 Audio Specification 4 Channels (SE) ........................ 7 11.1 Trademarks ........................................................... 35
6.8 Audio Specification Mono (PBTL) ............................ 8 11.2 Electrostatic Discharge Caution ............................ 35
6.9 Typical Characteristics .............................................. 9 11.3 Glossary ................................................................ 35
7 Detailed Description ............................................ 12 12 Mechanical, Packaging, and Orderable
Information ........................................................... 35

4 Revision History
Changes from Original (May 2012) to Revision A Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

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5 Pin Configuration and Functions

DDV Package
44-Pin HTSSOP
Top View

GVDD_AB BST_A
VDD BST_B
OC_ADJ GND
RESET GND
INPUT_A OUT_A
INPUT_B OUT_A
C_START PVDD_AB
DVDD PVDD_AB
GND PVDD_AB
GND OUT_B
GND GND
GND GND
AVDD OUT_C
INPUT_C PVDD_CD
INPUT_D PVDD_CD
FAULT PVDD_CD
OTW OUT_D
CLIP OUT_D
M1 GND
M2 GND
M3 BST_C
GVDD_CD BST_D

Pin Functions
PIN
I/O/P (1) DESCRIPTION
NAME NO.
AVDD 13 P Internal voltage regulator, analog section
BST_A 44 P Bootstrap pin, A-side
BST_B 43 P Bootstrap pin, B-side
BST_C 24 P Bootstrap pin, C-side
BST_D 23 P Bootstrap pin, D-side
CLIP 18 O Clipping warning, open drain, active low
C_START 7 O Start-up ramp
DVDD 8 P Internal voltage regulator, digital section
FAULT 16 O Shutdown signal, open drain, active low
9, 10, 11, 12, 25,
GND P Ground
26, 33, 34, 41, 42
GVDD_AB 1 P Gate-drive voltage supply, AB-side
GVDD_CD 22 P Gate-drive voltage supply, CD-side
INPUT_A 5 I PWM input signal for half-bridge A
INPUT_B 6 I PWM input signal for half-bridge B
INPUT_C 14 I PWM input signal for half-bridge C
INPUT_D 15 I PWM input signal for half-bridge D
M1 19 I Mode selection 1 (LSB)
M2 20 I Mode selection 2
M3 21 I Mode selection 3 (MSB)
OC_ADJ 3 O Overcurrent threshold programming pin

(1) I = Input, O = Output, P = Power

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Pin Functions (continued)

PIN
I/O/P (1) DESCRIPTION
NAME NO.
OTW 17 O Overtemperature warning, open drain, active low
OUT_A 39, 40 O Output, half-bridge A
OUT_B 35 O Output, half-bridge B
OUT_C 32 O Output, half-bridge C
OUT_D 27, 28 O Output, half-bridge D
PVDD_AB 36, 37, 38 P PVDD supply for half-bridge A and B
PVDD_CD 29, 30, 31 P PVDD supply for half-bridge C and D
RESET 4 I Device reset input, active low
VDD 2 P Input power supply
PowerPAD™ – P Ground, connect to grounded heat sink

6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range unless otherwise noted
MIN MAX UNIT
VDD to GND, GVDD_X (2) to GND –0.3 13.2 V
(2) (3) (3) (2) (3)
PVDD_X to GND , OUT_X to GND , BST_X to GVDD_X –0.3 50 V
BST_X to GND (3) (4) –0.3 62.5 V
DVDD to GND –0.3 4.2 V
AVDD to GND –0.3 8.5 V
OC_ADJ, M1, M2, M3, C_START, INPUT_X to GND –0.3 4.2 V
RESET, FAULT, OTW, CLIP, to GND –0.3 4.2 V
Maximum continuous sink current (FAULT, OTW, CLIP) 9 mA
Maximum operating junction temperature, TJ 0 150 °C
Lead temperature 260 °C
Storage temperature, Tstg –40 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) GVDD_X and PVDD_X represents a full bridge gate drive or power supply. GVDD_X is GVDD_AB or GVDD_CD, PVDD_X is
PVDD_AB or PVDD_CD
(3) These voltages represents the DC voltage + peak AC waveform measured at the pin of the device in all conditions.
(4) Maximum BST_X to GND voltage is the sum of maximum PVDD to GND and GVDD to GND voltages minus a diode drop.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
2000
pins (1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-
500
C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
PVDD_X Full-bridge supply DC supply voltage 12 36 38 V
Supply for logic regulators and
GVDD_X DC supply voltage 10.8 12 13.2 V
gate-drive circuitry
VDD Digital regulator supply voltage DC supply voltage 10.8 12 13.2 V
BTL Output filter: L = 10 µH, 1 µF. 3.0 4.0
RL Load impedance SE Output AD modulation, 1.5 3.0 Ω
PBTL switching frequency > 350 kHz. 1.5 2.0
Minimum inductance at overcurrent
limit, including inductor tolerance,
LOUTPUT Output filter inductance 5 μH
temperature and possible inductor
saturation
FPWM PWM frame rate 352 384 500 kHz
CPVDD PVDD close decoupling capacitors 0.44 1 μF
BTL and PBTL configuration 100 nF
C_START Start-up ramp capacitor
SE and 1xBTL+2xSE configuration 1 μF
Overcurrent programming
ROC Resistor tolerance = 5% 24 33 kΩ
resistor
Overcurrent programming
ROC_LATCHED Resistor tolerance = 5% 47 62 68 kΩ
resistor
TJ Junction temperature 0 125 °C

6.4 Thermal Information

TAS5614LA
THERMAL METRIC (1) DDV (HTSSOP) UNIT
44 PINS
RθJH Junction-to-heat sink thermal resistance 2.3
RθJC(top) Junction-to-case (top) thermal resistance 0.8
RθJB Junction-to-board thermal resistance 2.1
°C/W
ψJT Junction-to-top characterization parameter 0.8
ψJB Junction-to-board characterization parameter 2.1
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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6.5 Electrical Characteristics

PVDD_X = 36 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as a
DVDD VDD = 12 V 3.0 3.3 3.6 V
reference node
Voltage regulator, only used as a
AVDD VDD = 12 V 7.8 V
reference node
Operating, 50% duty cycle 20
IVDD VDD supply current mA
Idle, reset mode 20
50% duty cycle 9
IGVDD_X Gate-supply current per full-bridge mA
Reset mode 2
50% duty cycle without load 23
IPVDD_X Full-bridge idle current RESET low 1.9 mA
VDD and GVDD_X at 0V 0.35
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side
RDS(on), LS TJ = 25°C, excludes metalization 60 100 mΩ
(LS)
resistance,
Drain-to-source resistance, high side GVDD = 12 V
RDS(on), HS 60 100 mΩ
(HS)
I/O PROTECTION
Vuvp,GVDD Undervoltage protection limit, 8.5 V
Vuvp,GVDD, (1) GVDD_X 0.7 V
hyst

Vuvp,VDD 8.5 V
(1)
Undervoltage protection limit, VDD
Vuvp,VDD, hyst 0.7 V
Vuvp,PVDD 8.5 V
Undervoltage protection limit, PVDD_X
Vuvp,PVDD,hyst (1) 0.7 V
OTW (1) Overtemperature warning 115 125 135 °C
Temperature drop needed below OTW
(1)
OTWhyst temperature for OTW to be inactive 25 °C
after OTW event.
OTE (1) Overtemperature error 145 155 165 °C
OTE-OTWdifferential (1) OTE-OTW differential 30 °C
(1) A device reset is needed to clear
OTEHYST 25 °C
FAULT after an OTE event
OLPC Overload protection counter fPWM = 384 kHz 2.6 ms
Resistor – programmable, nominal
IOC Overcurrent limit protection peak current in 1-Ω load, ROC = 24 15 A
kΩ
Resistor – programmable, nominal
IOC_LATCHED Overcurrent limit protection, latched peak current in 1-Ω load, ROC = 62 15 A
kΩ
Time from application of short
IOCT Overcurrent response time 150 ns
condition to Hi-Z of affected half bridge
Connected when RESET is active to
Internal pulldown resistor at output of
IPD provide bootstrap charge. Not used in 3 mA
each half bridge
SE mode.
STATIC DIGITAL SPECIFICATIONS
VIH High level input voltage 1.9 V
INPUT_X, M1, M2, M3, RESET
VIL Low level input voltage 0.8 V
LEAKAGE Input leakage current 100 μA
OTW / SHUTDOWN (FAULT)
RINT_PU Internal pullup resistance, OTW, CLIP, FAULT to DVDD 20 26 33 kΩ
VOH High level output voltage Internal pullup resistor 3 3.3 3.6 V
VOL Low level output voltage IO = 4 mA 200 500 mV
FANOUT Device fanout OTW, FAULT, CLIP No external pullup 30 devices

(1) Specified by design.

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6.6 Audio Specification Stereo (BTL)

Audio performance is recorded as a chipset consisting of a PWM Processor (modulation index limited to 97.7%) and a
TAS5614LA power stage with PCB and system configurations in accordance with recommended guidelines. Audio frequency
= 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH,
CDEM = 1 µF, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 4 Ω, 10% THD+N 150
PO Power output per channel W
RL = 4 Ω, 1% THD+N 125
THD+N Total harmonic distortion + noise 1-W, 1-kHz signal 0.03%
Vn Output integrated noise A-weighted, AES17 measuring filter 180 μV
VOS Output offset voltage No signal 10 20 mV
SNR Signal-to-noise ratio (1) A-weighted, AES17 measuring filter 105 dB
A-weighted, –60 dBFS (rel 1%
DNR Dynamic range 105 dB
THD+N)
Power dissipation due to Idle losses
Pidle PO = 0, channels switching (2) 1.6 W
(IPVDD_X)

(1) SNR is calculated relative to 1% THD-N output level.

(2) Actual system idle losses also are affected by core losses of output inductors.

6.7 Audio Specification 4 Channels (SE)

Audio performance is recorded as a chipset consisting of a PWM Processor (modulation index limited to 97.7%) and a
TAS5614LA power stage with PCB and system configurations in accordance with recommended guidelines. Audio frequency
= 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH,
CDEM = 1 µF, CDCB = 470 µF, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 3 Ω, 10% THD+N 50
PO Power output per channel W
RL = 3 Ω, 1% THD+N 42
THD+N Total harmonic distortion + noise 1-W, 1-kHz signal 0.025%
Vn Output integrated noise A-weighted, AES17 measuring filter 180 μV
SNR Signal-to-noise ratio (1) A-weighted, AES17 measuring filter 102 dB
A-weighted, –60 dBFS (rel 1%
DNR Dynamic range 102 dB
THD+N)
Power dissipation due to Idle losses
Pidle PO = 0, channel switching (2) 1.6 W
(IPVDD_X)

(1) SNR is calculated relative to 1% THD-N output level.

(2) Actual system idle losses also are affected by core losses of output inductors.

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6.8 Audio Specification Mono (PBTL)

Audio performance is recorded as a chipset consisting of a PWM Processor (modulation index limited to 97.7%) and a
TAS5614LA power stage with PCB and system configurations in accordance with recommended guidelines. Audio frequency
= 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH,
CDEM = 1 μF, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 2 Ω, 10%, THD+N 300
RL = 3 Ω, 10% THD+N 200
RL = 4 Ω, 10% THD+N 160
PO Power output per channel W
RL = 2 Ω, 1% THD+N 250
RL = 3 Ω, 1% THD+N 160
RL = 4 Ω, 1% THD+N 130
THD+N Total harmonic distortion + noise 1-W, 1-kHz signal 0.025%
Vn Output integrated noise A-weighted, AES17 measuring filter 180 μV
VOS Output offset voltage No signal 10 20 mV
SNR Signal to noise ratio (1) A-weighted, AES17 measuring filter 105 dB
DNR Dynamic range A-weighted, –60 dBFS (rel 1% THD) 105 dB
Power dissipation due to idle losses (2)
Pidle PO = 0, All channels switching 1.6 W
(IPVDD_X)

(1) SNR is calculated relative to 1% THD-N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

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6.9 Typical Characteristics

6.9.1 BTL Configuration

Measurement conditions are: 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C,
Output Filter: LDEM = 10 μH, CDEM = 1 µF, 20-Hz to 20-kHz BW (AES17 low-pass filter), unless otherwise noted.

10 200
4Ω 4Ω
8Ω 180 8Ω
THD+N − Total Harmonic Distortion + Noise − %

160

1 140

PO − Output Power − W
120

100

0.1 80

60

40

0.01 20 TC = 75°C
TC = 75°C THD+N at 10%
0.005 0
0.02 0.1 1 10 100 200 10 15 20 25 30 35 40
PO − Output Power − W PVDD − Supply Voltage − V
G001 G003

Figure 1. Total Harmonic + Noise vs Output Power, 1 kHz Figure 2. Output Power vs Supply Voltage vs Distortion +
Noise = 10%

10 160
1W 4Ω
10 W 8Ω
THD+N − Total Harmonic Distortion + Noise − %

100 W 140

1 120
PO − Output Power − W

100

0.1 80

60

0.01 40

20

TC = 75°C TC = 75°C
0.001 0
20 100 1k 10k 20k 10 15 20 25 30 35 40
Frequency − Hz PVDD − Supply Voltage − V
G002 G004

Figure 3. Total Harmonic Distortion + Noise vs Frequency, Figure 4. Output Power vs Supply Voltage, vs Distortion +
4Ω Noise = 1%

100 45
95 4Ω
90 8Ω
40
85
80
35
75
70
65 30
Power Loss − W
Efficiency − %

60
55 25
50
45 20
40
35 15
30
25
10
20
15
10 5
4Ω
5 8Ω TC = 75°C TC = 75°C
0 0
0 100 200 300 400 0 100 200 300 400
2 Channel Output Power − W 2 Channel Output Power − W
G005 G006

Figure 5. System Efficiency vs Output Power Figure 6. System Power Loss vs Output Power

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BTL Configuration (continued)

Measurement conditions are: 1 kHz, PVDD_X = 36 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 24 kΩ, TC = 75°C,
Output Filter: LDEM = 10 μH, CDEM = 1 µF, 20-Hz to 20-kHz BW (AES17 low-pass filter), unless otherwise noted.
200 0
−10 TC = 75°C 4Ω
180 −20 VREF = 22.5 V
Sample Rate = 48kHz
−30
FFT Size = 16384
160 −40
−50
140 −60
PO − Output Power − W

Noise Amplitude − dB
−70
120 −80
−90
100 −100
−110
80 −120
−130
60 −140
−150
40 −160
−170
20 4Ω −180
8Ω THD+N at 10% −190
0 −200
−10 0 10 20 30 40 50 60 70 80 90 100 110 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k 24k
TC − Case Temperature − °C f − Frequency − Hz
G007 G008

Figure 7. Output Power vs Temperature Figure 8. Noise Amplitude vs Frequency

6.9.2 SE Configuration

10 100
2Ω 2Ω
3Ω 3Ω
THD+N − Total Harmonic Distortion + Noise − %

4Ω 4Ω
80

1
PO − Output Power − W

60

0.1 40

20

0.01 TC = 75°C
TC = 75°C THD+N at 10%
0.005 0
0.02 0.1 1 10 100 10 15 20 25 30 35 40
PO − Output Power − W PVDD − Supply Voltage − V
G009 G010

Figure 9. Total Harmonic Distortion + Noise vs Output Figure 10. Output Power vs Supply Voltage
Power

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6.9.3 PBTL Configuration

10 400
2Ω 2Ω
3Ω 3Ω
THD+N − Total Harmonic Distortion + Noise − %

4Ω 350 4Ω

300
1

PO − Output Power − W
250

200

0.1
150

100

50
0.01 TC = 75°C
TC = 75°C THD+N at 10%
0.005 0
0.02 0.1 1 10 100 400 10 15 20 25 30 35 40
PO − Output Power − W PVDD − Supply Voltage − V
G011 G012

Figure 11. Total Harmonic Distortion + Noise vs Output Figure 12. Output Power vs Supply Voltage
Power

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7 Detailed Description

7.1 Overview
TAS5614LA is a PWM input, audio PWM (class-D) amplifier. The output of the TAS5614LA can be configured for
single-ended, BTL (Bridge-Tied Load) or parallel BTL (PBTL) output. It requires two rails for power supply, PVDD
and 12 V (GVDD and VDD).
Functional Block Diagrams shows typical connections for BTL outputs. Detailed schematic can be viewed in
TAS5614LA EVM user's guide (SLAU375).

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7.2 Functional Block Diagrams

Capacitors for
System External
microcontroller Filtering
&
/AMP RESET Startup/Stop

I2C

/OTW
/FAULT

C_START
/CLIP
TASxxxx *NOTE1
PWM Modulator
/RESET
VALID BST_A
Bootstrap
BST_B Capacitors

nd
PWM_A INPUT_A OUT_A 2 Order
Left- L-C Output
Input Output
Channel Filter for
PWM_B INPUT_B H-Bridge 1 H-Bridge 1 OUT_B
Output each
H-Bridge

2-CHANNEL
H-BRIDGE
BTL MODE
nd
PWM_C INPUT_C 2 Order
OUT_C
Right- Input Output L-C Output
Channel PWM_D INPUT_D H-Bridge 2 H-Bridge 2 Filter for
OUT_D
Output each
H-Bridge
M1 BST_C
Hardwire
GVDD_AB, CD
PVDD_AB, CD

M2 Bootstrap
Mode
M3 BST_D Capacitors
OC_ADJ

Control
DVDD

AVDD
GND

GND

VDD

PVDD PVDD GVDD, VDD, Hardwire

36V Power Supply Over-
& VREG
Decoupling Current
SYSTEM Power Supply
Power Decoupling Limit
Supplies
GND
GND
GVDD (12V)/VDD (12V)
12V

VAC

(1) Logic AND is inside or outside the microprocessor.

Figure 13. Typical System Block Diagram

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Functional Block Diagrams (continued)

/CLIP

/OTW

/FAULT
BST_X
GVDD_X
UVP AVDD
DVDD
/RESET

MODE1-3

PROTECTION & I/O LOGIC

POWER-UP
RESET
AVDD
AVDD
TEMP
SENSE
VDD

DVDD CB3C OVER-

DVDD LOAD
PROTECTION

STARTUP
CONTROL
C_START

BST_A

PVDD_AB
PWM
INPUT_A
RECEIVER ANALOG + PWM &
TIMING GATE-DRIVE OUT_A
LOOP FILTER
- CONTROL

GND

GVDD_AB

BST_B

PVDD_AB
PWM
INPUT_B
RECEIVER ANALOG
+ PWM &
TIMING GATE-DRIVE OUT_B
LOOP FILTER
- CONTROL

GND

BST_C

PVDD_CD
PWM
INPUT_C
RECEIVER ANALOG
+ PWM &
TIMING GATE-DRIVE OUT_C
LOOP FILTER
- CONTROL

GND

GVDD_CD

BST_D

PVDD_CD
PWM
INPUT_D
RECEIVER ANALOG + PWM &
TIMING GATE-DRIVE OUT_D
LOOP FILTER
- CONTROL

GND

Figure 14. Functional Block Diagram

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7.3 Feature Description

7.3.1 Power Supplies
To facilitate system design, the TAS5614LA needs only a 12-V supply in addition to the (typical) 36-V power-
stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry. Additionally, all circuitry requiring a floating voltage supply, for example, the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
To provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive and
output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate
bootstrap pins (BST_X) and each full-bridge has separate power stage supply (PVDD_X) and gate supply
(GVDD_X) pins. Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although
supplied from the same 12-V source, it is highly recommended to separate GVDD_AB, GVDD_CD, and VDD on
the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the
recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as
close to their associated pins as possible. In general, inductance between the power supply pins and decoupling
capacitors must be avoided. (See reference board documentation for additional information.)
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each full-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X
connection is decoupled with minimum 2 × 220-nF ceramic capacitors placed as close as possible to each
supply pin. TI recommends following the PCB layout of the TAS5614LA reference design. For additional
information on recommended power supply and required components, see the application diagrams in this data
sheet.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 36-V power-
stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit. Moreover, the TAS5614LA is fully protected against
erroneous power-stage turn on due to parasitic gate charging when power supplies are applied. Thus, voltage-
supply ramp rates (dV/dt) are noncritical within the specified range (see Recommended Operating Conditions).

7.3.1.1 Boot Strap Supply

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 300 kHz to 400 kHz, TI recommends to use 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.

7.3.2 System Power-Up and Power-Down Sequence

7.3.2.1 Powering Up
The TAS5614LA does not require a power-up sequence. The outputs of the H-bridges remain in a high-
impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage
protection (UVP) voltage threshold (see Electrical Characteristics). Although not specifically required, TI
recommends holding RESET in a low state while powering up the device. This allows an internal circuit to charge
the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.

7.3.2.2 Powering Down

The TAS5614LA does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage
threshold (see Electrical Characteristics). Although not specifically required, it is a good practice to hold RESET
low during power down, thus preventing audible artifacts including pops or clicks.

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Feature Description (continued)

7.3.3 Start-up and Shutdown Ramp Sequence
The integrated start-up and stop sequence ensures a click and pop free startup and shutdown sequence of the
amplifier. The start-up sequence uses a voltage ramp with a duration set by the CSTART capacitor. The
sequence uses the input PWM signals to generate output PWM signals, hence input idle PWM should be present
during both startup and shut down ramping sequences.
VDD, GVDD_X, and PVDD_X power supplies must be turned on and with settled outputs before starting
the start-up ramp by setting RESET high.
During start-up and shutdown ramp the input PWM signals should be in muted condition with the PWM processor
noise shaper activity turned off (50% duty cycle).
The duration of the start-up and shutdown ramp is 100 ms + X ms, where X is the CSTART capacitor value in
nF.
TI recommends using 100-nF CSTART in BTL and PBTL mode and 1 µF in SE mode configuration. This results
in ramp times of 200 ms and 1.1 s, respectively. The longer ramp time in SE configuration allows charge and
discharge of the output ac coupling capacitor without audible artifacts.
Ramp Start Ramp End Ramp Start Ramp End

3.3V
/RESET
0V

3.3V
INPUT_X IS SWITCHING (MUTE) INPUT_X IS SWITCHING (MUTE)
INPUT_X (UNMUTED) Hi-Z
NOISE SHAPER OFF NOISE SHAPER OFF
0V

PVDD_X
OUT_X OUT_X IS SWITCHING (MUTE) (UNMUTED) OUT_X IS SWITCHING (MUTE) Hi-Z
0V

VI_CM
DC_RAMP
0V
50%

PVDD_X/2

SPEAKER OUT_X 0V

tStartup Ramp tStartup Ramp

INPUT_X IS SWITCHING (MUTE)

NOISE SHAPER ON

Figure 15. Start-up/Shutdown Ramp

7.3.4 Unused Output Channels

If all available output channels are not used, TI recommends disabling switching of unused output nodes to
reduce power consumption. Furthermore by disabling unused output channels the cost of unused output LC
demodulation filters can be avoided.
Disabling a channel is done by leave the bootstrap capacitor (BST) unstuffed and connecting the respective input
to GND. The unused output pin(s) can be left floating. Please note that the PVDD decoupling capacitors still
need to be mounted.

Table 1. Unused Output Channels

OPERATING PWM OUTPUT UNUSED UNSTUFFED
INPUT_A INPUT_B INPUT_C INPUT_D
MODE INPUT CONFIGURATION CHANNEL COMPONENT
000 2N + 1 BST_A and BST_B
AB GND GND PWMc PWMd capacitors
001 1N + 1 2 x BTL
CD PWMa PWMb GND GND BST_C and BST_D
010 2N + 1 capacitors

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Feature Description (continued)

Table 1. Unused Output Channels (continued)
OPERATING PWM OUTPUT UNUSED UNSTUFFED
INPUT_A INPUT_B INPUT_C INPUT_D
MODE INPUT CONFIGURATION CHANNEL COMPONENT
A GND PWMb PWMc PWMd BST_A capacitor
B PWMa GND PWMc PWMd BST_B capacitor
101 1N + 1 4 x SE
C PWMa PWMb GND PWMd BST_C capacitor
D PWMa PWMb PWMc GND BST_D capacitor

7.3.5 Device Protection System

The TAS5614LA contains advanced protection circuitry carefully designed to facilitate system integration and
ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions
such as short circuits, overload, overtemperature, and undervoltage. The TAS5614LA responds to a fault by
immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In
situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault
condition has been removed, that is, the supply voltage has increased.
The device will function on errors, as shown in the following table.

Table 2. Device Protection

BTL MODE PBTL MODE SE MODE
CHANNEL FAULT TURNS OFF CHANNEL FAULT TURNS OFF CHANNEL FAULT TURNS OFF
A A+B A A+B+C+D A A+B
B B B
C C+D C C C+D
D D D

Bootstrap UVP does not shutdown according to the table, it shuts down the respective high-side FET.

7.3.6 Pin-to-Pin Short-Circuit Protection (PPSC)

The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is
shorted to GND or PVDD_X. For comparison, the OC protection system detects an overcurrent after the
demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at
start-up that is, when VDD is supplied, consequently a short to either GND or PVDD_X after system start-up will
not activate the PPSC detection system. When PPSC detection is activated by a short on the output, all half-
bridges are kept in a Hi-Z state until the short is removed, the device then continues the start-up sequence and
starts switching. The detection is controlled globally by a two step sequence. The first step ensures that there are
no shorts from OUT_X to GND, the second step tests that there are no shorts from OUT_X to PVDD_X. The
total duration of this process is roughly proportional to the capacitance of the output LC filter. The typical duration
is <15 ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the device will not react to
changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and FAULT is
released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output
configurations, the detection is not performed in SE mode. To prevent to tripping the PPSC detection system TI
recommends not inserting resistive load to GND or PVDD_X.

7.3.7 Overtemperature Protection

The TAS5614LA has a two-level temperature-protection system that asserts an active-low warning signal (OTW)
when the device junction temperature exceeds 125°C (typical). If the device junction temperature exceeds 155°C
(typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-
impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To clear the OTE latch,
RESET must be asserted. Thereafter, the device resumes normal operation.

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7.3.8 Overtemperature Warning, OTW

The overtemperature warning OTW asserts when the junction temperature has exceeded recommended
operating temperature. Operation at junction temperatures above OTW threshold is exceeding recommended
operation conditions and is strongly advised to avoid.
If OTW asserts, action should be taken to reduce power dissipation to allow junction temperature to decrease
until it gets below the OTW hysteresis threshold. This action can be decreasing audio volume or turning on a
system cooling fan.

7.3.9 Undervoltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5614LA fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the GVDD_X and VDD supply voltages reach stated in Electrical Characteristics. Although
GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or
GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and
FAULT being asserted low. The device automatically resumes operation when all supply voltages have increased
above the UVP threshold.

7.3.10 Error Reporting

Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI
recommends monitoring the OTW signal using the system micro controller and responding to an overtemperature
warning signal by, for example, turning down the volume to prevent further heating of the device resulting in
device shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and OTW
outputs.
The FAULT, OTW, pins are active-low, open-drain outputs. Their function is for protection-mode signaling to a
PWM controller or other system-control device.
Any fault resulting in device shutdown is signaled by the FAULT pin going low. Likewise, OTW goes low when
the device junction temperature exceeds 125°C (see the following table).

Table 3. Error Reporting

FAULT OTW DESCRIPTION
0 0 Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)
0 1 Overload (OLP) or undervoltage (UVP)
1 0 Junction temperature higher than 125°C (overtemperature warning)
1 1 Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)

7.3.11 Fault Handling

If a fault situation occurs while in operation, the device will act accordingly to the fault being a global or a channel
fault. A global fault is a chip-wide fault situation and will cause all PWM activity of the device to be shut down,
and will assert FAULT low. A global fault is a latching fault and clearing FAULT and restart operation requires
resetting the device by toggling RESET. Toggling RESET should never be allowed with excessive system
temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET
(RESET high) if the OTW signal is cleared (high). A channel fault will result in shutdown of the PWM activity of
the affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults
being present. TI recommends monitoring the OTW signal using the system micro controller and responding to
an over temperature warning signal by, for example, turning down the volume to prevent further heating of the
device resulting in device shutdown (OTE).

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Table 4. Fault Handling

FAULT or EVENT GLOBAL or REPORTING LATCHED or SELF ACTION NEEDED TO
FAULT or EVENT OUTPUT FETs
DESCRIPTION CHANNEL METHOD CLEARING CLEAR
PVDD_X UVP
VDD UVP Increase affected supply
Voltage Fault Global FAULT Pin Self Clearing Hi-Z
GVDD_X UVP voltage

AVDD UVP
POR (DVDD UVP) Power On Reset Global FAULT Pin Self Clearing Allow DVDD to rise H-Z
Channel (half Allow BST cap to recharge
BST UVP Voltage Fault None Self Clearing High Side Off
bridge) (low side on, VDD 12 V)
Cool below lower OTW
OTW Thermal Warning Global OTW Pin Self Clearing Normal operation
threshold
OTE (OTSD) Thermal Shutdown Global FAULT Pin Latched Toggle RESET Hi-Z
OLP (CBC >2.6 ms) OC shutdown Channel FAULT Pin Latched Toggle RESET Hi-Z
Latched OC (ROC >
OC shutdown Channel FAULT Pin Latched Toggle RESET Hi-Z
47k)
CBC (24k < ROC < reduce signal level or remove Flip state, cycle by
OC Limiting Channel None Self Clearing
33k) short cycle at fs/2
Stuck at Fault (1) (1 to
No PWM Channel None Self Clearing resume PWM Hi-Z
3 channels)
(1)
Stuck at Fault (All
No PWM Global None Self Clearing resume PWM Hi-Z
channels)

(1) Stuck at Fault occurs when input PWM drops below minimum PWM frame rate given in Recommended Operating Conditions.

7.3.12 Device Reset

When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance
(Hi-Z) state.
In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables
weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state when
asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the
FAULT output, that is, FAULT is forced high. A rising-edge transition on reset input allows the device to resume
operation after an overload fault. To ensure thermal reliability, the rising edge of RESET must occur no sooner
than 4 ms after the falling edge of FAULT.

7.4 Device Functional Modes

There are three main output modes that the user can configure the device as per application requirement. In
addition there are two PWM modulation modes, AD and BD.
AD modulation can have single-ended (SE) or differential analog inputs. AD modulation can also be configured to
have SE, BTL, BTL+SE, or PBTL outputs. BD modulation requires differential analog inputs.
BD modulation can only be configured in BTL or PTBL mode.

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Device Functional Modes (continued)

7.4.1 Mode Selection Pins

MODE PINS PWM OUTPUT

INPUT A INPUT B INPUT C INPUT D MODE
M3 M2 M1 INPUT (1) CONFIGURATION
0 0 0 2N + 1 2 x BTL PWMa PWMb PWMc PWMd AD mode
0 0 1 1N + 1 (2) 2 x BTL PWMa Unused PWMc Unused AD mode
0 1 0 2N + 1 2 x BTL PWMa PWMb PWMc PWMd BD mode
(2)
0 1 1 1N + 1 1 x BTL + 2 x SE PWMa Unused PWMc PWMd AD mode
1 0 0 2N + 1 1 x PBTL PWMa PWMb 0 0 AD mode
1 0 0 1N + 1 (2) 1 x PBTL PWMa Unused 0 1 AD mode
1 0 0 2N + 1 1 x PBTL PWMa PWMb 1 0 BD mode
1 0 1 1N + 1 4 x SE (3) PWMa PWMb PWMc PWMd AD mode

(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
(2) Using 1N interface in BTL and PBTL mode results in increased DC offset on the output terminals.
(3) The 4xSE mode can be used as 1xBTL + 2xSE configuration by feeding a 2N PWM signal to either INPUT_AB or INPUT_CD for
improved dc offset accuracy

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 System Design Consideration
A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.
Apply audio only according to the timing information for startup and shutdown sequence. That will start and stop
the amplifier without audible artifacts in the output transducers.
The CLIP signal indicates that the output is approaching clipping (when output PWM starts skipping pulses due
to loop filter saturation). The signal can be used to initiate an audio volume decrease or to adjust the power
supply rail.
The device inverts the audio signal from input to output.
The DVDD and AVDD pins are not recommended to be used as a voltage source for external circuitry.

8.2 Typical Applications

The following sections discuss in detail three typical audio PWM (class-D) configurations:
• Differential input, stereo BTL outputs
• Differential input, mono PBTL output
• Single-ended inputs, quad single-ended outputs.

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8.2.1 Typical BTL Application

3.3R
+12V

GND

10uF 100 nF

1 GVDD_AB 33nF
BST_A 44
100 nF
2 VDD 33nF
BST_B 43
ROC-ADJUST
3 OC A
_ DJ GND 42 10 µH
10nF
/RESET 4 /RESET GND 41 1nF
100 nF 3R3
PWM_A 5 INPUT_A OUT_A 40

PWM_B 6 INPUT_B OUT_A 39

220 nF 220 nF 470 nF
7 C_START PVDD_AB 38 470 uF

8 DVDD 3R3
100 nF PVDD_AB 37 100 nF
1uF 1 nF
9 GND PVDD_AB 36

TAS5614LA
10nF
10 GND OUT_B 35
10 µH
11 GND GND 34 PVDD
12 GND GND 33 GND
1uF
13 AVDD OUT_C 32
10 µH
14 INPUT_C 10nF
PWM_C PVDD_CD 31
1nF
PWM_D 15 INPUT_D PVDD_CD 30 100 nF 3R3
/FAULT 16 /FAULT PVDD_CD 29 470 uF
220 nF 220 nF
/OTW 17 /OTW OUT_D 28 470 nF

/CLIP 18 /CLIP OUT_D 27

100 nF 3R3
19 M1 GND 26 1nF

20 M2 GND 25 10nF
33nF
21 M3 BST_C 24 10 µH
100 nF
33nF
22 GVDD_CD BST_D 23
3.3R

Figure 16. Typical Differential (2N) BTL Application With AD Modulation Filters

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8.2.1.1 Design Requirements

See Figure 16 for application schematic. In this application, differential PWM inputs are used with AD modulation
from the PWM modulator (TAS5558). AD modulation scheme is defined as PWM(+) is opposite polarity from
PWM(-).

8.2.1.2 Detailed Design Procedure

• Pin 1 - GVDD_AB is the gate drive voltage for half-bridges A and B. This pin needs a 3.3-Ω isolation resistor
and a 0.1-uF decoupling capacitor.
• Pin 2 - VDD is the supply for internal voltage regulators AVDD and DVDD. This pin needs a 10-uF bulk
capacitor and a 0.1-uF decoupling capacitor.
• Pin 3 - Roc adjust is the overcurrent programming resistor. Depending on the application, this resistor can be
between 24 kΩ to 68 kΩ.
• Pin 4 - RESET pin when asserted, it keeps outputs Hi-Z and no PWM switching. This pin can be controlled by
a microprocessor.
• Pins 5 and 6 - These are PWM (+) and PWM (–) pins with signals provided by a PWM modulator such as
TAS5558. These are PWM differential pair.
• Pin 7 - Start-up ramp capacitor should be 0.1 uF for BTL configuration.
• Pin 8 - Digital output supply pin is connected to 1-uF decoupling capacitor.
• Pins 9-12 - Ground pins are connected to board ground.
• Pin 13 - Analog output supply pin is connected to 1-uF decoupling capacitor.
• Pins 14 and 15 - These are PWM (+) and PWM (–) pins with signals provided by a PWM modulator such as
TAS5558. These are PWM differential pair.
• Pin 16 - Fault pin can be monitored by a micro-controller via GPIO pin. System can decide to assert reset or
shutdown.
• Pin 17 - Overtemperature warning pin can be monitored by a microcontroller through a GPIO pin. System can
decide to turn on fan or lower output power.
• Pin 18 - Output clip indicator can be monitored by a microcontroller via a GPIO pin. System can decide to
lower the volume.
• Pins 19-21 - Mode pins set the input and output configurations. For this configuration M1-M3 are grounded.
These mode pins must be hardware configured, such as, not through GPIO pins from a micro-controller.
• Pin 22 - GVDD_CD is the gate drive voltage for half-bridges C and D. This pin needs a 3.3-Ω isolation
resistor and a 0.1-uF decoupling capacitor.
• Pins 23, 24, 43, 44 - Bootstrap pins for half-bridges A, B, C, and D. Connect 33 nF from this pin to
corresponding output pins.
• Pins 25, 26, 33, 34, 41, 42 - These ground pins should be used to ground decoupling capacitors from
PVDD_X.
• Pins 27, 28, 32, 35, 39, 40 - Output pins from half-bridges A, B, C, and D. Connect appropriate bootstrap
capacitors and differential LC filter as shown in Figure 16.
• Pins 29, 30, 31, 36, 37, 38 - Power supply pins to half-bridges A, B, C, and D. A and B form a full-bridge and
C and D form another full-bridge. A 470-uF bulk capacitor is recommended for each full-bridge power pins.
Two 0.22-µF decoupling capacitors are placed on each full-bridge power pins. See Figure 16 for details.

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8.2.1.3 Application Curves

10 200
4Ω 4Ω
8Ω 180 8Ω
THD+N − Total Harmonic Distortion + Noise − %

160

1 140

PO − Output Power − W
120

100

0.1 80

60

40

0.01 20 TC = 75°C
TC = 75°C THD+N at 10%
0.005 0
0.02 0.1 1 10 100 200 10 15 20 25 30 35 40
PO − Output Power − W PVDD − Supply Voltage − V
G001 G003

Figure 17. Total Harmonic + Noise vs Output Power, 1 kHz Figure 18. Output Power vs Supply Voltage vs Distortion +
Noise = 10%

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8.2.2 Typical SE Configuration

3 .3R
+12V

GND

10uF 100nF

1 GVDD_ AB BST_ A 44 33nF

100 nF
33nF * 85°C, Low ESR
2 VDD BST_ B 43
ROC -ADJUST
3 OC_ ADJ GND 42 1 0uH
470 uF 10nF
/RESET 4 /RESET GND 41 1nF
1 µF 3R3
PWM_ A 5 INPUT_ A OUT_ A 40

PWM _B 6 INPUT_ B OUT_ A 39

220 nF 220nF
7 C_START PVDD_AB 38 470uF

1µF 8 DVDD PVDD_AB 37 1 µF 3R3

1nF
1 uF

TAS5614LA
9 GND PVDD_AB 36
470uF 10nF
10 GND OUT_ B 35
1 0uH
* 85°C, Low ESR
11 GND GND 34 PVDD
12 GND GND 33 * 85°C, Low ESR GND
1 uF
13 AVDD OUT_C 32
10 uH
PWM_C 14 INPUT_ C PVDD_CD 31 470uF 10nF
1nF
PWM_ D 15 INPUT_ D PVDD_CD 30 1µF 3R3
/FAULT 16 /FAULT PVDD_CD 29 470uF
220 nF 220nF
/OTW 17 /OTW OUT_D 28

/CLIP 18 /CLIP OUT_D 27 1µF 3R3

19 M 1 GND 26 1nF
470uF 10nF
20 M 2 GND 25
33nF 10 uH
100 nF
21 M 3 BST _C 24
* 85°C, Low ESR
22 GVDD_ CD 33nF
BST _D 23
3 .3R

Figure 19. Typical (1N) SE Application

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8.2.2.1 Design Requirements

See Figure 19 for application schematic. In this application, four single-ended PWM inputs are used with AD
modulation from the PWM modulator such as the TAS5558. AD modulation scheme is defined as PWM(+) is
opposite polarity from PWM(-). The single-ended (SE) output configuration is often used to drive 4 independent
channels in one TAS5614LA device.

8.2.2.2 Detailed Design Procedure

• Pin 1 - GVDD_AB is the gate drive voltage for half-bridges A and B. It needs a 3.3-Ω isolation resistor and a
0.1-uF decoupling capacitor.
• Pin 2 - VDD is the supply for internal voltage regulators AVDD and DVDD. It needs a 10-uF bulk cap and a
0.1-uF decoupling capacitor.
• Pin 3 - Roc adjust is the overcurrent programming resistor. Depending on the application, this resistor can be
between 24 kΩ to 68 kΩ.
• Pin 4 - RESET pin when asserted, it keeps outputs Hi-Z and no PWM switching. This pin can be controlled by
a microprocessor.
• Pins 5 and 6 - These are PWM (+) and PWM (–) pins with signals provided by a PWM modulator such as
TAS5558. These are PWM differential pair.
• Pin 7 - Start up ramp capacitor should be 1 uF for SE configuration.
• Pin 8 - Digital output supply pin is connected to 1-uF decoupling cap.
• Pins 9-12 - Ground pins are connected to board ground.
• Pin 13 - Analog output supply pin is connected to 1-uF decoupling cap.
• Pins 14 and 15 - These are PWM (+) and PWM (–) pins with signals provided by a PWM modulator such as
TAS5558. These are PWM differential pair.
• Pin 16 - Fault pin can be monitored by a microcontroller through GPIO pin. System can decide to assert reset
or shutdown.
• Pin 17 - Overtemperature warning pin can be monitored by a microcontroller through a GPIO pin. System can
decide to turn on fan or lower output power.
• Pin 18 - Output clip indicator can be monitored by a microcontroller through a GPIO pin. System can decide
to lower the volume.
• Pins 19-21 - Mode pins set the input and output configurations. For this configuration M1-M3 are grounded.
These mode pins must be hardware configured, such as, not through GPIO pins from a microcontroller.
• Pin 22 - GVDD_CD is the gate drive voltage for half-bridges C and D. This pin needs a 3.3-Ω isolation
resistor and a 0.1-uF decoupling capacitor.
• Pins 23, 24, 43, 44 - Bootstrap pins for half-bridges A, B, C, and D. Connect 33 nF from this pin to
corresponding output pins.
• Pins 25, 26, 33, 34, 41, 42 - These ground pins should be used to ground decoupling capacitors from
PVDD_X.
• Pins 27, 28, 32, 35, 39, 40 - Output pins from half-bridges A, B, C, and D. Connect appropriate bootstrap
capacitors and differential LC filter as shown in Figure 19.
• Pins 29, 30, 31, 36, 37, 38 - Power supply pins to half-bridges A, B, C, and D. A and B form a full-bridge and
C and D form another full-bridge. A 470-uF bulk cap is recommended for each full-bridge power pins. Two
0.22-µF decoupling capacitors are placed on each full-bridge power pins. See Figure 19 for details.

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8.2.2.3 Application Curves

10 100
2Ω 2Ω
3Ω 3Ω
THD+N − Total Harmonic Distortion + Noise − %

4Ω 4Ω
80

PO − Output Power − W
60

0.1 40

20

0.01 TC = 75°C
TC = 75°C THD+N at 10%
0.005 0
0.02 0.1 1 10 100 10 15 20 25 30 35 40
PO − Output Power − W PVDD − Supply Voltage − V
G009 G010

Figure 20. Total Harmonic Distortion + Noise vs Output Figure 21. Output Power vs Supply Voltage
Power

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8.2.3 Typical PBTL Configuration

3.3R
+12V

GND

10uF 100 nF

1 GVDD_AB BST_A 44 33 nF
100 nF
2 BST_B 43 33 nF
VDD
R OC-ADJUST
3 OC_ADJ GND 42 10µH

/RESET 4 /RESET GND 41

PWM_A 5 INPUT_A OUT_A 40

PWM_B 6 INPUT_B OUT_A 39

220 nF 220 nF
7 C_START PVDD_AB 38 470 uF

100nF 8 DVDD PVDD_AB 37

10nF
1uF
9 GND PVDD_AB 36

TAS5614LA
1 nF
100 nF
10 GND OUT_B 35 3R 3
10 µH
11 GND GND 34 PVDD
GND 470 nF
12 GND GND 33
1uF
13 AVDD OUT_C 32 100 nF 3R 3
10 µH
1 nF
14 INPUT_C PVDD_CD 31
10nF
15 INPUT_D PVDD_CD 30

/FAULT 16 /FAULT PVDD_CD 29 470 uF

220 nF 220 nF
/OTW 17 /OTW OUT_D 28

/CLIP 18 /CLIP OUT_D 27

19 M1 GND 26

20 M2 GND 25
33nF
21 M3 BST_C 24 10 µH
100 nF
33nF
22 GVDD_CD BST_D 23
3.3R

Figure 22. Typical Differential (2N) PBTL Application With AD Modulation Filter

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8.2.3.1 Design Requirements

See Figure 22 for application schematic. In this application, one differential PWM input is used with AD
modulation from the PWM modulator such as the TAS5558. AD modulation scheme is defined as PWM(+) is
opposite polarity from PWM(-). The output PBTL configuration is often used to drive lower impedance load such
as a subwoofer.

8.2.3.2 Detailed Design Procedure

• Pin 1 - GVDD_AB is the gate drive voltage for half-bridges A and B. This pin needs a 3.3-Ω isolation resistor
and a 0.1-uF decoupling capacitor.
• Pin 2 - VDD is the supply for internal voltage regulators AVDD and DVDD. This pin needs a 10-uF bulk cap
and a 0.1-uF decoupling capacitor.
• Pin 3 - Roc adjust is the over-current programming resistor. Depending on the application, this resistor can be
between 24 kΩ to 68 kΩ.
• Pin 4 - RESET pin when asserted, it keeps outputs Hi-Z and no PWM switching. This pin can be controlled by
a microprocessor.
• Pins 5 and 6 - These are PWM (+) and PWM (–) pins with signals provided by a PWM modulator such as
TAS5558. These are PWM differential pair.
• Pin 7 - Start up ramp capacitor should be 0.1 uF for PBTL configuration.
• Pin 8 - Digital output supply pin is connected to 1-uF decoupling capacitor.
• Pins 9-12 - Ground pins are connected to board ground.
• Pin 13 - Analog output supply pin is connected to 1-uF decoupling cap.
• Pins 14 and 15 - These are PWM (+) and PWM (–) pins with signals provided by a PWM modulator such as
TAS5558. These are PWM differential pair.
• Pin 16 - Fault pin can be monitored by a microcontroller through GPIO pin. System can decide to assert reset
or shutdown.
• Pin 17 - Overtemperature warning pin can be monitored by a microcontroller through a GPIO pin. System can
decide to turn on fan or lower output power.
• Pin 18 - Output clip indicator can be monitored by a microcontroller through a GPIO pin. System can decide
to lower the volume.
• Pins 19-21 - Mode pins set the input and output configurations. For this configuration M1-M3 are grounded.
These mode pins must be hardware configured, such as, not through GPIO pins from a microcontroller.
• Pin 22 - GVDD_CD is the gate drive voltage for half-bridges C and D. It needs a 3.3-Ω isolation resistor and a
0.1-uF decoupling capacitor.
• Pins 23, 24, 43, 44 - Bootstrap pins for half-bridges A, B, C, and D. Connect 33 nF from this pin to
corresponding output pins.
• Pins 25, 26, 33, 34, 41, 42 - These ground pins should be used to ground decoupling capacitors from
PVDD_X.
• Pins 27, 28, 32, 35, 39, 40 - Output pins from half-bridges A, B, C, and D. Connect appropriate bootstrap
capacitors and differential LC filter as shown in Figure 22.
• Pins 29, 30, 31, 36, 37, 38 - Power supply pins to half-bridges A, B, C, and D. A and B form a full-bridge and
C and D form another full-bridge. A 470-uF bulk cap is recommended for each full-bridge power pins. Two
0.22-µF decoupling capacitors are placed on each full-bridge power pins. See Figure 22 for details.

Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 29

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8.2.3.3 Application Curves

10 400
2Ω 2Ω
3Ω 3Ω
THD+N − Total Harmonic Distortion + Noise − %

4Ω 350 4Ω

300
1

PO − Output Power − W
250

200

0.1
150

100

50
0.01 TC = 75°C
TC = 75°C THD+N at 10%
0.005 0
0.02 0.1 1 10 100 400 10 15 20 25 30 35 40
PO − Output Power − W PVDD − Supply Voltage − V
G011 G012

Figure 23. Total Harmonic Distortion + Noise vs Output Figure 24. Output Power vs Supply Voltage
Power

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9 Power Supply Recommendations

The most important parameters are the absolute maximum rating on PVDD pins, bootstrap pins, and output pins.
Over stress the device with higher that maximum voltage rating may shorten device lifetime operation and even
cause device damage. Be sure that the specifications in Specifications are observed. For best audio
performance, low ESR bulk caps are recommended. Depending on the application 470-µF capacitor or higher
should be used. As always, decoupling capacitors must be placed no more than 1 mm from the power supply
pins. If PCB space is not allowed for close placement of the decoupling capacitor, the decoupling capacitors can
be placed on the back side of the device with vias. However, it still needs to be right below the pins.

10 Layout

10.1 Layout Guidelines

10.1.1 PCB Material Recommendation
FR-4 Glass Epoxy material with 1 oz. (35 μm) is recommended for use with the TAS5614LA. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance.

10.1.2 PVDD Capacitor Recommendation

The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000 μF, 50 V should support most
applications. The PVDD capacitors should be low ESR type because they are used in a circuit associated with
high-speed switching.

10.1.3 Decoupling Capacitor Recommendation

To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio
performance, good quality decoupling capacitors should be used. In practice, X5R or better should be used in
this application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the close decoupling capacitor that is placed on the power supply to each half-bridge. It must
withstand the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power
output, and the ripple current created by high power output. A minimum voltage rating of 50V is required for use
with a 36-V power supply.
See the TAS5614LADDVEVM user's guide, SLAU375, for more details including layout and bill of materials.

10.1.4 Circuit Component and Printed Circuit Board Recommendation

These requirements must be followed to achieve best performance and reliability and minimum ground bounce at
rated output power of TAS5614LA.

10.1.4.1 Circuit Component Requirements

A number of circuit components are critical to performance and reliability. They include LC filter inductors and
capacitors, decoupling capacitors and the heatsink. The best detailed reference for these is the TAS5614LA
EVM BOM in the user's guide, which includes components that meet all the following requirements.
• High frequency decoupling capacitors: small high frequency decoupling capacitors are placed next to the IC
to control switching spikes and keep high frequency currents in a tight loop to achieve best performance and
reliability and EMC. They must be high quality ceramic parts with material like X7R or X5R and voltage
ratings at least 30% greater than PVDD, to minimize loss of capacitance caused by applied dc voltage.
(Capacitors made of materials like Y5V or Z5U should never be used in decoupling circuits or audio circuits
because their capacitance falls dramatically with applied dc and ac voltage, often to 20% of rated value or
less.)
• Bulk decoupling capacitors: large bulk decoupling capacitors are placed as close as possible to the IC to

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Layout Guidelines (continued)

stabilize the power supply at lower frequencies. They must be high quality aluminum parts with low ESR and
ESL and voltage ratings at least 25% more than PVDD to handle power supply ripple currents and voltages
• LC filter inductors: to maintain high efficiency, short circuit protection and low distortion, LC filter inductors
must be linear to at least the OCP limit and must have low DC resistance and core losses. For SCP,
minimum working inductance, including all variations of tolerance, temperature and current level, must be 5
µH. Inductance variation of more than 1% over the output current range can cause increased distortion.
• LC filter capacitors: to maintain low distortion and reliable operation, LC filter capacitors must be linear to
twice the peak output voltage. For reliability, capacitors must be rated to handle the audio current generated
in them by the maximum expected audio output voltage at the highest audio frequency.
• Heatsink: The heatsink must be fabricated with the PowerPAD contact area spaced 1.0 mm ±0.01 mm above
mounting areas that contact the PCB surface. It must be supported mechanically at each end of the IC. This
mounting ensures the correct pressure to provide good mechanical, thermal and electrical contact with
TAS5614LA PowerPAD. The PowerPAD contact area must be bare and must be interfaced to the PowerPAD
with a thin layer (about 1 mil) of a thermal compound with high thermal conductivity.

10.1.4.2 Printed Circuit Board Requirements

PCB layout, audio performance, EMC and reliability are linked closely together, and solid grounding improves
results in all these areas. The circuit produces high, fast-switching currents, and care must be taken to control
current flow and minimize voltage spikes and ground bounce at IC ground pins. Critical components must be
placed for best performance and PCB traces must be sized for the high audio currents that the IC circuit
produces.
Grounding: ground planes must be used to provide the lowest impedance and inductance for power and audio
signal currents between the IC and its decoupling capacitors, LC filters and power supply connection. The area
directly under the IC should be treated as central ground area for the device, and all IC grounds must be
connected directly to that area. A matrix of vias must be used to connect that area to the ground plane. Ground
planes can be interrupted by radial traces (traces pointing away from the IC), but they must never be interrupted
by circular traces, which disconnect copper outside the circular trace from copper between it and the IC. Top and
bottom areas that do not contain any power or signal traces should be flooded and connected with vias to the
ground plane.
Decoupling capacitors: high frequency decoupling capacitors must be located within 2 mm of the IC and
connected directly to PVDD and GND pins with solid traces. Vias must not be used to complete these
connections, but several vias must be used at each capacitor location to connect top ground directly to the
ground plane. Placement of bulk decoupling capacitors is less critical, but they still must be placed as close as
possible to the IC with strong ground return paths. Typically the heatsink sets the distance.
LC filters: LC filters must be placed as close as possible to the IC after the decoupling capacitors. The capacitors
must have strong ground returns to the IC through top and bottom grounds for effective operation.
PCB copper must be at least 1 ounce thickness. PVDD and output traces must be wide enough to carry
expected average currents without excessive temperature rise. PWM input traces must be kept short and close
together on the input side of the IC and must be shielded with ground flood to avoid interference from high power
switching signals.
The heatsink must be grounded well to the PCB near the IC, and a thin layer of highly conductive thermal
compound (about 1 mil) must be used to connect the heatsink to the PowerPAD.

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10.2 Layout Example

T5

T1
T2
T3

T5

T6

Note T1: Bottom and top layer ground plane areas are used to provide strong ground connections. The area under
the IC must be treated as central ground, with IC grounds connected there and a strong via matrix connecting the
area to bottom ground plane. The ground path from the IC to the power supply ground through top and bottom layers
must be strong to provide very low impedance to high power and audio currents.
Note T2: Low impedance X7R or X5R ceramic high frequency decoupling capacitors must be placed within 2 mm of
PVDD and GND pins and connected directly to them and to top ground plane to provide good decoupling of high
frequency currents for best performance and reliability. Their dc voltage rating must be 2 × PVDD.
Note T3: Low impedance electrolytic bulk decoupling capacitors must be placed as close as possible to the IC.
Typically the heat sink sets the distance. Wide PVDD traces are routed on the top layer with direct connections to the
pins, without going through vias.
Note T4: LC filter inductors and capacitors must be placed as close as possible to the IC after decoupling capacitors.
Inductors must have low dc resistance and switching losses and must be linear to at least the OCP (over current
protection) limit. Capacitors must be linear to at least twice the maximum output voltage and must be capable of
conducting currents generated by the maximum expected high frequency output.
Note T5: Bulk decoupling capacitors and LC filter capacitors must have strong ground return paths through ground
plane to the central ground area under the IC.
Note T6: The heatsink must have a good thermal and electrical connection to PCB ground and to the IC PowerPAD.
It must be connected to the PowerPAD through a thin layer, about 1 mil, of highly conductive thermal compound.

Figure 25. Printed Circuit Board - Top Layer

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Layout Example (continued)

B1

B1
B2

Note B1: A wide PVDD bus and a wide ground path must be used to provide very low impedance to high power and
audio currents to the power supply. Top and bottom ground planes must be connected with vias at many points to
reinforce the ground connections.
Note B2: Wide output traces can be routed on the bottom layer and connected to output pins with strong via arrays.

Figure 26. Printed Circuit Board - Bottom Layer

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11 Device and Documentation Support

11.1 Trademarks
PurePath, PowerPAD are trademarks of Texas Instruments.
Blu-ray is a trademark of Blu-ray Disk Association (BDA).
All other trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 35

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 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TAS5614LADDV ACTIVE HTSSOP DDV 44 35 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 125 TAS5614LA

TAS5614LADDVR ACTIVE HTSSOP DDV 44 2000 RoHS & Green NIPDAU Level-3-260C-168 HR 0 to 125 TAS5614LA

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5614LADDVR HTSSOP DDV 44 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5614LADDVR HTSSOP DDV 44 2000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TAS5614LADDV DDV HTSSOP 44 35 530 11.89 3600 4.9

Pack Materials-Page 3
 PACKAGE OUTLINE
DDV0044D SCALE 1.250
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE

C
8.3
TYP SEATING PLANE
7.9
A PIN 1 ID
AREA 0.1 C
42X 0.635
44
1

2X (0.3)
NOTE 6

14.1 2X
13.9 13.335
NOTE 3 7.30
6.72

EXPOSED
THERMAL
PAD

(0.15) TYP
NOTE 6
2X (0.6)
NOTE 6

22 23
0.27
4.43 44X
0.17
3.85
0.08 C A B
6.2
B
6.0

(0.15) TYP

0.25
1.2
GAGE PLANE
SEE DETAIL A 1.0

0.75 0.15
0 -8 0.50 0.05

DETAIL A
TYPICAL

4218830/A 08/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. The exposed thermal pad is designed to be attached to an external heatsink.
6. Features may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDV0044D PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE

44X (1.45) SYMM SEE DETAILS

1
44

44X (0.4)

42X (0.635)

SYMM

(R0.05) TYP

22 23

(7.5)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER

SOLDER MASK METAL
OPENING SOLDER MASK
OPENING

0.05 MAX 0.05 MIN

AROUND AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE
4218830/A 08/2016
NOTES: (continued)

7. Publication IPC-7351 may have alternate designs.

8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDV0044D PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE

44X (1.45) SYMM

1
44

44X (0.4)

42X (0.635)

SYMM

22 23

(7.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL
SCALE :6X

4218830/A 08/2016
NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.

www.ti.com
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