EXPERIMENT-5

AIM: Implementation of combinational circuit using 16 ×1 MUX.

F( A,B,C,D,E)=∑m(1,4,12,14,16,18,21,25,26,29,31)+d(0,2,5,30)

Software required: Multisim

Circuit Diagram:

THEORY:
In the 16 to 1 multiplexer, there are total of 16 inputs, i.e., A0, A1, …, A16, 4 selection lines,
i.e., S0, S1, S2, and S3 and single output, i.e., Y. On the basis of the combination of inputs
that are present at the selection lines S0, S1, and S2, one of these 16 inputs will be connected
to the output.

PROCEDURE:
1. Open the Multisim in the system.
2. Firstly, we Design 4×1 multiplexer.
3. Place all the necessary components required for the design of 4×1
multiplexer i.e. Three 3-input AND gate(4073BD_10V), 2 NOT
gate(7404N), INTERACTIVE_DIGITAL_CONSTANT and PROBE.
4. Connect all the component by proper wiring, and also assure that nodes are
formed at the interconnection points.
5. Select 4×1 multiplexer excluding inputs  then left click and choose
Replace by hierarchical block option to convert it is in hierarchical block.
 6. Now, using this 4×1 hierarchical block, Design 16 ×1 multiplexer.
7. Now implement the function on 16 ×1 multiplexer.

OUTPUT:
Select line-(1111)2 OR (15)10

Select line-(0111)2 OR (7)10

Select line= (1100)2 OR (12)10

 RESULT:
We have Successfully implemented Function using 16×1 multiplexer.

EXPERIMENT-4
Aim:
To design a 4-bit magnitude Comparator.

Software Required: Multisim Circuit

Diagram:
Theory:
A comparator is a logic circuit used to compare the magnitudes of two binary numbers.
Depending on the design, it may either simply provide an output that is active when the two
numbers are equal, or additionally provide outputs that signify which of the numbers is greater
when equality does not hold.

Procedure:
1. Open the Multisim in the system.
2. Select Place-> Components and from the components, place all the components to
design a 4-bit magnitude comparator i.e. four NOT gate(7404N), four 2-input XNOR
gates(4077BD-10V), two 2-input AND gates(7408N), one 3-input AND
gate(4073BD_10V), three 4-input AND gates(4082BD_5V or 4082BD_10V), one 4-
input OR gate(4072BD_10V), one 2-input NOR gate,
INTERACTIVE_DIGITAL_CONSTANT and PROBES.
3. Connect all the components by proper wiring, and also assured that nodes are formed at
the interconnection points.
4. For different values of A and B, observe output through probes.

Output:
1)A0>B0

2)A0<B0
3)A0=B0

RESULT:
We have successfully designed 4-bit comparator.
 EXPERIMENT-3

AIM: Design a 4 bit BCD to XS-3 code converter and XS-3 code to BCD code convertor.
SOFTWARE REQUIRED: Multisim
CCIRCUIT DIAGRAM:
FOR BCD TO XS-3:

FOR XS-3 TO BCD:

PROCEDURE:

1. Open the Multisim in the system.

2. Place all the necessary components required for the design of BCD to XS-3 Code
converter and XS-3 to BCD code converter i.e. ONE 3-input AND
gate(4073BD_10V), 10 AND gate(7408N),4 NOT gate(7404N),10 OR
Gate(7432N),2 NOR gate (7402N),and ONE XOR(7486N),
INTERACTIVE_DIGITAL_CONSTANT and PROBE.
3. Connect all the components by proper wiring and also assured that nodes are formed
at the interconnection points.
4. Observe the Output according to Conversion table and output are shown below.
OUTPUT:
FOR BCD TO XS-3:

FOR (0001)2 WE GET (0100)2

FOR (0101)2 WE GET (1000)2
FOR BCD TO XS-3:
FOR (0110)2 WE GET (0011)2

FOR (0111)2 WE GET (0100)2

 RESULT:
We have successfully Designed BCD to XS-3 code converter and XS-3 to BCD
Code converter.

EXPERIMENT-2
Aim:
Design a 4-bit parallel adder and subtractor using full adder.

Software required:
Multisim

Circuit Diagram:
Theory:
• If initial carry Cin is 0, then each full adder gets the normal bit of binary number
A and B. So the four bit binary adder/ subtractor produces an output, which is
the addition of two binary number A and B.
• If initial borrow Cin is 1, then each full adder get the normal bit of binary
number A and complemented bits of binary number B. So the four bit binary
adder /subtractor produces an output, which is the subtraction of two binary
number A and B.
• Therefore, with the help of additional XOR gate, the same circuit can be used
for both addition and subtraction of two binary number.

Procedure:

1. Open the Multisim in the system.

2. Firstly, we design full adder.
3. Place all the necessary components required for the design of full adder i.e. nine
2-input NAND gate(7400), INTERACTIVE_DIGITAL_CONSTANT and
PROBE.
4. Connect all the component by proper wiring, and also assure that nodes are formed
at the interconnection points.
5. Select all NAND gates excluding inputs ,then left click and choose Replace by
hierarchical block option to convert it is in hierarchical block.
6. Now, using these full adder made IC’s to design 4-bit parallel adder and subtractor.
7. Now, run the circuit of 4-bit parallel adder and subtractor for output.

Output:

• When Cin = 0 , circuit will perform 4-bit parallel adder

Input (1011+1010) = O/P(1101) with Cout=1

Input (0110+0111) = O/P(1101) with Cout=1

• When Cin=1, circuit will perform 4-bit parallel subtractor

Input (1011-1010) = O/P(0001) with Cout=1

Input (1001-1101) = O/P(1100) with no borrow

Result:
We have successfully designed 4-bit parallel adder/subtractor using full adder.
 EXPERIMENT-1

AIM – DESIGN OF FULL ADDER, FULL SUBTRACTOR , 4 BIT BINARY PARLLEL ADDER
and 4 BIT
BINARY PARLLEL SUBTRACTOR

SOFTWARE USED – MULTISIM

FULL ADDER CIRCUIT DIAGRAM – USING NAND GATE:

THEORY –
The full-adder adds the bits A and B and the carry from the previous column
called the carry-in Cin and outputs the sum bit S and the carry bit called the
carry-out Cout. The variable S gives the value of the least significant bit of
the sum. The variable Cout gives the output carry.
PROCEDURE –

1. Open the Multisim in the system.

2. Select Place-> Components and from the components, place all the components to
design a FULL ADDER i.e.NAND gate(7400N)
INTERACTIVE_DIGITAL_CONSTANT and PROBES.
3. Connect all the components by proper wiring, and also assured that nodes are formed
at the interconnection points.
4. Observe the output according to truth table of FULL ADDER.

OUTPUT –
For input A=0, B=1, Cin=1

Output - SUM=0, Cout=1

For input A=0, B=0, Cin=1
Output - SUM=1, Cout=0

For input A=1, B=1, Cin=1

Output - SUM=1, Cout=1

RESULT – We have successfully implemented FULL ADDER using NAND gate.

FULL SUBTRACTOR
CIRCUIT DIAGRAM –
USING NAND GATE:

THEORY –
The half-subtractor can be only for LSB subtraction. IF there is a borrow during the subtraction of the
LSBs, it affects the subtraction in the next higher column; the subtrahend bit is subtracted from the
minuend bit, considering the borrow from that column used for the subtraction in the preceding column.
Such a subtraction is performed by a full-subtractor. It subtracts one bit (B) from another bit (A), when
already there is a borrow bi from this column for the subtraction in the preceding column, and outputs
the difference bit (d) and the borrow bit(b) required from the next d and b. The two outputs present the
difference and output borrow. The 1s and 0s for the output variables are determined from the subtraction
of A-B-bi.

PROCEDURE –
1. Open the Multisim in the system.
2. Select Place-> Components and from the components, place all the components to
design a FULL ADDER i.e. NAND gate(7400N)
INTERACTIVE_DIGITAL_CONSTANT and PROBES.
3. Connect all the components by proper wiring, and also assured that nodes are formed
at the interconnection points.
4. Observe the output according to truth table of FULL SUBTRACTOR.
OUTPUT –
Using NAND logic gates:

For input A=0, B=0, Bin=1

Output - DIFFERENCE=1, Bout=1

For input A=0, B=1, Bin=0

Output - DIFFERENCE=1, Bout=0

For input A=1, B=1, Bin=1

Output -DIFFERENCE=1, Bout=1

RESULT – We have successfully implemented FULL SUBTRACTOR using NAND gate.

4 BIT BINARY PARLLEL ADDER

Circuit diagram:

Theory:

A binary parallel adder is a digital circuit that adds two binary number in
parallel form and produces the arithmetic sum of those number in parallel
form. It consists of full adders connected in chain, with the output carry
from each full adder connected to the input carry of the next full adder in
the chain. For 4-bit parallel adder, we require four full adder circuit.

Procedure:
1. Open the Multisim in the software.
2. Firstly we design full adder circuit.
3. Place all the necessary components for design of full adder circuit i.e.
NAND gates(7400N), INTERACTIVE_DIGITAL_CONSTANT and
PROBE.
4. Connect all the components by proper wiring, and also assured that
nodes are formed at the interconnection points.
5. Select full adder circuit excluding inputs-> then right click and
choose Replace by hierarchical block option to convert it is in
hierarchical block.
6. Now, using this hierarchical block, design 4-bit parallel adder circuit
as per circuit diagram.
 7. Now for different values of A and B , observed the output of addition
of these two 4bit binary number on the probes.

OUTPUT:

I/P (1000+1000) = O/P (0000) with Cout=1

I/P (1111+1111) = O/P (0111) with Cout=1

Result: We have successfully design a 4-bit binary parallel adder.

4BIT BINARY PARLLEL SUBTRACTOR

Circuit diagram:

Theory:
The 4- bit binary subtractor produces the subtraction of two 4-bit number.
Internally, the operation of 4- bit binary subtractor is similar to that of 4- bit
binary adder. If normal bit of binary number A, complemented bit of binary
number B, and initial carry (Borrow) Cin as 1 are applied to 4-bit binary
adder, then it becomes 4 binary subtractor.

Procedure:
1. Open the Multisim in the software.
2. Firstly we design full adder circuit.
3. Place all the necessary components for design of full adder circuit i.e. NAND
gates(7400N), INTERACTIVE_DIGITAL_CONSTANT and PROBE.
4. Connect all the components by proper wiring, and also assured that nodes are
formed at the interconnection points.
5. Select full adder circuit excluding inputs-> then right click and choose Replace
by hierarchical block option to convert it is in hierarchical block.
6. Now, using this hierarchical block, design 4-bit parallel subtractor circuit as per
circuit diagram.
7. Now for different values of A and B , observed the output of subtraction of these
two 4bit binary number on the probes.
OUTPUT:

I/P (1111-1111) = O/P (0000) with Cout=1

I/P (1011-0010) = O/P (1001) with Cout=1

Result: We have successfully design a 4-bit binary parallel subtractor.

 EXPERIMENT-8
Aim:
To design a 3-bit gray code counter. The counter is designed with one input
terminal and one output terminal. When input is low, counter holds the present
state otherwise goes to next state. After count 100 is reached, output becomes
active high and will reset the counter to its initial state i.e. 000.
Software Required: Multisim
Circuit Diagram:

Procedure:
1. Open the Multisim in the system.
2. Select Place->Components. From components, place all the
necessary components to design a 3-bit gray code counter i.e. three J-
k flip flop(7473N), two inverters(7404N), three 2-input AND
gates(7408N), one 3-input AND gate(4073BD_5V), one 2-input
XNOR gate(4077BD_5V), one 2-input XOR gate(74136N),
INTERACTIVE_DIGITAL_CONSTANT, Digital Clock and
PROBES.
3. Connect all the components by proper wiring and also assured that
nodes are formed at the interconnection points.
4. Apply active high signal to the input and then 3-bit gray counting is
initiated.
5. At any moment , if we apply active low signal to the input, counter
holds the present counting state. Counting state is observed in upper
three probes.
 6. . If counted is reached at 100 , output becomes active high otherwise
zero.
7. ALSO observe this through Oscilliscope, after seven 7 clock cycle
output is 1 as expected according to question.

OUTPUT:
WHEN X=0 COUNT HOLD AT 101

AT(100) COUNT IS COMPLETE AND OUTPUT IS 1

Output is 1 after 7cycle

RESULT:
We have successfully design a 3-bit gray code counter using J-K flip flops.
 EXPERIMENT-12
AIM: To design an Asynchronous mod-10 counter.
Software Required: Multisim

CIRCUIT DIAGRAM:

THEORY:
A decade counter requires resetting to zero when the output count reaches the decimal value
of 10, i.e. when 1010 and to do this we need to feed this condition back to the reset input
through Nand gate. A counter with a count sequence from binary “0000” (BCD = “0”)
through to “1001” (BCD = “9”) is generally referred to as a BCD binary-coded-decimal
counter

PROCEDURE:
1. Open the Multisim in the system.
2. Select Place->Components. From Components, place all the components to
design a MOD-10 counter i.e. two inverter(7404N), one NAND
gate(7413N),four JK FLIP
FLOP(74LS112D),INTERACTIVE_DIGITAL_CONSTANT, PROBES,
Digital clock and LOGIC ANALYZER.
3. Connect all the components by proper wiring and also assured that nodes
are formed at the interconnection points.
4. Observe the output through PROBES AND ALSO LOGIC ANALYZER
which shows the timing diagram of MOD-10 Counter ,according to table
shown below.
OUTPUT:
COUNT-0000

COUNT-0001

COUNT-0010
COUNT-0011

COUNT-0100

COUNT-0101
COUNT-0110

COUNT-0111

COUNT-1000
COUNT-1001

OUTPUT OF LOGIC ANALYZER:

Q1-Shown by red waveform
Q2-shown by blue waveform
Q3-shown by green waveform
Q4-shown by yellow waveform
RESULT:
We have Successfully designed Asynchronous mod-10 counter Using JK flip
flop.

EXPERIMENT-11
AIM: To Design a SHIFT REGISTER COUNTER(Ring counter and Johnson
counter).
Software Required: Multisim Circuit
diagram:
RING COUNTER
JOHNSON COUNTER

THEORY:
A ring counter is a special type of application of the Serial IN Serial OUT Shift register. The only
difference between the shift register and the ring counter is that the last flip flop outcome is taken as
the output in the shift register. But in the ring counter, this outcome is passed to the first flip flop as
an input. All of the remaining things in the ring counter are the same as the shift register.

The Johnson counter is similar to the Ring counter. The only difference between the Johnson
counter and the ring counter is that the outcome of the last flip flop is passed to the first flip flop as
an input. But in Johnson counter, the inverted outcome Q' of the last flip flop is passed as an input.
The remaining work of the Johnson counter is the same as a ring counter
PROCEDURE:
1. Open the Multisim in the system.
2. Select Place->Components. From components, place all the components for design a
serial adder i.e. FOUR D-flip flop(74LS74D), Digital Clock
INTERACTIVE_DIGITAL_CONSTANT and PROBES.
3. Connect all the components by proper wiring, and also assured that nodes are formed
at the interconnection points.
4. In ring counter,First d flip PRESET should be given 0 and clear 1 and for
other three flip flop, clear 0 and preset is 1 because to obtain the sequence
table .
5. In Johnson counter, all preset and clear should be given low.
6. Observe the Output according to the above Sequence table
OUTPUT:
RING COUNTER:
1000

0100
0010

0001

JOHNSON COUNTER:
0000
1000

1100

1110
1111

RESULT:
We have successfully Designed Ring and Johnson Counter.

EXPERIMENT-10
Aim:

Implementation of BCD to seven segment decoder using ROM.

Software Required:
Multisim

Circuit Diagram:
Theory:
A read-only memory is essentially a memory device in which permanent binary information
is stored. The binary information must be specified by the designer and is then embedded in
the unit to form the required interconnection pattern. Once the pattern is established, it stays
with in the unit when the power is turned off and on again.
A ROM which can be programmed is called PROM. ROMs can be used for designing
combinational circuits. Depending on the type of ROM used, a user can design and modify
the circuits easily.

Procedure:
1. Open the Multisim in the system.
2. Select Place->Components. From components place all the components for designing
a BCD to seven segment decoder using ROM i.e. ROM(27C64E200-883), seven
segment display and INTERACTIVE_DIGITAL_CONSTANT.
3. Connect all the components by proper wiring and also assured that nodes are formed
at the interconnection points.
4. Now RUN the simulation and then PAUSE the simulation. Select MCU-
>27C64E200- 883->view memory table. Feed the data from 00 -09 into first ten
continuous memory locations(0000-0009).
5. Then give active high signal to PGMbar pin and then RUN the simulation.
6. Observe the seven segment output for different combination of memory location
i.e.(0000-0009).

Output:-
Result:
We have successfully implemented the BCD to seven segment decoder using ROM. In
seven segment,we successfully display BCD numbers from (0 to 9).
 EXPERIMENT-7
Aim:
To design a sequence detector to detect the sequence 1010(overlapping is
allowed).
Software Required: Multisim

CIRCUIT DIAGRAM:

Theory:
A sequence detector is a sequential machine which produces an output 1 every
time the desired sequence is detected and an output 0 at all other times.

PROCEDURE:
1. Open the Multisim in the system.
2. Select Place->Components. From Components, place all the components to design a
sequence detector to detect 1010 sequences i.e. one inverter(7404N), one 2-input AND
gate(7408N), two 3-input AND gates(4073BD_5V), one 2-input OR gate(7432N), two
Dflip flop(7474N), INTERACTIVE_DIGITAL_CONSTANT, PROBES, Digital clock
and Oscilloscope.
3. Connect all the components by proper wiring and also assured that nodes are formed
at the interconnection points.

4. Observe the output waveform in oscilloscope in B channel ,When output becomes active
high, sequence 1010 is detected otherwise Output will be low.
OUTPUT:

RESULT:
We have successfully designed Sequence detector to detect Sequence 1010 as shown in
above waveform. As 1010 is detected output is high and after some time only after (10
)output is detected as OVERLAPPING is also allowed.
 EXPERIMENT-6

AIM: To design Serial binary adder.

Software Required: Multisim

CIRCUIT DIAGRAM:

THEORY:
Serial adder is a combinational circuit that perform the addition of two binary numbers
in serial form. Serial adder perform bit by bit addition.

PROCEDURE:
1. Open the Multisim in the system.
2. Select Place->Components. From components, place all the components for
design a serial adder i.e. two 2-input AND gates(7408N), two 2-input OR
gates(7432N), two 2-
input XOR gates(74136N), one D-flip flop(7474N), Digital Clock
INTERACTIVE_DIGITAL_CONSTANT and PROBES.
3. Connect all the components by proper wiring, and also assured that nodes are
formed at the interconnection points.

4. Observe the output on the probes according to EXCITATION TABLE as shown

below:
OUTPUT:

WHEN X1 AND X2 =0
WHEN X1=0 AND X2=1

WHEN X1=1 AND X2=0

WHEN X1 AND X2=1,STATE CHANGE

WHEN X1=1 AND X2=0

WHEN X1=0 AND X2=1

Result:
We have successfully design a serial binary adder circuit.
 EXPERIMENT-9
AIM: TO DESIGN SHIFT REGISTERS (SERAIL-IN, SERIAL-0UT(SISO),SERIAL-IN-
PARALLEL-
OUT(SIPO),PARALLEL-IN-SERIAL-OUT(PISO),PARALLEL-IN-PARALLEL-
OUT(PIPO))

SOFTWARE REQUIRED:
MULTISIM
CIRCUIT DIAGRAM:
SISO AND SIPO:

PISO

PIPO
THEORY:
Shift Register is a group of flip flops used to store multiple bits of data. The bits stored in
such registers can be made to move within the registers and in/out of the registers by
applying clock pulses.

Serial-In Serial-Out Shift Register (SISO)

and produces a serial output is known as Serial-In Serial-Out shift register. Since there is
only one output, the data leaves the shift register one bit at a time in a serial pattern, thus
the name Serial-In Serial-Out Shift Register. The shift register, which allows serial input
(one bit after the other through a single data line)

Serial-In Parallel-Out shift Register (SIPO)

The shift register, which allows serial input (one bit after the other through a single data
line) and produces a parallel output is known as Serial-In Parallel-Out shift register.

Parallel-In Serial-Out Shift Register (PISO)

The shift register, which allows parallel input (data is given separately to each flip flop
and in a simultaneous manner) and produces a serial output is known as Parallel-In
Serial-Out shift register.

Parallel-In Parallel-Out Shift Register (PIPO)

The shift register, which allows parallel input (data is given separately to each flip flop
and in a simultaneous manner) and also produces a parallel output is known as Parallel-
In parallelOut shift register.
PROCEDURE:
1. Open the Multisim in the system.
2. Select Place->Components. From components, place all the components for
design a serial adder i.e. FOUR D-flip flop(74LS74D), Digital Clock
INTERACTIVE_DIGITAL_CONSTANT and PROBES.
3. Connect all the components by proper wiring, and also assured that nodes are
formed at the interconnection points.
4. Observe the output through probes for these shift registers.
OUTPUT: SERIAL- IN SERIAL-OUT AND SERIAL-IN PARALLEL-OUT:
PARALLEL-IN PARALLEL-OUT:

PARALLEL -IN SERIAL-OUT:

When s=0, data input appears at the D input of respective flip flop
When S=1 data bit to shift right from one FF to next
RESULT:
We have Successfully design SHIFT REGISTERS.