VLSI Manufacturing Technology

Instructor: Yiming MA
yimingma@shu.edu.cn
Office: Room 408, SME Building

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 Textbook
Silicon VLSI Technology (by Plummer, Deal and Griffin)

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 Grading

Homework 30%
Final (open-book) 70%

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Chapter 1 Introduction and Historical Perspective

1. Introduction.
2. Growth of IC – Moore’s law.
3. Some history in IC industry.
4. Semiconductors.
5. Semiconductor devices, semiconductor technology
families.

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 Introduction

State of art ICs

manufactured in the 1990s.

• This course is basically about silicon chip fabrication, the technologies used to manufacture
ICs (CPU, memory – DRAM, flash…).
• However, the same technology is also widely used for applications other than ICs, such as
large area displays (LCD), hard disk drive, semiconductor lasers, MEMS
(microelectromechanical systems), lab-on-a-chip, solar cell….
• For nano-application, microfabrication is the basis for nanofabrication; with the major
differences is that photolithography is used for microfabrication whereas nano-lithography
(electron beam lithography…) is used for nanofabrication.
• Therefore, you will find this course very useful even if you will not work in the IC industry
after graduation. 5
 Basic fabrication components
A sequence of additive and subtractive steps with lateral patterning.

Three components for micro- and nano-fabrication:

Lithography (lateral patterning): generate pattern in a material called resist
photolithography, electron-beam lithography, nanoimprint lithography…
Thin film deposition (additive): spin coating, chemical vapor deposition, molecular beam
epitaxy, sputtering, evaporation, electroplating…
Etching (subtractive): reactive ion etching, ion beam etching, wet chemical etching,
polishing…
Other techniques such as doping (ion implantation) is also important for semiconductor
device. 6
 One fabrication example
metal nanostructures

Metal nanostructures
side
view substrate substrate

Direct etch process Liftoff process

resist resist
(polymer) (polymer)
1. Thin film growth 1. Thin film growth

2. Lithography 2. Lithography

3. Etching
3. Deposition

4. Etching (dissolve resist) 4. Etching (dissolve resist)

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 One more step: pillar array with various diameters
Pitch: 200nm
Cr 35 nm diameter
silicon
1. Cr dots by liftoff

2. RIE silicon and remove Cr

(RIE: reactive ion etching)

70 nm diameter
115 nm diameter
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 Summary of general fabrication process

or doping

Direct etch Liftoff Electroplating…

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Chapter 1 Introduction and Historical Perspective

1. Introduction.
2. Growth of IC – Moore’s law.
3. Some history in IC industry.
4. Semiconductors.
5. Semiconductor devices, semiconductor technology
families.

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 Explosive growth of computing power

1st electronic computer

ENIAC (1946)

Pentium IV

1st computer(1832)
1st transistor
Vacuum Tuber 1947

Macroelectronics Microelectronics
11 Nanoelectronics
 Explosive growth of computing power

1971 1989 1991 2001 2003

4004 ® 386 ® 486 ® Pentium IV ® Itanium 2®
410M
transistor /chip

42M
1.2M
134 000
2300

10 µm 1 µm 0.1 µm
Human hair Red blood cell Bacteria Virus transistor size

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 Device scaling down over time in IC industry
Moore’s law: doubling of the number of transistors on a chip roughly every two years.
This is realized by:
Making transistor smaller - smallest lateral feature size decreases by 13% each year.
Making chip bigger – chip/wafer size increases 16%/year.
Number of transistors

Gordon Moore:
born 3 January 1929,
co-founder and
Miscellaneous early ICs Chairman Emeritus of
DRAM memory Intel Corporation;
Intel x86 microprocessors author of Moore's Law
Intel Itanium/IA64 microprocessors published in 1965.
nVIDIA graphics processors

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 Device scaling down over time in IC industry
Feature Size

100µm

Era of Simple Scaling

10µm Cell dimensions

1µm
Scaling + Innovation
130 nm in 2002 (ITRS)
0.1µm

Invention
10nm 18 nm in 2018
Transition Region
Atomic dimensions
1nm Quantum Effects Dominate

Atomic Dimensions
0.1nm
1960 1980 2000 2020 2040 Year

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 Device scaling down over time in IC industry
Assumes CMOS technology dominates over entire roadmap.
2 year cycle moving to 3 years (scaling + innovation now required).
SIA-NTRS: 2 year cycle 3 year cycle
Year of Production 1998 2000 2002 2004 2007 2010 2013 2016 2018

Technology Node (half pitch) 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 18 nm

Each node half pitch (1/2), area per transistor (1/2), i.e. for same chip size, # of transistors doubled
MPU Printed Gate Length 100 nm 70 nm 53 nm 35 nm 25 nm 18 nm 13 nm 10 nm
(MPU - microprocessor unit)
DRAM Bits/Chip (Sampling) 256M 512M 1G 4G 16G 32G 64G 128G 128G

MPU Transistors/Chip (x106) 550 1100 2200 4400 8800 14,000

Min Supply Voltage (volts) 1.8-2.5 1.5-1.8 1.2-1.5 0.9-1.2 0.8-1.1 0.7-1-0 06-0.9 0.5-0.8 0.5-0.7

Scaling down supply voltage because otherwise, as transistors get smaller, the electric
fields (voltage/feature size) in these devices will increase to unacceptable levels.
In addition, the number of levels of interconnection and photo-mask also increases.

SIA: Semiconductor Industry Association

NTRS: National Technology Roadmap for Semiconductors.
ITRS: International Technology Roadmap for Semiconductors
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 Device scaling down over time in IC industry

MBC: Multi-Bridge-Channel
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GAA: Gate-All-Around
Device scaling down over time in IC industry

MBC: Multi-Bridge-Channel

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Device scaling down over time in IC industry

During the highly competitive 90s, few

companies began to use new node definitions
to attract the attention of customers.
MBC: Multi-Bridge-Channel
Finally, the technology node definition became
70% of whatever the name of the node of the
previous generation was!

IRDS: International Roadmap for Devices and Systems

From Moore’s Law to NTRS to ITRS to IRDS 18
Device scaling down over time in IC industry

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Device scaling down over time in IC industry

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 Device scaling down over time in IC industry

No wonder Moore’s Law will be still valid for the next 10 years, once the real numbers of IC
features are used for node definition; there is still a lot of room to run for scaling as a
contributor to increasing transistor density!
Feature scaling will reach fundamental limits of around 7-8 nm at the end of this decade.
However, by early 2030 it is expected that quantum computing technologies will begin to
make real contributions to the advancement of the electronics industry. 21
Chapter 1 Introduction and Historical Perspective

1. Introduction.
2. Growth of IC – Moore’s law.
3. Some history in IC industry.
4. Semiconductors.
5. Semiconductor devices, semiconductor technology
families.

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 IC fabrication technology: brief history

• 1940s - setting the stage - the initial inventions that made integrated circuits
possible.
• In 1945, Bell Labs established a group to develop a semiconductor replacement
for the vacuum tube. The group led by William Shockley, included, John Bardeen,
Walter Brattain and others.
• In 1947 Bardeen and Brattain and Shockley succeeded in creating an amplifying
circuit utilizing a point-contact "transfer resistance" device that later became
known as a transistor.
• In 1951 Shockley developed the junction transistor, a more practical form of the
transistor.
• By 1954 the transistor was an essential component of the telephone system and
the transistor first appeared in hearing aids followed by radios.

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 Some history in IC industry: first transistor
1st transistor in 1947 by Bell Lab, it is a point contact transistor.

J. Bardeen

W. Brattain

W. Shockley

Bipolar transistor in Base is n-type Ge.

polycrystalline Germanium, Emitter and collector are two metal wires, which
1956 Nobel Prize in physics. are very thin and pushed onto the Ge base.
Distance between the two metal wires: 200-250m.
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 First junction transistor

Gordon Teal and Morgan Sparks made

the first junction transistor, the
construction of which eliminated many
of the reliability problems of the point
contact transistors.

Grown junction transistor technology of the

1950s, in single crystalline Si or Ge.
For Si device, Al wire is used to connect to
the middle P base region (it doesn’t matter
if Al is also contacted to the N-regions due
to the high contact resistance with N). 25
 Alloy junction technology of the 1950s

Indium melts at 157oC, and it is a P-type dopant.

(In is in the same group as B, the most popular P-type dopant. B, Al, Ga, In…)

It is a very simple idea.

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 Doubled diffused mesa transistor
technology of the late 1950s
Gas phase diffusion (e.g. PH3 gas to dope with P) to dope the silicon.
Many devices could be produced from a single substrate.
But exposed junctions were present on the wafer surface or at wafer edges.

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 Integrated Circuit (IC) invented by Kilby from TI
IC: integrate multiple
components on the same
chip and to interconnect
them to form a circuit.

A simple oscillator IC with five integrated

components (resistors, capacitors, distributed
capacitors and transistors) on Ge substrate. Jack Kilby, Nobel Prize
in Physics in 2000
To read (if interested) “Turning Potential into Realities: The Invention of
the Integrated Circuit (Nobel Lecture)” TI: Texas Instrument
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http://www3.interscience.wiley.com/cgi-bin/fulltext/85010385/PDFSTART
 Planar process invented in the late 1950s
• Kilby's invention had a serious drawback, the
individual circuit elements were connected together
with gold wires making the circuit difficult to scale up
to any complexity.
• By late 1958 Jean Hoerni at Fairchild had developed a
structure with N and P junctions formed in silicon.
Over the junctions a thin layer of silicon dioxide was
used as an insulator and holes were etched open in
the silicon dioxide to connect to the junctions.
• In 1959, Robert Noyce also of Fairchild had the idea
to evaporate a thin metal layer over the circuits
created by Hoerni's process.
Monolithic: made from same substrate
• The metal layer connected down to the junctions
through the holes in the silicon dioxide and was then Planar technology
etched into a pattern to interconnect the circuit.
• Planar technology set the stage for complex
integrated circuits and is the process used today.

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 Planar process invented in the late 1950s
• Gas phase diffusion masked by SiO2.
• SiO2 patterned by photolithography.
• Since only Si has this perfect oxide that can block the
diffusion, technology was shifted from Ge to Si.
• Junction is under SiO2 surface (no longer exposed to
surface/edges), it is thus passivated/protected.

Boron diffusion

Jean Hoerni from Fairchild,

Phosphorus inventor of planar process
diffusion
Oxidation and
drive-in diffusion

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 IC and basic photolithography process
Integrated circuit use photolithography and
masking to fabricate multiple components in
a common substrate.
Here are one bipolar transistor and two
Resistor Base resistors.
Contact to collector Emitter

Collector

The IC pattern is
transferred from a mask
to the silicon by printing
it on the wafer using a
light sensitive resist
material.

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 Modern integrated circuit

Actual cross-section of a modern

Schematic cross-section of a modern silicon
microprocessor chip.
IC. Here is a CMOS with an NMOS device on
Note the multiple levels of metal. The
the right, and PMOS on the left. There are
active parts of the transistors are barely
two levels of wiring shown.
visible at the bottom of the photography.

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 Breakthroughs in IC history (summary)
• Bardeen, Brattain, Shockley, First Ge-based bipolar transistor invented 1947, Bell Labs.
Nobel prize in 1956.
• Atalla, First Si-based MOSFET invented 1958, Bell Labs.
• Kilby (TI) & Noyce (Fairchild), Invention of integrated circuits 1959, Nobel prize in 2000.
• Planar technology, Jean Hoerni, Fairchild, 1959
• First CMOS circuit invented 1963, Fairchild
• “Moore’s law” coined 1965, Fairchild
• Dennard, scaling rule presented 1974, IBM
• First Si technology roadmap published 1994, USA

Intel was founded in 1968, 2250 transistors

by Gordon Moore and
Robert Noyce, both from
Fairchild.

For Fairchild’s history, go to

http://en.wikipedia.org/wiki/Fa
irchild_Semiconductor

M2 Max by Apple 2023, 67 billion transistors

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