1.
1 Brief History
1.2 Brief Overview
1.3 Summary
1.1 Brief History
1.1
Objective 1.2
After taking this course, you will able to
1.3
Use common semiconductor terminology
Describe a basic IC fabrication sequence
Briefly explain each process step
Relate your job or products to
semiconductor manufacturing process
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1
1.1
Topics 1.2
Introduction
1.3
ICDevice and Design
Semiconductor Manufacturing Processes
Future Trends
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1.1
Introduction 1.2
First Transistor, AT&T Bell Labs, 1947
1.3
First Single Crystal Germanium, 1952
First Single Crystal Silicon, 1954
First IC device, TI, 1958
First IC product, Fairchild Camera, 1961
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2
1.1
First Transistor, Bell Lab, 1947 1.2
1.3
Photo courtesy: AT&T Archive
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1.1
First Transistor and Its Inventors 1.2
1.3
John Bardeen,
William Shockley and Walter Brattain
Photo courtesy: Lucent Technologies Inc.
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3
1.1
First IC Device Made by Jack Kilby of 1.2
Texas Instrument in 1958 1.3
Photo courtesy: Texas Instruments
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1.1
First Silicon IC Chip Made by Robert 1.2
Noyce of Fairchild Camera in 1961 1.3
Photo courtesy: Fairchild Semiconductor International
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4
1.1
Jack Kilby and Robert Noyce 1.2
1.3
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1.1
Moore’s Law 1.2
Intel co-founder Gorden Moore notice in
1.3
1964
Number of transistors doubled every 12
months while price unchanged
Slowed down in the 1980s to every 18
months
Amazingly still correct.
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5
1.1
Moore’s Law 1.2
1.3
http://www.entrepreneursstartup.com/wp-content/uploads/2011/02/GordonMoore_1_2005_large.jpg
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1.1
Moore’s Law 1.2
1.3
http://chemlinks.beloit.edu/edetc/SlideShow/images/computer/Moores_Law.jpg
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6
1.1
Moore’s Law 1.2
1.3
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1.1
IC Scales 1.2
1.3
Integration level Abbreviation Number of devices
on a chip
Small Scale Integration SSI 2 ~ 50
Medium Scale Integration MSI 50 ~ 5,000
Large Scale Integration LSI 5,000 ~ 100,000
Very Large Scale Integration VLSI 100,000 ~ 10,000,000
Ultra Large Scale Integration ULSI 10,000,000 ~
1,000,000,000
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1.1
Feature Size and Wafer Size 1.2
1.3
Chip or die
Chip made with 450 mm
28nm node
With 20nm 300 mm
With 14nm 200 mm
with
10nm 150 mm
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1.1
Transistor Made by NEC in 2003 1.2
1.3
11 nm gate width Photo courtesy: NEC Corporation
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8
1.1
Technology Node Definition 1.2
1.3
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1.1
Limit of the IC device Scaling 1.2
Atom size: several Å
1.3
Need some atoms to form a device
Likely the final limit is around 50 Å or 5nm.
About 10 silicon atoms
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9
1.1
Limit of the IC Geometry 1.2
1.3
Size of the atom
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1.1
Factors that Limit the IC Scaling 1.2
Physics
1.3
Size of atom
Technology
Patterning
Finance
Technology vs. profitability
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1.1
R&D Cost of IC Technologies 1.2
1.3
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1.1
Slowdown of the Moore’s Law 1.2
1.3
http://www.indybay.org/uploads/2006/05/18/moore__sl_small.jpglsjprm.jpg
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1.1
Moore’s Law or Law of More 1.2
Reducing the minimum feature size can
1.3
make device smaller and allow more chips
per wafer.
Or more powerful chip with the same die
size.
Both ways can help IC fabs to make more
profit.
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1.2 Brief Overview
1.1
IC Design: First IC 1.2
1.3
Photo courtesy: Texas Instruments
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12
1.1
IC Design:CMOS Inverter 1.2
1.3
Vin
Vdd
(a)
NMOS PMOS
Vss
Vout
Shallow trench isolation (STI)
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1.1
IC Design:CMOS Inverter P-channel active region
P-channel Vt 1.2
P-channel LDD 1.3
N-channel active region P-channel S/D
N-channel Vt
N-channel LDD
N-channel S/D
(b)
P-well
N-well
Metal 1 Polycide gate and local
interconnection
Contact
Metal 1, AlCu
W
PMD
n+ n+ STI p+ p+
P-Well
P-Epi
N-Well
(c)
P-Wafer
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1.1
IC Design: Layout and Masks of CMOS 1.2
Inverter 1.3
CMOS inverter layout Mask 1, shallow trench isolation Mask 2, N-well
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1.1
IC Design: Layout and Masks of CMOS 1.2
Inverter 1.3
Mask 3, P-well Mask 4, 7, 9, N-Vt, LDD, S/D Mask 5, 8, 10, P-Vt, LDD, S/D
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1.1
IC Design: Layout and Masks of CMOS 1.2
Inverter 1.3
Mask 6, gate/local interconnection Mask 11, contact Mask 12, metal 1
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1.1
Practical Inverter Layout 1.2
1.3
Polysilicon gate
P-channel active area N-channel active area
P-channel Vt N-channel Vt
P-channel SDE N-channel SDE
P-channel S/D N-channel S/D
Contact Metal 1
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1.1
Mask/Reticle 1.2
1.3
Pellicle Chrome pattern Phase shift coating
Quartz substrate
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1.1
A Mask and a Reticle 1.2
1.3
Photo courtesy: SGS Thompson
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1.1
Wafer Process Flow 1.2
1.3
Materials IC Fab
Dielectric Test
Metallization CMP
deposition
Wafers
Thermal Implant Etch Packaging
Processes PR strip PR strip
Masks
Photo- Final Test
lithography
Design
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1.3 Summary
1.1
First transistor: 1947, Bell Labs 1.2
First IC: 1958, TI; 1961, Fairchild 1.3
Moore’s Law
IC scaling limit
IC design and processing
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