STM32WB5MMG

Datasheet

Bluetooth® Low Energy 5.3 and 802.15.4 module

Features
• Include ST state-of-the-art patented technology
• Integrated chip antenna
• Bluetooth® Low Energy 5.3, Zigbee® 3.0, OpenThread certified
• Dynamic and static concurrent modes
• IEEE 802.15.4-2011 MAC PHY
These pictures are not contractual • Supports 2 Mbits/s
• Frequency band 2402-2480 MHz
• Advertising extension
• Tx output power up to +6 dBm
• Rx sensitivity: -96 dBm (Bluetooth® Low Energy at 1 Mbps), -100 dBm
(802.15.4)
Product status link
• Range: up to 75 meters
STM32WB5MMG • Dedicated Arm® Cortex®-M0+ for radio and security tasks
• Dedicated Arm® Cortex®-M4 CPU with FPU and ART (adaptative real-time
Product summary
accelerator) up to 64 MHz speed
• 1-Mbyte Flash memory, 256-Kbyte SRAM
Order code STM32WB5MMG
• Fully integrated BOM, including 32 MHz radio and 32 KHz RTC crystals
Temperature
-40 °C to 85 °C • Integrated SMPS
range
• Ultra-low-power modes for battery longevity
Package LGA86L 7.3 × 11
• 68 GPIOs
Package 7.3 x 11 x 1.382 x • SWD, JTAG
dimensions (mm) 0.450 pitch
• Integrated IPD for best-in-class and reliable antenna matching
Packaging Tape and reel
• 1.71 V to 3.6 V VDD range
• -40 °C to 85 °C temperature range
• Built-in security features such as: secure firmware installation (SFI) for radio
stack, customer key storage/key management services, PKA, AES 256-bit,
TRNG, PCROP, CRC, 96-bit UID, possibility to derive 802.15.4 and Bluetooth®
Low Energy 48-bit UEI
• Certifications: CE, FCC, IC, JRF, SRRC, RoHS, REACH, GOST, KC, NCC
• Two-layer PCB compatibility (using external raw pins only)

Application
• Lighting and home automation
• Wireless audio devices
• Wellness, healthcare, personal trackers
• Gaming and toys
• Smart locks
• Beacons and accessories
• Industrial

DS13252 - Rev 5 - March 2023 www.st.com

For further information contact your local STMicroelectronics sales office.
 STM32WB5MMG
Introduction

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of the STM32WB5MMG
module.
This document should be read in conjunction with the Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4
with FPU, Bluetooth® 5.3 and 802.15.4 radio solution (DS11929) and Multiprotocol wireless 32-bit MCU Arm®-
based Cortex®-M4 with FPU, Bluetooth® Low Energy and 802.15.4 radio solution (RM0434). Both documents are
available from the STMicroelectronics website at www.st.com.
For information on the device errata with respect to the datasheet and reference manual, refer to the
STM32WB5MMG errata sheet (ES0525), available on the STMicroelectronics website www.st.com.
For information on the Arm® Cortex® cores, refer to the Cortex® Technical Reference Manual, available from the
www.arm.com website
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS13252 - Rev 5 page 2/39

 STM32WB5MMG
Description

2 Description

The STM32WB5MMG is an ultra-low-power and small form factor certified 2.4 GHz wireless module. It
supports Bluetooth® Low Energy 5.3, Zigbee® 3.0, OpenThread, dynamic and static concurrent modes, and
802.15.4 proprietary protocols. Based on STMicroelectronics STM32WB55VGY wireless microcontroller, the
STM32WB5MMG provides best-in-class RF performance thanks to its good receiver sensitivity and a high
output power signal. Its low-power features enable extended battery life time, small coin-cell batteries or energy
harvesting.
STM32WB5MMG revision Y is based on cut 2.1 of the STM32WB55VGY microcontroller. Revision X is based on
cut 2.2.
The STM32WB5MMG requires no RF expertise and is the best way to speed-up any development and to reduce
associated costs. The module is completely protocol stack royalty-free.

DS13252 - Rev 5 page 3/39

 STM32WB5MMG
Module overview

3 Module overview

The module is an SiP-LGA86 package (system in package land grid array) that integrates the proven
STM32WB55VGY MCU with several external components. The package includes:
• LSE crystal
• HSE crystal
• Passive components for SMPS
• Antenna matching and antenna
• IPD for RF matching and harmonics rejection

Figure 1. STM32WB5MMG module block diagram

Communication
Interfaces

SMPS STM32WB55VGY Antenna

RF IPD
passive 1MB Flash matching
components
256KB RAM

Power supply
filtering

DT63524V1
XTAL XTAL
32.774kHz 32 MHz

3.1 Versions
The STM32WB5MMG is shipped in two finished goods versions. In this datasheet they are referred to as versions
X and Y. X is the more recent version. The product version is identified by the package marking with X or Y as
shown in Section 9.3 Device marking for SiP-LGA86.

3.2 Power supply

The power supply requirements are identical to regular STM32WB55xx and described in the datasheet. Filtering
capacitors on power supply pins and components for the SMPS are already integrated into the module.
Note: An additional capacitor of 4.7 uF may be needed to eliminate ripple from the power supply. Refer to the
application note Development of RF hardware using STM32WB microcontrollers (AN5165).

3.2.1 SMPS
SMPS can be set to either ON or in BYPASS mode. The integrated passive components are for SMPS operation
running at 4MHz. For additional information on the SMPS, check the reference manual or the application note
Usage of SMPS on STM32WB Series microcontroller (AN5246).

DS13252 - Rev 5 page 4/39

 STM32WB5MMG
Clocks

3.3 Clocks
As the crystals are already integrated into the package, it is not possible to use any clock in bypass mode. The
module integrates 32.774 kHz crystal for LSE and 32 MHz crystal for the HSE clock.
• LSE must be used in medium high driving capability. (RCC_BDCR_LSEDRV[1:0] = 10, refer to
Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® Low Energy and
802.15.4 radio solution (RM0434) for more details).
• HSE is already tuned.
RCC_HSECR_HSETUNE[5:0] value is loaded automatically by HW. The RCC_HSECR register
configuration must not be changed by the user to keep the default parameters.
• LSCO and MCO outputs are available.
• HSEGMC[2:0] must be set to 0b011.

3.4 Antenna
The rectangular module has one shorter side clearly different from the remaining finish surface. This side is
unshielded and the mold cover contains the integrated antenna.
There is no option to use an external antenna.

3.5 One time programming (OTP)

The STM32WB5MMG features 1 Kbyte one time programmable (OTP) memory for use by the end product. This
is described in Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® Low Energy
and 802.15.4 radio solution (DS11929) and Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU,
Bluetooth® Low Energy and 802.15.4 radio solution (RM0434).
Note: STM32WB5MMG uses the first and last words of this area for trimming and identification purposes.
As a consequence addresses 0x1FFF7000 - 0x1FFF7007 and 0x1FFF73F8 - 0x1FFF73FF cannot be changed.

DS13252 - Rev 5 page 5/39

 STM32WB5MMG
Available peripherals

4 Available peripherals

All peripherals available in STM32WB Series microcontrollers based on the WLCSP100 package are available
and accessible on this module.
The pins on the module offer access to the following system peripherals:
• 2× DMA controllers (seven channels each) supporting ADC, SPI, I2C, USART, QSPI, SAI, AES, timers
• 1× USART (ISO 7816, IrDA, SPI master, Modbus and Smartcard mode)
• 1× LPUART (low power) – Two SPI running at 32 Mbit/s
• 2× I2C (SMBus/PMBus)
• 1× SAI (dual channel high quality audio)
• 1× USB 2.0 FS device, crystal-less, BCD and LPM
• 1× Touch sensing controller, up to 18 sensors
• 1× LCD 8x40 with step-up converter
• 1× 16-bit, four channels advanced timer
• 2× 16-bit, two channels timers
• 1× 32-bit, four channels timer
• 2× 16-bit ultra-low-power timers
• 1× independent Systick
• 1× independent watchdog
• 1× window watchdog.
The full pin description is available in Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU,
Bluetooth® 5.3 and 802.15.4 radio solution (DS11929).

DS13252 - Rev 5 page 6/39

 STM32WB5MMG
Pin description

5 Pin description

The following figure shows the module pinout package bottom view.

Figure 2. STM32WB5MMG module pinout: bottom view

ANT
VSS _NC

86 85

47 60 1

PB10 PB2 PC4 PA8 PA9 PA7 PA6 PA5 PA4 PA3 VSS ANT_IN RF_OUT VSS PA2

PB11 PA1
61
74 75 76

PC5 PA0

PD9 PD8 PD15 PH0

PB0 VREF+

73 84 77 62
PB1 VSS

PD4 VSS PD10 PH1

PE4 VDDA

PB12
72 83 78 63 PC3

PC13
PE3 PC8 PE2 PD14 PC2

PB6 PC1
71 82 79 64

PB15 NRST
PC7 PD11 PE0 PE1

PB14 PB9
70 81 80 65

PC6 PC0

PD3 PD6 PD5 PD13

PH3-
PB13
BOOT0

69 68 67 66
PD1 PB8

PC9 PD2 PD7 PD12

PD0 VBAT

VDD
VSS
USB

31 17
DT63749V2

VSS PA11 PA12 PA10 PA15 PA14 PA13 PC12 PC11 PC10 PB3 PB4 PB5 PB7 VDD

Note: PB0 and PB1 are only available for revision X parts.

DS13252 - Rev 5 page 7/39

 STM32WB5MMG
Pin description

Table 1. STM32WB5MMG pin/ball definition

Pin name
Pin name (function after reset) Pin type
STM32WB5MMG STM32WB55VGY

1 F6 PA2 I/O

2 G6 PA1 I/O

3 G7 PA0 I/O

4 H8 VREF+ S

5 J9 VSS S

6 H9 VDDA S

7 G10 PC3 I/O

8 G9 PC2 I/O

9 G8 PC1 I/O

10 F9 NRST RST

11 F10 PB9 I/O

12 F8 PC0 I/O

13 E8 PH3-BOOT0 I/O

14 F7 PB8 I/O

15 C10 VBAT S

16 F1 VSS S

17 D1 VDD S

18 D7 PB7 I/O

19 D6 PB5 I/O

20 C7 PB4 I/O

21 A9 PB3 I/O

22 A6 PC10 I/O

23 B6 PC11 I/O

24 C5 PC12 I/O

25 A5 PA13 I/O

26 A3 PA14 I/O

27 A4 PA15 I/O

28 B5 PA10 I/O

29 A2 PA12 I/O

30 A1 PA11 I/O

31 - VSS S

32 B3 VDDUSB S

33 C4 PD0 I/O

34 C3 PD1 I/O

35 C1 PB13 I/O

36 D2 PC6 I/O

37 E2 PB14 I/O

38 F3 PB15 I/O

39 F5 PB6 I/O

40 G5 PC13 I/O

41 G3 PB12 I/O

42 G1 PE4 I/O

43 H1(1)/NC(2) PB1 I/O

44 H2(1)/NC(2) PB0 I/O

45 H5 PC5 I/O

DS13252 - Rev 5 page 8/39

 STM32WB5MMG
Pin description

Pin name
Pin name (function after reset) Pin type
STM32WB5MMG STM32WB55VGY

46 J6 PB11 I/O

47 K6 PB10 I/O

48 K7 PB2 I/O

49 G4 PC4 I/O

50 J7 PA8 I/O

51 K8 PA9 I/O

52 H6 PA7 I/O

53 H7 PA6 I/O

54 K9 PA5 I/O

55 K10 PA4 I/O

56 J8 PA3 I/O

57 - VSS S

58 - ANT_IN I/O

59 - RF_OUT I/O

60 - VSS S

61 E10 PH0 I/O

62 E9 PH1 I/O

63 D8 PD14 I/O

64 B10 PE1 I/O

65 C9 PD13 I/O

66 B8 PD12 I/O

67 A8 PD7 I/O

68 A7 PD2 I/O

69 B4 PC9 I/O

70 C2 PD3 I/O

71 E3 PC7 I/O

72 G2 PE3 I/O

73 D3 PD4 I/O

74 D5 PD9 I/O

75 D4 PD8 I/O

76 E7 PD15 I/O

77 E4 PD10 I/O

78 E6 PE2 I/O

79 C8 PE0 I/O

80 B7 PD5 I/O

81 C6 PD6 I/O

82 E5 PD11 I/O

83 F4 PC8 I/O

84 - VSS S

85 - ANT_NC I/O

86 - VSS S

1. Version X
2. Version Y

DS13252 - Rev 5 page 9/39

 STM32WB5MMG
Recommendations

6 Recommendations

6.1 Pin recommendations

• ANT_IN and RF_OUT pins must be connected to GND. This module already integrates an antenna, so no
external antenna required.
• The ANT_NC is only used for soldering planarity purposes. So this pin must be soldered to an
unconnected pin on the customer board.
• PH3_BOOT0 is tied low through an internal pull-down to enable start from flash memory. However, it can
be tied high with a low resistive pull-up if required.
• A reset pull-up is already implemented in the STM32WB Series microcontrollers. The reset circuitry only
requires an external capacitor for filtering purpose (see Figure 3).

Figure 3. Reset circuit

STM32WB5MMG

8
PC2

9
PC1

10 To reset mechanism
NRST

100nF

11
PB9

12
PC0

DS13252 - Rev 5 page 10/39

 STM32WB5MMG
Layout recommendations

6.2 Layout recommendations

6.2.1 STM32WB5MMG placement

The embedded antenna manufacturer of the STM32WB5MMG recommends to place the module on the
application board as shown below.

Figure 4. STM32WB5MMG board placement

This position allows the antenna to work to its maximum performance. If it cannot be placed as recommended
above, the application board performance is be reduced. This does not, however, prevent correct operation.

6.2.2 Enclosure effects

Product casing properties must be also considered when designing an RF-enabled product as the following
generic best practices list illustrated:
• Conductive enclosure in the near field affects the impedance of the antenna, also the resonant frequency.
A metal case must not be in the near field. The threshold between near and far-field is provided in Figure 5.
• Plastic enclosures can be close to the antenna, but must not touch it. Contact between the casing and the
antenna may influence the tuning of the resonant frequency and impedance matching.
• The proximity of the human body attenuates the TX and RX signals due to a certain amount of water
content. Any contact may untune frequency and impedance matching.

Figure 5. Conductive enclosure around the antenna

DS13252 - Rev 5 page 11/39

 STM32WB5MMG
Layout recommendations

Table 2. Minimum enclosure dimensions (mm)

Impact level a b c d e

Impact threshold 46 60 27 23 17
High impact 13 24 3 8 5

Note: Impact is determined by measuring the reflection losses in the appropriate direction. In case conductive material
is present from other directions, the distances mentioned in Table 2 become larger. It means the same impact is
observed further from module.

DS13252 - Rev 5 page 12/39

 STM32WB5MMG
Layout recommendations

6.2.3 Ground plane

Here are some recommendations with respect to the ground plane design:
• Do not route any tracks to the right of the STM32WB5MMG and keep a large ground plane with the
associated ground via.
• Route the tracks down directly on the top layer or with via to the other layers.
• The ground plane must include the presence of vias (distance between two vias = 2 mm).

Figure 6. STM32WB5MMG ground plane layout

Tracks

Ground via

Ground plane

6.2.4 Sensitive GPIOs

This board contains three sensitive GPIOs as defined below:
• PB10
• PB11
• PC5
The GPIO locations are illustrated in Figure 7
When PB10, PB11 and/or PC5 are used, a 3.3 pF capacitor in a small package such as the 0201 or smaller, must
be placed as close as possible to the output pin. Also border the GPIO tracks with the ground plane.

Figure 7. Sensitive GPIO location

Superposition of Layer 1 Layer 4

four layers
Sensitive GPIO location on layer 1
Sensitive GPIO location on layer 4

6.2.5 Four layer reference board design

The reference schematics are illustrated in Figure 8 and the associated PCB layout is illustrated in Figure 9
When all the pads on the device need to be used, the mother board must be designed with four layers.

DS13252 - Rev 5 page 13/39

 Figure 8. Four layer reference board schematics for version X
DS13252 - Rev 5

1 2 3 4 5 6 7 8

PD10

PD12
PD13
PD14
PD15
PD11
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9

PH0
PH1
VDD

U1B

33
34
68
70
73
80
81
67
75
74
77
82
66
65
63
76

61
62
A U1A 4 31 A
VREF+ VSS_1
STM32WB5MMG 57
VSS_2

PD1

PD11

PD13

PH1
PD3

PD5

PD15
PD0

PD2

PD4

PD6
PD7
PD8
PD9
PD10

PD12

PD14

PH0
PA0 3 6 60
PA0 VDDA VSS_3
PA1 2 84
PA1 VSS_4
PA2 1 15 86
PA2 VBAT VSS_5
PA3 56 12 PC0 16
PA3 PC0 VSSSMPS
PA4 55 9 PC1 17
PA4 PC1 VDDSMPS
PA5 54 8 PC2 5
PA5 PC2 VSS_9
PA6 53 7 PC3
PA6 PC3
PA7 52 49 PC4 32
PA7 PC4 3V3 VDD_USB
PA8 50 45 PC5
PA8 PC5
PA9 51 36 PC6 STM32WB5MMG
PA9 PC6
PA10 28 71 PC7
PA10 PC7
USB_N 30 83 PC8
PA11 PC8
USB_P 29 69 PC9 GND
PA12 PC9
PA13 25 22 PC10
PA13 PC10
PA14 26 23 PC11
PA14 PC11
PA15 27 24 PC12 GND
PA15 PC12
40 PC13
PC13
85
ANT_NC R1
13 1K, 0.1%
PH3-BOOT0 VDD
58 10

PC5
ANT_IN NRST

PB10

PB11
59 Place as close as poosible to

1
RF_OUT

3
1
ESDALC6V1-1U2
the STM32WB5MMG pins

100nF, 50V
U4
C1 B1
PB10

PB12
PB13
PB14
PB15
PB11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9

PE0
PE1
PE2
PE3
PE4

KMR7
C7 C8 C9
B GND 3.3pF 3.3pF 3.3pF B
21

41
43

11

35
44

48

20
19
39
18
14

47
46

37
38

79
64
78
72
42

2
4
GND GND GND
2
PB10

PB12
PB13
PB14
PB15
PB11
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9

1
PE0
PE1
PE2
PE3
PE4

GND
JP6

JP3 JP4 JP5

PD1 PD0 PB8 PC0 PD9
1 2 1 2 1 2
PC6 PB13 PB9 PC1 PD8 PD15
3 4 3 4 3 4
PB15 PB14 PC2 PC3 PD4 PD10
5V_USB 5V_USB 5 6 5 6 5 6
PB12 PC13 PA0 PA1 PE2 PE3
7 8 7 8 GND 7 8
PC5 PE4 PA2 PA3 PC8 PE0
9 10 9 10 9 10
PA15 PA10 PA4 PA5 PC9 PD3
CN1 11 12 11 12 11 12
PA13 PA14 PA6 PA7 PC7 PD2
1 U2 13 14 13 14 13 14
VBUS PC11 PC12 PA9 PA8 PD6 PD11
2 D_N 1 6 USB_N 15 16 15 16 15 16
DM IO1 IO_1 PB3 PC10 PC4 PB2 PD7 PD5
USB_Micro-B receptacle

3 2 5 17 18 17 18 17 18
DP GND VBUS PB5 PB4 PB10 PB11 PH0 PD12
4 D_P 3 4 USB_P 19 20 19 20 19 20
ID IO2 IO_2 PD13 PE1
5 21 22
GND HEADER 10X2 HEADER 10X2 PD14 PH1
USBLC6-2P6 23 24
6 R5
Shield 100K HEADER 12X2
7
Shield
8
Shield
9
Shield
10 UART_RX
C EXP JP2 C
11
EXP PB6 1
2
USB_uB_105017-0001 GND
PB7 3
UART_RX
Header 3x1
GND GND GND

5V_USB 3V3 VDD

U3
LD3985M33R JP1
CR2032
Socket

1 Vin Vout 5 1 2 1
GND - + VBAT
2
3 C2 C3 3 S1
R4
INH VBAT

STM32WB5MMG
GND BYPASS 1uF, 50V 100nF, 50V CR2032-SOCKET
1K - 0.5% C4 C5 Header 3x1
2

1uF, 50V 100nF, 50V

LD1 C6
D TRUE GREEN 10nF, 50V D
GND

GND
GND
*
Title STM32WB55_MODULE_4L *
page 14/39

Number: MB1697 *
Size: A3
Revision: A *
Date: 2/9/2023 Time:9:16:08 AM Sheet 1 of 1 *

1 2 3 4 5 6 7 8
 STM32WB5MMG

Figure 9. Four layer PCB layout for version X

Layer 1 Layer 2

Layer 3 Layer 4

DS13252 - Rev 5 page 15/39

 STM32WB5MMG

6.2.6 Two layer reference board design

The reference schematics are illustrated in Figure 10. Two layer reference board schematics for version X and the
associated PCB layout is illustrated in Figure 11. Two layer PCB layout for version X
By using the first external pad ring, the mother board on which the module is soldered may be designed with only
two layers.

DS13252 - Rev 5 page 16/39

 Figure 10. Two layer reference board schematics for version X
DS13252 - Rev 5

1 2 3 4 5 6 7 8

PD10

PD12
PD13
PD14
PD15
PD11
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9

PH0
PH1
VDD

U1B

33
34
68
70
73
80
81
67
75
74
77
82
66
65
63
76

61
62
A U1A 4 31 A
VREF+ VSS_1
STM32WB5MMG 57
VSS_2

PD1

PD11

PD13

PH1
PD3

PD5

PD15
PD0

PD2

PD4

PD6
PD7
PD8
PD9
PD10

PD12

PD14

PH0
PA0 3 6 60
PA0 VDDA VSS_3
PA1 2 84
PA1 VSS_4
PA2 1 15 86
PA2 VBAT VSS_5
PA3 56 12 PC0 16
PA3 PC0 VSSSMPS
PA4 55 9 PC1 17
PA4 PC1 VDDSMPS
PA5 54 8 PC2 5
PA5 PC2 VSS_9
PA6 53 7 PC3
PA6 PC3
PA7 52 49 PC4 32
PA7 PC4 3V3 VDD_USB
PA8 50 45 PC5
PA8 PC5
PA9 51 36 PC6 STM32WB5MMG
PA9 PC6
PA10 28 71 PC7
PA10 PC7
USB_N 30 83 PC8
PA11 PC8
USB_P 29 69 PC9 GND
PA12 PC9
PA13 25 22 PC10
PA13 PC10
PA14 26 23 PC11
PA14 PC11
PA15 27 24 PC12 GND
PA15 PC12
40 PC13
PC13
85
ANT_NC R1
13 1K, 0.1%
PH3-BOOT0 VDD
58 10

PC5
ANT_IN NRST

PB10

PB11
59 Place as close as poosible to

1
RF_OUT

3
1
ESDALC6V1-1U2
the STM32WB5MMG pins

100nF, 50V
U4
C1 B1
PB10

PB12
PB13
PB14
PB15
PB11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9

PE0
PE1
PE2
PE3
PE4

KMR7
C7 C8 C9
B GND 3.3pF 3.3pF 3.3pF B
21

41
43

11

35
44

48

20
19
39
18
14

47
46

37
38

79
64
78
72
42

2
4
GND GND GND
2
PB10

PB12
PB13
PB14
PB15
PB11
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9

1
PE0
PE1
PE2
PE3
PE4

GND
JP6

JP3 JP4 JP5

PD1 PD0 PB8 PC0 PD9
1 2 1 2 1 2
PC6 PB13 PB9 PC1 PD8 PD15
3 4 3 4 3 4
PB15 PB14 PC2 PC3 PD4 PD10
5V_USB 5V_USB 5 6 5 6 5 6
PB12 PC13 PA0 PA1 PE2 PE3
7 8 7 8 GND 7 8
PC5 PE4 PA2 PA3 PC8 PE0
9 10 9 10 9 10
PA15 PA10 PA4 PA5 PC9 PD3
CN1 11 12 11 12 11 12
PA13 PA14 PA6 PA7 PC7 PD2
1 U2 13 14 13 14 13 14
VBUS PC11 PC12 PA9 PA8 PD6 PD11
2 D_N 1 6 USB_N 15 16 15 16 15 16
DM IO1 IO_1 PB3 PC10 PC4 PB2 PD7 PD5
USB_Micro-B receptacle

3 2 5 17 18 17 18 17 18
DP GND VBUS PB5 PB4 PB10 PB11 PH0 PD12
4 D_P 3 4 USB_P 19 20 19 20 19 20
ID IO2 IO_2 PD13 PE1
5 21 22
GND HEADER 10X2 HEADER 10X2 PD14 PH1
USBLC6-2P6 23 24
6 R5
Shield 100K HEADER 12X2
7
Shield
8
Shield
9
Shield
10 UART_RX
C EXP JP2 C
11
EXP PB6 1
2
USB_uB_105017-0001 GND
PB7 3
UART_RX
Header 3x1
GND GND GND

5V_USB 3V3 VDD

U3
LD3985M33R JP1
CR2032
Socket

1 Vin Vout 5 1 2 1
GND - + VBAT
2
3 C2 C3 3 S1
R4
INH VBAT

STM32WB5MMG
GND BYPASS 1uF, 50V 100nF, 50V CR2032-SOCKET
1K - 0.5% C4 C5 Header 3x1
2

1uF, 50V 100nF, 50V

LD1 C6
D TRUE GREEN 10nF, 50V D
GND

GND
GND
*
Title STM32WB55_MODULE_4L *
page 17/39

Number: MB1697 *
Size: A3
Revision: A *
Date: 2/9/2023 Time:9:16:08 AM Sheet 1 of 1 *

1 2 3 4 5 6 7 8
 STM32WB5MMG

Figure 11. Two layer PCB layout for version X

Layer 1 Layer 2

DT70109V1

DS13252 - Rev 5 page 18/39

 STM32WB5MMG
Electrical characteristics

7 Electrical characteristics

7.1 Operating conditions

Table 3. STM32WB5MMG operating conditions

Parameter Min. Typ. Max. Unit

VDD 1.71 3.3 3.6 V

Operating ambient temperature range -40 - 85 °C

Storage temperature range -40 - 125 °C

7.2 Power consumption

The power consumption is identical to the regular STM32WB55. For full details refer to Multiprotocol wireless
32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.3 and 802.15.4 radio solution (DS11929).

7.3 RF characteristics
Refer to Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.3 and 802.15.4 radio
solution (DS11929) for more details.

DS13252 - Rev 5 page 19/39

 STM32WB5MMG
Antenna radiation patterns and efficiency

7.4 Antenna radiation patterns and efficiency

The figure below illustrates the antenna field directions with the z-axis field rising vertically from the module.

Figure 12. Antenna field direction

DT70134V2
The following two figures present the radiation patterns that are taken from certification measurements.

DS13252 - Rev 5 page 20/39

 STM32WB5MMG
Antenna radiation patterns and efficiency

Figure 13. Antenna radiation patterns

XY axis

Z axis

DS13252 - Rev 5 page 21/39

 STM32WB5MMG
Thermal characteristics

8 Thermal characteristics

The thermal characteristics of the STM32WB5MMG are defined below and the constant values are given in
Table 4 where:
• ϴJA, is the junction-to-ambient thermal resistance (EIA/JESD51-2 and EIA/JESD51-6).
ϴJA represents the resistance to the heat flows from the chip to ambient air. It is an indicator of package
heat dissipation capability. Lower ϴJA, means better overall thermal performance and is calculated as
follows:
ϴJA, = (TJ - TA) / PH,
where:
– TJ = junction temperature
– TA = ambient temperature
– PH = power dissipation.
• ΨJT is the junction-to-top-center thermal characterization parameter (EIA/JESD51-2 and EIA/JESD51-6).
ΨJT is used for estimating the junction temperature by measuring TT in an actual environment and is
calculated as follows:
ΨJT = (TJ - TT) / PH
where TT = temperature at the top-center of the package.
• ϴJC is the junction-to-case thermal resistance.
ϴJC represents the resistance to the heat flows from the chip to package top case. ϴJC is important when
external heat sink is attached on package top and is calculated as follows:
ϴJC = (TJ – TC) / PH
where TC = case temperature attached with a cold plate.
• ϴJB is the junction-to-board thermal resistance (EIA/JESD51-8).
ϴJB represents the resistance to the heat flows from the chip to PCB. ϴJB is used in compact thermal
models for system-level thermal simulation and is calculated as follows:
ϴJB = (TJ – TB) / PH
where TB = board temperature with ring cold plate fixture applied.

Table 4. STM32WB5MMG thermal characteristics

Symbol TJ(°C) TT(°C) ΨJT(°C/W) ϴJA(°C/W) ϴJB(°C/W) ϴJC(°C/W)

Value 97.36 96.98 0.38 37.36 24.58 16.21

DS13252 - Rev 5 page 22/39

 STM32WB5MMG
Package information

9 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

9.1 SiP-LGA86 package information

This SiP-LGA is a 86 pin, 7.3 x 11mm, system in package land grid array package.

Figure 14. SiP-LGA86 - Outline

A
bbb C
G1 A1 CORNER
PIN A1 CORNER A1
F1
M S

(x2)b1xb1
E1 D2
G2 SPts DETAIL A
F4 G3
F2

SEATING PLANE
D (x56)b2xb3

(x24)b4xb4
D3
D1 eD
F3

G4
F3

C
(x4)b2xb2
B E SPsw
eE F2

ddd C
A E
aaa (4x)
BOTTOM VIEW TOP VIEW SIDE VIEW

H1
A2

DETAIL A
H2

1. Drawing is not to scale.

DS13252 - Rev 5 page 23/39

 STM32WB5MMG
Board design

Table 5. SiP-LGA86 - Mechanical data

Symbol Description Min Typ Max Unit

A Total thickness 1.382±0.046 mm

40±20(1)
A1 Pre-solder μm
30±20(2)
A2 - 0.150 mm
M Mold thickness 1.100
S Substrate thickness 0.242
D Body length 10925 11.000 11.075
D1 Lead pitch length 7.250
D2 - 2.563
D3 - 8.438
eD Lead pitch length 0.450
E Body width 7.225 7.300 7.375
eE Lead pitch width 0.450
b1 - 0.430
b2 - 0.350 mm
b3 - 0.300
b4 - 0.600
F1 - 0.600
F2 - 0.475
F3 - 0.900
F4 - 2.300
G1 - 0.465
G2 - 2.960
G3 - 4.800
G4 - 0.475
H1 - 0.600 mm
H2 - 0.400 mm

SPts(3) Top surface sputter 3 - 6 μm

SPsw (4)
Side wall sputter 1 - 3 μm

aaa Package edge tolerance 0.075

bbb Mold flatness 0.100 mm
ddd Coplanarity 0.100

1. Peripheral pads
2. Inner pads
3. Top surface sputter
4. Side wall sputter

9.2 Board design

For information and recommendations related to board design, landing pads, stencils and the solder reflow profile
for LGA packages, refer to Guidelines for design and board assembly of land grid array packages (AN 5886).

DS13252 - Rev 5 page 24/39

 STM32WB5MMG
Device marking for SiP-LGA86

9.3 Device marking for SiP-LGA86

The following figure gives an example of topside marking versus pin 1 position identifier location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 15. SiP-LGA86 marking example

Product
identification(1)
32WB5M
2D matrix
code
MGH6

Certification Revision
marking
WW X

Date code

DT63781V1
Pin 1 identifier

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.

DS13252 - Rev 5 page 25/39

 STM32WB5MMG
Ordering information

10 Ordering information

Example: STM32 WB 5 M M G H 6 TR

Device family
STM32 = Arm-based 32-bit
microcontroller

Product type

WB = Wireless Bluetooth®

Device subfamily
5 = STM32WB55, Die 5, full set of features

Pin count
M = 86 pins

Component type
M= module

Flash memory size

G = 1 Mbyte

Package
H = LGA 86 7.3 x 11 mm

Temperature range
6 = Industrial temperature range, –40 to 85 °C

Packing
TR = tape and reel

Note: For a list of available options (such as speed and package) or for further information on any aspect of this
device, contact your nearest ST sales office.

DS13252 - Rev 5 page 26/39

 STM32WB5MMG
Tape and reel packing

11 Tape and reel packing

The module tape and reel orientation and dimension are described in the figure below.

Figure 16. STM32WB5MMG packing drawing

DS13252 - Rev 5 page 27/39

 STM32WB5MMG
Certification

12 Certification

The STM32WB5MMG module certifications status is detailed in the table below:

Table 6. Certification status

Certification Revision Y Revision X

Bluetooth Light Energy RF-PHY X X

802.15.4 (Zigbee) RF-PHY X X
EU RED X X
USA FCC X X
Canada ISED-PCB X X
China SRRC pending Pending
Japan JRF X X
Korea KC or MSIP X X
Taiwan NCC X Pending
EU ROHS X X
EU REACH X X
Russia GOST X Pending

SRRC (China) certification is ongoing.

The following sections detail some of the module certifications from sample regions.
All certifications reports are available on STM32WB5MMG page.

12.1 BLE(RF_PHY) certification

The STM32WB5MMG module has obtained BLE RF_PHY certification.
The module is published under BLE SIG web site.

12.2 CE certification
The STM32WB5MMG module has obtained CE certification.
The module is provided with CE marking.

Figure 17. CE certification logo

DS13252 - Rev 5 page 28/39

 STM32WB5MMG
UKCA certification

12.3 UKCA certification

The STM32WB5MMG module has obtained UKCA certification.
The module is provided with UKCA marking.

Figure 18. UKCA certification logo

12.4 FCC certification

The STM32WB5MMG module complies with part 15 of the FCC Rules.
The FCC ID is YCP-STM32WB5M001 for version Y, and YCP-32WB5MMGH02 for version X.
The module label includes the corresponding FCC ID.
The operation is subject to the following two conditions:
• This device may not cause harmful interference
• This device must accept any interference received, including interference that may cause undesired
operation.
Note: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part
15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in
a residential installation.

Label requirements
If the identification number is not visible when the module is installed inside another device, then the outside of
the device into which the module is installed must also display a label referring to the enclosed module. This label
must contain the FCC ID that matches the one on the module.

RF radiation exposure statement caution

The module antenna must be installed to meet the RF exposure compliance separation distance of “20 cm” and
any additional testing and authorization processes as required.

Documentation requirements
The users manual or instruction manual for an intentional or unintentional radiator shall caution the user that
changes or modifications not expressly approved by the party responsible for compliance could void the user's
authority to operate the equipment.

Integration requirements
Co-location of this module with other transmitters that operate simultaneously are required to be evaluated using
the multi-transmitter procedures.
The host integrator must follow the integration instructions provided in this document and ensure that the
composite-system end product complies with the requirements by a technical assessment or evaluation to the
rules and to KDB Publication 996369.
The host integrator installing this module into their product must ensure that the final composite product complies
with the requirements by a technical assessment or evaluation to the rules, including the transmitter operation and
should refer to guidance in KDB 996369.

DS13252 - Rev 5 page 29/39

 STM32WB5MMG
ISED certification

12.5 ISED certification

The STM32WB5MMG module has been tested and found compliant with the ISED RSS-247 and RSS-Gen rules.
The IC ID is 8976A-STM32WB5M01 for version Y and 8976A-32WB5MMGH02 for version X .
This module contains license-exempt transmitter(s) that comply with Innovation, Science and Economic
Development Canada’s license-exempt RSS(s). Operation is subject to the following two conditions:
• This module may not cause interference
• This module must accept any interference, including interference that may cause undesired operation of
the module.
L’émetteur exempt de licence contenu dans le présent appareil est conforme aux CNR d’Innovation, Sciences
et Développement économique Canada applicables aux appareils radio exempts de licence. L’exploitation est
autorisée aux deux conditions suivantes :
• L’appareil ne doit pas produire de brouillage.
• L’appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d’en
compromettre le fonctionnement.

RF radiation exposure statement caution

This Transmitter must be installed to provide a separation distance of at least 20 cm from all persons.

12.6 JRF certification

The STM32WB5MMG is certified in Japan with certification number:
• 005-102490 for rev Y
• 217-220682 for rev X.
The JRF logo is the following:

Figure 19. JRF certification logo

DS13252 - Rev 5 page 30/39

 STM32WB5MMG
NCC certification

12.7 NCC certification

The STM32WB5MMG rev Y is certified in Taiwan with NCC certification number: CCAN20LP0740T3.

Figure 20. NCC certification logo

取得審驗證明之低功率射頻器材，非經核准，公司、商號或使用者均不得擅自變更頻率、加大功率或變更原設計之
特性及功能。
低功率射頻器材之使用不得影響飛航安全及干擾合法通信；經發現有干擾現象時，應立即停用，並改善至無干擾時
方得繼續使用。前述合法通信，指依電信管理法規定作業之無線電通信。低功率射頻器材須忍受合法通信或工業、
科學及醫療用電波輻射性電機設備之干擾。
系統廠商應於平台上標示「本內 品 內 含射頻模組：圖片 XXXyyyLPDzzzz-x」字樣
For low-power radio frequency equipment that has obtained certification, companies, firms or users are not
allowed to change the frequency, increase the power, or change the characteristics and functions of the original
design without approval. The use of low-power radio-frequency equipment must not affect flight safety and
interfere with legal communications; if any interference is found, it should be stopped immediately, and it can
only be used after improvement to no interference. The aforementioned legal communication refers to radio
communication operated in accordance with the provisions of the Telecommunications Management Act. Low-
power radio frequency equipment must endure the interference of legal communication or industrial, scientific and
medical radio wave radiation electrical equipment. System manufacturers should mark the words "This product
contains a radio frequency module: XXXyyyLPDzzzz-x" on the platform.

12.8 SRRC certification

The Chinese SRRC certification is ongoing.
Note: CMIIT ID is temporarily replaced with 32WBCERTIF. This code is updated with the code assigned by the China
Ministry of Industry and Information Technology after SRRC certification is completed.

12.9 KC certification
Applicant : STMicroelectronics SAS
Equipment Name: 특정소출력 무선기기(무선데이터통신시스템용 무선기기)
Basic Model Number: STM32WB5MMGH
Certification No.: R-R-2AS-32WB5MMGH002
Manufacturer / Country of Origin: STMicroelectronics SAS / France
Date of manufacture: notation separately

DS13252 - Rev 5 page 31/39

 STM32WB5MMG
Important security notice

13 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security, which is why the
ST product(s) identified in this documentation may be certified by various security certification bodies and/or
may implement our own security measures as set forth herein. However, no level of security certification and/or
built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the
customer needs both in relation to the ST product alone, as well as when combined with other components and/or
software for the customer end product or application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such as Platform
Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms
(www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received
security certification along with the level and current status of such certification, either visit the relevant
certification standards website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can change from time to
time, customers should re-check security certification status/level as needed. If an ST product is not shown
to be certified under a particular security standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST
products. These certification bodies are therefore independently responsible for granting or revoking
security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations,
assessments, testing, or other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard
technologies which may be used in conjunction with an ST product are based on standards which were not
developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open
technologies or for any methods which have been or may be developed to bypass, decrypt or crack such
algorithms or technologies.
• While robust security testing may be done, no level of certification can absolutely guarantee protections
against all attacks, including, for example, against advanced attacks which have not been tested for,
against new or unidentified forms of attack, or against any form of attack when using an ST product outside
of its specification or intended use, or in conjunction with other components or software which are used
by customer to create their end product or application. ST is not responsible for resistance against such
attacks. As such, regardless of the incorporated security features and/or any information or support that
may be provided by ST, each customer is solely responsible for determining if the level of attacks tested
for meets their needs, both in relation to the ST product alone and when incorporated into a customer end
product or application.
• All security features of ST products (inclusive of any hardware, software, documentation, and the
like), including but not limited to any enhanced security features added by ST, are provided on an
"AS IS" BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS
ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

DS13252 - Rev 5 page 32/39

 STM32WB5MMG

Revision history
Table 7. Document revision history

Date Revision Changes

12-Nov-2020 1 Initial release.

Added:
• Power supply
• SMPS
• Clocks
• Antenna
• Two layer reference board design
• BLE(RF_PHY) certification
Updated:
• Features
16-Jul-2021 2
• Figure 1. STM32WB5MMG module block diagram
• Section 3.3 Clocks
• Section 5 Pin description
• STM32WB5MMG pin/ball definition
• Section 6.2.2 Enclosure effects
• Figure 8. Four layer reference board schematics
• Section 7.4 Antenna radiation patterns and efficiency
• Section 9.1 SiP-LGA86 package information
• Section 12 Certification
• Section 12.1 BLE(RF_PHY) certification
Added:
• Section 3.1 Versions
• Section 3.5 One time programming (OTP)
• Figure 8. Four layer reference board schematics for version X
• Figure 9. Four layer PCB layout for version X
• Figure 10. Two layer reference board schematics for version X
• Figure 11. Two layer PCB layout for version X
• Section 12.3 UKCA certification
• Section 12.9 KC certification
• Section 13 Important security notice
Updated:
• Cerfication images
• Bluetooth Bluetooth® Low Energy protocol version support throughout the
document
• Document title
• Section Features
09-Nov-2022 3
• Certification logo representation
• Section 1 Introduction
• Section 2 Description
• Split Section 3 Module overview into a separate section
• Section 3.1 Versions
• Figure 1. STM32WB5MMG module block diagram
• Section 3.2.1 SMPS
• Section 3.3 Clocks
• Section 5 Pin description
• Table 1. STM32WB5MMG pin/ball definition
• Section 6.1 Pin recommendations
• Section 6.2.4 Sensitive GPIOs
• Table 5. SiP-LGA86 - Mechanical data
• Figure 8. Four layer reference board schematics for version Y
• Figure 10. Four layer PCB layout for version Y
• Figure 12. Two layer reference board schematics for version Y
• Figure 14. Two layer PCB layout for version Y

DS13252 - Rev 5 page 33/39

 STM32WB5MMG

Date Revision Changes

• Section 9.3 Device marking for SiP-LGA86

– Section 9.1 SiP-LGA86 package information
– Table 5. SiP-LGA86 - Mechanical data
• Section 9.3 Device marking for SiP-LGA86
– Figure 15. SiP-LGA86 marking example
• Figure 15. SiP-LGA86 marking example
09-Nov-2022 3 • Section 8 Thermal characteristics
• Section 12 Certification
• Section 12.4 FCC certification
• Section 12.5 ISED certification
• Section 12.6 JRF certification
• Section 12.7 NCC certification
Removed: Solder reflow recommendations section
Updated:
• Product status
• Figure 1. STM32WB5MMG module block diagram
• Section 5 Pin description
– Figure 2. STM32WB5MMG module pinout: bottom view
• Section 6.1 Pin recommendations
• Section 6.2.5 Four layer reference board design
– Figure 8. Four layer reference board schematics for version X
• Section 6.2.6 Two layer reference board design
01-Mar-2023 4
– Figure 10. Two layer reference board schematics for version X
• Section 7.4 Antenna radiation patterns and efficiency
– Added Figure 13. Antenna radiation patterns
• Section 9.2 Board design
Removed:
• "Four layer reference board schematics for version Y" figure
• "Four layer PCB layout for version Y" figure
• "Two layer reference board schematics for version Y" figure
• "Two layer PCB layout for version Y" figure
Updated:
• Figure 11. Two layer PCB layout for version X
10-Mar-2023 5
• Section 3.2 Power supply
• Section 5 Pin description

DS13252 - Rev 5 page 34/39

 STM32WB5MMG
Contents

Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3 Module overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3.1 Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.1 SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.3 Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.4 Antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.5 One time programming (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Available peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
6 Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6.1 Pin recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.2 Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.2.1 STM32WB5MMG placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.2.2 Enclosure effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.2.3 Ground plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.2.4 Sensitive GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.2.5 Four layer reference board design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.2.6 Two layer reference board design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3 RF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.4 Antenna radiation patterns and efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
9 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
9.1 SiP-LGA86 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.2 Board design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.3 Device marking for SiP-LGA86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
11 Tape and reel packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
12 Certification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
12.1 BLE(RF_PHY) certification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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 STM32WB5MMG
Contents

12.2 CE certification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.3 UKCA certification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12.4 FCC certification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12.5 ISED certification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12.6 JRF certification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12.7 NCC certification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
12.8 SRRC certification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
12.9 KC certification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

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 STM32WB5MMG
List of tables

List of tables
Table 1. STM32WB5MMG pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Minimum enclosure dimensions (mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. STM32WB5MMG operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. STM32WB5MMG thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. SiP-LGA86 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 6. Certification status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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 STM32WB5MMG
List of figures

List of figures
Figure 1. STM32WB5MMG module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. STM32WB5MMG module pinout: bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. STM32WB5MMG board placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Conductive enclosure around the antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. STM32WB5MMG ground plane layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Sensitive GPIO location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Four layer reference board schematics for version X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Four layer PCB layout for version X. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Two layer reference board schematics for version X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Two layer PCB layout for version X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Antenna field direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. Antenna radiation patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. SiP-LGA86 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 15. SiP-LGA86 marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 16. STM32WB5MMG packing drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17. CE certification logo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 18. UKCA certification logo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19. JRF certification logo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 20. NCC certification logo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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 STM32WB5MMG

IMPORTANT NOTICE – READ CAREFULLY

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