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a SHARC® Processor
Preliminary Technical Data ADSP-21369
SUMMARY
High performance 32-bit/40-bit floating point processor The ADSP-21369 is available with a 400 MHz core instruction
optimized for high performance audio processing rate with unique audio centric peripherals such as the Digi-
tal Audio Interface, S/PDIF transceiver, serial ports, 8-
Single-Instruction Multiple-Data (SIMD) computational
channel asynchronous sample rate converter, precision
architecture
clock generators and more. For complete ordering infor-
On-chip memory—2M bit of on-chip SRAM and 6M bit of on-
mation, see Ordering Guide on Page 52
chip mask programmable ROM
Code compatible with all other members of the SHARC family

CORE PRO CESSOR

4 BLOCKS O F
INSTRUCTION ON-CHIP MEMORY JTAG TEST & EMULATION
TIMER CACHE
32 X 48-BI T
2M BIT RAM,
6M BIT ROM (*Reserved)
FLAGS4-15
DAG 1 DAG2
PROGRAM ADDR DATA
8X4X32 8X4X32 PWM
SEQUENCER
32
EXTERNAL PORT
8 DATA

CO NTRO L PINS
P M A D D RE SS BU S 32 SDRAM
CONTROLLER 11
DM A DD R ES S B U S 32

ASYNCHRONOUS 3 CONTROL
PM DA TA B U S 64
MEMORY
INTERFACE 24

D M D A TA B U S 64 IOA(24) I OD(32) ADDRESS

PROCESSING PROCESSING PX REGISTER IOP REGISTER (MEMORY MAPPED) DMA

ELEMENT ELEMENT CONTROLLER
CONTRO L, STATUS, & DATA BUFFERS
(PEX) (PEY) 3 4 C H A N NE LS MEMORY-TO-
MEMORY DMA (2)

PRECISION CLOCK
DAI RO UTI NG UNIT

DPI ROUTING UNIT

SERIAL PORTS (8) SPI PORT (2)

GENERATORS (4)
4 UART (2)
GPIO FLAGS/
IRQ/TIMEXP SRC (8 CHANNELS) INPUT DATA POR T/ T WO WIRE
PDAP INTERFACE
TIMERS (3)

S
SPDIF (RX/TX) DAI PINS DPI PINS

DIGITAL AUDIO INTERFACE DIGITAL PERIP HERAL INTE RFACE

I/O PROCESSOR
20 14

*THE ADSP-21369 PROCESSOR INCLUDES A CUSTOMER-DEFINABLE ROM BLOCK.

PLEASE CONTACT YOUR ANALOG DEVICES SALES REPRESENTATIVE FOR ADDI TIONAL DETAILS

Figure 1. Functional Block Diagram

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Rev. PrB
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ADSP-21369 Preliminary Technical Data
KEY FEATURES – PROCESSOR CORE Up to 16 TDM stream support, each with 128 channels per
frame
At 400 MHz (2.5 ns) core instruction rate, the ADSP-21369
Companding selection on a per channel basis in TDM mode
performs 2.4 GFLOPS/800 MMACS
Input data port, configurable as eight channels of serial data
2M bit on-chip, SRAM (0.75M Bit in blocks 0 and 1, and 250K
or seven channels of serial data and up to a 20-bit wide
bit in blocks 2 and 3) for simultaneous access by the core
parallel data channel
processor and DMA
Signal routing unit provides configurable and flexible con-
6M bit on-chip, mask-programmable, ROM (3M bit in block 0
nections between all DAI/DPI components
and 3M bit in block 1)
2 Muxed Flag/IRQ lines
Dual data address generators (DAGs) with modulo and bit-
reverse addressing 1 Muxed Flag/Timer expired line /MS pin
Zero-overhead looping with single-cycle loop setup, provid- 1 Muxed Flag/IRQ /MS pin
ing efficient program sequencing DEDICATED AUDIO COMPONENTS
Single Instruction Multiple Data (SIMD) architecture
provides: S/PDIF Compatible Digital Audio receiver/transmitter sup-
Two computational processing elements ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
Concurrent execution Left-justified, I2S or right-justified serial data input with
16, 18, 20 or 24-bit word widths (transmitter)
Code compatibility with other SHARC family members at
the assembly level Four independent Asynchronous Sample Rate Converters
(SRC). Each converter has separate serial input and output
Parallelism in buses and computational units allows: Sin-
ports, a deemphasis filter providing up to -128dB SNR per-
gle cycle executions (with or without SIMD) of a multiply
formance, stereo sample rate converter (SRC) and supports
operation, an ALU operation, a dual memory read or
left-justified, I2S, TDM and right-justified modes and 24,
write, and an instruction fetch
20, 18 and 16 audio data word lengths.
Transfers between memory and core at a sustained 6.4G
Pulse Width Modulation provides:
bytes/s bandwidth at 400 MHz core instruction rate
16 PWM outputs configured as four groups of four outputs
INPUT/OUTPUT FEATURES supports center-aligned or edge-aligned PWM waveforms
ROM Based Security features include:
DMA controller supports:
JTAG access to memory permitted with a 64-bit key
34 zero-overhead DMA channels for transfers between
ADSP-21369 internal memory and a variety of Protected memory regions that can be assigned to limit
peripherals access under program control to sensitive code
32-bit DMA transfers at peripheral clock speed, in parallel PLL has a wide variety of software and hardware multi-
with full-speed processor execution plier/divider ratios
32-Bit wide external port provides glueless connection to Dual voltage: 3.3 V I/O, 1.3 V core
both synchronous (SDRAM) and asynchronous memory Available in 256-ball SBGA and 208-lead MQFP Packages (see
devices Ordering Guide on Page 52)
Programmable wait state options: 2 to 31 SCLK cycles
Delay-line DMA engine maintains circular buffers in exter-
nal memory with tap/offset based reads
SDRAM accesses at 166MHz and asynchronous accesses at
66MHz
4 memory select lines allows multiple external memory
devices
Digital audio interface (DAI) includes eight serial ports, four
precision clock generators, an input data port, an S/PDIF
transceiver, an 8-channel asynchronous sample rate con-
verter, and a signal routing unit
Digital peripheral interface (DPI) includes, three timers, two
UARTs, two SPI ports, and a two wire interface port
Outputs of PCG's C and D can be driven on to DPI pins
Eight dual data line serial ports that operate at up to 50M
bits/s on each data line — each has a clock, frame sync and
two data lines that can be configured as either a receiver or
transmitter pair
TDM support for telecommunications interfaces including
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
Preliminary Technical Data ADSP-21369
TABLE OF CONTENTS
Summary ................................................................1
Key Features – Processor Core ..................................2
Input/Output Features ............................................2
Dedicated Audio Components ..................................2
General Description ..................................................4
ADSP-21369 Family Core Architecture .......................4
ADSP-21369 Memory .............................................5
External Memory ...................................................5
ADSP-21369 Input/Output Features ...........................7
System Design .......................................................9
Development Tools .............................................. 10
Pin Function Descriptions ........................................ 12
Data Modes ........................................................ 15
Boot Modes ........................................................ 15
Core Instruction Rate to CLKIN Ratio Modes ............. 15
ADSP-21369 Specifications ....................................... 16
Recommended Operating Conditions ....................... 16
Electrical Characteristics ........................................ 16
Absolute Maximum Ratings ................................... 17
Maximum Power Dissipation ................................. 17
ESD Sensitivity .................................................... 17
Timing Specifications ........................................... 17
Output Drive Currents .......................................... 46
Test Conditions ................................................... 46
Thermal Characteristics ........................................ 46
Capacitive Loading ............................................... 46
256-Ball SBGA Pinout .............................................. 48
208-Lead MQFP Pinout ............................................ 50
Package Dimensions ................................................ 51
Ordering Guide ...................................................... 52

REVISION HISTORY
6/05–Data sheet changed from REV. PrA to REV. PrB
This revision corrects the pin assignments on the SBGA Ball
Grid Array package. Pin V13 is now correctly identified as
IOVDD, and pin V14 is GND. See Table 43 on page 48.
ADSP-21369 Preliminary Technical Data
GENERAL DESCRIPTION
The ADSP-21369 SHARC processor is a members of the SIMD • On-Chip mask-programmable ROM (6M bit)
SHARC family of DSPs that feature Analog Devices' Super Har- • JTAG test access port
vard Architecture. The ADSP-21369 is source code compatible
with the ADSP-2126x, and ADSP-2116x, DSPs as well as with The block diagram of the ADSP-21369 on Page 1 also illustrates
first generation ADSP-2106x SHARC processors in SISD (Sin- the following architectural features:
gle-Instruction, Single-Data) mode. The ADSP-21369 is a 32- • DMA controller
bit/40-bit floating point processors optimized for high perfor-
• Eight full duplex serial ports
mance automotive audio applications with its large on-chip
SRAM, and mask-programmable ROM, multiple internal buses • Digital audio interface that includes four precision clock
to eliminate I/O bottlenecks, and an innovative Digital Audio generators (PCG), an input data port (IDP), an S/PDIF
Interface (DAI). receiver/transmitter, eight channels asynchronous sample
rate converters, eight serial ports, eight serial interfaces, a
As shown in the functional block diagram on Page 1, the
16-bit parallel input port (PDAP), a flexible signal routing
ADSP-21369 uses two computational units to deliver a signifi-
unit (DAI SRU).
cant performance increase over the previous SHARC processors
on a range of DSP algorithms. Fabricated in a state-of-the-art, • Digital peripheral interface that includes three timers, an
high speed, CMOS process, the ADSP-21369 processor achieves I2C interface, two UARTs, two serial peripheral interfaces
an instruction cycle time of 2.5 ns at 400 MHz. With its SIMD (SPI), and a flexible signal routing unit (DPI SRU).
computational hardware, the ADSP-21369 can perform 2.4
GFLOPS running at 400 MHz.
ADSP-21369 FAMILY CORE ARCHITECTURE
Table 1 shows performance benchmarks for the ADSP-21369. The ADSP-21369 is code compatible at the assembly level with
the ADSP-2126x, ADSP-21160 and ADSP-21161, and with the
Table 1. ADSP-21369 Benchmarks (at 400 MHz) first generation ADSP-2106x SHARC processors. The ADSP-
21369 shares architectural features with the ADSP-2126x and
Benchmark Algorithm Speed ADSP-2116x SIMD SHARC processors, as detailed in the fol-
(at 400 MHz) lowing sections.
1024 Point Complex FFT (Radix 4, with reversal) 23.25 µs SIMD Computational Engine
FIR Filter (per tap)1 1.25 ns
1 The ADSP-21369 contains two computational processing ele-
IIR Filter (per biquad) 5.0 ns ments that operate as a Single-Instruction Multiple-Data
Matrix Multiply (pipelined) (SIMD) engine. The processing elements are referred to as PEX
[3x3] × [3x1] 11.25 ns and PEY and each contains an ALU, multiplier, shifter and reg-
[4x4] × [4x1] 20.0 ns ister file. PEX is always active, and PEY may be enabled by
Divide (y/×) 8.75 ns setting the PEYEN mode bit in the MODE1 register. When this
Inverse Square Root 13.5 ns mode is enabled, the same instruction is executed in both pro-
1 cessing elements, but each processing element operates on
Assumes two files in multichannel SIMD mode
different data. This architecture is efficient at executing math
intensive DSP algorithms.
The ADSP-21369 continues SHARC’s industry leading stan-
dards of integration for DSPs, combining a high performance Entering SIMD mode also has an effect on the way data is trans-
32-bit DSP core with integrated, on-chip system features. ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
The block diagram of the ADSP-21369 on Page 1, illustrates the computational operation in the processing elements. Because of
following architectural features: this requirement, entering SIMD mode also doubles the band-
• Two processing elements, each of which comprises an width between memory and the processing elements. When
ALU, Multiplier, Shifter and Data Register File using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
• Data Address Generators (DAG1, DAG2)
• Program sequencer with instruction cache Independent, Parallel Computation Units
• PM and DM buses capable of supporting four 32-bit data Within each processing element is a set of computational units.
transfers between memory and the core at every core pro- The computational units consist of an arithmetic/logic unit
cessor cycle (ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
• Three Programmable Interval Timers with PWM Genera-
element are arranged in parallel, maximizing computational
tion, PWM Capture/Pulse width Measurement, and
throughput. Single multifunction instructions execute parallel
External Event Counter Capabilities
ALU and multiplier operations. In SIMD mode, the parallel
• On-Chip SRAM (2M bit) ALU and multiplier operations occur in both processing ele-
Preliminary Technical Data ADSP-21369
ments. These computation units support IEEE 32-bit single- On-Chip Memory
precision floating-point, 40-bit extended precision floating-
The ADSP-21369 contains two megabits of internal RAM and
point, and 32-bit fixed-point data formats.
six megabits of internal mask-programmable ROM. Each block
Data Register File can be configured for different combinations of code and data
storage (see Table 2). Each memory block supports single-cycle,
A general-purpose data register file is contained in each pro- independent accesses by the core processor and I/O processor.
cessing element. The register files transfer data between the The ADSP-21369 memory architecture, in combination with its
computation units and the data buses, and store intermediate separate on-chip buses, allow two data transfers from the core
results. These 10-port, 32-register (16 primary, 16 secondary) and one from the I/O processor, in a single cycle.
register files, combined with the ADSP-2136x enhanced Har-
vard architecture, allow unconstrained data flow between The ADSP-21369’s, SRAM can be configured as a maximum of
computation units and internal memory. The registers in PEX 64K words of 32-bit data, 128K words of 16-bit data, 42K words
are referred to as R0-R15 and in PEY as S0-S15. of 48-bit instructions (or 40-bit data), or combinations of differ-
ent word sizes up to two megabits. All of the memory can be
Single-Cycle Fetch of Instruction and Four Operands accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-
The ADSP-21369 features an enhanced Harvard architecture in ing-point storage format is supported that effectively doubles
which the data memory (DM) bus transfers data and the pro- the amount of data that may be stored on-chip. Conversion
gram memory (PM) bus transfers both instructions and data between the 32-bit floating-point and 16-bit floating-point for-
(see Figure 1 on page 1). With the ADSP-21369’s separate pro- mats is performed in a single instruction. While each memory
gram and data memory buses and on-chip instruction cache, block can store combinations of code and data, accesses are
the processor can simultaneously fetch four operands (two over most efficient when one block stores data using the DM bus for
each data bus) and one instruction (from the cache), all in a sin- transfers, and the other block stores instructions and data using
gle cycle. the PM bus for transfers.
Using the DM bus and PM buses, with one bus dedicated to
Instruction Cache each memory block, assures single-cycle execution with two
The ADSP-21369 includes an on-chip instruction cache that data transfers. In this case, the instruction must be available in
enables three-bus operation for fetching an instruction and four the cache.
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This EXTERNAL MEMORY
cache allows full-speed execution of core, looped operations The External Port on the ADSP-21369 SHARC provides a high
such as digital filter multiply-accumulates, and FFT butterfly performance, glueless interface to a wide variety of industry-
processing. standard memory devices. The 32-bit wide bus may be used to
interface to synchronous and/or asynchronous memory devices
Data Address Generators With Zero-Overhead Hardware through the use of it's separate internal memory controllers: the
Circular Buffer Support first is an SDRAM controller for connection of industry-stan-
The ADSP-21369’s two data address generators (DAGs) are dard synchronous DRAM devices and DIMMs (Dual Inline
used for indirect addressing and implementing circular data Memory Module), while the second is an asynchronous mem-
buffers in hardware. Circular buffers allow efficient program- ory controller intended to interface to a variety of memory
ming of delay lines and other data structures required in digital devices. Four memory select pins enable up to four separate
signal processing, and are commonly used in digital filters and devices to coexist, supporting any desired combination of syn-
Fourier transforms. The two DAGs of the ADSP-21369 contain chronous and asynchronous device types. Non SDRAM
sufficient registers to allow the creation of up to 32 circular buff- external memory address space is shown in Table 3.
ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over- SDRAM Controller
head, increase performance, and simplify implementation. The SDRAM controller provides an interface to up to four sepa-
Circular buffers can start and end at any memory location. rate banks of industry-standard SDRAM devices or DIMMs, at
speeds up to fSCLK. Fully compliant with the SDRAM standard,
Flexible Instruction Set each bank can has it's own memory select line (MS0–MS3), and
The 48-bit instruction word accommodates a variety of parallel can be configured to contain between 16M bytes and
operations, for concise programming. For example, the 128M bytes of memory. SDRAM external memory address
ADSP-21369 can conditionally execute a multiply, an add, and a space is shown in Table 4.
subtract in both processing elements while branching and fetch- The controller maintains all of the banks as a contiguous
ing up to four 32-bit values from memory—all in a single address space so that the processor sees this as a single address
instruction. space, even if different size devices are used in the different
banks.
ADSP-21369 MEMORY
The ADSP-21369 adds the following architectural features to
the SIMD SHARC family core.
ADSP-21369 Preliminary Technical Data
Table 2. ADSP-21369 Internal Memory Space 1

IOP Registers 0x0000 0000–0x0003 FFFF

Long Word (64 bits) Extended Precision Normal or Normal Word (32 bits) Short Word (16 bits)
Instruction Word (48 bits)
BLOCK 0 ROM (Reserved) BLOCK 0 ROM (Reserved) BLOCK 0 ROM (Reserved) BLOCK 0 ROM (Reserved)
0x0004 0000–0x0004 BFFF 0x0008 0000–0x0008 FFFF 0x0008 0000–0x0009 7FFF 0x0010 0000–0x0012 FFFF
Reserved Reserved Reserved Reserved
0x0004 F000–0x0004 FFFF 0x0009 4000–0x0009 FFFF 0x0009 E0000–0x0009 FFFF 0x0013 C000–0x0013 FFFF
BLOCK 0 RAM BLOCK 0 RAM BLOCK 0 RAM BLOCK 0 RAM
0x0004 C000–0x0004 EFFF 0x0009 0000–0x0009 3FFF 0x0009 8000–0x0009 DFFF 0x0013 0000–0x0013 BFFF
BLOCK 1 ROM (Reserved) BLOCK 1 ROM (Reserved) BLOCK 1 ROM (Reserved) BLOCK 1 ROM (Reserved)
0x0005 0000–0x0005 BFFF 0x000A 0000–0x000A FFFF 0x000A 0000–0x000B 7FFF 0x0014 0000–0x0016 FFFF
Reserved Reserved Reserved Reserved
0x0005 F000–0x0005 FFFF 0x000B 4000–0x000B FFFF 0x000B E000–0x000B FFFF 0x0017 C000–0x0017 FFFF
BLOCK 1 RAM BLOCK 1 RAM BLOCK 1 RAM BLOCK 1 RAM
0x0005 C000–0x0005 EFFF 0x000B 0000–0x000B 3FFF 0x000B 8000–0x000B DFFF 0x0017 0000–0x0017 BFFF
BLOCK 2 RAM BLOCK 2 RAM BLOCK 2 RAM BLOCK 2 RAM
0x0006 0000–0x0006 0FFF 0x000C 0000–0x000C 1554 0x000C 0000–0x000C 1FFF 0x0018 0000–0x0018 3FFF
Reserved Reserved Reserved Reserved
0x0006 1000–0x0006 FFFF 0x000C 1555–0x000D FFFF 0x000C 2000–0x000D FFFF 0x0018 4000–0x001B FFFF
BLOCK 3 RAM BLOCK 3 RAM BLOCK 3 RAM BLOCK 3 RAM
0x0007 0000–0x0007 0FFF 0x000E 0000–0x000E 1554 0x000E 0000–0x000E 1FFF 0x001C 0000–0x001C 3FFF
Reserved Reserved Reserved Reserved
0x0007 1000–0x0007 FFFF 0x000E 1555–0x000F FFFF 0x000E 2000–0x000F FFFF 0x001C 4000–0x001F FFFF
1
The ADSP-21369 processor includes a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details.

Table 3. External Memory for Non SDRAM Addresses Table 4. External Memory for SDRAM Addresses

Bank Size in Address Range Bank Size in Address Range

words words
Bank 0 12M 0x0020 0000 – 0x00FF FFFF Bank 0 60M 0x0020 0000 – 0x03FF FFFF
Bank 1 16M 0x0400 0000 – 0x04FF FFFF Bank 1 64M 0x0400 0000 – 0x07FF FFFF
Bank 2 16M 0x0800 0000 – 0x08FF FFFF Bank 2 64M 0x0800 0000 – 0x0BFF FFFF
Bank 3 16M 0x0C00 0000 – 0x0CFF FFFF Bank 3 64M 0x0C00 0000 – 0x0FFF FFFF

A set of programmable timing parameters is available to config- Asynchronous Controller

ure the SDRAM banks to support slower memory devices. The
The asynchronous memory controller provides a configurable
memory banks can be configured as either 32 bits wide for max-
interface for up to four separate banks of memory or I/O
imum performance and bandwidth or 16 bits wide for
devices. Each bank can be independently programmed with dif-
minimum device count and lower system cost.
ferent timing parameters, enabling connection to a wide variety
The SDRAM controller address, data, clock, and command pins of memory devices including SRAM, ROM, flash, and EPROM,
can drive loads up to 30 pF. For larger memory systems, the as well as I/O devices that interface with standard memory con-
SDRAM controller external buffer timing should be selected trol lines. Bank0 occupies a 14.7M word window and banks 1, 2,
and external buffering should be provided so that the load on and 3 occupy a 16M word window in the processor’s address
the SDRAM controller pins does not exceed 30 pF. space but, if not fully populated, these windows are not made
contiguous by the memory controller logic. The banks can also
be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of
interfacing to a range of memories and I/O devices tailored
either to high performance or to low cost and power.
Preliminary Technical Data ADSP-21369
The asynchronous memory controller is capable of a maximum The SRU is a matrix routing unit (or group of multiplexers) that
throughput of 267M bytes/sec using a 66MHz external bus enables the peripherals provided by the DAI to be intercon-
speed. Other features include 8 to 32-bit and 16 to 32-bit pack- nected under software control. This allows easy use of the DAI
ing and unpacking, booting from Bank Select 1, and support for associated peripherals for a much wider variety of applications
delay line DMA. by using a larger set of algorithms than is possible with non con-
figurable signal paths.
ADSP-21369 INPUT/OUTPUT FEATURES
The DAI also includes eight serial ports, an S/PDIF
The ADSP-21369 I/O processor provides 34 channels of DMA, receiver/transmitter, four precision clock generators (PCG),
as well as an extensive set of peripherals. These include a 20 pin eight channels of synchronous sample rate converters, and an
Digital Audio Interface which controls: input data port (IDP). The IDP provides an additional input
• Eight serial ports path to the ADSP-21369 core, configurable as either eight chan-
nels of I2S serial data or as seven channels plus a single 20-bit
• S/PDIF Receiver/Transmitter
wide synchronous parallel data acquisition port. Each data
• Four precision clock generators channel has its own DMA channel that is independent from the
• Four stereo sample rate converters ADSP-21369's serial ports.
• Internal data port/parallel data acquisition port For complete information on using the DAI, see the ADSP-
2136x SHARC Processor Hardware Reference for the ADSP-
The ADSP-21369 processor also contains a 14 pin Digital 21367/8/9 Processors.
Peripheral Interface which controls:
• Three general-purpose timers Serial Ports
• Two Serial Peripheral Interfaces The ADSP-21369 features eight synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
• Two universal asynchronous receiver/transmitters mixed-signal peripheral devices such as Analog devices AD183x
(UARTs) family of audio codecs, ADCs, and DACs. The serial ports are
• A two wire interface/I2C made up of two data lines, a clock and frame sync. The data
lines can be programmed to either transmit or receive and each
DMA Controller data line has a dedicated DMA channel.
The ADSP-21369’s on-chip DMA controller allows data trans- Serial ports are enabled via 16 programmable and simultaneous
fers without processor intervention. The DMA controller receive or transmit pins that support up to 32 transmit or 32
operates independently and invisibly to the processor core, receive channels of audio data when all eight SPORTS are
allowing DMA operations to occur while the core is simulta- enabled, or eight full duplex TDM streams of 128 channels per
neously executing its program instructions. DMA transfers can frame.
occur between the ADSP-21369’s internal memory and its serial
ports, the SPI-compatible (Serial Peripheral Interface) ports, the The serial ports operate at a maximum data rate of 50M bits/s.
IDP (Input Data Port), the Parallel Data Acquisition Port Serial port data can be automatically transferred to and from
(PDAP) or the UART. Thirty-four channels of DMA are avail- on-chip memory via dedicated DMA channels. Each of the
able on the ADSP-21369—sixteen via the serial ports, eight via serial ports can work in conjunction with another serial port to
the Input Data Port, four for the UARTs, two for the SPI inter- provide TDM support. One SPORT provides two transmit sig-
face, two for the external port, and two for memory-to-memory nals while the other SPORT provides the two receive signals.
transfers. Programs can be downloaded to the ADSP-21369 The frame sync and clock are shared.
using DMA transfers. Other DMA features include interrupt Serial ports operate in five modes:
generation upon completion of DMA transfers, and DMA • Standard DSP serial mode
chaining for automatic linked DMA transfers.
• Multichannel (TDM) mode with support for Packed I2S
Delay Line DMA mode
The ADSP-21369 processor provides Delay Line DMA func- • I2S mode
tionality. This allows processor reads and writes to external
• Packed I2S mode
Delay Line Buffers (and hence to external memory) with limited
core interaction. • Left-justified sample pair mode
Left-justified sample pair mode is a mode where in each frame
Digital Audio Interface (DAI)
sync cycle two samples of data are transmitted/received—one
The Digital Audio Interface (DAI) provides the ability to con- sample on the high segment of the frame sync, the other on the
nect various peripherals to any of the DSPs DAI pins low segment of the frame sync. Programs have control over var-
(DAI_P20–1). ious attributes of this mode.
Programs make these connections using the Signal Routing Each of the serial ports supports the left-justified sample pair
Unit (SRU, shown in Figure 1. and I2S protocols (I2S is an industry standard interface com-
monly used by audio codecs, ADCs and DACs such as the
ADSP-21369 Preliminary Technical Data
Analog Devices AD183x family), with two data pins, allowing device. The ADSP-21369 SPI compatible peripheral implemen-
four left-justified sample pair or I2S channels (using two stereo tation also features programmable baud rate and clock phase
devices) per serial port, with a maximum of up to 32 I2S chan- and polarities. The ADSP-21369 SPI compatible port uses open
nels. The serial ports permit little-endian or big-endian drain drivers to support a multimaster configuration and to
transmission formats and word lengths selectable from 3 bits to avoid data contention.
32 bits. For the left-justified sample pair and I2S modes, data-
word lengths are selectable between 8 bits and 32 bits. Serial UART Port
ports offer selectable synchronization and transmit modes as The ADSP-21369 processor provides a full-duplex Universal
well as optional µ-law or A-law companding selection on a per Asynchronous Receiver/Transmitter (UART) port, which is
channel basis. Serial port clocks and frame syncs can be inter- fully compatible with PC-standard UARTs. The UART port
nally or externally generated. provides a simplified UART interface to other peripherals or
The serial ports also contain frame sync error detection logic hosts, supporting full-duplex, DMA-supported, asynchronous
where the serial ports detect frame syncs that arrive early (for transfers of serial data. The UART also has multiprocessor com-
example frame syncs that arrive while the transmission/recep- munication capability using 9-bit address detection. This allows
tion of the previous word is occurring). All the serial ports also it to be used in multidrop networks through the RS-485 data
share one dedicated error interrupt. interface standard. The UART port also includes support for 5
to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The
S/PDIF Compatible Digital Audio Receiver/Transmitter UART port supports two modes of operation:
and Synchronous/Asynchronous Sample Rate Converter • PIO (Programmed I/O) – The processor sends or receives
The S/PDIF receiver/transmitter has no separate DMA chan- data by writing or reading I/O-mapped UART registers.
nels. It receives audio data in serial format and converts it into a The data is double-buffered on both transmit and receive.
biphase encoded signal. The serial data input to the • DMA (Direct Memory Access) – The DMA controller
receiver/transmitter can be formatted as left justified, I2S or transfers both transmit and receive data. This reduces the
right justified with word widths of 16, 18, 20, or 24 bits. number and frequency of interrupts required to transfer
The serial data, clock, and frame sync inputs to the S/PDIF data to and from memory. The UART has two dedicated
receiver/transmitter are routed through the Signal Routing Unit DMA channels, one for transmit and one for receive. These
(SRU). They can come from a variety of sources such as the DMA channels have lower default priority than most DMA
SPORTs, external pins, the precision clock generators (PCGs), channels because of their relatively low service rates.
or the sample rate converters (SRC) and are controlled by the The UART port's baud rate, serial data format, error code gen-
SRU control registers. eration and status, and interrupts are programmable:
The sample rate converter (SRC) contains four SRC blocks and • Supporting bit rates ranging from (fSCLK/ 1,048,576) to
is the same core as that used in the AD1896 192 kHz Stereo (fSCLK/16) bits per second.
Asynchronous Sample Rate Converter and provides up to
128dB SNR. The SRC block is used to perform synchronous or • Supporting data formats from 7 to12 bits per frame.
asynchronous sample rate conversion across independent stereo • Both transmit and receive operations can be configured to
channels, without using internal processor resources. The four generate maskable interrupts to the processor.
SRC blocks can also be configured to operate together to con- Where the 16-bit UART_Divisor comes from the DLH register
vert multichannel audio data without phase mismatches. (most significant 8 bits) and DLL register (least significant
Finally, the SRC is used to clean up audio data from jittery clock 8 bits).
sources such as the S/PDIF receiver.
In conjunction with the general-purpose timer functions, auto-
Digital Peripheral Interface (DPI) baud detection is supported.
The Digital Peripheral Interface provides connections to two Timers
serial peripheral interface ports (SPI), two universal asynchro-
nous receiver-transmitters (UARTs), a Two Wire Interface The ADSP-21369 has a total of four timers: a core timer that can
(TWI), 12 Flags, and three general-purpose timers. generate periodic software interrupts and three general purpose
timers that can generate periodic interrupts and be indepen-
Serial Peripheral (Compatible) Interface dently set to operate in one of three modes:
The ADSP-21369 SHARC processor contains two Serial Periph- • Pulse Waveform Generation mode
eral Interface ports (SPIs). The SPI is an industry standard • Pulse Width Count /Capture mode
synchronous serial link, enabling the ADSP-21369 SPI compati-
ble port to communicate with other SPI compatible devices. The • External Event Watchdog mode
SPI consists of two data pins, one device select pin, and one The core timer can be configured to use FLAG3 as a Timer
clock pin. It is a full-duplex synchronous serial interface, sup- Expired signal, and each general purpose timer has one bidirec-
porting both master and slave modes. The SPI port can operate tional pin and four registers that implement its mode of
in a multimaster environment by interfacing with up to four operation: a 6-bit configuration register, a 32-bit count register,
other SPI compatible devices, either acting as a master or slave
Preliminary Technical Data ADSP-21369
a 32-bit period register, and a 32-bit pulse width register. A sin- SYSTEM DESIGN
gle control and status register enables or disables all three
The following sections provide an introduction to system design
general purpose timers independently.
options and power supply issues.
Two Wire Interface Port (TWI)
Program Booting
The TWI is a bi-directional 2-wire, serial bus used to move 8-bit
The internal memory of the ADSP-21369 boots at system
data while maintaining compliance with the I2C bus protocol.
power-up from an 8-bit EPROM via the external port, an SPI
The TWI Master incorporates the following features:
master, an SPI slave or an internal boot. Booting is determined
• Simultaneous Master and Slave operation on multiple by the Boot Configuration (BOOTCFG1–0) pins (see Table 7 on
device systems with support for multi master data page 15). Selection of the boot source is controlled via the SPI as
arbitration either a master or slave device, or it can immediately begin exe-
• Digital filtering and timed event processing cuting from ROM.
• 7 and 10 bit addressing Power Supplies
• 100K bits/s and 400K bits/s data rates The ADSP-21369 has separate power supply connections for the
• Low interrupt rate internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS)
power supplies. The internal and analog supplies must meet the
Pulse Width Modulation 1.3V requirement. The external supply must meet the 3.3V
The PWM module is a flexible, programmable, PWM waveform requirement. All external supply pins must be connected to the
generator that can be programmed to generate the required same power supply.
switching patterns for various applications related to motor and Note that the analog supply pin (AVDD) powers the ADSP-
engine control or audio power control. The PWM generator can 21369’s internal clock generator PLL. To produce a stable clock,
generate either center-aligned or edge-aligned PWM wave- it is recommended that PCB designs use an external filter circuit
forms. In addition, it can generate complementary signals on for the AVDD pin. Place the filter components as close as possi-
two outputs in paired mode or independent signals in non ble to the AVDD/AVSS pins. For an example circuit, see Figure 2.
paired mode (applicable to a single group of four PWM (A recommended ferrite chip is the muRata
waveforms). BLM18AG102SN1D). To reduce noise coupling, the PCB
The entire PWM module has four groups of four PWM outputs should use a parallel pair of power and ground planes for
each. Therefore, this module generates 16 PWM outputs in VDDINT and GND. Use wide traces to connect the bypass capac-
total. Each PWM group produces two pairs of PWM signals on itors to the analog power (AVDD) and ground (AVSS) pins. Note
the four PWM outputs. that the AVDD and AVSS pins specified in Figure 2 are inputs to
the processor and not the analog ground plane on the board—
The PWM generator is capable of operating in two distinct the AVSS pin should connect directly to digital ground (GND) at
modes while generating center-aligned PWM waveforms: single the chip.
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period.
This results in PWM patterns that are symmetrical about the
ADSP-213xx
mid-point of the PWM period. In double update mode, a sec- 100nF 10nF 1nF
ond updating of the PWM registers is implemented at the mid- VDDINT AVDD

point of the PWM period. In this mode, it is possible to produce

asymmetrical PWM patterns that produce lower harmonic dis- HI Z FERRITE
tortion in three-phase PWM inverters. BEAD CHIP AVSS

ROM Based Security

LOCATE ALL COMPONENTS
The ADSP-21369 has a ROM security feature that provides CLOSE TO AVDD AND AVSS PINS

hardware support for securing user software code by preventing

unauthorized reading from the internal code when enabled. Figure 2. Analog Power (AVDD) Filter Circuit
When using this feature, the processor does not boot-load any
external code, executing exclusively from internal SRAM/ROM. Target Board JTAG Emulator Connector
Additionally, the processor is not freely accessible via the JTAG
port. Instead, a unique 64-bit key, which must be scanned in Analog Devices DSP Tools product line of JTAG emulators uses
through the JTAG or Test Access Port will be assigned to each the IEEE 1149.1 JTAG test access port of the ADSP-21369 pro-
customer. The device will ignore a wrong key. Emulation fea- cessor to monitor and control the target board processor during
tures and external boot modes are only available after the emulation. Analog Devices DSP Tools product line of JTAG
correct key is scanned. emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces-
sor stacks. The processor's JTAG interface ensures that the
emulator will not affect target system loading or timing.
ADSP-21369 Preliminary Technical Data
For complete information on Analog Devices’ SHARC DSP The VisualDSP++ IDDE lets programmers define and manage
Tools product line of JTAG emulator operation, see the appro- DSP software development. Its dialog boxes and property pages
priate “Emulator Hardware User's Guide”. let programmers configure and manage all of the SHARC devel-
opment tools, including the color syntax highlighting in the
DEVELOPMENT TOOLS VisualDSP++ editor. This capability permits programmers to:
The ADSP-21369 is supported with a complete set of • Control how the development tools process inputs and
CROSSCORE® software and hardware development tools, generate outputs
including Analog Devices emulators and VisualDSP++® devel-
• Maintain a one-to-one correspondence with the tool’s
opment environment. The same emulator hardware that
command line switches
supports other SHARC processors also fully emulates the
ADSP-21369. The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
The VisualDSP++ project management environment lets pro-
ory and timing constraints of DSP programming. These
grammers develop and debug an application. This environment
capabilities enable engineers to develop code more effectively,
includes an easy to use assembler (which is based on an alge-
eliminating the need to start from the very beginning, when
braic syntax), an archiver (librarian/library builder), a linker, a
developing new application code. The VDK features include
loader, a cycle-accurate instruction-level simulator, a C/C++
Threads, Critical and Unscheduled regions, Semaphores,
compiler, and a C/C++ runtime library that includes DSP and
Events, and Device flags. The VDK also supports Priority-based,
mathematical functions. A key point for these tools is C/C++
Preemptive, Cooperative, and Time-Sliced scheduling
code efficiency. The compiler has been developed for efficient
approaches. In addition, the VDK was designed to be scalable. If
translation of C/C++ code to DSP assembly. The SHARC has
the application does not use a specific feature, the support code
architectural features that improve the efficiency of compiled
for that feature is excluded from the target system.
C/C++ code.
Because the VDK is a library, a developer can decide whether to
The VisualDSP++ debugger has a number of important fea-
use it or not. The VDK is integrated into the VisualDSP++
tures. Data visualization is enhanced by a plotting package that
development environment, but can also be used via standard
offers a significant level of flexibility. This graphical representa-
command line tools. When the VDK is used, the development
tion of user data enables the programmer to quickly determine
environment assists the developer with many error-prone tasks
the performance of an algorithm. As algorithms grow in com-
and assists in managing system resources, automating the gen-
plexity, this capability can have increasing significance on the
eration of various VDK based objects, and visualizing the
designer’s development schedule, increasing productivity. Sta-
system state, when debugging an application that uses the VDK.
tistical profiling enables the programmer to non intrusively poll
the processor as it is running the program. This feature, unique VisualDSP++ Component Software Engineering (VCSE) is
to VisualDSP++, enables the software developer to passively Analog Devices’ technology for creating, using, and reusing
gather important code execution metrics without interrupting software components (independent modules of substantial
the real-time characteristics of the program. Essentially, the functionality) to quickly and reliably assemble software applica-
developer can identify bottlenecks in software quickly and effi- tions. Download components from the Web and drop them into
ciently. By using the profiler, the programmer can focus on the application. Publish component archives from within
those areas in the program that impact performance and take VisualDSP++. VCSE supports component implementation in
corrective action. C/C++ or assembly language.
Debugging both C/C++ and assembly programs with the Use the Expert Linker to visually manipulate the placement of
VisualDSP++ debugger, programmers can: code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
• View mixed C/C++ and assembly code (interleaved source
to different areas of the processor or external memory with the
and object information)
drag of the mouse, examine run time stack and heap usage. The
• Insert breakpoints Expert Linker is fully compatible with the existing Linker Defi-
• Set conditional breakpoints on registers, memory, nition File (LDF), allowing the developer to move between the
and stacks graphical and textual environments.
• Trace instruction execution In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
• Perform linear or statistical profiling of program execution
range of tools supporting the SHARC processor family. Hard-
• Fill, dump, and graphically plot the contents of memory ware tools include SHARC processor PC plug-in cards. Third
• Perform source level debugging party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
• Create custom debugger windows
Preliminary Technical Data ADSP-21369
Designing an Emulator-Compatible DSP Board (Target) Evaluation Kit
The Analog Devices family of emulators are tools that every Analog Devices offers a range of EZ-KIT Lite evaluation plat-
DSP developer needs to test and debug hardware and software forms to use as a cost effective method to learn more about
systems. Analog Devices has supplied an IEEE 1149.1 JTAG developing or prototyping applications with Analog Devices
Test Access Port (TAP) on each JTAG DSP. Nonintrusive in- processors, platforms, and software tools. Each EZ-KIT Lite
circuit emulation is assured by the use of the processor’s JTAG includes an evaluation board along with an evaluation suite of
interface—the emulator does not affect target system loading or the VisualDSP++ development and debugging environment
timing. The emulator uses the TAP to access the internal fea- with the C/C++ compiler, assembler, and linker. Also included
tures of the processor, allowing the developer to load code, set are sample application programs, power supply, and a USB
breakpoints, observe variables, observe memory, and examine cable. All evaluation versions of the software tools are limited
registers. The processor must be halted to send data and com- for use only with the EZ-KIT Lite product.
mands, but once an operation has been completed by the The USB controller on the EZ-KIT Lite board connects the
emulator, the DSP system is set running at full speed with no board to the USB port of the user’s PC, enabling the
impact on system timing. VisualDSP++ evaluation suite to emulate the on-board proces-
To use these emulators, the target board must include a header sor in-circuit. This permits the customer to download, execute,
that connects the DSP’s JTAG port to the emulator. and debug programs for the EZ-KIT Lite system. It also allows
For details on target board design issues including mechanical in-circuit programming of the on-board Flash device to store
layout, single processor connections, signal buffering, signal ter- user-specific boot code, enabling the board to run as a standal-
mination, and emulator pod logic, see the EE-68: Analog Devices one unit without being connected to the PC.
JTAG Emulation Technical Reference on the Analog Devices With a full version of VisualDSP++ installed (sold separately),
website (www.analog.com)—use site search on “EE-68.” This engineers can develop software for the EZ-KIT Lite or any cus-
document is updated regularly to keep pace with improvements tom defined system. Connecting one of Analog Devices JTAG
to emulator support. emulators to the EZ-KIT Lite board enables high-speed, non-
intrusive emulation.

ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-21369
architecture and functionality. For detailed information on the
ADSP-2136x Family core architecture and instruction set, refer
to the ADSP-2136x SHARC Processor Hardware Reference for
the ADSP-21367/8/9 Processors and the ADSP-2136x SHARC
Processor Programming Reference.
ADSP-21369 Preliminary Technical Data
PIN FUNCTION DESCRIPTIONS
The following symbols appear in the Type column of Table 5:
A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State, (pd) = pull-down
resistor, (pu) = pull-up resistor.

Table 5. Pin List

Name Type State During Description

and After
Reset

ADDR23–0 I/O with program- Three state External Address. The ADSP-21369 outputs addresses for external memory and
mable pu1 with pull-up peripherals on these pins.
enabled,
driven low

DATA31–0 I/O with program- Three-state External Data. The data pins can be multiplexed to support the external memory
mable pu with pull-up interface data (I/O), the PDAP (I), FLAGS (I/O), and PWM (O). After reset, all DATA pins will
enabled be in EMIF mode and FLAG(0-3) pins will be in FLAGS mode (default). When configured
in the IDP_PDAP_CTL register, IDP Channel 0 scans the DATA31–8 pins for parallel
input data.

DAI _P20–1 I/O with program- Three-state Digital Audio Interface Pins. These pins provide the physical interface to the DAI SRU.
mable pu2 with program- The DAI SRU configuration registers define the combination of on-chip audio centric
mable pull-up peripheral inputs or outputs connected to the pin and to the pin’s output enable. The
configuration registers of these peripherals then determines the exact behavior of the
pin. Any input or output signal present in the DAI SRU may be routed to any of these
pins. The DAI SRU provides the connection from the serial ports (8), the SRC module, the
PWM module, the S/PDIF module, input data ports (2), and the precision clock genera-
tors (4), to the DAI_P20–1 pins.

DPI _P14–1 I/O with program- Three-state Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.
mable pu2 with program- The DPI SRU configuration registers define the combination of on-chip peripheral inputs
mable pull-up or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU
provides the connection from the timers (3), SPIs (2), UARTs (2), flags (12) I2C (1), and
general-purpose I/O (9) to the DPI_P14–1 pins. The I2C output is an open-drain output—
so the pins used for I2C data and clock should be connected to logic level 0.

ACK Input with pro- Memory Acknowledge. External devices can deassert ACK (low) to add wait states to
grammable pu1 an external memory access. ACK is used by I/O devices, memory controllers, or other
peripherals to hold off completion of an external memory access.

RD Output with pro- Pull-up, driven External Port Read Enable. RD is asserted whenever the ADSP-21369 reads a word
grammable pu1 high from external memory. RD has a 22.5 kΩ internal pull-up resistor.

WR Output with pu1 Pull-up, driven External Port Write Enable. WR is asserted when the ADSP-21369 writes a word to
high external memory. WR has a 22.5 kΩ internal pull-up resistor.

SDRAS Output with pu1 Pull-up, driven SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other
high SDRAM command pins, defines the operation for the SDRAM to perform.

SDCAS Output with pu1 Pull-up, driven SDRAM Column Address Select. Connect to SDRAM's CAS pin. In conjunction with
high other SDRAM command pins, defines the operation for the SDRAM to perform.

SDWE Output with pu1 Pull-up, driven SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.
high
Preliminary Technical Data ADSP-21369
Table 5. Pin List

Name Type State During Description

and After
Reset

SDCKE Output with pu1 Pull-up, driven SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK
high signal. For details, see the data sheet supplied with the SDRAM device.

SDA10 Output with pu1 Pull-up, driven SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-
high SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.

SDCLK0 I/O SDRAM Clock Configure.

MS0–1 I/O with program- Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-
mable pu1 sponding banks of external memory. The MS3-0 lines are decoded memory address lines
that change at the same time as the other address lines. When no external memory
access is occurring the MS3-0 lines are inactive; they are active however when a condi-
tional memory access instruction is executed, whether or not the condition is true.

FLAG[0]/IRQ0 I/O FLAG0/Interrupt Request0.

FLAG[1]/IRQ1 I/O FLAG1/Interrupt Request1.

FLAG[2]/IRQ2/ I/O with FLAG2/Interrupt Request/Memory Select2.

MS2 programmable1
pu (for MS mode)

FLAG[3]/TIMEXP/ I/O with FLAG3/Timer Expired/Memory Select3.

MS3 programmable1
pull-up (for MS
mode)

TDI Input with pu Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5
kΩ internal pull-up resistor.

TDO Output Test Data Output (JTAG). Serial scan output of the boundary scan path.

TMS Input with pu Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ
internal pull-up resistor.

TCK Input Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-21369.

TRST Input with pu Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-21369. TRST has a 22.5 kΩ
internal pull-up resistor.

EMU Output with pu Emulation Status. Must be connected to the ADSP-21369 Analog Devices DSP Tools
product line of JTAG emulators target board connector only. EMU has a 22.5 kΩ internal
pull-up resistor.

CLK_CFG1–0 Input Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 8 for
a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.

BOOT_CFG1–0 Input Boot Configuration Select. These pins select the boot mode for the processor. The
BOOTCFG pins must be valid before reset is asserted. See Table 7 for a description of the
boot modes.
ADSP-21369 Preliminary Technical Data
Table 5. Pin List

Name Type State During Description

and After
Reset

RESET Input Processor Reset. Resets the ADSP-21369 to a known state. Upon deassertion, there is
a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.

XTAL Output Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.

CLKIN Input Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21369 clock input. It
configures the ADSP-21369 to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the internal
clock generator. Connecting the external clock to CLKIN while leaving XTAL uncon-
nected configures the ADSP-21369 to use the external clock source such as an external
clock oscillator. CLKIN may not be halted, changed, or operated below the specified
frequency.

CLKOUT Output Local Clock Out. CLKOUT can also be configured as a reset out pin.The functionality
can be switched between the PLL output clock and reset out by setting bit 12 of the
PMCTREG register. The default is reset out.
1
Pull-up is always enabled
2
Pull-up can be enabled/disabled, value of pull-up cannot be programmed.
Preliminary Technical Data ADSP-21369
DATA MODES
The upper 32 data pins of the external memory interface are
muxed (using bits in the SYSCTL register) to support the exter-
nal memory interface data (input/output), the PDAP (input
only), the FLAGS (input/output), and the PWM channels (out-
put). Table 6 provides the pin settings.

Table 6. Function of Data Pins

DATA PIN MODE DATA31–16 DATA15–8 DATA7–0

000 EPDATA32–0
001 FLAGS/PWM15–01 EPDATA15–0
010 FLAGS/PWM15–01 FLAGS15–8 EPDATA7–0
011 FLAGS/PWM15–01 FLAGS15–0
100 PDAP (DATA + CTRL) EPDATA7–0
101 PDAP (DATA + CTRL) FLAGS7–0
110 Reserved
111 Three-state all pins
1
These signals can be FLAGS or PWM or a mix of both. However, they can be selected only in groups of four. Their function is determined by the control signals
FLAGS/PWM_SEL. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21367/8/9 Processors.

BOOT MODES

Table 7. Boot Mode Selection

BOOTCFG1–0 Booting Mode

00 SPI Slave Boot
01 SPI Master Boot
10 EPROM/FLASH Boot

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

For details on processor timing, see Timing Specifications and
Figure 3 on Page 18.

Table 8. Core Instruction Rate/ CLKIN Ratio Selection

CLKCFG1–0 Core to CLKIN Ratio

00 6:1
01 32:1
10 16:1
ADSP-21369 Preliminary Technical Data
ADSP-21369 SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS

K Grade B Grade2

Parameter1 Min Max Min Max Unit

VDDINT Internal (Core) Supply Voltage 1.235 1.365 1.235 1.365 V

AVDD Analog (PLL) Supply Voltage 1.235 1.365 1.235 1.365 V
VDDEXT External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 V
3
VIH High Level Input Voltage @ VDDEXT = max 2.0 VDDEXT + 0.5 2.0 VDDEXT + 0.5 V
VIL3 Low Level Input Voltage @ VDDEXT = min –0.5 +0.8 –0.5 +0.8 V
VIH_CLKIN4 High Level Input Voltage @ VDDEXT = max 1.74 VDDEXT + 0.5 1.74 VDDEXT + 0.5 V
VIL_CLKIN Low Level Input Voltage @ VDDEXT = min –0.5 +1.19 –0.5 +1.19 V
TAMB 5, 6
Ambient Operating Temperature 0 +70 –40 +85 °C
1
Specifications subject to change without notice.
2
Pending package qualification.
3
Applies to input and bidirectional pins: AD23–0, DATA31–0, FLAG3–0, DAI_Px, DPI_Px, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.
4
Applies to input pin CLKIN.
5
See Thermal Characteristics on Page 46 for information on thermal specifications.
6
See Engineer-to-Engineer Note (No. TBD) for further information.

ELECTRICAL CHARACTERISTICS

Parameter1 Test Conditions Min Max Unit

VOH2 High Level Output Voltage @ VDDEXT = min, IOH = –1.0 mA3 2.4 V
2 3
VOL Low Level Output Voltage @ VDDEXT = min, IOL = 1.0 mA 0.4 V
4, 5
IIH High Level Input Current @ VDDEXT = max, VIN = VDDEXT max 10 µA
4
IIL Low Level Input Current @ VDDEXT = max, VIN = 0 V 10 µA
5
IILPU Low Level Input Current Pull-up @ VDDEXT = max, VIN = 0 V 200 µA
6, 7
IOZH Three-State Leakage Current @ VDDEXT= max, VIN = VDDEXT max 10 µA
6
IOZL Three-State Leakage Current @ VDDEXT = max, VIN = 0 V 10 µA
7
IOZLPU Three-State Leakage Current Pull-up @ VDDEXT = max, VIN = 0 V 200 µA
8, 9
IDD-INTYP Supply Current (Internal) tCCLK = 5.0 ns, VDDINT = 1.3 500 mA
10
AIDD Supply Current (Analog) AVDD = max 10 mA
11, 12
CIN Input Capacitance fIN=1 MHz, TCASE=25°C, VIN=1.3V 4.7 pF
1
Specifications subject to change without notice.
2
Applies to output and bidirectional pins: ADDR23-0, DATA31-0, RD, WR, ALE, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, CLKOUT, XTAL.
3
See Output Drive Currents on Page 46 for typical drive current capabilities.
4
Applies to input pins: BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.
5
Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.
6
Applies to three-statable pins: FLAG3–0.
7
Applies to three-statable pins with 22.5 kΩ pull-ups: DAI_Px, DPI_Px, EMU.
8
Typical internal current data reflects nominal operating conditions.
9
See Engineer-to-Engineer Note (No. TBD) for further information.
10
Characterized, but not tested.
11
Applies to all signal pins.
12
Guaranteed, but not tested.
Preliminary Technical Data ADSP-21369
ABSOLUTE MAXIMUM RATINGS

Parameter Rating
Internal (Core) Supply Voltage (VDDINT)1 –0.3 V to +1.5 V
Analog (PLL) Supply Voltage (AVDD)1 –0.3 V to +1.5 V
External (I/O) Supply Voltage (VDDEXT)1 –0.3 V to +4.6 V
Input Voltage –0.5 V to VDDEXT1 +0.5 V
Output Voltage Swing –0.5 V to VDDEXT1 +0.5 V
Load Capacitance1 200 pF
Storage Temperature Range1 –65°C to +150°C
Junction Temperature under Bias 125°C
1
Stresses greater than those listed above may cause permanent damage to the device. These
are stress ratings only; functional operation of the device at these or any other conditions
greater than those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

MAXIMUM POWER DISSIPATION

The data in this table is based on theta JA (θJA) established per
JEDEC standards JESD51-2 and JESD51-6. See Engineer-to-
Engineer note (EE-TBD) for further information. For informa-
tion on package thermal specifications, see Thermal
Characteristics on Page 46.

Max Ambient Temp1 208 LQFP 256 SBGA

70°C TBD W TBD W
85°C TBD W TBD W
1
Power Dissipation greater than that listed above may cause permanent damage
to the device. For more information, see Thermal Characteristics on page 46.

ESD SENSITIVITY

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-21369 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

TIMING SPECIFICATIONS
The ADSP-21369’s internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, and serial ports. During reset, program the ratio between
the processor’s internal clock frequency and external (CLKIN)
clock frequency with the CLKCFG1–0 pins (see Table 8 on
page 15). To determine switching frequencies for the serial
ports, divide down the internal clock, using the programmable
divider control of each port (DIVx for the serial ports).
The ADSP-21369’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL).
This PLL-based clocking minimizes the skew between the sys-
tem clock (CLKIN) signal and the processor’s internal clock.
ADSP-21369 Preliminary Technical Data
Figure 3 shows Core to CLKIN ratios of 6:1, 16:1 and 32:1 with
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the ADSP-
2136x SHARC Processor Programming Reference.

PLLICLK

CLKOUT
CLKIN

XTAL INDIV DIVEN CCLK

PLLM
XTAL OSC ÷1, 2 ÷2, 4, 8, 16 (CORE CLOCK)

PCLK, SDCLK
(PERIPHERAL CLOCK,
SDRAM CLOCK)
CLK-CFG [1:0]
(6:1, 16:1, 32:1)

Figure 3. Core Clock and System Clock Relationship to CLKIN

Note the definitions of various clock periods shown in Table 10 Use the exact timing information given. Do not attempt to
which are a function of CLKIN and the appropriate ratio con- derive parameters from the addition or subtraction of others.
trol shown in Table 9. While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
Table 9. ADSP-21369 CLKOUT and CCLK Clock reflect statistical variations and worst cases. Consequently, it is
Generation Operation not meaningful to add parameters to derive longer times. See
Figure 38 on page 46 under Test Conditions for voltage refer-
Timing Description Calculation ence levels.
Requirements
Switching Characteristics specify how the processor changes its
CLKIN Input Clock 1/tCK
signals. Circuitry external to the processor must be designed for
CCLK Core Clock 1/tCCLK compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
Table 10. Clock Periods circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
Timing Description1
as memory) is satisfied.
Requirements
tCK CLKIN Clock Period Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
tCCLK (Processor) Core Clock Period
operation. Timing requirements guarantee that the processor
tPCLK (Peripheral) Clock Period = 2 × tCCLK operates correctly with other devices.
tSCLK Serial Port Clock Period = (tPCLK) × SR
tSDCLK SDRAM Clock Period = (tCCLK) × SDR
tSPICLK SPI Clock Period = (tPCLK) × SPIR
1
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV
bits in DIVx register)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register
setting)
SPICLK = SPI Clock
SDR=SDRAM-to-Core Clock Ratio (Values determined by bits 20-18 of the
PMCTL register)
Preliminary Technical Data ADSP-21369
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 11.

Table 11. Power Up Sequencing Timing Requirements (Processor Startup)

Parameter Min Max Unit

Timing Requirements
tRSTVDD RESET Low Before VDDINT/VDDEXT On 0 ns
tIVDDEVDD VDDINT on Before VDDEXT –50 200 ms
tCLKVDD1 CLKIN Valid After VDDINT/VDDEXT Valid 0 200 ms
tCLKRST CLKIN Valid Before RESET Deasserted 102 µs
tPLLRST PLL Control Setup Before RESET Deasserted 203 µs

Switching Characteristic
tCORERST Core Reset Deasserted After RESET Deasserted 4096tCK + 2 tCCLK 4, 5
1
Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.3 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time.
Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4096 cycle count depends on tSRST specification in Table 13. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.

RESET

tRSTVDD

VDDINT
tIVDDEVDD

VDDEXT tCLKVDD

CLKIN

tCLKRST

CLK_CFG1-0

tCORERST
tPLLRST
RSTOUT

Figure 4. Power-Up Sequencing

ADSP-21369 Preliminary Technical Data
Clock Input

Table 12. Clock Input

Parameter 400 MHz Unit

Min Max
Timing Requirements
tCK CLKIN Period 151 3202 ns
tCKL CLKIN Width Low 61 1502 ns
tCKH CLKIN Width High 61 1502 ns
tCKRF CLKIN Rise/Fall (0.4V–2.0V) TBD ns
tCCLK3 CCLK Period 2.51 10 ns
1
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
2
Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.
3
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.

tCK

CLKIN
tCKH tCKL

Figure 5. Clock Input

Clock Signals
The ADSP-21369 can use an external clock or a crystal. See the
CLKIN pin description in Table 5. The programmer can config-
ure the ADSP-21369 to use its internal clock generator by
connecting the necessary components to CLKIN and XTAL.
Figure 6 shows the component connections used for a crystal
operating in fundamental mode. Note that the clock rate is
achieved using a 16.67 MHz crystal and a PLL multiplier ratio
16:1 (CCLK:CLKIN achieves a clock speed of 400 MHz). To
achieve the full core clock rate, programs need to configure the
multiplier bits in the PMCTL register.

ADSP-2136X

CLKIN R1 XTAL
1M⍀*

R2
47⍀*

C1 C2
22pF Y1 22pF

24.576MHz

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL

DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS

*TYPICAL VALUES

Figure 6. 400 MHz Operation (Fundamental Mode Crystal)

Preliminary Technical Data ADSP-21369
Reset

Table 13. Reset

Parameter Min Max Unit

Timing Requirements
tWRST1 RESET Pulse Width Low 4tCK ns
tSRST RESET Setup Before CLKIN Low 8 ns
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 µs while RESET is low, assuming
stable VDD and CLKIN (not including start-up time of external clock oscillator).

CLKIN

tWRST tSRST

RESET

Figure 7. Reset

Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts.

Table 14. Interrupts

Parameter Min Max Unit

Timing Requirement
tIPW IRQx Pulse Width 2 × tPCLK +2 ns

DAI_P20-1
DPI_14-1
FLAG2-0
(IRQ2-0) tIPW

Figure 8. Interrupts
ADSP-21369 Preliminary Technical Data
Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (CTIMER).

Table 15. Core Timer

Parameter Min Max Unit

Switching Characteristic
tWCTIM CTIMER Pulse width 4 × tPCLK – 1 ns

FLAG3 tWCTIM
(CTIMER)

Figure 9. Core Timer

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1,
and Timer2 in PWM_OUT (pulse width modulation) mode.
Timer signals are routed to the DPI_P14–1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DPI_P14–1 pins.

Table 16. Timer PWM_OUT Timing

Parameter Min Max Unit

Switching Characteristic
tPWMO Timer Pulse Width Output 2 tPCLK – 1 2(231 – 1) tPCLK ns

tPWMO
DPI14-1
(TIMER2-0)

Figure 10. Timer PWM_OUT Timing

Preliminary Technical Data ADSP-21369
Timer WDTH_CAP Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in WDTH_CAP (pulse width count and capture)
mode. Timer signals are routed to the DPI_P14–1 pins through
the SRU. Therefore, the timing specification provided below are
valid at the DPI_P14–1 pins.

Table 17. Timer Width Capture Timing

Parameter Min Max Unit

Timing Requirement
tPWI Timer Pulse Width 2 tPCLK 2(231– 1) tPCLK ns

tPWI
DPI_14-1
(TIMER2-0)

Figure 11. Timer Width Capture Timing

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example DAI_PB01_I to
DAI_PB02_O).

Table 18. DAI Pin to Pin Routing

Parameter Min Max Unit

Timing Requirement
tDPIO Delay DAI/DPI Pin Input Valid to DAI Output Valid 1.5 10 ns

DAI_Pn
DPI_Pn

DAI_pm
DPI_Pm

tDPIO

Figure 12. DAI Pin to Pin Direct Routing

ADSP-21369 Preliminary Technical Data
Precision Clock Generator (Direct Pin Routing) inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All Timing Param-
This timing is only valid when the SRU is configured such that
eters and Switching Characteristics apply to external DAI pins
the Precision Clock Generator (PCG) takes its inputs directly
(DAI_P01 – DAI_P20).
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s

Table 19. Precision Clock Generator (Direct Pin Routing)

Parameter Min Max Unit

Timing Requirements
tPCGIW Input Clock Period 24 ns
tSTRIG PCG Trigger Setup Before Falling Edge of PCG Input 2 ns
Clock
tHTRIG PCG Trigger Hold After Falling Edge of PCG Input 2 ns
Clock
Switching Characteristics
tDPCGIO PCG Output Clock and Frame Sync Active Edge Delay
After PCG Input Clock 2.5 10 ns
tDTRIGCLK PCG Output Clock Delay After PCG Trigger 2.5 + ((2.5 + D) × tPCGIW) 10 + ((2.5 + D) × tPCGIW) ns
tDTRIGFS PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × tPCGIW) 10 + ((2.5 + D – PH) × tPCGIW) ns
tPCGOW Output Clock Period 2 × tPCGIW1 ns
D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21367/8/9 Processors,
“Precision Clock Generators” chapter.
1
Normal mode of operation.

tSTRIG tHTRIG

DAI_Pn
DPI_Pn
PCG_TRIGx_I
tPCGIW

DAI_Pm
DPI_Pm
PCG_EXTx_I
(CLKIN)
tDPCGIO

DAI_Py
DPI_Py tDTRIGCLK tDPCGIO tPCGOW
PCG_CLKx_O

DAI_Pz
DPI_Pz
PCG_FSx_O tDTRIGFS

Figure 13. Precision Clock Generator (Direct Pin Routing)

Preliminary Technical Data ADSP-21369
Flags
The timing specifications provided below apply to the FLAG3–0
and DPI_P14–1 pins, and the serial peripheral interface (SPI).
See Table 5 for more information on flag use.

Table 20. Flags

Parameter Min Max Unit

Timing Requirement
tFIPW FLAG3–0 IN Pulse Width 2 × tPCLK + 3 ns

Switching Characteristic
tFOPW FLAG3–0 OUT Pulse Width 2 × tPCLK – 1 ns

DPI_P14-1
(FLAG3-0IN)
(DATA31-0)
tFIPW

DPI_P14-1
(FLAG3-0OUT )
(DATA31-0)
tFOPW

Figure 14. Flags

ADSP-21369 Preliminary Technical Data
SDRAM Interface Timing (166 MHz SDCLK)
The 166MHz mode on the SDRAM interface is available on the
333 MHz processor only. It is not available on the 400 MHz and
266 MHz processors.

Table 21. SDRAM Interface Timing1

Parameter Minimum Maximum Unit

Timing Requirement
tSSDAT DATA Setup Before SDCLK 0 ns
tHSDAT DATA Hold After SDCLK 1.0 ns
Switching Characteristic
tSCLK SDCLK Period 6.0 ns
tSCLKH SDCLK Width High 2.9 ns
tSCLKL SDCLK Width Low 2.9 ns
tDCAD Command, ADDR, Data Delay After SDCLK2 4.0 ns
tHCAD Command, ADDR, Data Hold After SDCLK2 1.47 ns
tDSDAT Data Disable After SDCLK 5.3 ns
tENSDAT Data Enable After SDCLK 2.6 ns
1
For FCCLK = 333 MHz (SDCK ratio 1:2).
2
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.

tSCLK tSCLKH

SDCLK

tSSDAT
tSCLKL
tHSDAT

DATA (IN)

tDCAD tDSDAT

tENSDAT tHCAD

DATA(OUT)

tDCAD
CMND ADDR
(OUT)

tHCAD

NOTE: COMMAND = S DCAS , S DR AS , S DWE , MS x, SDA10, SDCKE.

Figure 15. SDRAM Interface Timing for 166 MHz SDCLK

Preliminary Technical Data ADSP-21369
SDRAM Interface Timing (133 MHz SDCLK)

Table 22. SDRAM Interface Timing1

Parameter Minimum Maximum Unit

Timing Requirement
tSSDAT DATA Setup Before SDCLK 0.0 ns
tHSDAT DATA Hold After SDCLK 1.0 ns
Switching Characteristic
tSCLK SDCLK Period 7.5 ns
tSCLKH SDCLK Width High 3.65 ns
tSCLKL SDCLK Width Low 3.65 ns
tDCAD Command, ADDR, Data Delay After SDCLK2 4.0 ns
tHCAD Command, ADDR, Data Hold After SDCLK2 1.5 ns
tDSDAT Data Disable After SDCLK 5.3 ns
tENSDAT Data Enable After SDCLK 2.6 ns
1
For FCCLK = 400 MHz (SDCK ratio = 1:3).
2
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.

tSCLK tSCLKH

SDCLK

tSSDAT
tSCLKL
tHSDAT

DATA (IN)

tDCAD tDSDAT

tENSDAT tHCAD

DATA(OUT)

tDCAD
CMND ADDR
(OUT)

tHCAD

NOTE: COMMAND = S DCAS , S DR AS , S DWE , MS x, SDA10, SDCKE.

Figure 16. SDRAM Interface Timing for 133 MHz SDCLK

ADSP-21369 Preliminary Technical Data
Memory Read – Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. These specifications apply when the ADSP-21369 is the bus
master accessing external memory space in asynchronous access
mode. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.

Table 23. Memory Read – Bus Master

Parameter Min Max Unit

Timing Requirements
tDAD Address, Selects Delay to Data Valid1, 2 W+tSDCK–5.12 ns
tDRLD RD Low to Data Valid1 W– 1.5 + tSDCK ns
tSDS Data Setup to RD High 1.79 ns
tHDRH Data Hold from RD High3, 4 0 ns
tDAAK ACK Delay from Address, Selects2, 5 tSDCK –9.5+ W ns
tDSAK ACK Delay from RD Low4 W– 7.0 ns
tHAKC ACK Hold After RD High 0 ns

Switching Characteristics
tDRHA Address Selects Hold After RD High RH + 0.44 ns
2
tDARL Address Selects to RD Low tSDCK –3.3 ns
tRW RD Pulsewidth W – 0.5 ns
tRWR RD High to WR, RD, Low HI +tSDCK –1 ns
W = (number of wait states specified in AMICTLx register) × tSDCK.
HI =RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) x tSDCK
IC = (number of Idle Cycles specified in AMICTLx register) x tSDCK).
H = (number of Hold Cycles specified in AMICTLx register) x tSDCK.
1
Data Delay/Setup: User must meet tDAD, tDRLD, or tSDS.
2
The falling edge of MSx, is referenced.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
4
Data Hold: User must meet tHDA or tHDRH in asynchronous access mode. See Test Conditions on Page 46 for the calculation of hold times given capacitive and dc loads.
5
ACK Delay/Setup: User must meet tDAAK, or tDSAK, for deassertion of ACK (Low). For asynchronous assertion of ACK (High) user must meet tDAAK or tDSAK.

tHDA

ADDRESS
MSx

tDRHA
tDARL tRW

RD

tDRLD tSDS
tDAD tHDRH

DATA
tDSAK
tDAAK tRWR

ACK

WR

Figure 17. Memory Read – Bus Master

Preliminary Technical Data ADSP-21369
Memory Write – Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. These specifications apply when the ADSP-21369 is the bus
master accessing external memory space in asynchronous access
mode. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.

Table 24. Memory Write – Bus Master

Parameter Min Max Unit

Timing Requirements
tDAAK ACK Delay from Address, Selects1, 2 tSDCK – 9.7 + W ns
tDSAK ACK Delay from WR Low 1, 3 W – 7.1 ns
tHAKC ACK Hold After WR High1 0 ns

Switching Characteristics
tDAWH Address, Selects to WR Deasserted2 tSDCK – 3.1+ W ns
2
tDAWL Address, Selects to WR Low tSDCK – 2.7 ns
tWW WR Pulsewidth W – 0.4 ns
tDDWH Data Setup Before WR High tSDCK – 2.1+ W ns
tDWHA Address Hold After WR Deasserted H + 0.3 ns
tDWHD Data Hold After WR Deasserted H + 0.4 ns
tDATRWH Data Disable After WR Deasserted4 tSDCK – 1.37+ H tSDCK + 3.9+ H ns
tWWR WR High to WR, RD Low tSDCK – 0.2+ H ns
tDDWR Data Disable Before RD Low 2tSDCK – 4.11 ns
tWDE WR Low to Data Enabled tSDCK – 3.5 ns
W = (number of wait states specified in AMICTLx register) × tSDCK.
H = (number of hold cycles specified in AMICTLx register) x tSDCK.
1
ACK Delay/Setup: User must meet tDAAK, or tDSAK, for deassertion of ACK (Low). For asynchronous assertion of ACK (High) user must meet tDAAK or tDSAK.
2
The falling edge of MSx is referenced.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
4
See Test Conditions on Page 46 for calculation of hold times given capacitive and dc loads.

ADDRESS
MSx

tDAWH tDWHA
tDAWL tWW
WR

tWWR
tWDE tDATRWH
tDDWH tDDWR

DATA

tDSAK
tDWHD
tDAAK
ACK
tHAKC

RD

Figure 18. Memory Write – Bus Master

ADSP-21369 Preliminary Technical Data
Serial Ports
To determine whether communication is possible between two Serial port signals (SCLK, FS, data channel A, data channel B)
devices at clock speed n, the following specifications must be are routed to the DAI_P20–1 pins using the SRU. Therefore, the
confirmed: 1) frame sync delay and frame sync setup and hold, timing specifications provided below are valid at the
2) data delay and data setup and hold, and 3) SCLK width. DAI_P20–1 pins.

Table 25. Serial Ports—External Clock

Parameter Min Max Unit

Timing Requirements
tSFSE1 FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode) 2.5 ns
tHFSE1 FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode) 2.5 ns
1
tSDRE Receive Data Setup Before Receive SCLK 2.5 ns
tHDRE1 Receive Data Hold After SCLK 2.5 ns
tSCLKW SCLK Width 10 ns
tSCLK SCLK Period 20 ns

Switching Characteristics
tDFSE2 FS Delay After SCLK
(Internally Generated FS in either Transmit or Receive Mode) 7 ns
tHOFSE2 FS Hold After SCLK
(Internally Generated FS in either Transmit or Receive Mode) 2 ns
tDDTE2 Transmit Data Delay After Transmit SCLK 7 ns
tHDTE2 Transmit Data Hold After Transmit SCLK 2 ns
1
Referenced to sample edge.
2
Referenced to drive edge.

Table 26. Serial Ports—Internal Clock

Parameter Min Max Unit

Timing Requirements
tSFSI1 FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode) 7 ns
tHFSI1 FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode) 2.5 ns
1
tSDRI Receive Data Setup Before SCLK 7 ns
tHDRI1 Receive Data Hold After SCLK 2.5 ns

Switching Characteristics
tDFSI2 FS Delay After SCLK (Internally Generated FS in Transmit Mode) 3 ns
tHOFSI2 FS Hold After SCLK (Internally Generated FS in Transmit Mode) –1.0 ns
2
tDFSI FS Delay After SCLK (Internally Generated FS in Receive or Mode) 3 ns
tHOFSI2 FS Hold After SCLK (Internally Generated FS in Receive Mode) –1.0 ns
tDDTI2 Transmit Data Delay After SCLK 3 ns
2
tHDTI Transmit Data Hold After SCLK –1.0 ns
tSCLKIW Transmit or Receive SCLK Width 0.5tSCLK – 2 0.5tSCLK + 2 ns
1
Referenced to the sample edge.
2
Referenced to drive edge.
Preliminary Technical Data ADSP-21369
Table 27. Serial Ports—Enable and Three-State

Parameter Min Max Unit

Switching Characteristics
tDDTEN1 Data Enable from External Transmit SCLK 2 ns
tDDTTE1 Data Disable from External Transmit SCLK 7 ns
tDDTIN1 Data Enable from Internal Transmit SCLK –1 ns
1
Referenced to drive edge.

Table 28. Serial Ports—External Late Frame Sync

Parameter Min Max Unit

Switching Characteristics
tDDTLFSE1 Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0 7 ns
tDDTENFS1 Data Enable for MCE = 1, MFD = 0 0.5 ns
1
The tDDTLFSE and tDDTENFS parameters apply to Left-justified Sample Pair as well as DSP serial mode, and MCE = 1, MFD = 0.

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DAI_P20-1 DRIVE SAMPLE DRIVE

(SCLK)

tSFSE/I tHFSE/I
DAI_P20-1
(FS)

tDDTENFS tDDTE/I

DAI_P20-1
tHDTE/I
(DATA CHANNEL A/B)
1ST BIT 2ND BIT

tDDTLFSE

LATE EXTERNAL TRANSMIT FS

DRIVE SAMPLE DRIVE

DAI_P20-1
(SCLK)

tSFSE/I tHFSE/I
DAI_P20-1
(FS)

tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20-1
(DATA CHANNEL A/B)
1ST BIT 2ND BIT

tDDTLFSE

NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.

Figure 19. External Late Frame Sync1

1
This figure reflects changes made to support Left-justified Sample Pair mode.
ADSP-21369 Preliminary Technical Data

DATA RECEIVE— INTERNAL CLOCK DATA RECEIVE— EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE

tSCLKIW tSCLKW
DAI_P20-1 DAI_P20-1
(SCLK) (SCLK)

tDFSI tDFSE
tSFSI tHFSI tHFSE
tHOFSI tHOFSE tSFSE
DAI_P20-1 DAI_P20-1
(FS) (FS)

tSDRI tHDRI tSDRE tHDRE

DAI_P20-1 DAI_P20-1
(DATA CHANNEL A/B) (DATA CHANNEL A/B)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT — INTERNAL CLOCK DATA TRANSMIT — EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE

tSCLKIW tSCLKW
DAI_P20-1 DAI_P20-1
(SCLK) (SCLK)

tDFSI tDFSE
tHOFSI tSFSI tHFSI tHOFSE tSFSE tHFSE
DAI_P20-1 DAI_P20-1
(FS) (FS)

tDDTI tDDTE
tHDTI tHDTE
DAI_P20-1 DAI_P20-1
(DATA CHANNEL A/B) (DATA CHANNEL A/B)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE DRIVE EDGE

DAI_P20-1 SCLK
SCLK (EXT)
tDDTEN tDDTTE

DAI_P20-1
(DATA CHANNEL A/B)

DRIVE EDGE

DAI_P20-1
SCLK (INT)
tDDTIN

DAI_P20-1
(DATA CHANNEL A/B)

Figure 20. Serial Ports

Preliminary Technical Data ADSP-21369
Input Data Port
The timing requirements for the IDP are given in Table 29.IDP
Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.

Table 29. IDP

Parameter Min Max Unit

Timing Requirements
tSISFS1 FS Setup Before SCLK Rising Edge 2.5 ns
1
tSIHFS FS Hold After SCLK Rising Edge 2.5 ns
tSISD1 SData Setup Before SCLK Rising Edge 2.5 ns
tSIHD1 SData Hold After SCLK Rising Edge 2.5 ns
tIDPCLKW Clock Width 9 ns
tIDPCLK Clock Period 24 ns
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE
tIPDCLK

DAI_P20-1 tIPDCLKW
(SCLK)

tSISFS tSIHFS

DAI_P20-1
(FS)
tSISD tSIHD

DAI_P20-1
(SDATA)

Figure 21. IDP Master Timing

ADSP-21369 Preliminary Technical Data
Parallel Data Acquisition Port (PDAP) ence for the ADSP-21367/8/9 Processors. Note that the most
significant 16 bits of external PDAP data can be provided
The timing requirements for the PDAP are provided in
through the DATA31–16 pins. The remaining 4 bits can only be
Table 30. PDAP is the parallel mode operation of channel 0 of
sourced through DAI_P4–1. The timing below is valid at the
the IDP. For details on the operation of the IDP, see the IDP
DATA31–16 pins.
chapter of the ADSP-2136x SHARC Processor Hardware Refer-

Table 30. Parallel Data Acquisition Port (PDAP)

Parameter Min Max Unit

Timing Requirements
tSPCLKEN1 PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 2.5 ns
1
tHPCLKEN PDAP_CLKEN Hold After PDAP_CLK Sample Edge 2.5 ns
tPDSD1 PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 2.5 ns
tPDHD1 PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 2.5 ns
tPDCLKW Clock Width 7 ns
tPDCLK Clock Period 24 ns

Switching Characteristics
tPDHLDD Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × tPCLK – 1 ns
tPDSTRB PDAP Strobe Pulse Width 2 × tPCLK – 1 ns
1
Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

SAMPLE EDGE

t PDCLK
t PDCLKW

DAI_P20-1
(PDAP_CLK)

t SPCLKEN
t HPCLKEN
DAI_P20-1
(PDAP_CLKEN)

t PDSD t PDHD

DATA

DAI_P20-1
(PDAP_STROBE) tPDSTRB
t PDHLDD

Figure 22. PDAP Timing

Preliminary Technical Data ADSP-21369
Pulse Width Modulation Generators

Table 31. PWM Timing

Parameter Min Max Unit

Switching Characteristics
tPWMW PWM Output Pulse Width tPCLK – 2 216 – 2) x tPCLK – 2 ns
tWCTIM PWM Output Period 2 × tPCLK (216 – 1) x tPCLK ns

tPWMW

PWM
OUTPUTS

tPWMP

Figure 23. PWM Timing

ADSP-21369 Preliminary Technical Data
Sample Rate Converter—Serial Input Port
The SRC input signals (SCLK, FS, and SDATA) are routed from
the DAI_P20–1 pins using the SRU. Therefore, the timing spec-
ifications provided in Table 32 are valid at the DAI_P20–1 pins.

Table 32. SRC, Serial Input Port

Parameter Min Max Unit

Timing Requirements
tSRCSFS1 FS Setup Before SCLK Rising Edge 4 ns
tSRCHFS1 FS Hold After SCLK Rising Edge 5.5 ns
tSRCSD1 SData Setup Before SCLK Rising Edge 4 ns
1
tSRCHD SData Hold After SCLK Rising Edge 5.5 ns
tSRCCLKW Clock Width 9 ns
tSRCCLK Clock Period 20 ns
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE
tSRCCLK

DAI_P20-1 tSRCCLKW
(SCLK)

tSRCSFS tSRCHFS

DAI_P20-1
(FS)
tSRCSD tSRCHD

DAI_P20-1
(SDATA)

Figure 24. SRC Serial Input Port Timing

Preliminary Technical Data ADSP-21369
Sample Rate Converter—Serial Output Port and delay specification with regard to SCLK. Note that SCLK
rising edge is the sampling edge and the falling edge is the drive
For the serial output port, the frame-sync is an input and it
edge.
should meet setup and hold times with regard to SCLK on the
output port. The serial data output, SDATA, has a hold time

Table 33. SRC, Serial Output Port

Parameter Min Max Unit

Timing Requirements
tSRCSFS1 FS Setup Before SCLK Rising Edge 4 ns
tSRCHFS1 FS Hold Before SCLK Rising Edge 5.5 ns

Switching Characteristics
tSRCTDD1 Transmit Data Delay After SCLK Falling Edge 7 ns
1
tSRCTDH Transmit Data Hold After SCLK Falling Edge 2 ns
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE
tSRCCLK

DAI_P20-1 tSRCCLKW
(SCLK)

tSRCSFS tSRCHFS

DAI_P20-1
(FS)

tSRCTDD

DAI_P20-1
(SDATA)

tSRCTDH

Figure 25. SRC Serial Output Port Timing

ADSP-21369 Preliminary Technical Data
SPDIF Transmitter
Serial data input to the SPDIF transmitter can be formatted as
left justified, I2S or right justified with word widths of 16, 18, 20,
or 24 bits. The following sections provide timing for the
transmitter.
SPDIF Transmitter—Serial Input Waveforms
Figure 26 shows the right-justified mode. LRCLK is HI for the mode) from an LRCLK transition, so that when there are 64
left channel and LO for the right channel. Data is valid on the SCLK periods per LRCLK period, the LSB of the data will be
rising edge of SCLK. The MSB is delayed 12-bit clock periods right-justified to the next LRCLK transition.
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output

DAI_P20-1
LRCLK LEFT CHANNEL RIGHT CHANNEL

DAI_P20-1
SCLK

DAI_P20-1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB

SDATA

Figure 26. Right-Justified Mode

Figure 27 shows the default I2S-justified mode. LRCLK is LO for

the left channel and HI for the right channel. Data is valid on the
rising edge of SCLK. The MSB is left-justified to an LRCLK
transition but with a single SCLK period delay.

RIGHT CHANNEL
DAI_P20-1
LEFT CHANNEL
LRCLK

DAI_P20-1
SCLK

DAI_P20-1 MSB MSB-1 MS B-2 LS B+2 LSB+1 LSB MSB MS B-1 MS B-2 LSB+2 LS B+1 LSB MSB
SDATA

Figure 27. I2S-Justified Mode

Figure 28 shows the left-justified mode. LRCLK is HI for the left

channel and LO for the right channel. Data is valid on the rising
edge of SCLK. The MSB is left-justified to an LRCLK transition
with no MSB delay.

DAI_P20-1
LRCLK LEFT CHANNEL RIGHT CHANNEL

DAI_P20-1
SCLK

MSB MSB-1 MSB-2 LS B+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB +1 LSB MSB MSB+1
DAI_P20-1
SDATA

Figure 28. Left-Justified Mode

Preliminary Technical Data ADSP-21369
SPDIF Transmitter Input Data Timing
The timing requirements for the Input port are given in
Table 34. Input Signals (SCLK, FS, SDATA) are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.

Table 34. SPDIF Transmitter Input Data Timing

Parameter Min Max Unit

Timing Requirements
tSIFS1 FS Setup Before SCLK Rising Edge 4 ns
tSIHFS1 FS Hold After SCLK Rising Edge 5.5 ns
tSISD1 SData Setup Before SCLK Rising Edge 4 ns
tSIHD1 SData Hold After SCLK Rising Edge 5.5 ns
tSISCLKW Clock Width 36 ns
tSISCLK Clock Period 80 ns
tSITXCLKW Transmit Clock Width 9 ns
tSITXCLK Transmit Clock Period 20 ns
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

tSITXCLKW
SAMPLE EDGE tSITXCLK
DAI_P20-1
(TXCLK)

tSISCLKW
DAI_P20-1
(SCLK)

tSISFS tSIHFS
DAI_P20-1
(FS)

tSISD tSIHD
DAI_P20-1
(SDATA)

Figure 29. SPDIF Transmitter Input Timing

Over Sampling Clock (TXCLK) Switching Characteristics

The SPDIF transmitter has an over sampling clock. This
TXCLK input is divided down to generate the biphase clock.

Table 35. Over Sampling Clock (TXCLK) Switching Characteristics

Parameter Min Max Unit

TXCLK Frequency for TXCLK = 768 × FS 147.5 MHz
TXCLK Frequency for TXCLK = 512 × FS 98.4 MHz
TXCLK Frequency for TXCLK = 384 × FS 73.8 MHz
TXCLK Frequency for TXCLK = 256 × FS 49.2 MHz
Frame Rate 192.0 kHz
ADSP-21369 Preliminary Technical Data
SPDIF Receiver
The following section describes timing as it relates to the SPDIF
receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × Fs clock.

Table 36. SPDIF Receiver Internal Digital PLL Mode Timing

Parameter Min Max Unit

Switching Characteristics
tDFSI LRCLK Delay After SCLK 5 ns
tHOFSI LRCLK Hold After SCLK –2 ns
tDDTI Transmit Data Delay After SCLK 5 ns
tHDTI Transmit Data Hold After SCLK –2 ns
tSCLKIW1 Transmit SCLK Width 40 ns
tCCLK Core Clock Period 5 ns
1
SCLK frequency is 64 x FS where FS = the frequency of LRCLK.

DRIVE EDGE SAMPLE EDGE

tSCLKIW

DAI_P20-1
(SCLK)
tDFSI
tHOFSI
DAI_P20-1
(FS)
tDDTI
tHDTI
DAI_P20-1
(DATA CHANNEL A/B)

Figure 30. SPDIF Receiver Internal Digital PLL Mode Timing

Preliminary Technical Data ADSP-21369
SPI Interface—Master
The ADSP-21369 contains two SPI ports. The primary has dedi-
cated pins and the secondary is available through the DPI. The
timing provided in Table 37 and Table 38 on page 42 applies to
both.

Table 37. SPI Interface Protocol — Master Switching and Timing Specifications

Parameter Min Max Unit

Timing Requirements
tSSPIDM Data Input Valid To SPICLK Edge (Data Input Set-up Time) 8 ns
tHSPIDM SPICLK Last Sampling Edge To Data Input Not Valid 2 ns

Switching Characteristics
tSPICLKM Serial Clock Cycle 8 × tPCLK ns
tSPICHM SErial Clock High Period 4 × tPCLK ns
tSPICLM Serial Clock Low Period 4 × tPCLK – 2 ns
tDDSPIDM SPICLK Edge to Data Out Valid (Data Out Delay Time) 0
tHDSPIDM SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 ns
tSDSCIM FLAG3–0IN (SPI device select) Low to First SPICLK Edge 4 × tPCLK – 2 ns
tHDSM Last SPICLK Edge to FLAG3–0IN High 4 × tPCLK – 1 ns
tSPITDM Sequential Transfer Delay 4 × tPCLK – 1 ns

DPI_P14-1
[FLAG3-0]
(OUTPUT)
t SD SCIM t SPI CH M t SPIC LM t SPIC LK M t HDSM tSPIT DM

DPI_P14-1
[SPICLK]
(CP = 0)
(OUTPUT)
t SPIC LM t SPI CHM

DPI_P14-1
[SPICLK]
(CP = 1)
(OUTPUT)
t DDSPI DM t HDSPIDM

DPI_P14-1
MSB LSB
[MOSI]
(OUTPUT)
t SSPID M
t SSPI DM
CPHASE=1
t HSSPIDM t HSPIDM
DPI_P14-1 MSB LSB
[MISO] VALID VALID
(INPUT)

t DDSPIDM t HDSPIDM

DPI_P14-1 MSB LSB

[MOSI]
(OUTPUT)
t SSPIDM tH SPID M
CPHASE=0

DPI_P14-1 MSB LSB

[MISO] VALID VALID
(INPUT)

Figure 31. SPI Master Timing

ADSP-21369 Preliminary Technical Data
SPI Interface—Slave

Table 38. SPI Interface Protocol —Slave Switching and Timing Specifications

Parameter Min Max Unit

Timing Requirements
tSPICLKS Serial Clock Cycle 4 × tPCLK ns
tSPICHS Serial Clock High Period 2 × tPCLK ns
tSPICLS Serial Clock Low Period 2 × tPCLK – 2 ns
tSDSCO SPIDS Assertion to First SPICLK Edge ns
CPHASE = 0 2 × tPCLK
CPHASE = 1 2 × tPCLK
tHDS Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × tPCLK ns
tSSPIDS Data Input Valid to SPICLK edge (Data Input Set-up Time) 2 ns
tHSPIDS SPICLK Last Sampling Edge to Data Input Not Valid 2 ns
tSDPPW SPIDS Deassertion Pulse Width (CPHASE=0) 2 × tPCLK ns

Switching Characteristics
tDSOE SPIDS Assertion to Data Out Active 0 4 ns
tDSDHI SPIDS Deassertion to Data High Impedance 0 4 ns
tDDSPIDS SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.4 ns
tHDSPIDS SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × tPCLK ns
tDSOV SPIDS Assertion to Data Out Valid (CPHASE=0) 5 × tPCLK ns

DPI_P14-1
[FLAG3-0]
(OUTPUT)

t S PI CH S t S P IC LS t S PI CL KS
DPI_P14-1 tH DS t S DP P W
[SPICLK]
(CP = 0)
(OUTPUT)
t S P IC LS
t S DSCO t SP I CHS
DPI_P14-1
[SPICLK]
(CP = 1)
(OUTPUT) t DS DHI
t DDS P I DS
t DSOE t DDS PI DS
t HDL S BS

DPI_P14-1 MSB LSB

[MOSI]
(OUTPUT)
t HS P I DS
CPHASE=1 t S S P I DS t S S P ID S
DPI_P14-1
MSB LSB
[MISO]
VALID VALID
(INPUT)
t DS OV
t DDSP I DS t HDL S BS
t DS DHI
t DS O E

DPI_P14-1 MSB LSB

[MOSI]
(OUTPUT)
CPHASE=0 t HSP I DS
t S S P I DS
DPI_P14-1
MSB LSB
[MISO]
VALID VALID
(INPUT)

Figure 32. SPI Slave Timing

Preliminary Technical Data ADSP-21369
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing
Figure 33 describes UART port receive and transmit operations. interrupts and the external data operations. These latencies are
The maximum baud rate is SCLK/16. As shown in Figure 33 negligible at the data transmission rates for the UART.
there is some latency between the generation internal UART

DPI_P14-1
[CLKOUT]
(SAMPLE CLOCK)

DPI_P14-1
[RXD] DATA(5–8)
STOP
RECEIVE

INTERNAL
UART RECEIVE UART RECEIVE BIT SET BY DATA STOP;
INTERRUPT CLEARED BY FIFO READ

START
DPI_P14-1
[TXD] DATA(5–8) STOP(1–2)

TRANSMIT

INTERNAL UART TRANSMIT BIT SET BY PROGRAM;

UART TRANSMIT CLEARED BY WRITE TO TRANSMIT
INTERRUPT

Figure 33. UART Port—Receive and Transmit Timing

ADSP-21369 Preliminary Technical Data
TWI Controller Timing
Table 39 and Figure 34 provide timing information for the TWI
interface. Input Signals (SCL, SDA) are routed to the
DPI_P14–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DPI_P14–1 pins.

Table 39. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices1

Parameter Standard-mode Fast-mode Unit

Min Max Min Max
fSCL SCL Clock Frequency 0 100 0 400 kHz
tHDSTA Hold Time (repeated) START Condition. After this
Period, the First Clock Pulse is Generated. 4.0 0.6 µs
tLOW LOW Period of the SCL Clock 4.7 1.3 µs
tHIGH HIGH period of the SCL Clock 4.0 0.6 µs
tSUSTA Set-up time for a repeated START condition 4.7 0.6 µs
tHDDAT Data Hold Time for TWI-bus Devices 0 0 µs
tSUDAT Data Set-up Time 250 100 ns
tSUSTO Set-up Time for STOP Condition 4.0 0.6 µs
tBUF Bus Free Time Between a STOP and START Condition 4.7 1.3 µs
tSP Pulse Width of Spikes Suppressed By the Input Filter n/a n/a 0 50 ns
1
All values referred to VIHmin and VILmax levels. For more information, see Electrical Characteristics on page 16.

DPI_P14-1
SDA

tSUDA T
tHDS TA tBUF
tLOW t SP

DPI_P14-1
SCL
tSUS TA t SUSTO
tHDS TA tHIGH P S
S tH DDA T Sr

Figure 34. Fast and Standard Mode Timing on the TWI Bus
Preliminary Technical Data ADSP-21369
JTAG Test Access Port and Emulation

Table 40. JTAG Test Access Port and Emulation

Parameter Min Max Unit

Timing Requirements
tTCK TCK Period tCK ns
tSTAP TDI, TMS Setup Before TCK High 5 ns
tHTAP TDI, TMS Hold After TCK High 6 ns
tSSYS1 System Inputs Setup Before TCK High 7 ns
1
tHSYS System Inputs Hold After TCK High 18 ns
tTRSTW TRST Pulse Width 4tCK ns

Switching Characteristics
tDTDO TDO Delay from TCK Low 7 ns
2
tDSYS System Outputs Delay After TCK Low tCK ÷ 2 + 7 ns
1
System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.
2
System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.

tTCK
TCK

tSTAP tHTAP
TMS
TDI
tDTDO

TDO

tSSYS tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS

Figure 35. IEEE 1149.1 JTAG Test Access Port

ADSP-21369 Preliminary Technical Data
OUTPUT DRIVE CURRENTS CAPACITIVE LOADING
Figure 36 shows typical I-V characteristics for the output driv- Output delays and holds are based on standard capacitive loads:
ers of the ADSP-21369. The curves represent the current drive 30 pF on all pins (see Figure 37). Figure 41 shows graphically
capability of the output drivers as a function of output voltage. how output delays and holds vary with load capacitance. The
graphs of Figure 39, Figure 40, and Figure 41 may not be linear
outside the ranges shown for Typical Output Delay vs. Load
Capacitance and Typical Output Rise Time (20%-80%, V=Min)
vs. Load Capacitance.

TBD
TBD

Figure 36. ADSP-21369 Typical Drive

TEST CONDITIONS
The ac signal specifications (timing parameters) appear
Table 13 on page 21 through Table 40 on page 45. These include Figure 39. Typical Output Rise/Fall Time (20%-80%,
output disable time, output enable time, and capacitive loading. VDDEXT = Max)
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 37.
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 38. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.

TBD
50⍀
TO
OUTPUT 1.5V
PIN

30pF
Figure 40. Typical Output Rise/Fall Time (20%-80%,
VDDEXT =Min)

Figure 37. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

INPUT
TBD
OR 1.5V 1.5V
OUTPUT

Figure 41. Typical Output Delay or Hold vs. Load Capacitance

Figure 38. Voltage Reference Levels for AC Measurements (at Ambient Temperature)

THERMAL CHARACTERISTICS temperature range specified in Recommended Operating Con-

ditions on Page 16.
The ADSP-21369 processor is rated for performance over the
Preliminary Technical Data ADSP-21369
Table 41 and Table 42 airflow measurements comply with Table 41. Thermal Characteristics for 256 Ball SBGA (No
JEDEC standards JESD51-2 and JESD51-6 and the junction-to- thermal vias in PCB)
board measurement complies with JESD51-8. Test board design
complies with JEDEC standards JESD51-9 (SBGA) and JESD51- Parameter Condition Typical Unit
7 (MQFP). The junction-to-case measurement complies with θJA Airflow = 0 m/s 12.5 °C/W
MIL- STD-883. All measurements use a 2S2P JEDEC test board. θJMA Airflow = 1 m/s 10.6 °C/W
To determine the Junction Temperature of the device while on θJMA Airflow = 2 m/s 9.9 °C/W
the application PCB, use: θJC 0.7 °C/W
T J = T CASE + ( Ψ JT × P D ) θJB 5.3 °C/W
ΨJT Airflow = 0 m/s 0.3 °C/W
where: ΨJMT Airflow = 1 m/s 0.3 °C/W
TJ = Junction temperature °C ΨJMT Airflow = 2 m/s 0.3 °C/W
TCASE = Case temperature (°C) measured at the top center of
Table 42. Thermal Characteristics for 208-Lead MQFP
the package
ΨJT = Junction-to-Top (of package) characterization parameter Parameter Condition Typical Unit
is the Typical value from Table 41 and Table 42. θJA Airflow = 0 m/s 25.0 °C/W
PD = Power dissipation (see EE Note #TBD) θJMA Airflow = 1 m/s 22.5 °C/W
Values of θJA are provided for package comparison and PCB θJMA Airflow = 2 m/s 21.6 °C/W
design considerations. θJA can be used for a first order approxi- θJC 9.6 °C/W
mation of TJ by the equation: ΨJT Airflow = 0 m/s 0.7 °C/W
T J = T A + ( θ JA × P D ) ΨJMT Airflow = 1 m/s 0.8 °C/W
ΨJMT Airflow = 2 m/s 0.9 °C/W
where:
TA = Ambient Temperature °C
Values of θJC are provided for package comparison and PCB
design considerations when an external heatsink is required.
Values of θJB are provided for package comparison and PCB
design considerations. Note that the thermal characteristics val-
ues provided in Table 41 and Table 42 are modeled values.
ADSP-21369 Preliminary Technical Data
256-BALL SBGA PINOUT
Table 43. 256-Ball SBGA Pin Assignment (Numerically by Ball Number)

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal
A01 NC B01 DAI5 C01 DAI9 D01 DAI10
A02 TDI B02 SDCLK1 C02 DAI7 D02 DAI6
A03 TMS B03 TRST C03 GND D03 GND
A04 CLK_CFG0 B04 TCK C04 IOVDD D04 IOVDD
A05 CLK_CFG1 B05 BOOTCFG_0 C05 GND D05 GND
A06 EMU B06 BOOTCFG_1 C06 GND D06 IOVDD
A07 DAI4 B07 TDO C07 VDD D07 VDD
A08 DAI1 B08 DAI3 C08 GND D08 GND
A09 DPI14 B09 DAI2 C09 GND D09 IOVDD
A10 DPI12 B10 DPI13 C10 VDD D10 VDD
A11 DPI10 B11 DPI11 C11 GND D11 GND
A12 DPI9 B12 DPI8 C12 GND D12 IOVDD
A13 DPI7 B13 DPI5 C13 VDD D13 VDD
A14 DPI6 B14 DPI4 C14 GND D14 GND
A15 DPI3 B15 DPI1 C15 GND D15 IOVDD
A16 DPI2 B16 RESET C16 VDD D16 GND
A17 CLKOUT B17 DATA30 C17 VDD D17 IOVDD
A18 DATA31 B18 DATA29 C18 VDD D18 GND
A19 NC B19 DATA28 C19 DATA27 D19 DATA26
A20 NC B20 NC C20 NC D20 DATA24
E01 DAI11 F01 DAI14 G01 DAI15 H01 DAI17
E02 DAI8 F02 DAI12 G02 DAI13 H02 DAI16
E03 VDD F03 GND G03 GND H03 VDD
E04 VDD F04 GND G04 IOVDD H04 VDD
E17 GND F17 IOVDD G17 VDD H17 IOVDD
E18 GND F18 GND G18 VDD H18 GND
E19 DATA25 F19 GND G19 DATA22 H19 DATA19
E20 DATA23 F20 DATA21 G20 DATA20 H20 DATA18
J01 DAI19 K01 FLAG0 L01 FLAG2 M01 ACK
J02 DAI18 K02 DAI20 L02 FLAG1 M02 FLAG3
J03 GND K03 GND L03 VDD M03 GND
J04 GND K04 IOVDD L04 VDD M04 GND
Preliminary Technical Data ADSP-21369
Table 43. 256-Ball SBGA Pin Assignment (Numerically by Ball Number) (Continued)

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal
J17 GND K17 VDD L17 VDD M17 IOVDD
J18 GND K18 VDD L18 VDD M18 GND
J19 GND K19 GND L19 DATA15 M19 DATA12
J20 DATA17 K20 DATA16 L20 DATA14 M20 DATA13
N01 RD P01 SDA10 R01 SDWE T01 SDCKE
N02 SDCLK0 P02 WR R02 SDRAS T02 SDCAS
N03 GND P03 VDD R03 GND T03 GND
N04 IOVDD P04 VDD R04 GND T04 IOVDD
N17 GND P17 VDD R17 IOVDD T17 GND
N18 GND P18 VDD R18 GND T18 GND
N19 DATA11 P19 DATA8 R19 DATA6 T19 DATA5
N20 DATA10 P20 DATA9 R20 DATA7 T20 DATA4
U01 MS0 V01 ADDR22 W01 GND Y01 GND
U02 MS1 V02 ADDR23 W02 ADDR21 Y02 NC
U03 VDD V03 VDD W03 ADDR19 Y03 NC
U04 GND V04 GND W04 ADDR20 Y04 ADDR18
U05 IOVDD V05 GND W05 ADDR17 Y05 NC
U06 GND V06 GND W06 ADDR16 Y06 NC
U07 IOVDD V07 GND W07 ADDR15 Y07 XTAL2
U08 VDD V08 VDD W08 ADDR14 Y08 CLKIN
U09 IOVDD V09 GND W09 AVDD Y09 NC
U10 GND V10 GND W10 AVSS Y10 NC
U11 IOVDD V11 GND W11 ADDR13 Y11 NC
U12 VDD V12 VDD W12 ADDR12 Y12 NC
U13 IOVDD V13 IOVDD W13 ADDR10 Y13 ADDR11
U14 IOVDD V14 GND W14 ADDR8 Y14 ADDR9
U15 VDD V15 VDD W15 ADDR5 Y15 ADDR7
U16 IOVDD V16 GND W16 ADDR4 Y16 ADDR6
U17 VDD V17 GND W17 ADDR1 Y17 ADDR3
U18 VDD V18 GND W18 ADDR2 Y18 GND
U19 DATA0 V19 DATA1 W19 ADDR0 Y19 GND
U20 DATA2 V20 DATA3 W20 NC Y20 NC
ADSP-21369 Preliminary Technical Data
208-LEAD MQFP PINOUT
Table 44. 208-Lead MQFP Pin Assignment (Numerically by Lead Number)

Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal
1 VDD 53 VDD 105 VDD 157 VDD
2 DATA28 54 GND 106 GND 158 VDD
3 DATA27 55 IOVDD 107 IOVDD 159 GND
4 GND 56 ADDR0 108 SDCAS 160 VDD
5 IOVDD 57 ADDR2 109 SDRAS 161 VDD
6 DATA26 58 ADDR1 110 SDCKE 162 VDD
7 DATA25 59 ADDR4 111 SDWE 163 TDI
8 DATA24 60 ADDR3 112 WR 164 TRST
9 DATA23 61 ADDR5 113 SDA10 165 TCK
10 GND 62 GND 114 GND 166 GND
11 VDD 63 VDD 115 IOVDD 167 VDD
12 DATA22 64 GND 116 SDCLK0 168 TMS
13 DATA21 65 IOVDD 117 GND 169 CLK_CFG0
14 DATA20 66 ADDR6 118 VDD 170 BOOTCFG0
15 IOVDD 67 ADDR7 119 RD 171 CLK_CFG1
16 GND 68 ADDR8 120 ACK 172 EMU
17 DATA19 69 ADDR9 121 FLAG3 173 BOOTCFG1
18 DATA18 70 ADDR10 122 FLAG2 174 TDO
19 VDD 71 GND 123 FLAG1 175 DAI4
20 GND 72 VDD 124 FLAG0 176 DAI2
21 DATA17 73 GND 125 DAI20 177 DAI3
22 VDD 74 IOVDD 126 GND 178 DAI1
23 GND 75 ADDR11 127 VDD 179 IOVDD
24 VDD 76 ADDR12 128 GND 180 GND
25 GND 77 ADDR13 129 IOVDD 181 VDD
26 DATA16 78 GND 130 DAI19 182 GND
27 DATA15 79 VDD 131 DAI18 183 DPI14
28 DATA14 80 AVSS 132 DAI17 184 DPI13
29 DATA13 81 AVDD 133 DAI16 185 DPI12
30 DATA12 82 GND 134 DAI15 186 DPI11
31 IOVDD 83 CLKIN 135 DAI14 187 DPI10
32 GND 84 XTAL2 136 DAI13 188 DPI9
33 VDD 85 IOVDD 137 DAI12 189 DPI8
34 GND 86 GND 138 VDD 190 DPI7
35 DATA11 87 VDD 139 IOVDD 191 IOVDD
36 DATA10 88 ADDR14 140 GND 192 GND
37 DATA9 89 GND 141 VDD 193 VDD
38 DATA8 90 IOVDD 142 GND 194 GND
39 DATA7 91 ADDR15 143 DAI11 195 DPI6
40 DATA6 92 ADDR16 144 DAI10 196 DPI5
41 IOVDD 93 ADDR17 145 DAI8 197 DPI4
42 GND 94 ADDR18 146 DAI9 198 DPI3
43 VDD 95 GND 147 DAI6 199 DPI1
44 DATA4 96 IOVDD 148 DAI7 200 DPI2
Preliminary Technical Data ADSP-21369
Table 44. 208-Lead MQFP Pin Assignment (Numerically by Lead Number) (Continued)

Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal
45 DATA5 97 ADDR19 149 DAI5 201 CLKOUT
46 DATA2 98 ADDR20 150 IOVDD 202 RESET
47 DATA3 99 ADDR21 151 GND 203 IOVDD
48 DATA0 100 ADDR23 152 VDD 204 GND
49 DATA1 101 ADDR22 153 GND 205 DATA30
50 IOVDD 102 MS1 154 VDD 206 DATA31
51 GND 103 MS0 155 GND 207 DATA29
52 VDD 104 VDD 156 VDD 208 VDD

PACKAGE DIMENSIONS
The ADSP-21369 is available in a 208-lead, Pb-free MQFP pack-
age and 256-ball Pb-free and leaded SBGA packages

A1 CORNER
INDEX AREA
20 18 16 14 12 10 8 6 4 2
19 17 15 13 11 9 7 5 3 1
A
B
A1 BALL C
INDICATOR D
E
F
BOTTOM G
VIEW H
J
27.00 K
TOP VIEW BSC SQ L
M
N
P
R
T
U
V
W
Y

24.13
REF SQ

1.00
0.80
0.60 1.70 MAX
0.70
1.27 0.60
NOM 0.10
0.50
MIN

0.20
COPLANARITY SEATING
PLANE
0.90
DIMENSIONS ARE IN MILLIMETERS AND COMPLY BALL 0.75 0.25 MIN 4X
WITH JEDEC STANDARDS MO-192-BAL-2. DIAMETER
0.60

Figure 42. 256-Lead SBGA, Thermally Enhanced (BP-256)

ADSP-21369 Preliminary Technical Data

30.85
0.75 30.60 SQ
0.60 4.10 30.35
0.45 MAX
208 157
1 156
SEATING
PLANE PIN 1 INDICATOR

28.20
TOP VIEW 28.00 SQ
(PINS DOWN) 27.80

3.60 VIEW A
3.40
52 105
3.20 0.20
53 104
0.09
0.50
0.50 0.27
BSC
0.25 0.17
0.08 MAX (LEAD PITCH)
(LEAD COPLANARITY) (LEAD WIDTH)
VIEW A
ROTATED 90° CCW
NOTES:
1. THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL
POSITION WHEN MEASURED IN THE LATERAL DIRECTION.
2. CENTER DIMENSIONS ARE TYPICAL UNLESS OTHERWISE NOTED.
3. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC
STANDARD MS-029, FA-1.

Figure 43. 208-Lead MQFP (S-208-2)

ORDERING GUIDE

Part Number1, 2 Ambient Temper- On-Chip ROM Operating Voltage Packages

ature Range SRAM (Reserved)3
ADSP-21369KSZ-ENG 0°C to +70°C 2M bit 6M bit 1.2 INT/3.3 EXT V 208-Lead MQFP, Pb-Free
ADSP-21369KBP-ENG 0°C to +70°C 2M bit 6M bit 1.2 INT/3.3 EXT V 256-Ball SBGA, Pb-Bearing
ADSP-21369KBPZ-ENG 0°C to +70°C 2M bit 6M bit 1.2 INT/3.3 EXT V 256-Ball SBGA, Pb-Free
1
B indicates Ball Grid Array package.
2
Z indicates Lead Free package. For more information about lead free package offerings, please visit www.analog.com.
3
The ADSP-21369 processor includes a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details.

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