TSZ121, TSZ122, TSZ124

Datasheet

Very high accuracy (5 µV) zero drift micropower 5 V operational amplifiers

Single (TSZ121)
Features
SC70-5 SOT23-5
• Very high accuracy and stability: offset voltage 5 µV max at 25 °C, 8 µV over full
Dual (TSZ122) temperature range (-40 °C to 125 °C)
• Rail-to-rail input and output
• Low supply voltage: 1.8 - 5.5 V
DFN8 2x2 MiniSO8 SO8 • Low power consumption: 40 µA max. at 5 V
• Gain bandwidth product: 400 kHz
Quad (TSZ124)
• High tolerance to ESD: 4 kV HBM
• Extended temperature range: -40 to 125 °C
• Micro-packages: SC70-5, DFN8 2x2, and QFN16 3x3

QFN16 3x3 TSSOP14

Applications
• Battery-powered applications
• Portable devices
• Signal conditioning
Maturity status link • Medical instrumentation

TSZ121
Description
TSZ122
TSZ124 The TSZ12x series of high precision operational amplifiers offer very low input offset
voltages with virtually zero drift.
TSZ121 is the single version, TSZ122 the dual version, and TSZ124 the quad
Related products version, with pinouts compatible with industry standards.
TSV711 Continuous-time The TSZ12x series offers rail-to-rail input and output, excellent speed/power
precision amplifiers consumption ratio, and 400 kHz gain bandwidth product, while consuming less than
TSV731
40 µA at 5 V. The devices also feature an ultra-low input bias current.
TSZ181 Zero drift 3 MHz These features make the TSZ12x family ideal for sensor interfaces, battery-powered
TSZ182 amplifiers applications and portable applications.

Benefits

Higher accuracy without calibration

Accuracy virtually unaffected by
temperature change

DS9216 - Rev 11 - April 2022 www.st.com

For further information contact your local STMicroelectronics sales office.
 TSZ121, TSZ122, TSZ124
Package pin connections

1 Package pin connections

Figure 1. Pin connections for each package (top view)

SC70-5 SOT23-5

DFN8 2x2 MiniSO8 and SO8

QFN16 3x3 TSSOP14

1. The exposed pads of the DFN8 2x2 and the QFN16 3x3 can be connected to VCC- or left floating.

DS9216 - Rev 11 page 2/37

 TSZ121, TSZ122, TSZ124
Absolute maximum ratings and operating conditions

2 Absolute maximum ratings and operating conditions

Table 1. Absolute maximum ratings (AMR)

Symbol Parameter Value Unit

VCC Supply voltage (1) 6

Vid Differential input voltage (2) ±VCC

V
(VCC-) - 0.2 to
Vin Input voltage (3)
(VCC+) + 0.2

Iin Input current (4) 10 mA

Tstg Storage temperature -65 to 150

°C
Tj Maximum junction temperature 150

SC70-5 205
SOT23-5 250
DFN8 2x2 57
Rthja Thermal resistance junction to ambient (5) (6) MiniSO8 190 °C/W
SO8 125
QFN16 3x3 39
TSSOP14 100

HBM: human body model (7) 4 kV

ESD MM: machine model (8) 300 V

CDM: charged device model (9) 1.5 kV

Latch-up immunity 200 mA

1. All voltage values, except the differential voltage are with respect to the network ground terminal.
2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal.
3. Vcc - Vin must not exceed 6 V, Vin must not exceed 6 V
4. Input current must be limited by a resistor in series with the inputs.
5. Rth are typical values.
6. Short-circuits can cause excessive heating and destructive dissipation.
7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin
combinations with other pins floating.
8. Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two pins of the device
with no external series resistor (internal resistor < 5 Ω), done for all couples of pin combinations with other pins floating.
9. Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to
ground.

Table 2. Operating conditions

Symbol Parameter Value Unit

VCC Supply voltage 1.8 to 5.5

V
Vicm Common mode input voltage range (VCC -) - 0.1 to (VCC +) + 0.1

Toper Operating free air temperature range -40 to 125 °C

DS9216 - Rev 11 page 3/37

 TSZ121, TSZ122, TSZ124
Electrical characteristics

3 Electrical characteristics

Table 3. Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to
VCC/2 (unless otherwise specified)

Symbol Parameter Conditions Min. Typ. Max. Unit

DC performance
T = 25 °C 1 5
Vio Input offset voltage μV
-40 °C < T < 125 °C 8
ΔVio/ΔT Input offset voltage drift (1) -40 °C < T < 125 °C 10 30 nV/°C

T = 25 °C 50 200 (2)
Iib Input bias current (Vout = VCC/2)
-40 °C < T < 125 °C 300 (2)
pA
T = 25 °C 100 400 (2)
Iio Input offset current (Vout = VCC/2)
-40 °C < T < 125 °C 600 (2)
Common mode rejection ratio, 20 T = 25 °C 110 122
CMR log (ΔVicm/ΔVio), Vic = 0 V to VCC,
Vout = VCC/2, RL > 1 MΩ -40 °C < T < 125 °C 110
dB
Large signal voltage gain, Vout = T = 25 °C 118 135
Avd
0.5 V to (VCC - 0.5 V) -40 °C < T < 125 °C 110
T = 25 °C 30
VOH High-level output voltage
-40 °C < T < 125 °C 70
mV
T = 25 °C 30
VOL Low-level output voltage
-40 °C < T < 125 °C 70
T = 25 °C 7 8
Isink (Vout = VCC)
-40 °C < T < 125 °C 6
Iout mA
T = 25 °C 5 7
Isource (Vout = 0 V)
-40 °C < T < 125 °C 4

Supply current (per amplifier, Vout = T = 25 °C 28 40

ICC μA
VCC/2, RL > 1 MΩ) -40 °C < T < 125 °C 40
AC performance
GBP Gain bandwidth product 400
kHz
Fu Unity gain frequency 300

ɸm Phase margin RL = 10 kΩ, CL = 100 pF 55 Degrees

Gm Gain margin 17 dB

SR Slew rate (3) 0.17 V/μs

To 0.1 %, Vin = 1 Vp-p, RL = 10 kΩ, CL =

ts Setting time 50 μs
100 pF
f = 1 kHz 60
en Equivalent input noise voltage nV/√Hz
f = 10 kHz 60
Low-frequency peak-to-peak input
∫en Bandwidth, f = 0.1 to 10 Hz 1.1 µVpp
noise
Cs Channel separation f = 100 Hz 120 dB

T = 25 °C 50
tinit Initialization time μs
-40 °C < T < 125 °C 100

DS9216 - Rev 11 page 4/37

 TSZ121, TSZ122, TSZ124
Electrical characteristics

1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain configuration. The
amplifiers and the gain setting resistors are at the same temperature.
2. Guaranteed by design
3. Slew rate value is calculated as the average between positive and negative slew rates.

Table 4. Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to
VCC/2 (unless otherwise specified)

Symbol Parameter Conditions Min. Typ. Max. Unit

DC performance
T = 25 °C 1 5
Vio Input offset voltage μV
-40 °C < T < 125 °C 8
ΔVio/ΔT Input offset voltage drift (1) -40 °C < T < 125 °C 10 30 nV/°C

T = 25 °C 60 200 (2)
Iib Input bias current (Vout = VCC/2)
-40 °C < T < 125 °C 300 (2)
pA
T = 25 °C 120 400 (2)
Iio Input offset current (Vout = VCC/2)
-40 °C < T < 125 °C 600 (2)
Common mode rejection ratio, 20 T = 25 °C 115 128
CMR log (ΔVicm/ΔVio), Vic = 0 V to VCC,
Vout = VCC/2, RL > 1 MΩ -40 °C < T < 125 °C 115
dB
Large signal voltage gain, Vout = T = 25 °C 118 135
Avd
0.5 V to (VCC - 0.5 V) -40 °C < T < 125 °C 110
T = 25 °C 30
VOH High-level output voltage
-40 °C < T < 125 °C 70
mV
T = 25 °C 30
VOL Low-level output voltage
-40 °C < T < 125 °C 70
T = 25 °C 15 18
Isink (Vout = VCC)
-40 °C < T < 125 °C 12
Iout mA
T = 25 °C 14 16
Isource (Vout = 0 V)
-40 °C < T < 125 °C 10

Supply current (per amplifier, Vout = T = 25 °C 29 40

ICC μA
VCC/2, RL > 1 MΩ) -40 °C < T < 125 °C 40
AC performance
GBP Gain bandwidth product 400
kHz
Fu Unity gain frequency 300

ɸm Phase margin RL = 10 kΩ, CL = 100 pF 56 Degrees

Gm Gain margin 19 dB

SR Slew rate (3) 0.19 V/μs

To 0.1 %, Vin = 1 Vp-p, RL = 10 kΩ, CL =

ts Setting time 50 μs
100 pF
f = 1 kHz 40
en Equivalent input noise voltage nV/√Hz
f = 10 kHz 40
Low-frequency peak-to-peak input
∫en Bandwidth, f = 0.1 to 10 Hz 0.8 µVpp
noise
Cs Channel separation f = 100 Hz 120 dB

DS9216 - Rev 11 page 5/37

 TSZ121, TSZ122, TSZ124
Electrical characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

T = 25 °C 50
tinit Initialization time μs
-40 °C < T < 125 °C 100

1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain configuration. The
amplifiers and the gain setting resistors are at the same temperature.
2. Guaranteed by design
3. Slew rate value is calculated as the average between positive and negative slew rates.

Table 5. Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to
VCC/2 (unless otherwise specified)

Symbol Parameter Conditions Min. Typ. Max. Unit

DC performance
T = 25 °C 1 5
Vio Input offset voltage μV
-40 °C < T < 125 °C 8
ΔVio/ΔT Input offset voltage drift (1) -40 °C < T < 125 °C 10 30 nV/°C

T = 25 °C 70 200 (2)
Iib Input bias current (Vout = VCC/2)
-40 °C < T < 125 °C 300 (2)
pA
T = 25 °C 140 400 (2)
Iio Input offset current (Vout = VCC/2)
-40 °C < T < 125 °C 600 (2)
Common mode rejection ratio, 20 T = 25 °C 115 136
CMR log (ΔVicm/ΔVio), Vic = 0 V to VCC,
Vout = VCC/2, RL > 1 MΩ -40 °C < T < 125 °C 115

Supply voltage rejection ratio, 20 T = 25 °C 120 140

SVR log (ΔVCC/ΔVio), VCC = 1.8 V to 5.5
V, Vout = VCC/2, RL > 1 MΩ -40 °C < T < 125 °C 120

Large signal voltage gain, Vout = T = 25 °C 120 135

Avd dB
0.5 V to (VCC - 0.5 V) -40 °C < T < 125 °C 110
VRF = 100 mVp, f = 400 MHz 84

EMI rejection rate = -20 log VRF = 100 mVp, f = 900 MHz 87
EMIRR (3) (VRFpeak/ΔVio) VRF = 100 mVp, f = 1800 MHz 90

VRF = 100 mVp, f = 2400 MHz 91

T = 25 °C 30
VOH High-level output voltage
-40 °C < T < 125 °C 70
mV
T = 25 °C 30
VOL Low-level output voltage
-40 °C < T < 125 °C 70
T = 25 °C 15 18
Isink (Vout = VCC)
-40 °C < T < 125 °C 14
Iout mA
T = 25 °C 14 17
Isource (Vout = 0 V)
-40 °C < T < 125 °C 12

Supply current (per amplifier, Vout = T = 25 °C 31 40

ICC μA
VCC/2, RL > 1 MΩ) -40 °C < T < 125 °C 40
AC performance
GBP Gain bandwidth product 400
RL = 10 kΩ, CL = 100 pF kHz
Fu Unity gain frequency 300

DS9216 - Rev 11 page 6/37

 TSZ121, TSZ122, TSZ124
Electrical characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

ɸm Phase margin 53 Degrees

Gm Gain margin RL = 10 kΩ, CL = 100 pF 19 dB

SR Slew rate (4) 0.19 V/μs

To 0.1 %, Vin = 100 mVp-p, RL = 10 kΩ, CL

ts Setting time 10 μs
= 100 pF
f = 1 kHz 37
en Equivalent input noise voltage nV/√Hz
f = 10 kHz 37
Low-frequency peak-to-peak input
∫en Bandwidth, f = 0.1 to 10 Hz 0.75 µVpp
noise
Cs Channel separation f = 100 Hz 120 dB

T = 25 °C 50
tinit Initialization time μs
-40 °C < T < 125 °C 100

1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain configuration. The
amplifiers and the gain setting resistors are at the same temperature.
2. Guaranteed by design
3. Tested on SC70-5 package
4. Slew rate value is calculated as the average between positive and negative slew rates.

DS9216 - Rev 11 page 7/37

 TSZ121, TSZ122, TSZ124
Electrical characteristic curves

4 Electrical characteristic curves

Figure 2. Supply current vs. supply voltage Figure 3. Input offset voltage distribution at VCC = 5 V
40
60

35
T=-40°C 50 T=25°C
30 Vcc=5V,
T=25°C
Supply Current (µA)

Vicm=2.5V
40
25

Population
20 T=125°C 30

15
20

10
10
5
VICM=VCC/2
0
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -5 -4 -3 -2 -1 0 1 2 3 4 5
Supply voltage (V) Input offset voltage (µV)

Figure 4. Input offset voltage distribution at VCC = 3.3 V Figure 5. Input offset voltage distribution at VCC = 1.8 V

60 60

50 T=25°C 50 T=25°C
Vcc=3.3V, Vcc=1.8V,
Vicm=1.65V Vicm=0.6V
40 40
Population
Population

30 30

20 20

10 10

0 0
-5 -4 -3 -2 -1 0 1 2 3 4 5 -5 -4 -3 -2 -1 0 1 2 3 4 5
Input offset voltage (µV) Input offset voltage (µV)

Figure 6. Vio temperature co-efficient distribution Figure 7. Vio temperature co-efficient distribution
(-40 °C to 25 °C) (25 °C to 125 °C)

60 60

T=-40°C to 25°C 50
T=25°C to 125°C
50
Vcc=5V, Vcc=5V,
Vicm=2.5V Vicm=2.5V
40 40
Population
Population

30 30

20 20

10 10

0 0
-0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 0.015 0.020 0.025 0.030 -0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 0.015 0.020 0.025 0.030
Input offset voltage drift [µV/°C] Input offset voltage drift [µV/°C]

DS9216 - Rev 11 page 8/37

 TSZ121, TSZ122, TSZ124
Electrical characteristic curves

Figure 9. Input offset voltage vs. input common-mode at

Figure 8. Input offset voltage vs. supply voltage
VCC = 1.8 V
5
5
4
4
3
3 T=125°C
T=125°C
2
2
1
1
Vio (µV)

Vio (µV)
0 T=-40°C
0
-1
T=25°C -1
T=-40°C T=25°C
-2
-2
-3
-3
-4 Vicm=Vcc/2
-4 Vcc=1.8V
-5
2.0 2.3 2.5 2.8 3.0 3.3 3.5 3.8 4.0 4.3 4.5 4.8 5.0 -5
Vcc(V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Vicm (V)

Figure 10. Input offset voltage vs. input common-mode at Figure 11. Input offset voltage vs. input common-mode at
VCC = 2.7 V VCC = 5.5 V

5 5
4 4
3 3
3 3
T=125°C 2 T=125°C
2
1 1
Vio (µV)
Vio (µV)

T=25°C 0 T=25°C
0
-1 -1
-2 T=-40°C -2 T=-40°C
-3 -3
-3 -3
-4 Vcc=2.7V -4 Vcc=5.5V
-5 -5
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6

Vicm (V) Vicm (V)

Figure 12. Input offset voltage vs. temperature Figure 13. VOH vs. supply voltage

10 20
Output swing (mV from Vcc+)

8 Limit for TSZ121 18

6
15
Input offset voltage (µV)

4
T=25°C
2 13
T=125°C
0 10
-2
8 T=-40°C
-4
-6 5

-8 Vcc=5V, Vicm=2.5V 3 Rl=10kΩ

-10 Vicm=Vcc/2
-40 -20 0 20 40 60 80 100 120 0
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4
Temperature (°C) Vcc (V)

DS9216 - Rev 11 page 9/37

 TSZ121, TSZ122, TSZ124
Electrical characteristic curves

Figure 14. VOL vs. supply voltage Figure 15. Output current vs. output voltage at VCC = 1.8 V

20 30
Output swing (mV from Vcc-)

18
20

Output Current (mA)

15 T=25°C
T=-40°C
10
13
T=125°C T=125°C
10 0 T=125°C
T=25°C T=25°C
8
T=-40°C -10
T=-40°C
5
-20
3 Rl=10kΩ
Vicm=Vcc/2 Vcc=1.8V
0 -30
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 0.0 0.3 0.5 0.8 1.0 1.3 1.5 1.8
Vcc (V) Output Voltage (V)

Figure 17. Input bias current vs. common mode at

Figure 16. Output current vs. output voltage at VCC = 5.5 V
VCC = 5 V
30 100
T=-40°C T=25°C
20 75
Output Current (mA)

50
10 T=125°C IiBp
25
IiB (pA)

0
0

-10 T=25°C T=125°C -25

IiBn
-50
-20
T=-40°C -75 Vcc=5V
Vcc=5.5V T=25°C
-30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage (V)
Common Mode Voltage (V)

Figure 18. Input bias current vs. common mode at

Figure 19. Input bias current vs. temperature at VCC = 5 V
VCC = 1.8 V

100 100

75
75
50
50 IiBp
25
25 IiBp
IiB (pA)
IiB (pA)

0
0
-25
-25
IiBn
-50 IiBn
-50
-75
-75 Vcc=1.8V Vcc=5V
T=25°C -100
-100 -25 0 25 50 75 100 125
0.0 0.3 0.5 0.8 1.0 1.3 1.5 1.8 Temperature (°C)
Common Mode Voltage (V)

DS9216 - Rev 11 page 10/37

 TSZ121, TSZ122, TSZ124
Electrical characteristic curves

Figure 20. Bode diagram at VCC = 1.8 V Figure 21. Bode diagram at VCC = 2.7 V

250 250

40 200 40 200
Gain Gain
T=-40°C 150 T=-40°C 150

20 100 20 100
T=25°C T=25°C
T=125°C

Gain (dB)
T=125°C 50
Gain (dB)

50

Phase (°)
Phase (°)
0 0 0 0

-50 -50

-20 Phase -100 -20 Phase -100

-150 -150
Vcc=1.8V, Vicm=0.9V, G=-100 Vcc=2.7V, Vicm=1.35V, G=-100
-40 Rl=10kΩ, Cl=100pF, Vrl=Vcc/2 -200 -40 Rl=10kΩ, Cl=100pF, Vrl=Vcc/2 -200

-250 -250
1 10 100 1000 1 10 100 1000
Frequency (kHz) Frequency (kHz)

Figure 22. Bode diagram at VCC = 5.5 V Figure 23. Open loop gain vs. frequency
250 100 100

40 200
Gain 80 Phase 80
T=-40°C 150

20 100
T=25°C 60 60

Phase (°)
T=125°C
Gain (dB)

Gain (dB)

50
Phase (°)

0 0
Gain
40 40

-50
20 20
-20 Phase -100

-150
Vcc=5.5V, Vicm=2.75V, G=-100 0
Vcc=5V, Vicm=2.5V,
0
-40 Rl=10kΩ, Cl=100pF, Vrl=Vcc/2 -200
Rl=10k Ω, Cl=100pF
-250 -20 -20
1 10 100 1000 0.01 0.1 1 10 100 1000

Frequency (kHz) Frequency (kHz)

Figure 24. Positive slew rate vs. supply voltage Figure 25. Negative slew rate vs. supply voltage
0.3 0.0
Negative Slew Rate (V/µs)
Positive Slew Rate (V/µs)

T=125°C

0.2 -0.1
T=-40°C
T=25°C
T=-40°C T=25°C

0.1 T=125°C -0.2

Rl=10kΩ, Cl=100pF Rl=10kΩ, Cl=100pF

Vin: from 0.3V to Vcc-0.3V Vin: from Vcc-0.3V to 0.3V
SR calculated from 10% to 90% SR calculated from 10% to 90%
0.0 -0.3
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V) Supply Voltage (V)

DS9216 - Rev 11 page 11/37

 TSZ121, TSZ122, TSZ124
Electrical characteristic curves

Figure 26. 0.1 Hz to 10 Hz noise Figure 27. Noise vs. frequency

55

Equivalent Input Voltage Noise (nV/√Hz)

200
50 180
45
noise density (nV/√Hz)

160
40 140 Vicm=Vcc/2
Tamb=25°C
35 120

30 100
80 Vcc=1.8V
25 Vcc=3.3V
60
20 Vcc = 5.5V
40
15 Vicm=Vcc/2 Noise 0.1Hz_10Hz
T=25°C equivalent to 0.75 µVpp 20 Vcc=5.5V
10
100m 1 10 100 1k 10k
Frequency (Hz) Frequency (Hz)

Figure 28. Noise vs. frequency and temperature Figure 29. Output overshoot vs. load capacitance
40
Equivalent Input Voltage Noise (nV/√Hz)

200
180 35
160
30
140 Vicm=Vcc/2
Overshoot (%)

Vcc=5.5V 25
120
100 20

80 15
25°C 125°C
60
10
40 Vcc=5.5V
5 100mVpp
20 -40°C Rl=10kΩ
100 1k 10k 0
10 100 1000
Frequency (Hz)
Load capacitance (pF)

Figure 30. Small signal Figure 31. Large signal

0.10

2.00
0.05
Output Voltage (V)
Output Voltage (V)

0.00 0.00

Vcc = 5.5V
Rl=10kΩ
Vcc = 5.5V
-0.05 Cl=100pF
Rl=10kΩ
-2.00 T=25°C
Cl=100pF
T=25°C

-0.10
-100 0 100 200 300 400 500 600
-10 0 10 20 30
Time (µs)
Time (µs)

DS9216 - Rev 11 page 12/37

 TSZ121, TSZ122, TSZ124
Electrical characteristic curves

Figure 32. Positive overvoltage recovery at VCC = 1.8 V Figure 33. Positive overvoltage recovery at VCC = 5 V

1.0 1.0
0.00 0.00
0.5
0.5 Vin Vin
0.0
-0.05 -0.05
0.0
-0.5 Vout
Vout

Vout (V)
Vout (V)

Vin (V)
Vin (V)
-0.5 -1.0
-0.10 -0.10

-1.5
-1.0

-0.15 -2.0 -0.15

-1.5
Vcc=1.8V, Vicm=0.9V, G=101 -2.5 Vcc=5.5V, Vicm=2.75V, G=101
Rl=10kΩ, Cl=100pF Rl=10kΩ, Cl=100pF
-2.0 -0.20 -3.0 -0.20
-100µ -50µ 0 50µ 100µ 150µ 200µ 250µ 300µ 350µ 400µ -100µ -50µ 0 50µ 100µ 150µ 200µ 250µ 300µ 350µ 400µ
Time (s) Time (s)

Figure 34. Negative overvoltage recovery at VCC = 1.8 V Figure 35. Negative overvoltage recovery at VCC = 5 V

1.0 0.20 3.0 0.20

0.15 2.5 0.15

0.5 0.10 2.0 0.10

Vout Vout
Vin 0.05 1.5 Vin 0.05
Vout (V)

Vout (V)
Vin (V)

Vin (V)
0.0 0.00 1.0 0.00

-0.05 0.5 -0.05

-0.5 -0.10 0.0 -0.10

Vcc=1.8V, Vicm=0.9V, G=101 -0.15 -0.5 Vcc=5.5V, Vicm=2.75V, G=101 -0.15

Rl=10kΩ, Cl=100pF Rl=10kΩ , Cl=100pF
-1.0 -0.20 -1.0 -0.20
-100µ -50µ 0 50µ 100µ 150µ 200µ 250µ 300µ 350µ 400µ -100µ -50µ 0 50µ 100µ 150µ 200µ 250µ 300µ 350µ 400µ
Time (s) Time (s)

Figure 36. PSRR vs. frequency Figure 37. Output impedance vs. frequency
-100
2000
1800 Vcc=2.7V to 5.5V
+PSRR
-80 1600 Osc level=30mVRMS
Output Impedance (Ω)

G=1
1400 Ta=25°C
PSRR (dB)

-60 1200
1000
-PSRR
-40 800
600
-20 400
Vcc=5.5V, Vicm=2.75V, G=1 200
Rl=10kΩ, Cl=100pF, Vripple=100mVpp
0
10 100 1000 10000 100000 1000000 100 1k 10k 100k 1M
Frequency (Hz) Frequency (Hz)

DS9216 - Rev 11 page 13/37

 TSZ121, TSZ122, TSZ124
Application information

5 Application information

5.1 Operation theory

The TSZ121, TSZ122, and TSZ124 are high precision CMOS devices. They achieve a low offset drift and no
1/f noise thanks to their chopper architecture. Chopper-stabilized amps constantly correct low-frequency errors
across the inputs of the amplifier.
Chopper-stabilized amplifiers can be explained with respect to:
• Time domain
• Frequency domain

5.1.1 Time domain

The basis of the chopper amplifier is realized in two steps. These steps are synchronized thanks to a clock
running at 400 kHz.

Figure 38. Block diagram in the time domain (step 1)

Chop 1 Chop 2
Vinp
Vinn A1(f) A2(f) Filter Vo ut

Figure 39. Block diagram in the time domain (step 2)

Chop 1 Chop 2
Vinp
A1(f) A2 (f) Filter Vo ut
Vinn

Figure 38. Block diagram in the time domain (step 1) shows step 1, the first clock cycle, where Vio is amplified in
the normal way.
Figure 39. Block diagram in the time domain (step 2) shows step 2, the second clock cycle, where Chop1 and
Chop2 swap paths. At this time, the Vio is amplified in a reverse way as compared to step 1.
At the end of these two steps, the average Vio is close to zero.
The A2(f) amplifier has a small impact on the Vio because the Vio is expressed as the input offset and is
consequently divided by A1(f).
In the time domain, the offset part of the output signal before filtering is shown in Figure 40. Vio cancellation
principle.

Figure 40. Vio cancellation principle

Step 1 Step 1 S tep 1

Vio
Time
Vio

Step 2 Step 2 S tep 2

DS9216 - Rev 11 page 14/37

 TSZ121, TSZ122, TSZ124
Operating voltages

The low pass filter averages the output value resulting in the cancellation of the Vio offset.
The 1/f noise can be considered as an offset in low frequency and it is canceled like the Vio, thanks to the chopper
technique.

5.1.2 Frequency domain

The frequency domain gives a more accurate vision of chopper-stabilized amplifier architecture.

Figure 41. Block diagram in the frequency domain

Vinn
Chop1 Chop2 A(f) Filter Vout
A(f)
Vi np

Vos + Vn

1 2 3 4

The modulation technique transposes the signal to a higher frequency where there is no 1/f noise, and
demodulate it back after amplification.
1. According to Figure 41. Block diagram in the frequency domain, the input signal Vin is modulated once
(Chop1) so all the input signal is transposed to the high frequency domain.
2. The amplifier adds its own error (Vio (output offset voltage) + the noise Vn (1/f noise)) to this modulated
signal.
3. This signal is then demodulated (Chop2), but since the noise and the offset are modulated only once, they
are transposed to the high frequency, leaving the output signal of the amplifier without any offset and low
frequency noise. Consequently, the input signal is amplified with a very low offset and 1/f noise.
4. To get rid of the high frequency part of the output signal (which is useless) a low pass filter is implemented.
To further suppress the remaining ripple down to a desired level, another low pass filter may be added externally
on the output of the TSZ121, TSZ122, or TSZ124 device.

5.2 Operating voltages

TSZ121, TSZ122, and TSZ124 devices can operate from 1.8 to 5.5 V. The parameters are fully specified for 1.8
V, 3.3 V, and 5 V power supplies. However, the parameters are very stable in the full VCC range and several
characterization curves show the TSZ121, TSZ122, and TSZ124 device characteristics at 1.8 V and 5.5 V.
Additionally, the main specifications are guaranteed in extended temperature ranges from -40 to 125 ° C.

5.3 Input pin voltage ranges

TSZ121, TSZ122, and TSZ124 devices have internal ESD diode protection on the inputs. These diodes are
connected between the input and each supply rail to protect the input MOSFETs from electrical discharge.
If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become conductive and excessive
current can flow through them. Without limitation this over current can damage the device.
In this case, it is important to limit the current to 10 mA, by adding resistance on the input pin, as described in
Figure 42. Input current limitation.

DS9216 - Rev 11 page 15/37

 TSZ121, TSZ122, TSZ124
Rail-to-rail input

Figure 42. Input current limitation

TSZ121, TSZ122, TSZ124

5V

R - +
Vout
Vin + -

5.4 Rail-to-rail input

TSZ121, TSZ122, and TSZ124 devices have a rail-to-rail input, and the input common mode range is extended
from (VCC -) - 0.1 V to (VCC+) + 0.1 V.

5.5 Input offset voltage drift over temperature

The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset
value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and
the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be
compensated during production at application level. The maximum input voltage drift over temperature enables
the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
Equation 1

∆V io V ( T ) – V io ( 25 °C)
= ma x io
∆T T – 25 °C
Where T = -40 °C and 125 °C.
The TSZ121, TSZ122, and TSZ124 datasheet maximum value is guaranteed by measurements on a
representative sample size ensuring a Cpk (process capability index) greater than 1.3.

5.6 Rail-to-rail output

The operational amplifier output levels can go close to the rails: to a maximum of 30 mV above and below the rail
when connected to a 10 kΩ resistive load to VCC/2.

5.7 Capacitive load

Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain
peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that
with a gain peaking higher than 2.3 dB an op amp might become unstable.
Generally, the unity gain configuration is the worst case for stability and the ability to drive large capacitive loads.
Figure 43. Stability criteria with a serial resistor at VDD = 5 V and Figure 44. Stability criteria with a serial resistor
at VDD = 1.8 V show the serial resistor that must be added to the output, to make a system stable. Figure 45. Test
configuration for Riso shows the test configuration using an isolation resistor, Riso.

DS9216 - Rev 11 page 16/37

 TSZ121, TSZ122, TSZ124
PCB layout recommendations

Figure 43. Stability criteria with a serial resistor at Figure 44. Stability criteria with a serial resistor at
VDD = 5 V VDD = 1.8 V

Figure 45. Test configuration for Riso

+VCC

- Riso
VOUT
VIN +
Cload 10 kΩ
-VCC

5.8 PCB layout recommendations

Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier, load, and power
supply. The power and ground traces are critical as they must provide adequate energy and grounding for all
circuits. Good practice is to use short and wide PCB traces to minimize voltage drops and parasitic inductance.
In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that connects the
bottom and top layer ground planes together in many locations is often used.
The copper traces that connect the output pins to the load and supply pins should be as wide as possible to
minimize trace resistance.

5.9 Optimized application recommendation

TSZ121, TSZ122, and TSZ124 devices are based on chopper architecture. As they are switched devices, it is
strongly recommended to place a 0.1 µF capacitor as close as possible to the supply pins.
A good decoupling has several advantages for an application. First, it helps to reduce electromagnetic
interference. Due to the modulation of the chopper, the decoupling capacitance also helps to reject the small
ripple that may appear on the output.
TSZ121, TSZ122, and TSZ124 devices have been optimized for use with 10 kΩ in the feedback loop. With this, or
a higher value of resistance, these devices offer the best performance.

5.10 EMI rejection ration (EMIRR)

The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF
signal rectification.
The TSZ121, TSZ122, and TSZ124 have been specially designed to minimize susceptibility to EMIRR and show
an extremely good sensitivity. Figure 46. EMIRR on IN+ pin shows the EMIRR IN+ of the TSZ121, TSZ122, and
TSZ124 measured from 10 MHz up to 2.4 GHz.

DS9216 - Rev 11 page 17/37

 TSZ121, TSZ122, TSZ124
Application examples

Figure 46. EMIRR on IN+ pin

120

100

EMIRR In+(dB)
80

60

40

20
Vcc=5.5V, G=1
Prf=-10dBm
0
10 100 1000
Frequency (MHz)

5.11 Application examples

5.11.1 Oxygen sensor

The electrochemical sensor creates a current proportional to the concentration of the gas being measured. This
current is converted into voltage thanks to R resistance. This voltage is then amplified by TSZ121, TSZ122, and
TSZ124 devices (see Figure 47. Oxygen sensor principle schematic).

Figure 47. Oxygen sensor principle schematic

R1 R2

VCC
I +
-
Vout
O2_ sensor +
-
TSZ121, TSZ122, TSZ124

The output voltage is calculated using Equation 2:

Equation 2
R2
V ou t = ( I × R – V io ) × +1
R1

As the current delivered by the O2 sensor is extremely low, the impact of the Vio can become significant with a
traditional operational amplifier. The use of the chopper amplifier of the TSZ121, TSZ122, or TSZ124 is perfect for
this application.
In addition, using TSZ121, TSZ122, or TSZ124 devices for the O2 sensor application ensures that the
measurement of O2 concentration is stable even at different temperature thanks to a very good ΔVio/ΔT.

5.11.2 Precision instrumentation amplifier

The instrumentation amplifier uses three op amps. The circuit, shown in Figure 48. Precision instrumentation
amplifier schematic, exhibits high input impedance, so that the source impedance of the connected sensor has no
impact on the amplification.

DS9216 - Rev 11 page 18/37

 TSZ121, TSZ122, TSZ124
Application examples

Figure 48. Precision instrumentation amplifier schematic

TSZ12x R2 R4
V1 +
-

Rf
TSZ12x
-
Rg + Vout
Rf

R1 R3
-
+
V2
TSZ12x

The gain is set by tuning the Rg resistor. With R1 = R2 and R3 = R4, the output is given by
Section 5.11.2 Equation 3.
Equation 3
R4 2Rf
Vout = V2 − V1 R2 ⋅ Rg + 1
The matching of R1, R2 and R3, R4 is important to ensure a good common mode rejection ratio (CMR).

5.11.3 Low-side current sensing

Power management mechanisms are found in most electronic systems. Current sensing is useful for protecting
applications. The low-side current sensing method consists of placing a sense resistor between the load and
the circuit ground. The resulting voltage drop is amplified using TSZ121, TSZ122, and TSZ124 devices (see
Figure 49. Low-side current sensing schematic).

Figure 49. Low-side current sensing schematic

C1

Rg1 Rf1

I
In 5V
Rshunt - +
Vout
+ -
Ip TSZ121, TSZ122, TSZ124
Rg2

Rf2

Vout can be expressed as follows:

Equation 4

R g2 R f1 R g2 × R f2 R f1 R f1
V ou t = R shun t × I 1 – 1+ + Ip × 1+ – l n × R f1 – V io 1 +
R g2 + R f2 R g1 R g2 + R f2 R g1 R g1

Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, Equation 4 can be simplified as follows:
Equation 5
Rf Rf
V out = R shunt × I – V io 1 + + R f × I io
Rg Rg

The main advantage of using the chopper of the TSZ121, TSZ122, and TSZ124, for a low-side current sensing, is
that the errors due to Vio and Iio are extremely low and may be neglected.

DS9216 - Rev 11 page 19/37

 TSZ121, TSZ122, TSZ124
Application examples

Therefore, for the same accuracy, the shunt resistor can be chosen with a lower value, resulting in lower power
dissipation, lower drop in the ground path, and lower cost.
Particular attention must be paid on the matching and precision of Rg1, Rg2, Rf1, and Rf2, to maximize the
accuracy of the measurement.

DS9216 - Rev 11 page 20/37

 TSZ121, TSZ122, TSZ124
Package information

6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

DS9216 - Rev 11 page 21/37

 TSZ121, TSZ122, TSZ124
SC70-5 (or SOT323-5) package information

6.1 SC70-5 (or SOT323-5) package information

Figure 50. SC70-5 (or SOT323-5) package outline

SIDE VIEW
DIMENSIONS IN MM

GAUGE PLANE

COPLANAR LEADS

SEATING PLANE

TOP VIEW

Table 6. SC70-5 (or SOT323-5) mechanical data

Dimensions

Ref. Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 0.80 1.10 0.032 0.043

A1 0.10 0.004
A2 0.80 0.90 1.00 0.032 0.035 0.039
b 0.15 0.30 0.006 0.012
c 0.10 0.22 0.004 0.009
D 1.80 2.00 2.20 0.071 0.079 0.087
E 1.80 2.10 2.40 0.071 0.083 0.094
E1 1.15 1.25 1.35 0.045 0.049 0.053
e 0.65 0.025
e1 1.30 0.051
L 0.26 0.36 0.46 0.010 0.014 0.018
< 0° 8° 0° 8°

DS9216 - Rev 11 page 22/37

 TSZ121, TSZ122, TSZ124
SOT23-5 package information

6.2 SOT23-5 package information

Figure 51. SOT23-5 package outline

Table 7. SOT23-5 mechanical data

Dimensions

Ref. Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 0.90 1.20 1.45 0.035 0.047 0.057

A1 0.15 0.006
A2 0.90 1.05 1.30 0.035 0.041 0.051
B 0.35 0.40 0.50 0.014 0.016 0.020
C 0.09 0.15 0.20 0.004 0.006 0.008
D 2.80 2.90 3.00 0.110 0.114 0.118
D1 1.90 0.075
e 0.95 0.037
E 2.60 2.80 3.00 0.102 0.110 0.118
F 1.50 1.60 1.75 0.059 0.063 0.069
L 0.10 0.35 0.60 0.004 0.014 0.024
K 0 degrees 10 degrees 0 degrees 10 degrees

DS9216 - Rev 11 page 23/37

 TSZ121, TSZ122, TSZ124
DFN8 2 x 2 package information

6.3 DFN8 2 x 2 package information

Figure 52. DFN8 2 x 2 package outline

Table 8. DFN8 2 x 2 mechanical data

Dimensions

Ref. Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 0.51 0.55 0.60 0.020 0.022 0.024

A1 0.05 0.002
A3 0.15 0.006
b 0.18 0.25 0.30 0.007 0.010 0.012
D 1.85 2.00 2.15 0.073 0.079 0.085
D2 1.45 1.60 1.70 0.057 0.063 0.067
E 1.85 2.00 2.15 0.073 0.079 0.085
E2 0.75 0.90 1.00 0.030 0.035 0.039
e 0.50 0.020
L 0.225 0.325 0.425 0.009 0.013 0.017
ddd 0.08 0.003

DS9216 - Rev 11 page 24/37

 TSZ121, TSZ122, TSZ124
DFN8 2 x 2 package information

Figure 53. DFN8 2 x 2 recommended footprint

DS9216 - Rev 11 page 25/37

 TSZ121, TSZ122, TSZ124
MiniSO8 package information

6.4 MiniSO8 package information

Figure 54. MiniSO8 package outline

Table 9. MiniSO8 package mechanical data

Dimensions

Ref. Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 1.1 0.043
A1 0 0.15 0 0.0006
A2 0.75 0.85 0.95 0.030 0.033 0.037
b 0.22 0.40 0.009 0.016
c 0.08 0.23 0.003 0.009
D 2.80 3.00 3.20 0.11 0.118 0.126
E 4.65 4.90 5.15 0.183 0.193 0.203
E1 2.80 3.00 3.10 0.11 0.118 0.122
e 0.65 0.026
L 0.40 0.60 0.80 0.016 0.024 0.031
L1 0.95 0.037
L2 0.25 0.010
k 0° 8° 0° 8°
ccc 0.10 0.004

DS9216 - Rev 11 page 26/37

 TSZ121, TSZ122, TSZ124
SO8 package information

6.5 SO8 package information

Figure 55. SO8 package outline

Table 10. SO8 package mechanical data

Dimensions

Ref. Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 1.75 0.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.010
D 4.80 4.90 5.00 0.189 0.193 0.197
E 5.80 6.00 6.20 0.228 0.236 0.244
E1 3.80 3.90 4.00 0.150 0.154 0.157
e 1.27 0.050
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
L1 1.04 0.040
k 0° 8° 0° 8°
ccc 0.10 0.004

DS9216 - Rev 11 page 27/37

 TSZ121, TSZ122, TSZ124
QFN16 3x3 package information

6.6 QFN16 3x3 package information

Figure 56. QFN16 3x3 package outline

DS9216 - Rev 11 page 28/37

 TSZ121, TSZ122, TSZ124
QFN16 3x3 package information

Table 11. QFN16 3x3 mechanical data

Dimensions

Ref. Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 0.80 0.90 1.00 0.031 0.035 0.039

A1 0 0.05 0 0.002
A3 0.20 0.008
b 0.18 0.30 0.007 0.012
D 2.90 3.00 3.10 0.114 0.118 0.122
D2 1.50 1.80 0.059 0.071
E 2.90 3.00 3.10 0.114 0.118 0.122
E2 1.50 1.80 0.059 0.071
e 0.50 0.020
L 0.30 0.50 0.012 0.020

Figure 57. QFN16 3x3 recommended footprint

DS9216 - Rev 11 page 29/37

 TSZ121, TSZ122, TSZ124
TSSOP14 package information

6.7 TSSOP14 package information

Figure 58. TSSOP14 package outline

aaa

Table 12. TSSOP14 package mechanical data

Dimensions

Ref. Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 1.20 0.047
A1 0.05 0.15 0.002 0.004 0.006
A2 0.80 1.00 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0089
D 4.90 5.00 5.10 0.193 0.197 0.201
E 6.20 6.40 6.60 0.244 0.252 0.260
E1 4.30 4.40 4.50 0.169 0.173 0.176
e 0.65 0.0256
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
k 0° 8° 0° 8°
aaa 0.10 0.004

DS9216 - Rev 11 page 30/37

 TSZ121, TSZ122, TSZ124
Ordering information

7 Ordering information

Table 13. Order codes

Order code Temperature range Package Packaging Marking

TSZ121ICT SC70-5 K44

TSZ121ILT SΟΤ23-5 K143
TSZ122IQ2T DFN8 2x2 K33
TSZ122IST -40 to 125 °C MiniSO8 K208
TSZ122IDT SO8 TSZ122I
TSZ124IQ4T QFN16 3x3 K193
Tape and reel
TSZ124IPT TSSOP14 TSZ124I

TSZ121IYCT (1) SC70-5 K4J

TSZ121IYLT (1) SΟΤ23-5 K192

TSZ122IYDT (1) -40 to 125 °C automotive grade SO8 K192D

TSZ122IYST (1) MiniSO8 K192

TSZ124IYPT (1) TSSOP14 TSZ124IY

1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001
& Q002 or equivalent. For qualification status detail, check "Maturity status link" on first page ("Quality & Reliability" tab on
www.st.com).

DS9216 - Rev 11 page 31/37

 TSZ121, TSZ122, TSZ124

Revision history

Table 14. Document revision history

Date Revision Changes

16-Aug-2012 1 Initial release.

Added dual and quad products (TSZ122 and TSZ124 respectively)
Updated title
Added following packages: DFN8 2x2, MiniSO8, QFN16 3x3, TSSOP14
Updated Features
Added Benefits and Related products
Updated Description
Updated Table 1 (Rthja, ESD)

25-Apr-2013 2 Updated Table 3 (Vio, ∆Vio/∆T, CMR, Avd, ICC, en, and Cs)
Updated Table 4 (Vio, ∆Vio/∆T, CMR, ICC, en, and Cs)
Updated Table 5 (Vio, ∆Vio/∆T, CMR, SVR, EMIRR, ICC, ts, en, and Cs)
Updated curves of Section 3: Electrical characteristics
Added Section 4.7: Capacitive load
Small update Section 4.9: Optimized application recommendation (capacitor)
Added Section 4.10: EMI rejection ration (EMIRR)
Updated Table 10: Order codes
Added SO8 package for commercial part number TSZ122IDT
Related products: added hyperlinks for TSV71x and TSV73x products
Table 1: updated CDM information
Figure 6, Figure 7: updated X-axes titles
11-Sep-2013 3
Figure 12: updated X-axis and Y-axis titles
Figure 19: updated title
Figure 26: updated X-axis (logarithmic scale)
Figure 27 and Figure 28: updated Y-axis titles
Table 1: updated ESD information
Table 5: added footnote 3
23-May-2014 4
Table 10: Order codes: added automotive qualification footnotes 1 and 2; updated marking of TSZ122IST.
Updated disclaimer
Updated document layout
09-May-2016 5 Table 13: "Order codes": added new automotive grade order code TSZ122IYD, updated footnotes of other
automotive grade order codes.
Table 3, Table 4, and Table 5: added parameter "Low-frequency peak-to-peak input noise" (∫en). Figure 26:
07-Feb-2017 6
"0.1 Hz to 10 Hz noise": updated legend (0.75 μVpp instead of 0.2 μVpp)
Updated footnote related to TSZ122IYDT in Table 13: "Order codes". Minor changes throughout the
12-Apr-2017 7
document.
18-May-2017 8 Updated package outline drawing and mechanical data in Section 6.2: SOT23-5 package information.
Updated Figure 43. Stability criteria with a serial resistor at VDD = 5 V and Figure 44. Stability criteria with a
12-Nov-2018 9
serial resistor at VDD = 1.8 V

Updated Figure 43. Stability criteria with a serial resistor at VDD = 5 V and Figure 44. Stability criteria with a
26-Feb-2019 10
serial resistor at VDD = 1.8 V

07-Apr-2022 11 Added new TSZ121IYCT order code and updated footnote in Table 13. Order codes.

DS9216 - Rev 11 page 32/37

 TSZ121, TSZ122, TSZ124
Contents

Contents
1 Package pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Electrical characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.1 Operation theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1 Time domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.2 Frequency domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Input pin voltage ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4 Rail-to-rail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5 Input offset voltage drift over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6 Rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.7 Capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.8 PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.9 Optimized application recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.10 EMI rejection ration (EMIRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.11 Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.11.1 Oxygen sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.11.2 Precision instrumentation amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.11.3 Low-side current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.1 SC70-5 (or SOT323-5) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2 SOT23-5 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3 DFN8 2 x 2 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4 MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5 SO8 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.6 QFN16 3x3 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7 TSSOP14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

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 TSZ121, TSZ122, TSZ124
List of tables

List of tables
Table 1. Absolute maximum ratings (AMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 3. Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to
VCC/2 (unless otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 4. Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to
VCC/2 (unless otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 5. Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to
VCC/2 (unless otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 6. SC70-5 (or SOT323-5) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. SOT23-5 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. DFN8 2 x 2 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. MiniSO8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. SO8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. QFN16 3x3 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. TSSOP14 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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 TSZ121, TSZ122, TSZ124
List of figures

List of figures
Figure 1. Pin connections for each package (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Supply current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Input offset voltage distribution at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Input offset voltage distribution at VCC = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Input offset voltage distribution at VCC = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Vio temperature co-efficient distribution (-40 °C to 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Vio temperature co-efficient distribution (25 °C to 125 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Input offset voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. Input offset voltage vs. input common-mode at VCC = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10. Input offset voltage vs. input common-mode at VCC = 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 11. Input offset voltage vs. input common-mode at VCC = 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 12. Input offset voltage vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 13. VOH vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 14. VOL vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 15. Output current vs. output voltage at VCC = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 16. Output current vs. output voltage at VCC = 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 17. Input bias current vs. common mode at VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 18. Input bias current vs. common mode at VCC = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 19. Input bias current vs. temperature at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 20. Bode diagram at VCC = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 21. Bode diagram at VCC = 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 22. Bode diagram at VCC = 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 23. Open loop gain vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 24. Positive slew rate vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 25. Negative slew rate vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 26. 0.1 Hz to 10 Hz noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 27. Noise vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 28. Noise vs. frequency and temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 29. Output overshoot vs. load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 30. Small signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 31. Large signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 32. Positive overvoltage recovery at VCC = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 33. Positive overvoltage recovery at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 34. Negative overvoltage recovery at VCC = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 35. Negative overvoltage recovery at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 36. PSRR vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 37. Output impedance vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 38. Block diagram in the time domain (step 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 39. Block diagram in the time domain (step 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 40. Vio cancellation principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 41. Block diagram in the frequency domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 42. Input current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 43. Stability criteria with a serial resistor at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 44. Stability criteria with a serial resistor at VDD = 1.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 45. Test configuration for Riso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 46. EMIRR on IN+ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 47. Oxygen sensor principle schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 48. Precision instrumentation amplifier schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 49. Low-side current sensing schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 50. SC70-5 (or SOT323-5) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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 TSZ121, TSZ122, TSZ124
List of figures

Figure 51. SOT23-5 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 52. DFN8 2 x 2 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 53. DFN8 2 x 2 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 54. MiniSO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 55. SO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 56. QFN16 3x3 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 57. QFN16 3x3 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 58. TSSOP14 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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 TSZ121, TSZ122, TSZ124

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DS9216 - Rev 11 page 37/37