TS4962M

3 W filter-free class D audio power amplifier

Datasheet - production data

Related products
• See TS2007 for further gain settings e.g.
6 or 12 dB
• See TS2012 for stereo settings

Applications
• Portable gaming consoles
• VR headsets
• Smart phones
• Tablets

Description
The TS4962M is a differential Class-D BTL power
Features amplifier. It is able to drive up to 2.3 W into a 4 Ω
• Operating from VCC = 2.4 V to 5.5 V load and 1.4 W into a 8 Ω load at 5 V. It achieves
outstanding efficiency (88% typ.) compared to
• Standby mode active low classical Class-AB audio amps.
• Output power: 3 W into 4 Ω and 1.75 W into 8
The gain of the device can be controlled via two
Ω with 10% THD+N max. and 5 V power supply
external gain-setting resistors. Pop and click
• Output power: 2.3 W @5 V or 0.75 W @ 3.0 V reduction circuitry provides low on/off switch
into 4 Ω with 1% THD+N max. noise while allowing the device to start within
• Output power: 1.4 W @5 V or 0.45 W @ 3.0 V 5 ms. A standby function (active low) allows the
into 8 Ω with 1% THD+N max. reduction of current consumption to 10 nA typ.
• Adjustable gain via external resistors
• Low current consumption 2 mA @ 3 V
• Efficiency: 88% typ.
• Signal to noise ratio: 85 dB typ.
• PSRR: 63 dB typ. @217 Hz with 6 dB gain
• PWM base frequency: 250 kHz
• Low pop and click noise
• Available in Flip Chip 9 x 300 µm (Pb-free)

March 2020 DocID11703 Rev 7 1/41

This is information on a product in full production. www.st.com
Contents TS4962M

Contents

1 Block diagram and pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Application component information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Electrical characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1 Differential configuration principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2 Gain in typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3 Common-mode feedback loop limitations . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4 Low frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.5 Decoupling of the circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.6 Wake-up time (tWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.7 Shutdown time (tSTBY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.8 Consumption in shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.9 Single-ended input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.10 Output filter considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.11 Different examples with summed inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7 Evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.1 9-bump Flip Chip package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2/41 DocID11703 Rev 7

TS4962M Block diagram and pinout

1 Block diagram and pinout

Figure 1. Block diagram

B1 B2
Vcc
C2 Stdby Internal
Bias

300k
Out+
150k
C3
C1 - Output
In- PWM H
In+ +
A1 Bridge

A3
150k
Out-
Oscillator
GND
A2 B3

Figure 2. Pinout (top view)

,1 *1' 287

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9'' 9'' *1'

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,1 67%< 287

& & &

1. Legend:
IN+ = positive differential input
IN- = negative differential input
VDD = analog power supply
GND = power supply ground
STBY = standby pin (active low)
OUT+ = positive differential output
OUT- = negative differential output
2. Bumps are underneath, bump diameter = 300 µm

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41
Application component information TS4962M

2 Application component information

Table 1. Component information

Component Functional description

Bypass supply capacitor. Install as close as possible to the TS4962M to

Cs minimize high-frequency ripple. A 100 nF ceramic capacitor should be
added to enhance the power supply filtering at high frequency.
Input resistor to program the TS4962M differential gain (gain = 300 kΩ/Rin
Rin
with Rin in kΩ).
Due to common-mode feedback, these input capacitors are optional.
Input capacitor However, they can be added to form with Rin a 1st order high-pass filter with
-3 dB cut-off frequency = 1/(2*π*Rin*Cin).

Figure 3. Typical application schematics

Vcc

Vcc B1 B2 Cs
Vcc 1u
In+
C2 Stdby Internal
Bias
300k

Out+ GND
GND 150k
C3
GND
Rin
+ C1 - Output
Differential In- H
PWM
Input In+ +
A1 Bridge
- Rin SPEAKER
In-
A3
Input 150k
Out-
capacitors
are optional Oscillator

GND GND TS4962

A2 B3

GND

Vcc

Vcc B1 B2 Cs
Vcc 1u
In+
C2 Stdby Internal
4 Ohms LC Output Filter
Bias
300k

Out+ GND
GND 150k 15µH
C3
GND
Rin
+ C1 - Output
Differential In- H 2µF
PWM
Input In+ +
Bridge GND Load
A1
- Rin
In- 2µF
A3 15µH
Input 150k
Out-
capacitors
are optional Oscillator

GND GND TS4962

A2 B3 30µH

GND
1µF
GND

1µF
30µH

8 Ohms LC Output Filter

4/41 DocID11703 Rev 7

TS4962M Absolute maximum ratings

3 Absolute maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

VCC Supply voltage (1) (2) 6

V
Vin Input voltage (3) GND to VCC

Toper Operating free-air temperature range -40 to + 85

Tstg Storage temperature -65 to +150 °C
Tj Maximum junction temperature 150
Rthja Thermal resistance junction to ambient 200 °C/W

Pdiss Power dissipation Internally limited(4)

ESD Human body model 2 kV
ESD Machine model 200 V
Latch-up Latch-up immunity 200 mA
VSTBY Standby pin voltage maximum voltage (5) GND to VCC V
Lead temperature (soldering, 10 s) 260 °C
1. Caution: this device is not protected in the event of abnormal operating conditions, such as for example,
short-circuiting between any one output pin and ground, between any one output pin and VCC, and
between individual output pins.
2. All voltage values are measured with respect to the ground pin.
3. The magnitude of the input signal must never exceed VCC + 0.3 V / GND - 0.3 V.
4. Exceeding the power derating curves during a long period causes abnormal operation.
5. The magnitude of the standby signal must never exceed VCC + 0.3 V / GND - 0.3 V.

Table 3. Operating conditions

Symbol Parameter Value Unit

VCC Supply voltage (1) 2.4 to 5.5

VIC Common-mode input voltage range (2) 0.5 to VCC - 0.8
V
Standby voltage input: (3)
VSTBY Device ON 1.4 ≤ VSTBY ≤ VCC
Device OFF GND ≤ VSTBY ≤ 0.4 (4)
RL Load resistor ≥4 Ω
Rthja Thermal resistance junction to ambient (5) 90 °C/W
1. For VCC from 2.4 V to 2.5 V, the operating temperature range is reduced to 0 °C ≤ Tamb ≤ 70 °C.
2. For VCC from 2.4 V to 2.5 V, the common-mode input range must be set at VCC/2.
3. Without any signal on VSTBY, the device is in standby.
4. Minimum current consumption is obtained when VSTBY = GND.
5. With heat sink surface = 125 mm2.

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41
Electrical characteristics TS4962M

4 Electrical characteristics

Table 4. VCC = 5 V, GND = 0 V, VIC = 2.5 V, tamb = 25 °C (unless otherwise specified)

Symbol Parameter Conditions Min. Typ. Max. Unit

ICC Supply current No input signal, no load 2.3 3.3 mA

ISTBY (1)
Standby current No input signal, VSTBY = GND 10 1000 nA
VOO Output offset voltage No input signal, RL = 8 Ω 3 25 mV
G=6 dB
THD = 1% max., F = 1 kHz, RL = 4 Ω 2.3
Pout Output power THD = 10% max., F = 1 kHz, RL = 4 Ω 3 W
THD = 1% max., F = 1 kHz, RL = 8 Ω 1.4
THD = 10% max., F = 1 kHz, RL = 8 Ω 1.75
Pout = 900 mWRMS,
Total harmonic G = 6 dB, 20 Hz < F < 20 kHz 1
THD + N RL = 8 Ω + 15 µH, BW < 30 kHz %
distortion + noise
Pout = 1 WRMS, G = 6 dB, F = 1 kHz,
0.4
RL = 8 Ω + 15 µH, BW < 30 kHz
Pout = 2 WRMS, RL = 4 Ω + ≥ 15 µH 78
Efficiency Efficiency %
Pout =1.2 WRMS, RL = 8 Ω+ ≥ 15 µH 88
Power supply
F = 21 Hz, RL = 8 Ω, G=6 dB,
PSRR rejection ratio with 63 dB
Vripple = 200 mVpp
inputs grounded (2)
Common-mode F = 217 Hz, RL = 8 Ω, G = 6 dB,
CMRR 57 dB
rejection ratio ∆Vicm = 200 mVpp
273k Ω 300k Ω 327k Ω
Gain Gain value Rin in kΩ ------------------ ------------------ ------------------ V/V
R in R in R in

Internal resistance
RSTBY 273 300 327 kΩ
from Standby to GND
Pulse width modulator
FPWM 180 250 320 kHz
base frequency
SNR Signal to noise ratio A-weighting, Pout = 1.2 W, RL = 8 Ω 85 dB
tWU Wake-up time 5 10 ms
tSTBY Standby time 5 10 ms

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TS4962M Electrical characteristics

Table 4. VCC = 5 V, GND = 0 V, VIC = 2.5 V, tamb = 25 °C (unless otherwise specified) (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit

F = 20 Hz to 20 kHz, G = 6 dB
Unweighted RL = 4 Ω 85
A-weighted RL = 4 Ω 60
Unweighted RL = 8 Ω 86
A-weighted RL = 8 Ω 62
Unweighted RL = 4 Ω + 15 µH 83
A-weighted RL = 4 Ω + 15 µH 60
VN Output voltage noise Unweighted RL = 4 Ω + 30 µH 88 µVRMS
A-weighted RL = 4 Ω + 30 µH 64
Unweighted RL = 8 Ω + 30 µH 78
A-weighted RL = 8 Ω + 30 µH 57
Unweighted RL = 4 Ω + filter 87
A-weighted RL = 4 Ω + filter 65
Unweighted RL = 4 Ω + filter 82
A-weighted RL = 4 Ω + filter 59
1. Standby mode is active when VSTBY is tied to GND.
2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinusoidal signal to VCC @
F = 217 Hz.

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Electrical characteristics TS4962M

Table 5. VCC = 4.2V, GND = 0V, VIC = 2.5V, Tamb = 25°C (unless otherwise specified) (1)
Symbol Parameter Conditions Min. Typ. Max. Unit

ICC Supply current No input signal, no load 2.1 3 mA

Standby current
ISTBY (2) No input signal, VSTBY = GND 10 1000 nA

Output offset
VOO No input signal, RL = 8 Ω 3 25 mV
voltage
G=6dB
THD = 1% max, F = 1 kHz,
RL = 4 Ω
THD = 10% max, F = 1 kHz, 1.6
Pout Output power RL = 4 Ω 2 W
THD = 1% max, F = 1 kHz, 0.95
RL = 8 Ω 1.2
THD = 10% max, F = 1 kHz,
RL = 8 Ω
Pout = 600mWRMS, G = 6 dB,
20 Hz < F < 20k Hz
Total harmonic
RL = 8 Ω + 15 µH, BW < 30 kHz 1
THD + N distortion + %
Pout = 700 mWRMS, G = 6 dB,
noise
F = 1 kHz, 0.35
RL = 8 Ω + 15 µH, BW < 30 kHz
Pout = 1.45 WRMS, RL = 4 Ω +
≥ 15 µH 78
Efficiency Efficiency %
Pout =0.9 WRMS, RL = 8 Ω+ 88
≥ 15 µH
Power supply
rejection ratio F = 217 Hz, RL = 8 Ω, G=6 dB,
PSRR 63 dB
with inputs Vripple = 200 mVpp
grounded (3)
Common-mode F = 217 Hz, RL = 8 Ω, G = 6 dB,
CMRR 57 dB
rejection ratio ∆Vicm = 200 mVpp
273k Ω 300k Ω 327k Ω
Gain Gain value Rin in kΩ ------------------ ------------------ ------------------ V/V
R in R in R in

Internal
RSTBY resistance from 273 300 327 kΩ
Standby to GND
Pulse width
FPWM modulator base 180 250 320 kHz
frequency
Signal to noise A-weighting, Pout = 0.9 W,
SNR 85 dB
ratio RL = 8 Ω
tWU Wake-uptime 5 10 ms
tSTBY Standby time 5 10 ms

8/41 DocID11703 Rev 7

TS4962M Electrical characteristics

Table 5. VCC = 4.2V, GND = 0V, VIC = 2.5V, Tamb = 25°C (unless otherwise specified) (1)
Symbol Parameter Conditions Min. Typ. Max. Unit

F = 20Hz to 20 kHz, G = 6 dB
Unweighted RL = 4 Ω 85
A-weighted RL = 4 Ω 60
Unweighted RL = 8 Ω 86
A-weighted RL = 8 Ω 62
Unweighted RL = 4 Ω + 15 µH 83
A-weighted RL = 4 Ω + 15 µH 60
Output voltage
VN Unweighted RL = 4 Ω + 30 µH 88 µVRMS
noise
A-weighted RL = 4 Ω + 30 µH 64
Unweighted RL = 8 Ω + 30 µH 78
A-weighted RL = 8 Ω + 30 µH 57
Unweighted RL = 4 Ω + filter 87
A-weighted RL = 4 Ω + filter 65
Unweighted RL = 4 Ω + filter 82
A-weighted RL = 4 Ω + filter 59
1. All electrical values are guaranteed with correlation measurements at 2.5 V and 5 V.
2. Standby mode is active when VSTBY is tied to GND.
3. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinusoidal signal to VCC @
F = 217 Hz.

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Electrical characteristics TS4962M

Table 6. VCC = 3.6 V, GND = 0 V, VIC = 2.5 V, Tamb = 25 °C (unless otherwise specified) (1)
Symbol Parameter Conditions Min. Typ. Max. Unit

ICC Supply current No input signal, no load 2 2.8 mA

(2)
ISTBY Standby current No input signal, VSTBY = GND 10 1000 nA
VOO Output offset voltage No input signal, RL = 8 Ω 3 25 mV
G=6dB
THD = 1% max., F = 1 kHz, RL = 4 Ω 1.15
Pout Output power THD = 10% max., F = 1 kHz, RL = 4 Ω 1.51 W
THD = 1% max., F = 1 kHz, RL = 8 Ω 0.7
THD = 10% max., F = 1 kHz, RL = 8 Ω 0.9
Pout = 500 mWRMS,
G = 6 dB, 20 Hz < F< 20 kHz
Total harmonic 1
THD + N RL = 8 Ω + 15 µH, BW < 30 kHz %
distortion + noise
Pout = 500 mWRMS, G = 6 dB, F = 1 kHz, 0.27
RL = 8 Ω + 15 µH, BW < 30 kHz
Pout = 1 WRMS, RL = 4 Ω + ≥ 15 µH 78
Efficiency Efficiency %
Pout =0.65 WRMS, RL = 8 Ω+ ≥ 15 µH 88
Power supply
F = 217 Hz, RL = 8 Ω, G=6 dB,
PSRR rejection ratio with 62 dB
Vripple = 200 mVpp
inputs grounded (3)
Common-mode F = 217 Hz, RL = 8 Ω, G = 6 dB,
CMRR 56 dB
rejection ratio ∆Vicm = 200 mVpp
273k Ω 300k Ω 327k Ω
Gain Gain value Rin in kΩ ------------------ ------------------ ------------------ V/V
R in R in R in

Internal resistance
RSTBY 273 300 327 kΩ
from Standby to GND
Pulse width modulator
FPWM 180 250 320 kHz
base frequency
SNR Signal to noise ratio A-weighting, Pout = 0.6 W, RL = 8 Ω 83 dB
tWU Wake-uptime 5 10 ms
tSTBY Standby time 5 10 ms

10/41 DocID11703 Rev 7

TS4962M Electrical characteristics

Table 6. VCC = 3.6 V, GND = 0 V, VIC = 2.5 V, Tamb = 25 °C (unless otherwise specified) (1)
Symbol Parameter Conditions Min. Typ. Max. Unit

F = 20 Hz to 20 kHz, G = 6 dB
Unweighted RL = 4 Ω 83
A-weighted RL = 4 Ω 57
Unweighted RL = 8 Ω 83
A-weighted RL = 8 Ω 61
Unweighted RL = 4 Ω + 15 µH 81
A-weighted RL = 4 Ω + 15 µH 58
VN Output voltage noise Unweighted RL = 4 Ω + 30 µH 87 µVRMS
A-weighted RL = 4 Ω + 30 µH 62
Unweighted RL = 8 Ω + 30 µH 77
A-weighted RL = 8 Ω + 30 µH 56
Unweighted RL = 4 Ω + filter 85
A-weighted RL = 4 Ω + filter 63
Unweighted RL = 4 Ω + filter 80
A-weighted RL = 4 Ω + filter 57
1. All electrical values are guaranteed with correlation measurements at 2.5 V and 5 V.
2. Standby mode is active when VSTBY is tied to GND.
3. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinusoidal signal to VCC @ F = 217 Hz.

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Electrical characteristics TS4962M

Table 7. VCC = 3 V, GND = 0 V, VIC = 2.5 V, Tamb = 25 °C (unless otherwise specified) (1)
Symbol Parameter Conditions Min. Typ. Max. Unit

ICC Supply current No input signal, no load 1.9 2.7 mA

(2)
ISTBY Standby current No input signal, VSTBY = GND 10 1000 nA
VOO Output offset voltage No input signal, RL = 8Ω 3 25 mV
G=6dB
THD = 1% max., F = 1 kHz, RL = 4 Ω 0.75
Pout Output power THD = 10% max., F = 1 kHz, RL = 4 Ω 1 W
THD = 1% max., F = 1 kHz, RL = 8 Ω 0.5
THD = 10% max., F = 1 kHz, RL = 8 Ω 0.6
Pout = 350 mWRMS, G = 6 dB,
20 Hz < F < 20 kHz
Total harmonic 1
THD + N RL = 8 Ω + 15 µH, BW < 30 kHz %
distortion + noise
Pout = 350 mWRMS, G = 6 dB, F = 1 kHz,
0.21
RL = 8 Ω + 15 µH, BW < 30 kHz
Pout = 0.7 WRMS, RL = 4 Ω + ≥ 15 µH 78
Efficiency Efficiency %
Pout = 0.45 WRMS, RL = 8 Ω+ ≥ 15 µH 88
Power supply
F = 217 Hz, RL = 8 Ω, G=6 dB,
PSRR rejection ratio with 60 dB
Vripple = 200 mVpp
inputs grounded (3)
Common-mode F = 217Hz, RL = 8Ω, G = 6 dB,
CMRR 54 dB
rejection ratio ∆Vicm = 200 mVpp
273k Ω 300k Ω 327k Ω
Gain Gain value Rin in kΩ ------------------ ------------------ ------------------ V/V
R in R in R in

Internal resistance
RSTBY 273 300 327 kΩ
from Standby to GND
Pulse width modulator
FPWM 180 250 320 kHz
base frequency
SNR Signal to noise ratio A-weighting, Pout = 0.4 W, RL = 8 Ω 82 dB
tWU Wake-up time 5 10 ms
tSTBY Standby time 5 10 ms

12/41 DocID11703 Rev 7

TS4962M Electrical characteristics

Table 7. VCC = 3 V, GND = 0 V, VIC = 2.5 V, Tamb = 25 °C (unless otherwise specified) (1) (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit

f = 20 Hz to 20 kHz, G = 6 dB
Unweighted RL = 4 Ω 83
A-weighted RL = 4 Ω 57
Unweighted RL = 8 Ω 83
A-weighted RL = 8 Ω 61
Unweighted RL = 4 Ω + 15 µH 81
A-weighted RL = 4 Ω + 15 µH 58
VN Output Voltage Noise Unweighted RL = 4 Ω + 30 µH 87 µVRMS
A-weighted RL = 4 Ω + 30 µH 62
Unweighted RL = 8 Ω + 30 µH 77
A-weighted RL = 8 Ω + 30 µH 56
Unweighted RL = 4 Ω + filter 85
A-weighted RL = 4 Ω + filter 63
Unweighted RL = 4 Ω + filter 80
A-weighted RL = 4 Ω + filter 57
1. All electrical values are guaranteed with correlation measurements at 2.5 V and 5 V.
2. Standby mode is active when VSTBY is tied to GND.
3. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinusoidal signal to VCC @ F = 217 Hz.

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Electrical characteristics TS4962M

Table 8. VCC = 2.5 V, GND = 0 V, VIC = 2.5 V, Tamb = 25 °C (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit

ICC Supply current No input signal, no load 1.7 2.4 mA

(1)
ISTBY Standby current No input signal, VSTBY = GND 10 1000 nA
VOO Output offset voltage No input signal, RL = 8 Ω 3 25 mV
G=6dB
THD = 1% max., F = 1 kHz, RL = 4 Ω 0.52
Pout Output power THD = 10% max., F = 1 kHz, RL = 4 Ω 0.71 W
THD = 1% max., F = 1 kHz, RL = 8 Ω 0.33
THD = 10% max., F = 1 kHz, RL = 8 Ω 0.42
Pout = 200 mWRMS, G = 6 dB, 20 Hz < F<
20 kHz
Total harmonic 1
THD + N RL = 8 Ω + 15 µH, BW < 30 kHz %
distortion + noise
Pout = 200 WRMS, G = 6 dB, F = 1 kHz,
0.19
RL = 8 Ω + 15 µH, BW < 30 kHz
Pout = 0.47 WRMS, RL = 4 Ω + ≥ 15 µH 78
Efficiency Efficiency %
Pout = 0.3 WRMS, RL = 8 Ω+ ≥ 15 µH 88
Power supply
F = 217 Hz, RL = 8 Ω, G=6 dB,
PSRR rejection ratio with 60 dB
Vripple = 200 mVpp
inputs grounded (2)
Common-mode F = 217 Hz, RL = 8 Ω, G = 6 dB,
CMRR 54 dB
rejection ratio ∆Vicm = 200 mVpp
273k Ω 300k Ω 327k Ω
Gain Gain value Rin in kΩ ------------------ ------------------ ------------------ V/V
R in R in R in

Internal resistance
RSTBY 273 300 327 kΩ
from Standby to GND
Pulse width modulator
FPWM 180 250 320 kHz
base frequency
SNR Signal to noise ratio A-weighting, Pout = 1.2 W, RL = 8 Ω 80 dB
tWU Wake-up time 5 10 ms
tSTBY Standby time 5 10 ms

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TS4962M Electrical characteristics

Table 8. VCC = 2.5 V, GND = 0 V, VIC = 2.5 V, Tamb = 25 °C (unless otherwise specified) (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit

F = 20Hz to 20kHz, G = 6 dB
Unweighted RL = 4 Ω 85
A-weighted RL = 4 Ω 60
Unweighted RL = 8 Ω 86
A-weighted RL = 8 Ω 62
Unweighted RL = 4 Ω + 15 µH 76
A-weighted RL = 4 Ω + 15 µH 56
VN Output voltage noise Unweighted RL = 4 Ω + 30 µH 82 µVRMS
A-weighted RL = 4 Ω + 30 µH 60
Unweighted RL = 8 Ω + 30 µH 67
A-weighted RL = 8 Ω + 30 µH 53
Unweighted RL = 4 Ω + filter 78
A-weighted RL = 4 Ω + filter 57
Unweighted RL = 4 Ω + filter 74
A-weighted RL = 4 Ω + filter 54
1. Standby mode is active when VSTBY is tied to GND.
2. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the superimposed sinusoidal signal to VCC @ F = 217 Hz.

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Electrical characteristics TS4962M

Table 9. VCC = 2.4 V, GND = 0 V, VIC = 2.5 V, Tamb = 25 °C (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit

ICC Supply current No input signal, no load 1.7 mA

(1)
ISTBY Standby current No input signal, VSTBY = GND 10 nA
VOO Output offset voltage No input signal, RL = 8 Ω 3 mV
G=6dB
THD = 1% max., F = 1 kHz, RL = 4 Ω 0.48
Pout Output power THD = 10% max., F = 1 kHz, RL = 4 Ω 0.65 W
THD = 1% max., F = 1 kHz, RL = 8 Ω 0.3
THD = 10% max., F = 1 kHz, RL = 8 Ω 0.38
Pout = 200 mWRMS, G = 6 dB, 20 Hz < F<
Total harmonic 1
THD + N 20 kHz %
distortion + noise
RL = 8 Ω + 15 µH, BW < 30 kHz
Pout = 0.38 WRMS, RL = 4 Ω + ≥ 15 µH 77
Efficiency Efficiency %
Pout = 0.25 WRMS, RL = 8 Ω+ ≥ 15 µH 86
Common-mode F = 217 Hz, RL = 8 Ω, G = 6 dB,
CMRR 54 dB
rejection ratio ∆Vicm = 200 mVpp
273k Ω 300k Ω 327k Ω
Gain Gain value Rin in kΩ ------------------ ------------------ ------------------ V/V
R in R in R in

Internal resistance
RSTBY 273 300 327 kΩ
from Standby to GND
Pulse width modulator
FPWM 250 kHz
base frequency
SNR Signal to noise ratio A Weighting, Pout = 1.2 W, RL = 8 Ω 80 dB
tWU Wake-up time 5 ms
tSTBY Standby time 5 ms
F = 20 Hz to 20 kHz, G = 6 dB
Unweighted RL = 4 Ω 85
A-weighted RL = 4 Ω 60
Unweighted RL = 8 Ω 86
A-weighted RL = 8 Ω 62
Unweighted RL = 4 Ω + 15 µH 76
A-weighted RL = 4 Ω + 15 µH 56
VN Output voltage noise Unweighted RL = 4 Ω + 30 µH 82 µVRMS
A-weighted RL = 4 Ω + 30 µH 60
Unweighted RL = 8 Ω + 30 µH 67
A-weighted RL = 8 Ω + 30 µH 53
Unweighted RL = 4 Ω + Filter 78
A-weighted RL = 4 Ω + Filter 57
Unweighted RL = 4 Ω + Filter 74
A-weighted RL = 4 Ω + Filter 54
1. Standby mode is active when VSTBY is tied to GND.

16/41 DocID11703 Rev 7

TS4962M Electrical characteristic curves

5 Electrical characteristic curves

The graphs included in this section use the following abbreviations:

• RL + 15 µH or 30 µH = pure resistor + very low series resistance inductor
• Filter = LC output filter (1 µF+30 µH for 4 Ω and 0.5 µF+60 µH for 8 Ω)
• All measurements made with Cs1=1 µF and Cs2=100 nF except for PSRR where Cs1 is
removed.

Figure 4. Test diagram for measurements

Vcc
1uF 100nF

Cs1 + Cs2

GND GND
Cin Rin
Out+ 4 or 8 Ohms
In+
15uH or 30uH
150k 5th order
TS4962 or RL 50kHz low pass
Cin Rin filter
LC Filter
In-
Out-
150k

GND

Audio Measurement
Bandwidth < 30kHz

Figure 5. Test diagram for PSRR measurements

100nF

Cs2 20Hz to 20kHz

Vcc

GND
GND
4.7uF Rin
Out+ 4 or 8 Ohms
In+
15uH or 30uH
150k 5th order
TS4962 or RL 50kHz low pass
4.7uF Rin filter
LC Filter
In-
Out-
150k

GND
GND

5th order
RMS Selective Measurement
Reference
50kHz low pass
Bandwidth=1% of Fmeas
filter

DocID11703 Rev 7 17/41

41
Electrical characteristic curves TS4962M

Figure 6. Current consumption vs. power Figure 7. Current consumption vs. standby
supply voltage voltage at VCC = 5 V

 
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Figure 8. Current consumption vs. standby Figure 9. Output offset voltage vs.
voltage at VCC = 3 V common-mode input voltage

 
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Figure 10. Efficiency vs. output power at Figure 11. Efficiency vs. output power at
VCC = 5 V and RL = 4 Ω VCC = 3 V and RL = 4 Ω

  


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18/41 DocID11703 Rev 7

TS4962M Electrical characteristic curves

Figure 12. Efficiency vs. output power at Figure 13. Efficiency vs. output power at
VCC = 5 V and RL = 8 Ω VCC = 3 V and RL = 8 Ω

  


 

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Figure 14. Output power vs. power supply Figure 15. Output power vs. power supply
voltage at RL = 4 Ω voltage at RL = 8 Ω

 
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Figure 16. PSRR vs. frequency at Figure 17. PSRR vs. frequency at
RL = 4 Ω + 15 µH RL = 4 Ω + 30 µH
 
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DocID11703 Rev 7 19/41

41
Electrical characteristic curves TS4962M

Figure 18. PSRR vs. frequency at Figure 19. PSR R vs. frequency at
RL = 4 Ω + filter RL = 8 Ω + 15 µH

 
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Figure 20. PSRR vs. frequency at



Figure 21. PSRR vs. frequency at

RL = 8 Ω + 30 µH RL = 8 Ω + filter

 
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Figure 22. PSRR vs. common-mode input



Figure 23. CMRR vs. frequency at

voltage RL = 4 Ω + 15 µH
 
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20/41 DocID11703 Rev 7

TS4962M Electrical characteristic curves

Figure 24. CMRR vs. frequency at Figure 25. CMRR vs. frequency at
RL = 4 Ω + 30 µH RL = 4 Ω + filter

 
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Figure 26. CMRR vs. frequency at Figure 27. CMRR vs. frequency at
RL = 8 Ω + 15 µH RL = 8 Ω + 30 µH

 
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Figure 28. CMRR vs. frequency at Figure 29. CMRR vs. common-mode input
RL = 8 Ω + filter voltage
 
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DocID11703 Rev 7 21/41

41
Electrical characteristic curves TS4962M

Figure 30. THD+N vs. output power at Figure 31. THD+N vs. output power at
RL = 4 Ω + 15 µH, F = 100 Hz RL = 4 Ω + 30 µH or filter, F = 100 Hz

 
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Figure 32. THD+N vs. output power at Figure 33. THD+N vs. output power at
RL = 8 Ω + 15 µH, F = 100 Hz RL = 8 Ω + 30 µH or filter, F = 100 Hz

 
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Figure 34. THD+N vs. output power at Figure 35. THD+N vs. output power at
RL = 4 Ω + 15 µH, F = 1 kHz RL = 4 Ω + 30 µH or filter, F = 1 kHz

 
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22/41 DocID11703 Rev 7

TS4962M Electrical characteristic curves

Figure 36. THD+N vs. output power at Figure 37. THD+N vs. output power at
RL = 8 Ω + 15 µH, F = 1 kHz RL = 8 Ω + 30 µH or filter, F = 1 kHz

 

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Figure 38. THD+N vs. frequency at Figure 39. THD+N vs. frequency at
RL = 4 Ω + 15 µH, VCC = 5 V RL = 4 Ω + 30 µH or filter, VCC = 5 V
 
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Figure 40. THD+N vs. frequency at Figure 41. THD+N vs. frequency at
RL = 4 Ω + 15 µH, VCC = 3.6 V RL = 4 Ω + 30 H or filter, VCC = 3.6 V


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DocID11703 Rev 7 23/41

41
Electrical characteristic curves TS4962M

Figure 42. THD+N vs. frequency at Figure 43. THD+N vs. frequency at
RL = 4 Ω + 15 µH, VCC = 2.5 V RL = 4 Ω + 30 µH or filter, VCC = 2.5 V
 
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Figure 44. THD+N vs. frequency at Figure 45. THD+N vs. frequency at
RL = 8 Ω + 15 µH, VCC = 5 V RL = 8 Ω + 30 µH or filter, VCC = 5 V
 
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Figure 46. THD+N vs. frequency at Figure 47. THD+N vs. frequency at
RL = 8 Ω + 15 µH, VCC = 3.6 V RL = 8 Ω + 30 µH or filter, VCC = 3.6 V
 
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24/41 DocID11703 Rev 7

TS4962M Electrical characteristic curves

Figure 48. THD+N vs. frequency at Figure 49. THD+N vs. frequency at
RL = 8 Ω + 15 µH, VCC = 2.5 V RL = 8 Ω + 30 µH or filter, VCC = 2.5 V
 
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Figure 50. Gain vs. frequency at Figure 51. Gain vs. frequency at
RL = 4 Ω + 15 µH RL = 4 Ω + 30 µH
 

 
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Figure 52. Gain vs. frequency at



Figure 53. Gain vs. frequency at

RL = 4 Ω + filter RL = 8 Ω + 15 µH
 

 
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DocID11703 Rev 7 25/41

41
Electrical characteristic curves TS4962M

Figure 54. Gain vs. frequency at Figure 55. Gain vs. frequency at
RL = 8 Ω + 30 µH RL = 8 Ω + filter
 

 
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Figure 56. Gain vs. frequency at Figure 57. Startup and shutdown time VCC = 5 V,
RL = no load G = 6 dB, Cin = 1 µF (5 ms/div)

Vo1

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Figure 58. Startup and shutdown time VCC = 3 V, Figure 59. Startup and shutdown time VCC = 5 V,
G = 6 dB, Cin = 1 µF (5 ms/div) G = 6 dB, Cin = 100 nF (5 ms/div)

Vo1 Vo1

Vo2 Vo2

Standby Standby

Vo1-Vo2 Vo1-Vo2

26/41 DocID11703 Rev 7

TS4962M Electrical characteristic curves

Figure 60. Startup and shutdown time VCC = 3 V, Figure 61. Startup and shutdown time VCC = 5 V,
G = 6 dB, Cin = 100 nF (5 ms/div) G = 6 dB, No Cin (5 ms/div)

Vo1 Vo1

Vo2 Vo2

Standby Standby

Vo1-Vo2 Vo1-Vo2

Figure 62. Startup and shutdown time VCC = 3 V, G = 6 dB, no Cin (5 ms/div)

Vo1

Vo2

Standby

Vo1-Vo2

DocID11703 Rev 7 27/41

41
Application information TS4962M

6 Application information

6.1 Differential configuration principle

The TS4962M is a monolithic fully-differential input/output class D power amplifier. The
TS4962M also includes a common-mode feedback loop that controls the output bias value
to average it at VCC/2 for any DC common-mode input voltage. This allows the device to
always have a maximum output voltage swing, and by consequence, maximizes the output
power. Moreover, as the load is connected differentially compared to a single-ended
topology, the output is four times higher for the same power supply voltage.
The advantages of a full-differential amplifier are:
• High PSRR (power supply rejection ratio)
• High common-mode noise rejection
• Virtually zero pop without additional circuitry, giving a faster start-up time compared to
conventional single-ended input amplifiers.
• Easier interfacing with differential output audio DAC
• No input coupling capacitors required due to common-mode feedback loop
The main disadvantage is:
• As the differential function is directly linked to external resistor mismatching, particular
attention to this mismatching is mandatory to obtain the best performance from the
amplifier.

6.2 Gain in typical application schematic

Typical differential applications are shown in Figure 3 on page 4.
In the flat region of the frequency-response curve (no input coupling capacitor effect), the
differential gain is expressed by the relation:
+ -
Out – Out 300
AV = ------------------------------
+ -
- = ----------
diff
In – In R in

with Rin expressed in kΩ.

Due to the tolerance of the internal 150 kΩ feedback resistor, the differential gain will be in
the range (no tolerance on Rin):
273 327
---------- ≤ A V ≤ ----------
R in d iff R in

28/41 DocID11703 Rev 7

TS4962M Application information

6.3 Common-mode feedback loop limitations

The common-mode feedback loop allows the output DC bias voltage to be averaged at
VCC/2 for any DC common-mode bias input voltage.
However, due to Vicm limitation in the input stage (see Table 3: Operating conditions on
page 5), the common-mode feedback loop can ensure its role only within a defined range.
This range depends upon the values of VCC and Rin (AVdiff). To have a good estimation of
the Vicm value, we can apply this formula (no tolerance on Rin):

VCC × R in + 2 × V IC × 150kΩ
V icm = ---------------------------------------------------------------------------- (V)
2 × ( R in + 150kΩ )

with
+ -
In + In
V IC = --------------------- (V)
2

and the result of the calculation must be in the range:

0.5V ≤ V icm ≤ V CC – 0.8V

Due to the ±9% tolerance on the 150kΩ resistor, it is also important to check Vicm in these
conditions:

V CC × R in + 2 × V IC × 136.5kΩ VCC × R in + 2 × V IC × 163.5kΩ

--------------------------------------------------------------------------------- ≤ V icm ≤ ---------------------------------------------------------------------------------
2 × ( R in + 136.5kΩ ) 2 × ( R in + 163.5kΩ )

If the result of the Vicm calculation is not in the previous range, input coupling capacitors
must be used (with VCC from 2.4V to 2.5V, input coupling capacitors are mandatory).

Example
With VCC = 3 V, Rin = 150 k and VIC = 2.5 V, we typically find Vicm = 2 V and this is lower
than 3V - 0.8 V = 2.2 V. With 136.5 kΩ we find 1.97 V, and with 163.5 kΩ we have 2.02 V.
So, no input coupling capacitors are required.

6.4 Low frequency response

If a low frequency bandwidth limitation is requested, it is possible to use input coupling
capacitors.
In the low frequency region, Cin (input coupling capacitor) starts to have an effect. Cin forms,
with Rin, a first order high-pass filter with a -3dB cut-off frequency:
1
F CL = ------------------------------------ (Hz)
2π × R in × C in

So, for a desired cut-off frequency we can calculate Cin,

1
C in = -------------------------------------- (F)
2π × Rin × F CL

with Rin in Ω and FCL in Hz.

DocID11703 Rev 7 29/41

41
Application information TS4962M

6.5 Decoupling of the circuit

A power supply capacitor, referred to as CS, is needed to correctly bypass the TS4962M.
The TS4962M has a typical switching frequency at 250 kHz and an output fall and rise time
about 5ns. Due to these very fast transients, careful decoupling is mandatory.
A 1 µF ceramic capacitor is enough, but it must be located very close to the TS4962M in
order to avoid any extra parasitic inductance created by an overly long track wire. In relation
with dI/dt, this parasitic inductance introduces an overvoltage that decreases the global
efficiency and, if it is too high, may cause a breakdown of the device.
In addition, even if a ceramic capacitor has an adequate high-frequency ESR value, its
current capability is also important. A 0603 size is a good compromise, particularly when a
4 Ω load is used.
Another important parameter is the rated voltage of the capacitor. A 1 µF/6.3 V capacitor
used at 5 V, loses about 50% of its value. In fact, with a 5V power supply voltage, the
decoupling value is about 0.5 µF instead of 1µF. As CS has particular influence on the
THD+N in the medium-high frequency region, this capacitor variation becomes decisive. In
addition, less decoupling means higher overshoots, which can be problematic if they reach
the power supply AMR value (6 V).

6.6 Wake-up time (tWU)

When the standby is released to set the device ON, there is a wait of about 5ms. The
TS4962M has an internal digital delay that mutes the outputs and releases them after this
time in order to avoid any pop noise.

6.7 Shutdown time (tSTBY)

When the standby command is set, the time required to put the two output stages into high
impedance and to put the internal circuitry in shutdown mode, is about 5 ms. This time is
used to decrease the gain and avoid any pop noise during shutdown.

6.8 Consumption in shutdown mode

Between the shutdown pin and GND there is an internal 300 kΩ resistor. This resistor forces
the TS4962M to be in standby mode when the standby input pin is left floating.
However, this resistor also introduces additional power consumption if the shutdown pin
voltage is not 0 V.
For example, with a 0.4 V standby voltage pin, Table 3: Operating conditions on page 5,
shows that you must add 0.4 V/300 kΩ = 1.3 µA in typical (0.4 V/273 kΩ = 1.46 µA in
maximum) to the shutdown current specified in Table 4 on page 6.

30/41 DocID11703 Rev 7

TS4962M Application information

6.9 Single-ended input configuration

It is possible to use the TS4962M in a single-ended input configuration. However, input
coupling capacitors are needed in this configuration. The schematic in Figure 63 shows a
single-ended input typical application.

Figure 63. Single-ended input typical application

Vcc

B1 B2 Cs
Vcc 1u
Ve
C2 Stdby Internal
Standby
Bias

300k
Out+ GND
150k
C3
Cin Rin
GND C1 Output
-
In- PWM H
In+ +
A1 Bridge
Rin SPEAKER
A3
Cin 150k
Out-

GND Oscillator
GND TS4962
A2 B3

GND

All formulas are identical except for the gain (with Rin in kΩ):
Ve 300
AV = ------------------------------
-- = ----------
sin gle
Out – Out
+ R in

And, due to the internal resistor tolerance we have:

273 327
---------- ≤ A V ≤ ----------
R in sin g le R in

In the event that multiple single-ended inputs are summed, it is important that the
impedance on both TS4962M inputs (In- and In+) are equal.

Figure 64. Typical application schematic with multiple single-ended inputs

Vcc
Vek
Standby Cs
B1 B2
Vcc 1u
Cink Rink C2 Stdby Internal
Bias
300k

GND Out+ GND

150k
C3
Ve1 Cin1 Rin1
C1 - Output
In- PWM H
In+ +
A1 Bridge
GND Req SPEAKER
Ceq A3
150k
Out-
Oscillator
GND
GND TS4962
A2 B3

GND

DocID11703 Rev 7 31/41

41
Application information TS4962M

We have the following equations:

+ - 300 300
Out – Out = V e1 × ------------- + … + V ek × ------------- (V)
R R
in1 ink

k
C eq = Σ Cinj
j=1

1
C = ---------------------------------------------------- (F)
2×π×R ×F
inj
inj CLj

1
R eq = -------------------
k
1
 ---------Rinj
-
j =1

In general, for mixed situations (single-ended and differential inputs), it is best to use the
same rule, that is, to equalize impedance on both TS4962M inputs.

6.10 Output filter considerations

The TS4962M is designed to operate without an output filter. However, due to very sharp
transients on the TS4962M output, EMI radiated emissions may cause some standard
compliance issues.
These EMI standard compliance issues can appear if the distance between the TS4962M
outputs and loudspeaker terminal is long (typically more than 50mm, or 100mm in both
directions, to the speaker terminals). As the PCB layout and internal equipment device are
different for each configuration, it is difficult to provide a one-size-fits-all solution.
However, to decrease the probability of EMI issues, there are several simple rules to follow:
• Reduce, as much as possible, the distance between the TS4962M output pins and the
speaker terminals.
• Use ground planes for “shielding” sensitive wires
• Place, as close as possible to the TS4962M and in series with each output, a ferrite
bead with a rated current at minimum 2A and impedance greater than 50Ω at
frequencies above 30MHz. If, after testing, these ferrite beads are not necessary,
replace them by a short-circuit. Murata BLM18EG221SN1 or BLM18EG121SN1 are
possible examples of devices you can use.
• Allow enough of a footprint to place, if necessary, a capacitor to short perturbations to
ground (see the schematics in Figure 65).

Figure 65. Method for shorting pertubations to ground

Ferrite chip bead To speaker

From TS4962 output
about 100pF

Gnd

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TS4962M Application information

In the case where the distance between the TS4962M outputs and speaker terminals is
high, it is possible to have low frequency EMI issues due to the fact that the typical operating
frequency is 250kHz. In this configuration, we recommend using an output filter (as shown
in Figure 3: Typical application schematics on page 4). It should be placed as close as
possible to the device.

6.11 Different examples with summed inputs

Example 1: Dual differential inputs

Figure 66. Typical application schematic with dual differential inputs

Vcc
Standby Cs
B1 B2
Vcc 1u
C2 Stdby Internal
R2 Bias

300k
E2+ Out+ GND
150k
C3
R1
C1 - Output
E1+
In- PWM H
In+ +
E1- Bridge
A1
R1 SPEAKER
A3
150k
E2- Out-
R2 Oscillator
GND TS4962
A2 B3

GND

With (Ri in kΩ):

+ -
Out – Out 300
A V = ------------------------------
+ -
- = ----------
1
E1 – E1 R1

+ -
Out – Out 300
A V = ------------------------------
- = ----------
2
E2 – E2
+ - R2

V CC × R 1 × R 2 + 300 × ( V IC1 × R 2 + V IC2 × R 1 )

0.5V ≤ --------------------------------------------------------------------------------------------------------------------------- ≤ VCC – 0.8V
300 × ( R 1 + R 2 ) + 2 × R 1 × R 2

+ - + -
E1 + E1 E2 + E2
V IC = ------------------------ and V IC = ------------------------
1 2 2 2

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Application information TS4962M

Example 2: One differential input plus one single-ended input

Figure 67. Typical application schematic with one differential input plus
one single-ended input

Vcc
Standby Cs
B1 B2
Vcc 1u
C2 Stdby Internal
R2 Bias

300k
E2+ Out+ GND
150k
C3
C1 R1
C1 - Output
E1+
In- PWM H
In+ +
E2- Bridge
A1
R2 SPEAKER
A3
150k
Out-
GND C1 R1 Oscillator
GND TS4962
A2 B3

GND

With (Ri in kΩ):

+ -
Out – Out 300
A V = ------------------------------
- = ----------
1
E1
+ R1

+ -
Out – Out 300
A V = ------------------------------
+ -
- = ----------
2
E2 – E2 R2

1
C 1 = ------------------------------------ (F)
2π × R1 × F CL

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TS4962M Evaluation board

7 Evaluation board

An evaluation board for the TS4962M is available with a Flip Chip to DIP adapter. For more
information about this board, refer to AN2134.

Figure 68. Schematic diagram of mono class D evaluation board for TS4962M

Vcc Vcc
Cn1 + J1
1 +
Cn2 C1
2 2.2uF/10V
3
GND GND GND Vcc
Cn4 + J2
3 8
U1
Vcc
4 Stdby Internal
Bias

300k
C2 R1 Out+
150k
6
Cn3 Cn6
5 Output
Positive Input 100nF 150k - Positive Output
In- PWM H
Negative input In+ + Negative Output
100nF R2 Bridge
1
10
150k 150k
C3 Out-
Oscillator
GND TS4962 Flip-Chip to DIP Adapter
2 3
Cn5 + J3
GND

Figure 69. Diagram for Flip Chip to DIP adapter

Pin3

pin8

R1
+
OR C1 C2
1uF
100nF
B1 B2
Vcc
C2 Stdby Internal
Pin4
Bias
300k

Out+
150k
C3
Pin6
C1 - Output
Pin5
In- PWM H
In+ +
Pin1 Bridge
A1
Pin10
A3
150k
Out-
Oscillator
GND TS4962
A2 B3

R2

OR
Pin2

Pin9

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Evaluation board TS4962M

Figure 70. Top view

Figure 71. Bottom layer

Figure 72. Top layer

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TS4962M Package information

8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

8.1 9-bump Flip Chip package information

Figure 73. 9-bump Flip Chip package outline

PP

PP
PP

‡ PP
PP
%DFNVLGH
FRDWLQJ
RSWLRQDO —P

Table 10. 9-bump Flip Chip mechanical data

Parameter Dimensions

Die size 1.6 mm x 1.6 mm ±30 µm

Die height (including bumps) 600 µm
Bump diameter 315 µm ±50 µm
Bump diameter before re-flow 300 µm ±10 µm
Bump height 250 µm ±40 µm
Die height 350 µm ±20 µm
Pitch 500 µm ±50 µm
Coplanarity 50 µm max.
Backside coating
25 µm ±3 µm
(optional, only for the TS4962MEIKJT)

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Package information TS4962M

Figure 74. 9-bump Flip Chip marking (top view)

XXX
YWW

1. Legend:
ST logo
E = symbol for lead-free
First two “XX” = product code = 62
Third X = assembly code
Three-digit date code, Y = year, WW = week
Black dot is for marking pin A1

Figure 75. 9-bump Flip Chip recommended footprint

75µm min.
500µm 500µm 100µm max.
Φ=250µm
Track

Φ=400µm typ. 150µm min.

500µm

Φ=340µm min.
500µm

Non Solder mask opening

Pad in Cu 18µm with Flash NiAu (2-6µm, 0.2µm max.)

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TS4962M Ordering information

9 Ordering information

Table 11. Order code table

Part number Temperature range Package Packing Marking

TS4962MEIJT Lead-free Flip Chip

-40 °C to 85 °C Lead-free Flip Chip Tape and reel 62L
TS4962MEIKJT
with backside coating

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Revision history TS4962M

10 Revision history

Table 12. Document revision history

Date Revision Changes

Oct. 2005 1 First release corresponding to the product preview version.

Electrical data updated for output voltage noise, see Table 4,
Nov. 2005 2 Table 5, Table 6, Table 7, Table 8 and Table 9
Formatting changes throughout.
Dec. 2005 3 Product in full production.
10-Jan-2007 4 Template update, no technical changes.
Updated datasheet layout
Added package silhouettes
Added Related products
Updated Applications
Section 5: Electrical characteristic curves: updated titles of
graphs which had same titles.
10-Oct-2016 5 Figure 73: 9-bump Flip Chip package outline: updated diagram
to display the optional backside coating for order code
TS4962MEIKJT.
Added Table 10 to display package mechanical data as a
separate table (with information concerning the optional
backside coating for order code TS4962MEIKJT).
Table 11: Order code table: updated marking of order code
TS4962MEIJT, added order code TS4962MEIKJT.
15-Jan-2018 6 Updated Table 10: 9-bump Flip Chip mechanical data.
Removed feature on the cover page and footnote Rthja
17-Mar-2020 7
parameter in Table 2.

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TS4962M

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2020 STMicroelectronics – All rights reserved

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