LTC3555/LTC3555-X

High Efficiency USB Power

Manager + Triple
Step-Down DC/DC
FEATURES DESCRIPTION
Power Manager The LTC®3555 family are highly integrated USB com-
n High Efficiency Switching PowerPath™ Controller patible power management and battery charger ICs for
with Bat-Track™ Adaptive Output Control Li-Ion/Polymer battery applications. They include a high
n Programmable USB or Wall Current Limit efficiency current limited switching PowerPath manager
(100mA/500mA/1A) with automatic load prioritization, a battery charger, an ideal
n Full Featured Li-Ion/Polymer Battery Charger diode and three general purpose synchronous step-down
n 1.5A Maximum Charge Current switching regulators.
n Internal 180mΩ Ideal Diode + External Ideal Diode
The LTC3555 family limits input current to either 100mA
Controller Powers Load in Battery Mode or 500mA for USB applications or 1A for adapter-powered
n Low No-Load Quiescent Current when Powered from
applications. Unlike linear chargers, the LTC3555 family’s
BAT (<32µA) switching architecture transmits nearly all of the power
DC/DCs available from the USB port to the load with minimal loss
n Triple High Efficiency Step-Down DC/DCs and heat which eases thermal constraints in small spaces.
(1A/400mA/400mA IOUT) Two of the three general purpose switching regulators can
n All Regulators Operate at 2.25MHz
provide up to 400mA and the third can deliver 1A. The
n Dynamic Voltage Scaling on Two Outputs
entire product can be controlled via I2C or simple I/O. The
n I2C or Independent Enable, V
OUT Controls LTC3555-1/LTC3555-3 versions offer “instant-on” power
n Low No-Load Quiescent Current: 20µA
delivery to the portable product even with a very low battery
n 28-Pin (4mm × 5mm × 0.75mm) QFN Package
voltage. The LTC3555-3 version also has a reduced charger
float voltage of 4.100V for battery safety and longevity.
APPLICATIONS The LTC3555 family is available in the low profile 28-pin
n HDD-Based MP3 Players, PDAs, GPS, PMPs (4mm × 5mm × 0.75mm) QFN surface mount package.
n Portable Medical Products L, LT, LTC, LTM Linear Technology, the Linear logo and Burst Mode are registered trademarks
and PowerPath and Bat-Track are trademarks of Linear Technology Corporation. All other
n Handheld Instrumentation trademarks are the property of their respective owners. Protected by U.S. Patents, including
6522118 and 6404251.
n Other USB-Based Handheld Products

TYPICAL APPLICATION
High Efficiency PowerPath Manager and Triple Step-Down Regulator
Switching Regulator Efficiency to
USB/WALL
4.35V TO 5.5V
USB COMPLIANT TO OTHER
LOADS System Load (POUT/PBUS)
STEP-DOWN
REGULATOR 100
CC/CV 90
0V OPTIONAL
BATTERY
CURRENT 80
CHARGER
CONTROL
CHARGE 70 BAT = 4.2V
+
EFFICIENCY (%)

Li-Ion 60
T BAT = 3.3V
LTC3555/LTC3555-X
50
3.3V/25mA RTC/LOW
ALWAYS ON LDO 40
POWER LOGIC
0.8V TO 3.6V/400mA 30
TRIPLE 1 MEMORY
5 HIGH EFFICIENCY 20
ENABLE 0.8V TO 3.6V/400mA VBUS = 5V
STEP-DOWN 2 I/O IBAT = 0mA
CONTROLS 10
SWITCHING 0.8V TO 3.6V/1A 10x MODE
REGULATORS 3 CORE 0
RST 0.01 0.1 1
µPROCESSOR
2 IOUT (A)
2C PORT
I I2C
3555 TA01b
3555 TA01
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LTC3555/LTC3555-X
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
(Notes 1, 2, 3)
VBUS (Transient) t < 1ms, TOP VIEW
Duty Cycle < 1% .......................................... –0.3V to 7V

ILIM1
ILIM0

VBUS
VOUT
BAT
SW
VIN1, VIN2, VIN3, VBUS (Static), DVCC, 28 27 26 25 24 23

FB1, FB2, FB3, NTC, BAT, SCL, SDA, LDO3V3 1 22 GATE

RST3, CHRG ................................................. –0.3V to 6V CLPROG 2 21 CHRG

NTC 3 20 PROG
EN1, EN2, EN3................................ –0.3V to VOUT +0.3V FB2 4 19 FB1
ILIM0, ILIM1 ...................–0.3V to MAX (VBUS, VOUT BAT) VIN2 5
29
18 VIN1
ICLPROG ....................................................................3mA SW2 6 17 SW1
IRST3, ICHRG............................................................50mA EN2 7 16 EN1
IPROG ........................................................................2mA DVCC 8 15 RST3

ILDO3V3 ...................................................................30mA 9 10 11 12 13 14

ISW1, ISW2 ........................................................... 600mA

SCL
SDA
VIN3
SW3
EN3
FB3
ISW, ISW3, IBAT, IVOUT ..................................................2A UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
Junction Temperature ........................................... 125°C TJMAX = 125°C, θJA = 37°C/W
Operating Temperature Range (Note 2)....–40°C to 85°C EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB

Storage Temperature Range .................. –65°C to 125°C

ORDER INFORMATION http://www.linear.com/product/LTC3555#orderinfo

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3555EUFD#PBF LTC3555EUFD#TRPBF 3555 28-Lead (4mm x 5mm) Plastic QFN –40°C to 85°C
LTC3555IUFD#PBF LTC3555IUFD#TRPBF 3555 28-Lead (4mm x 5mm) Plastic QFN –40°C to 85°C
LTC3555EUFD-1#PBF LTC3555EUFD-1#TRPBF 35551 28-Lead (4mm x 5mm) Plastic QFN –40°C to 85°C
LTC3555IUFD-1#PBF LTC3555IUFD-1#TRPBF 35551 28-Lead (4mm x 5mm) Plastic QFN –40°C to 85°C
LTC3555EUFD-3#PBF LTC3555EUFD-3#TRPBF 35553 28-Lead (4mm x 5mm) Plastic QFN –40°C to 85°C
LTC3555IUFD-3#PBF LTC3555IUFD-3#TRPBF 35553 28-Lead (4mm x 5mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, BAT = 3.8V, DVCC = 3.3V, RPROG = 1k, RCLPROG = 3k,
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PowerPath Switching Regulator
VBUS Input Supply Voltage 4.35 5.5 V
IBUSLIM Total Input Current 1x Mode, VOUT = BAT l 87 95 100 mA
5x Mode, VOUT = BAT l 436 460 500 mA
10x Mode, VOUT = BAT l 800 860 1000 mA
Suspend Mode, VOUT = BAT l 0.31 0.38 0.50 mA
IVBUSQ VBUS Quiescent Current 1x Mode, IOUT = 0mA 7 mA
5x Mode, IOUT = 0mA 15 mA
10x Mode, IOUT = 0mA 15 mA
Suspend Mode, IOUT = 0mA 0.044 mA
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 LTC3555/LTC3555-X
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, BAT = 3.8V, DVCC = 3.3V, RPROG = 1k, RCLPROG = 3k,
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
hCLPROG Ratio of Measured VBUS Current to 1x Mode 224 mA/mA
(Note 4) CLPROG Program Current 5x Mode 1133 mA/mA
10x Mode 2140 mA/mA
Suspend Mode 11.3 mA/mA
IOUT(POWERPATH) VOUT Current Available Before 1x Mode, BAT = 3.3V 135 mA
Loading BAT 5x Mode, BAT = 3.3V 672 mA
10x Mode, BAT = 3.3V 1251 mA
Suspend Mode 0.32 mA
VCLPROG CLPROG Servo Voltage in Current 1x, 5x, 10x Modes 1.188 V
Limit Suspend Mode 100 mV
VUVLO_VBUS VBUS Undervoltage Lockout Rising Threshold 4.30 4.35 V
Falling Threshold 3.95 4.00 V
VUVLO_VBUS-BAT VBUS to BAT Differential Undervoltage Rising Threshold 200 mV
Lockout Falling Threshold 50 mV
VOUT VOUT Voltage 1x, 5x, 10x Modes, 0V < BAT < 4.2V, 3.4 BAT + 0.3 4.7 V
IOUT = 0mA, Battery Charger Off
USB Suspend Mode, IVOUT = 250µA 4.5 4.6 4.7 V
fOSC Switching Frequency 1.8 2.25 2.7 MHz
RPMOS_POWERPATH PMOS On Resistance 0.18 Ω
RNMOS_POWERPATH NMOS On Resistance 0.30 Ω
IPEAK_POWERPATH Peak Switch Current Limit 1x, 5x Modes 2 A
10x 3 A
Battery Charger
VFLOAT BAT Regulated Output Voltage LTC3555/LTC3555-1 4.179 4.200 4.221 V
LTC3555/LTC3555-1 l 4.165 4.200 4.235 V
LTC3555-3 4.079 4.100 4.121 V
LTC3555-3 l 4.065 4.100 4.135 V
ICHG Constant Current Mode Charge RPROG = 1k 980 1022 1065 mA
Current RPROG = 5k 185 204 223 mA
IBAT Battery Drain Current VBUS > VUVLO, Battery Charger Off, IVOUT = 0µA 2 3.5 5 µA
VBUS = 0V, IVOUT = 0µA (Ideal Diode Mode)
LTC3555 27 38 µA
LTC3555-1/LTC3555-3 32 44 µA
VPROG PROG Pin Servo Voltage 1.000 V
VPROG_TRKL PROG Pin Servo Voltage in Trickle BAT < VTRKL 0.100 V
Charge
VC/10 C/10 Threshold Voltage at PROG 100 mV
hPROG Ratio of IBAT to PROG Pin Current 1022 mA/mA
ITRKL Trickle Charge Current BAT < VTRKL 100 mA
VTRKL Trickle Charge Threshold Voltage BAT Rising 2.7 2.85 3.0 V
ΔVTRKL Trickle Charge Hysteresis Voltage 135 mV
ΔVRECHRG Recharge Battery Threshold Voltage Threshold Voltage Relative to VFLOAT –75 –100 –125 mV
tTERM Safety Timer Termination Timer Starts when BAT = VFLOAT 3.3 4 5 Hour
tBADBAT Bad Battery Termination Time BAT < VTRKL 0.42 0.5 0.63 Hour
hC/10 End of Charge Indication Current Ratio (Note 5) 0.088 0.1 0.112 mA/mA

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LTC3555/LTC3555-X
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, BAT = 3.8V, DVCC = 3.3V, RPROG = 1k, RCLPROG = 3k,
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCHRG CHRG Pin Output Low Voltage ICHRG = 5mA 65 100 mV
ICHRG CHRG Pin Leakage Current VCHRG = 5V 1 µA
RON_CHG Battery Charger Power FET On 0.18 Ω
Resistance (Between VOUT and BAT)
TLIM Junction Temperature in Constant 110 °C
Temperature Mode
NTC
VCOLD Cold Temperature Fault Threshold Rising Threshold 75.0 76.5 78.0 %VBUS
Voltage Hysteresis 1.5 %VBUS
VHOT Hot Temperature Fault Threshold Falling Threshold 33.4 34.9 36.4 %VBUS
Voltage Hysteresis 1.5 %VBUS
VDIS NTC Disable Threshold Voltage Falling Threshold 0.7 1.7 2.7 %VBUS
Hysteresis 50 mV
INTC NTC Leakage Current VNTC = VBUS = 5V –50 50 nA
Ideal Diode
VFWD Forward Voltage VBUS = 0V, IVOUT = 10mA 2 mV
IVOUT = 10mA 15 mV
RDROPOUT Internal Diode On Resistance, Dropout VBUS = 0V 0.18 Ω
IMAX_DIODE Internal Diode Current Limit 1.6 A
Always On 3.3V LDO Supply
VLDO3V3 Regulated Output Voltage 0mA < ILDO3V3 < 25mA 3.1 3.3 3.5 V
RCL_LDO3V3 Closed-Loop Output Resistance 4 Ω
ROL_LDO3V3 Dropout Output Resistance 23 Ω
Logic (ILIM0, ILIM1, EN1, EN2, EN3)
VIL Logic Low Input Voltage 0.4 V
VIH Logic High Input Voltage 1.2 V
IPD1 ILIM0, ILIM1, EN1, EN2, EN3 2 µA
Pull-Down Currents
I2C Port
DVCC Input Supply Voltage 1.6 5.5 V
IDVCC DVCC Current SCL/SDA = 0kHz 0.5 µA
VDVCC_UVLO DVCC UVLO 1.0 V
ADDRESS I2C Address 0001 001[0]
VIH, SDA, SCL Input High Threshold 70 %DVCC
VIL, SDA, SCL Input Low Threshold 30 %DVCC
IPD2 SDA, SCL Pull-Down Current 2 µA
VOL Digital Output Low (SDA) IPULLUP = 3mA 0.4 V
fSCL Clock Operating Frequency 400 kHz
tBUF Bus Free Time Between Stop and Start 1.3 µs
Condition
tHD_STA Hold Time After (Repeated) Start 0.6 µs
Condition
tSU_STA Repeated Start Condition Setup Time 0.6 µs

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 LTC3555/LTC3555-X
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, BAT = 3.8V, DVCC = 3.3V, RPROG = 1k, RCLPROG = 3k,
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSU_STD Stop Condition Time 0.6 µs
tHD_DAT(OUT) Data Hold Time 225 ns
tHD_DAT(IN) Input Data Hold Time 0 900 ns
tSU_DAT Data Setup Time 100 ns
tLOW Clock Low Period 1.3 µs
tHIGH Clock High Period 0.6 µs
tf Clock Data Fall Time 20 300 ns
tr Clock Data Rise Time 20 300 ns
tSP Spike Suppression Time 50 ns
General Purpose Switching Regulators 1, 2 and 3
VIN1,2,3 Input Supply Voltage 2.7 5.5 V
VOUTUVLO VOUT UVLO—VOUT Falling VIN1,2,3 Connected to VOUT Through Low 2.5 2.6 V
VOUT UVLO—VOUT Rising Impedance. Switching Regulators are Disabled in 2.8 2.9 V
UVLO
fOSC Oscillator Frequency 1.8 2.25 2.7 MHz
IFB1,2,3 FBx Input Current VFB1,2,3 = 0.85V –50 50 nA
D1,2,3 Maximum Duty Cycle 100 %
RSW1,2,3_PD SWx Pull-Down in Shutdown 10 kΩ
General Purpose Switching Regulator 1
IVIN1 Pulse Skip Mode Input Current IOUT1 = 0µA (Note 6) 225 µA
Burst Mode Input Current IOUT1 = 0µA (Note 6) 35 60 µA
Forced Burst Mode® Input Current IOUT1 = 0µA (Note 6) 20 35 µA
LDO Mode Input Current IOUT1 = 0µA (Note 6) 20 35 µA
Shutdown Input Current IOUT1 = 0µA, FB1 = 0V 1 µA
ILIMSW1 PMOS Switch Current Limit Pulse Skip/Burst Mode Operation 600 800 1100 mA
IOUT1 Available Output Current Pulse Skip/Burst Mode Operation (Note 7) 400 mA
Forced Burst Mode Operation (Note 7) 60 mA
LDO Mode (Note 7) 50 mA
VFB1 VFB1 Servo Voltage (Note 8) l 0.78 0.80 0.82 V
RP1 PMOS RDS(ON) 0.6 Ω
RN1 NMOS RDS(ON) 0.7 Ω
RLDO_CL1 LDO Mode Closed-Loop ROUT 0.25 Ω
RLDO_OL1 LDO Mode Open-Loop ROUT (Note 9) 2.5 Ω
General Purpose Switching Regulator 2
IVIN2 Pulse Skip Mode Input Current IOUT2 = 0µA (Note 6) 225 µA
Burst Mode Input Current IOUT2 = 0µA (Note 6) 35 60 µA
Forced Burst Mode Input Current IOUT2 = 0µA (Note 6) 20 35 µA
LDO Mode Input Current IOUT2 = 0µA (Note 6) 20 35 µA
Shutdown Input Current IOUT2 = 0µA, FB2 = 0V 1 µA
ILIMSW2 PMOS Switch Current Limit Pulse Skip/Burst Mode Operation 600 800 1100 mA
IOUT2 Available Output Current Pulse Skip/Burst Mode Operation (Note 7) 400 mA
Forced Burst Mode Operation (Note 7) 60 mA
LDO Mode (Note 7) 50 mA

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LTC3555/LTC3555-X
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, BAT = 3.8V, DVCC = 3.3V, RPROG = 1k, RCLPROG = 3k,
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VFBHIGH2 Maximum Servo Voltage Full Scale (1, 1, 1, 1) (Note 8) l 0.78 0.80 0.82 V
VFBLOW2 Minimum Servo Voltage Zero Scale (0, 0, 0, 0) (Note 8) 0.405 0.425 0.445 V
VLSB2 VFB2 Servo Voltage Step Size 25 mV
RP2 PMOS RDS(ON) 0.6 Ω
RN2 NMOS RDS(ON) 0.7 Ω
RLDO_CL2 LDO Mode Closed-Loop ROUT 0.25 Ω
RLDO_OL2 LDO Mode Open-Loop ROUT (Note 9) 2.5 Ω
General Purpose Switching Regulator 3
IVIN3 Pulse Skip Mode Input Current IOUT3 = 0µA (Note 6) 225 µA
Burst Mode Input Current IOUT3 = 0µA (Note 6) 35 60 µA
Forced Burst Mode Input Current IOUT3 = 0µA (Note 6) 20 35 µA
LDO Mode Input Current IOUT3 = 0µA (Note 6) 20 35 µA
Shutdown Input Current IOUT3 = 0µA, FB3 = 0V 1 µA
ILIMSW3 PMOS Switch Current Limit Pulse Skip/Burst Mode Operation 1500 2000 2800 mA
IOUT3 Available Output Current Pulse Skip/Burst Mode Operation (Note 7) 1000 mA
Forced Burst Mode Operation (Note 7) 150 mA
LDO Mode (Note 7) 50 mA
VFBHIGH3 Maximum Servo Voltage Full Scale (1, 1, 1, 1) (Note 8) l 0.78 0.80 0.82 V
VFBLOW3 Minimum Servo Voltage Zero Scale (0, 0, 0, 0) (Note 8) 0.405 0.425 0.445 V
VLSB3 VFB Servo Voltage Step Size 25 mV
RP3 PMOS RDS(ON) 0.18 Ω
RN3 NMOS RDS(ON) 0.30 Ω
RLDOCL3 LDO Mode Closed Loop ROUT 0.25 Ω
RLDOOL3 LDO Mode Open Loop ROUT (Note 9) 2.5 Ω
tRST3 Power On Reset Time for Switching VFB3 Within 92% of Final Value to RST3 Hi-Z 230 ms
Regulator

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 4: Total input current is the sum of quiescent current, IVBUSQ, and
may cause permanent damage to the device. Exposure to any Absolute measured current given by:
Maximum Rating condition for extended periods may affect device VCLPROG/RCLPROG • (hCLPROG +1)
reliability and lifetime. Note 5: hC/10 is expressed as a fraction of measured full charge current
Note 2: The LTC3555E/LTC3555E-X are guaranteed to meet performance with indicated PROG resistor.
specifications from 0°C to 85°C. Specifications over the – 40°C to 85°C Note 6: FBx above regulation such that regulator is in sleep. Specification
operating temperature range are assured by design, characterization and does not include resistive divider current reflected back to VINx.
correlation with statistical process controls. The LTC3555I/LTC3555I-X are
Note 7: Guaranteed by design but not explicitly tested.
guaranteed to meet performance specifications over the full –40°C to 85°C
operating temperature range. Note 8: Applies to pulse skip, Burst Mode operation and forced Burst
Mode operation only.
Note 3: The LTC3555/LTC3555-X include overtemperature protection that
is intended to protect the device during momentary overload conditions. Note 9: Inductor series resistance adds to open-loop ROUT.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.

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 LTC3555/LTC3555-X
TYPICAL PERFORMANCE CHARACTERISTICS
Ideal Diode Resistance Output Voltage vs Output Current
Ideal Diode V-I Characteristics vs Battery Voltage (Battery Charger Disabled)
1.0 0.25 4.50
INTERNAL IDEAL DIODE VBUS = 5V
WITH SUPPLEMENTAL BAT = 4V 5x MODE
0.8 EXTERNAL VISHAY 0.20 4.25
Si2333 PMOS
INTERNAL IDEAL

OUTPUT VOLTAGE (V)

RESISTANCE (Ω)
DIODE
CURRENT (A)

0.6 0.15 4.00

INTERNAL IDEAL
DIODE ONLY BAT = 3.4V
0.4 0.10 3.75
INTERNAL IDEAL DIODE
WITH SUPPLEMENTAL
0.2 0.05 EXTERNAL VISHAY 3.50
Si2333 PMOS
VBUS = 0V
VBUS = 5V
0 0 3.25
0 0.04 0.08 0.12 0.16 0.20 2.7 3.0 3.3 3.6 3.9 4.2 0 200 400 600 800 1000
FORWARD VOLTAGE (V) BATTERY VOLTAGE (V) OUTPUT CURRENT (mA)
3555 G01 3555 G02 3555 G03

USB Limited Battery Charge USB Limited Battery Charge Battery Drain Current
Current vs Battery Voltage Current vs Battery Voltage vs Battery Voltage
700 150 25
LTC3555 LTC3555 IVOUT = 0µA
600 125 VBUS = 0V
LTC3555-1/ LTC3555-1/ 20
LTC3555-3 LTC3555-3
CHARGE CURRENT (mA)
CHARGE CURRENT (mA)

BATTERY CURRENT (µA)

500 VBUS = 5V VBUS = 5V
RPROG = 1k 100 RPROG = 1k
RCLPROG = 3k RCLPROG = 3k 15
400
75
300 LTC3555-3 10
LTC3555-3 50
200
VBUS = 5V
5 (SUSPEND MODE)
100 25
5x USB SETTING, 1x USB SETTING,
BATTERY CHARGER SET FOR 1A BATTERY CHARGER SET FOR 1A
0 0 0
2.7 3.0 3.3 3.6 3.9 4.2 2.7 3.0 3.3 3.6 3.9 4.2 2.7 3.0 3.3 3.6 3.9 4.2
BATTERY VOLTAGE (V) BATTERY VOLTAGE (V) BATTERY VOLTAGE (V)
3555 G04 3555 G05 3555 G06

Battery Charging Efficiency vs

PowerPath Switching Regulator Battery Voltage with No External VBUS Current vs VBUS Voltage
Efficiency vs Output Current Load (PBAT/PBUS) (Suspend)
100 100 50
BAT = 3.8V RCLPROG = 3k BAT = 3.8V
5x, 10x MODE
1x MODE RPROG = 1k IVOUT = 0mA
90 IVOUT = 0mA
40
QUIESCENT CURRENT (µA)

90
80
EFFICIENCY (%)

EFFICIENCY (%)

LTC3555-1/ 30
LTC3555-3
70 80
LTC3555-3 20
60
70 1x CHARGING EFFICIENCY
50 10

5x CHARGING EFFICIENCY
40 60 0
0.01 0.1 1 2.7 3.0 3.3 3.6 3.9 4.2 0 1 2 3 4 5
OUTPUT CURRENT (A) BATTERY VOLTAGE (V) BUS VOLTAGE (V)
3555 G07
3555 G08 3555 G09
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LTC3555/LTC3555-X
TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage vs Load Current in VBUS Current vs Load Current in 3.3V LDO Output Voltage vs Load
Suspend Suspend Current, VBUS = 0V
5.0 0.5 3.4
VBUS = 5V BAT = 3.9V, 4.2V BAT = 3.5V
BAT = 3.4V
BAT = 3.3V BAT = 3.6V
4.5 RCLPROG = 3k
0.4
3.2
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

VBUS CURRENT (mA)
4.0 0.3
3.0
3.5 0.2

BAT = 3V
2.8
3.0 VBUS = 5V 0.1 BAT = 3.1V
BAT = 3.3V BAT = 3.2V
RCLPROG = 3k BAT = 3.3V
2.5 0 2.6
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5 0 5 10 15 20 25
LOAD CURRENT (mA) LOAD CURRENT (mA) LOAD CURRENT (mA)
3555 G10 3555 G11 3555 G12

Battery Charge Current vs Normalized Battery Charger Float Low-Battery (Instant-On) Output
Temperature Voltage vs Temperature Voltage vs Temperature
600 1.001 3.68
BAT = 2.7V
IVOUT = 100mA
500 5x MODE
1.000
NORMALIZED FLOAT VOLTAGE

3.66
CHARGE CURRENT (mA)

OUTPUT VOLTAGE (V)

400
THERMAL REGULATION 0.999
300 3.64

0.998
200
3.62
0.997
100
RPROG = 2k
10x MODE
0 0.996 3.60
–40 –20 0 20 40 60 80 100 120 –40 –15 10 35 60 85 –40 –15 10 35 60 85
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3555 G13 3555 G14 3555 G15

Oscillator Frequency vs VBUS Quiescent Current vs VBUS Quiescent Current in

Temperature Temperature Suspend vs Temperature
2.6 15 70
VBUS = 5V IVOUT = 0µA
IVOUT = 0µA
5x MODE
QUIESCENT CURRENT (mA)

QUIESCENT CURRENT (µA)

2.4 BAT = 3.6V 12 60

VBUS = 5V
FREQUENCY (MHz)

VBUS = 0V

2.2 9 50

BAT = 3V
VBUS = 0V 1x MODE
2.0 6 40

BAT = 2.7V
VBUS = 0V
1.8 3 30
–40 –15 10 35 60 85 –40 –15 10 35 60 85 –40 –15 10 35 60 85
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3555 G16 3555 G17 3555 G18

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 LTC3555/LTC3555-X
TYPICAL PERFORMANCE CHARACTERISTICS
RST3, CHRG Pin Current vs 3.3V LDO Step Response Battery Drain Current vs
Voltage (Pull-Down State) (5mA to 15mA) Temperature
100 50
VBUS = 5V BAT = 3.8V
BAT = 3.8V VBUS = 0V
BUCK REGULATORS OFF
RST3, CHRG PIN CURRENT (mA)

80 ILDO3V3
40
5mA/DIV

BATTERY CURRENT (µA)

60 0mA 30

VLDO3V3
40 20mV/DIV 20
AC COUPLED

20 3555 G20
10
BAT = 3.8V 20µs/DIV

0 0
0 1 2 3 4 5 –40 –15 10 35 60 85
RST3, CHRG PIN VOLTAGE (V) TEMPERATURE (°C)
3555 G19 3555 G21

RDS(ON) for Switching Regulator Switching Regulator Current Limit Switching Regulator Low Power
Power Switches vs Temperature vs Temperature Mode Quiescent Currents
1.0 2.0 50
VIN1,2,3 = 3.8V
REGULATOR 3 VOUT1,2,3 = 2.5V
REGULATORS 1, 2
0.8 40
NMOS SWITCH 1.5
Burst Mode

INPUT CURRENT (µA)

ON-RESISTANCE (Ω)

CURRENT LIMIT (A)

OPERATION
0.6 30 FORCED
1.0 Burst Mode
PMOS SWITCH REGULATORS 1, 2 OPERATION
0.4 REGULATOR 3 20
LDO MODE

NMOS SWITCH 0.5

0.2 10
PMOS SWITCH
VIN1,2,3 = 3.8V
0 0 0
–40 –15 10 35 60 85 –40 –15 10 35 60 85 –40 –15 10 35 60 85
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3555 G22 3555 G23 3555 G24

Switching Regulators 1, 2 Pulse Switching Regulator 3 Pulse Skip Switching Regulator Soft-Start
Skip Mode Quiescent Currents Mode Quiescent Currents Waveform
325 1.95 400 11
VIN1,2 = 3.8V VOUT3 = 2.5V

300 1.90
350 10
VOUT 500mV/DIV

VOUT1,2 = 2.5V
INPUT CURRENT (mA)

INPUT CURRENT (mA)

INPUT CURRENT (µA)

INPUT CURRENT (µA)

(CONSTANT FREQUENCY) VIN3 = 3.5V

275 1.85 (CONSTANT FREQUENCY)
300 9
250 1.80

250 8
225 1.75
VIN3 = 3.8V 50µs/DIV
3555 G27
VOUT1,2 = 1.25V
(PULSE
(PULSE SKIPPING)
SKIPPING)
200 1.70 200 7
–40 –15 10 35 60 85 –40 –15 10 35 60 85
TEMPERATURE (°C) TEMPERATURE (°C)
3555 G25 3555 G26

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LTC3555/LTC3555-X
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Regulators 1, 2 Switching Regulators 1, 2 Switching Regulators 1, 2
Pulse Skip Mode Efficiency Burst Mode Efficiency Forced Burst Mode Efficiency
100 100 100
VOUT1,2 = 2.5V VOUT1,2 = 2.5V
90 90 90
VOUT1,2 = 2.5V
80 80 VOUT1,2 = 1.2V 80 VOUT1,2 = 1.2V
VOUT1,2 = 1.2V 70 VOUT1,2 = 1.8V 70
70 VOUT1,2 = 1.8V

EFFICIENCY (%)

EFFICIENCY (%)
EFFICIENCY (%)

VOUT1,2 = 1.8V
60 60 60
50 50 50
40 40 40
30 30 30
20 20 20
10 10 10
VIN1,2 = 3.8V VIN1,2 = 3.8V VIN1,2 = 3.8V
0 0 0
1 10 100 1000 0.1 1 10 100 1000 0.1 1 10 100 1000
LOAD CURRENT (mA) LOAD CURRENT (mA) LOAD CURRENT (mA)
3555 G28 3555 G29 3555 G30

Switching Regulator 3 Switching Regulator 3 Switching Regulator 3

Pulse Skip Mode Efficiency Burst Mode Efficiency Forced Burst Mode Efficiency
100 100 100
VIN3 = 3.8V VIN3 = 3.8V VOUT3 = 2.5V VIN3 = 3.8V VOUT3 = 2.5V
90 90 90
80 80 80
VOUT3 = 2.5V VOUT3 = 1.2V VOUT3 = 1.2V
70 70 70
VOUT3 = 1.2V VOUT3 = 1.8V VOUT3 = 1.8V
EFFICIENCY (%)

EFFICIENCY (%)

EFFICIENCY (%)
60 60 60
VOUT3 = 1.8V
50 50 50
40 40 40
30 30 30
20 20 20
10 10 10
0 0 0
1 10 100 1000 0.1 1 10 100 1000 0.1 1 10 100 1000
LOAD CURRENT (mA) LOAD CURRENT (mA) LOAD CURRENT (mA)
3555 G31 3555 G32 3555 G33

Switching Regulators 1, 2 Load Switching Regulators 1, 2 Load Switching Regulators 1, 2 Load

Regulation at VOUT1,2 = 1.2V Regulation at VOUT1,2 = 1.8V Regulation at VOUT1,2 = 2.5V
1.230 1.845 2.56
VIN1,2 = 3.8V VIN1,2 = 3.8V VIN1,2 = 3.8V

Burst Mode Burst Mode OPERATION

1.215 OPERATION 1.823 2.53 Burst Mode OPERATION
OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

PULSE SKIP MODE PULSE SKIP MODE

FORCED FORCED
1.200 1.800 Burst Mode 2.50
Burst Mode
PULSE SKIP OPERATION OPERATION
MODE

1.185 FORCED 1.778 2.47

Burst Mode
OPERATION
1.170 1.755 2.44
0.1 1 10 100 1000 0.1 1 10 100 1000 0.1 1 10 100 1000
LOAD CURRENT (mA) LOAD CURRENT (mA) LOAD CURRENT (mA)
3555 G34 3555 G35 3555 G36

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 LTC3555/LTC3555-X
PIN FUNCTIONS
LDO3V3 (Pin 1): 3.3V LDO Output Pin. This pin provides DVCC (Pin 8): Logic Supply for the I2C Serial Port. If the
a regulated always-on 3.3V supply voltage. LDO3V3 serial port is not needed it can be disabled by grounding
gets its power from VOUT. It may be used for light loads DVCC. When DVCC is grounded, chip control is automati-
such as a watchdog microprocessor or real time clock. cally passed to the individual logic input pins.
A 1µF capacitor is required from LDO3V3 to ground. If SCL (Pin 9): Clock Input Pin for the I2C Serial Port. The
the LDO3V3 output is not used it should be disabled by I2C logic levels are scaled with respect to DVCC. If DVCC
connecting it to VOUT. is grounded, the SCL pin is equivalent to the B5 bit in the
CLPROG (Pin 2): USB Current Limit Program and Moni- I2C serial port. SCL in conjunction with SDA determine
tor Pin. A resistor from CLPROG to ground determines the operating modes of switching regulators 1, 2 and 3
the upper limit of the current drawn from the VBUS pin. when DVCC is grounded. See Tables 2 and 5.
A fraction of the VBUS current is sent to the CLPROG pin SDA (Pin 10): Data Input Pin for the I2C Serial Port. The
when the synchronous switch of the PowerPath switching I2C logic levels are scaled with respect to DVCC. If DVCC
regulator is on. The switching regulator delivers power until is grounded, the SDA pin is equivalent to the B6 bit in the
the CLPROG pin reaches 1.188V. Several VBUS current limit I2C serial port. SDA in conjunction with SCL determine
settings are available via user input which will typically the operating modes of switching regulators 1, 2 and 3
correspond to the 500mA and 100mA USB specifications. when DVCC is grounded. See Tables 2 and 5.
A multi-layer ceramic averaging capacitor or R-C network
is required at CLPROG for filtering. VIN3 (Pin 11): Power Input for Switching Regulator 3.
This pin will generally be connected to VOUT. A 1µF MLCC
NTC (Pin 3): Input to the Thermistor Monitoring Circuits. capacitor is recommended on this pin.
The NTC pin connects to a battery’s thermistor to deter-
mine if the battery is too hot or too cold to charge. If the SW3 (Pin 12): Power Transmission Pin for Switching
battery’s temperature is out of range, charging is paused Regulator 3.
until it re-enters the valid range. A low drift bias resistor EN3 (Pin 13): Logic Input. This logic input pin indepen-
is required from VBUS to NTC and a thermistor is required dently enables switching regulator 3. This pin is logically
from NTC to ground. If the NTC function is not desired, OR-ed with its corresponding bit in the I2C serial port.
the NTC pin should be grounded. See Table 2.
FB2 (Pin 4): Feedback Input for Switching Regulator 2. FB3 (Pin 14): Feedback Input for Switching Regulator 3.
When regulator 2’s control loop is complete, this pin servos When regulator 3’s control loop is complete, this pin servos
to 1 of 16 possible set-points based on the commanded to 1 of 16 possible set-points based on the commanded
value from the I2C serial port. See Table 4. value from the I2C serial port. See Table 4.
VIN2 (Pin 5): Power Input for Switching Regulator 2. This RST3 (Pin 15): Logic Output. This in an open-drain output
pin will generally be connected to VOUT. A 1µF MLCC which indicates that switching regulator 3 has settled to
capacitor is recommended on this pin. its final value. It can be used as a power-on reset for the
SW2 (Pin 6): Power Transmission Pin for Switching primary microprocessor or to enable the other switching
Regulator 2. regulators for supply sequencing.
EN2 (Pin 7): Logic Input. This logic input pin independently EN1 (Pin 16): Logic Input. This logic input pin indepen-
enables switching regulator 2. This pin is logically OR-ed dently enables switching regulator 1. This pin is logically
with its corresponding bit in the I2C serial port. See Table 2. OR-ed with its corresponding bit in the I2C serial port.
See Table 2.

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LTC3555/LTC3555-X
PIN FUNCTIONS
SW1 (Pin 17): Power Transmission Pin for Switching BAT (Pin 23): Single Cell Li-Ion Battery Pin. Depending on
Regulator 1. available VBUS power, a Li-Ion battery on BAT will either
deliver power to VOUT through the ideal diode or be charged
VIN1 (Pin 18): Power Input for Switching Regulator 1.
from VOUT via the battery charger.
This pin will generally be connected to VOUT. A 1µF MLCC
capacitor is recommended on this pin. VOUT (Pin 24): Output voltage of the Switching PowerPath
Controller and Input Voltage of the Battery Charger. The
FB1 (Pin 19): Feedback Input for Switching Regulator 1.
majority of the portable product should be powered from
When regulator 1’s control loop is complete, this pin
VOUT. The LTC3555 family will partition the available power
servos to a fixed voltage of 0.8V.
between the external load on VOUT and the internal battery
PROG (Pin 20): Charge Current Program and Charge charger. Priority is given to the external load and any extra
Current Monitor Pin. Connecting a resistor from PROG power is used to charge the battery. An ideal diode from
to ground programs the charge current. If sufficient in- BAT to VOUT ensures that VOUT is powered even if the load
put power is available in constant-current mode, this pin exceeds the allotted power from VBUS or if the VBUS power
servos to 1V. The voltage on this pin always represents source is removed. VOUT should be bypassed with a low
the actual charge current. impedance ceramic capacitor.
CHRG (Pin 21): Open-Drain Charge Status Output. The VBUS (Pin 25): Primary Input Power Pin. This pin delivers
CHRG pin indicates the status of the battery charger. Four power to VOUT via the SW pin by drawing controlled cur-
possible states are represented by CHRG: charging, not rent from a DC source such as a USB port or wall adapter.
charging, unresponsive battery and battery temperature
SW (Pin 26): Power Transmission Pin for the USB Power
out of range. CHRG is modulated at 35kHz and switches
Path. The SW pin delivers power from VBUS to VOUT via the
between a low and a high duty cycle for easy recognition
step-down switching regulator. A 3.3µH inductor should
by either humans or microprocessors. See Table 1. CHRG
be connected from SW to VOUT.
requires a pull-up resistor and/or LED to provide indication.
ILIM0, ILIM1 (Pins 27, 28): Logic Inputs. ILIM0 and ILIM1
GATE (Pin 22): Analog Output. This pin controls the gate
control the current limit of the PowerPath switching
of an optional external P-channel MOSFET transistor used
regulator. See Table 3. Both of the ILIM0 and ILIM1 pins are
to supplement the ideal diode between VOUT and BAT. The
logically OR-ed with their corresponding bits in the I2C
external ideal diode operates in parallel with the internal
serial port. See Table 2.
ideal diode. The source of the P-channel MOSFET should
be connected to VOUT and the drain should be connected Exposed Pad (Pin 29): Ground. The Exposed Pad should
to BAT. If the external ideal diode FET is not used, GATE be connected to a continuous ground plane on the second
should be left floating. layer of the printed circuit board by several vias directly
under the part.

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 LTC3555/LTC3555-X
BLOCK DIAGRAM
VBUS 25

2.25MHz
PowerPath
SWITCHING 26 SW
REGULATOR 1 LDO3V3
3.3V LDO
SUSPEND
LDO 24 VOUT
500µA
+
– – CC/CV IDEAL 22 GATE
CLPROG 2 –
CHARGER
+
+
–
+
+
0.3V 15mV
+–
BATTERY 23 BAT
NTC 3 TEMPERATURE 1.188V 3.6V
MONITOR 20 PROG

18 VIN1
CHRG 21 ENABLE
CHARGE 17 SW1
STATUS
400mA 2.25MHz
SWITCHING
REGULATOR 1
19 FB1

5 VIN2
ENABLE
400mA 2.25MHz 6 SW2
D/A SWITCHING
REGULATOR 2
4 FB2
4
ILIM
DECODE
11 VIN3
LOGIC
ENABLE
1A 2.25MHz 12 SW3
D/A SWITCHING
REGULATOR 3
ILIM0 27
14 FB3
ILIM1 28

EN1 16 4 15 RST3

EN2 7

EN3 13

DVCC 8

SDA 10 I2C PORT

SCL 9

29
3555 BD
GND

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LTC3555/LTC3555-X
TIMING DIAGRAM
DATA BYTE A DATA BYTE B
ADDRESS WR

0 0 0 1 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0

START STOP
SDA 0 0 0 1 0 0 1 0 ACK ACK ACK

SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SDA

tSU, DAT tSU, STA tBUF

tLOW tHD, DAT tHD, STA tSU, STO

3555 TD
SCL

tHD, STA tHIGH tSP

START tr tf REPEATED START STOP START
CONDITION CONDITION CONDITION CONDITION

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 LTC3555/LTC3555-X
OPERATION
Introduction The three general purpose switching regulators can be
independently enabled via either direct digital control or
The LTC3555 family are highly integrated power manage-
by operating the I2C serial port. Under I2C control, two of
ment ICs which include a high efficiency switch mode
the three switching regulators have adjustable set-points
PowerPath controller, a battery charger, an ideal diode,
so that voltages can be reduced when high processor
an always-on LDO and three general purpose step-down
performance is not needed. Along with constant frequency
switching regulators. The entire chip is controlled by either
PWM mode, all three switching regulators have a low
direct digital control, by an I2C serial port or both.
power burst-only mode setting as well as automatic Burst
Designed specifically for USB applications, the PowerPath Mode operation and LDO modes for significantly reduced
controller incorporates a precision average input current quiescent current under light load conditions.
step-down switching regulator to make maximum use of
the allowable USB power. Because power is conserved, the High Efficiency Switching PowerPath Controller
LTC3555 family allows the load current on VOUT to exceed Whenever VBUS is available and the PowerPath switching
the current drawn by the USB port without exceeding the regulator is enabled, power is delivered from VBUS to VOUT
USB load specifications. via SW. VOUT drives the combination of the external load
The PowerPath switching regulator and battery charger (switching regulators 1, 2 and 3) and the battery charger.
communicate to ensure that the input current never violates If the combined load does not exceed the PowerPath switch-
the USB specifications. ing regulator’s programmed input current limit, VOUT will
The ideal diode from BAT to VOUT guarantees that ample track 0.3V above the battery. By keeping the voltage across
power is always available to VOUT even if there is insuf- the battery charger low, efficiency is optimized because
ficient or absent power at VBUS. power lost to the linear battery charger is minimized.
Power available to the external load is therefore optimized.
An “always on” LDO provides a regulated 3.3V from
available power at VOUT. Drawing very little quiescent
current, this LDO will be on at all times and can be used
to supply up to 25mA.

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LTC3555/LTC3555-X
OPERATION
4.5
If the combined load at VOUT is large enough to cause the
switching power supply to reach the programmed input 4.2

current limit, the battery charger will reduce its charge cur- 3.9
rent by that amount necessary to enable the external load NO LOAD
to be satisfied. Even if the battery charge current is set to 3.6

VOUT (V)
300mV
exceed the allowable USB current, the USB specification 3.3
will not be violated. The switching regulator will limit the 3.0
average input current so that the USB specification is never
violated. Furthermore, load current at VOUT will always be 2.7

prioritized and only excess available power will be used 2.4

2.4 2.7 3.0 3.3 3.6 3.9 4.2
to charge the battery. BAT (V)

If the voltage at BAT is below 3.3V, or the battery is not 3555 F01

present, and the load requirement does not cause the Figure 1. VOUT vs BAT
switching regulator to exceed the USB specification, VOUT
will regulate at 3.6V. If the load exceeds the available power, The LTC3555 vs the LTC3555-1 and LTC3555-3
VOUT will drop to a voltage between 3.6V and the battery
For very low battery voltages, the battery charger acts
voltage. If there is no battery present when the load exceeds
like a load and, due to limited input power, its current will
the available USB power, VOUT can drop toward ground.
tend to pull VOUT below the 3.6V “instant-on” voltage. To
The power delivered from VBUS to VOUT is controlled prevent VOUT from falling below this level, the LTC3555-1
by a 2.25MHz constant-frequency step-down switching and LTC3555-3 include an undervoltage circuit that auto-
regulator. To meet the USB maximum load specification, matic detects that VOUT is falling and reduces the battery
the switching regulator includes a control loop which charge current as needed. This reduction ensures that load
ensures that the average input current is below the level current and output voltage are always prioritized and yet
programmed at CLPROG. delivers as much battery charge current as possible. The
The current at CLPROG is a fraction (hCLPROG–1) of the VBUS standard LTC3555 does not include this circuit and thus
current. When a programming resistor and an averaging favors maximum charge current at all times over output
capacitor are connected from CLPROG to GND, the voltage voltage preservation.
on CLPROG represents the average input current of the If instant-on operation under low battery conditions is a
switching regulator. When the input current approaches requirement then the LTC3555-1 or LTC3555-3 should be
the programmed limit, CLPROG reaches VCLPROG, 1.188V, used. If maximum charge efficiency at low battery voltages
and power out is held constant. The input current limit is preferred, and instant-on operation is not a requirement,
is programmed by the ILIM0 and ILIM1 pins or by the I2C then the standard LTC3555 should be selected. All versions
serial port. It can be configured to limit average input of the LTC3555 family will start up with a removed battery.
current to one of several possible settings as well as be
The LTC3555-3 has a battery charger float voltage of
deactivated (USB suspend). The input current limit will
4.100V rather than the 4.200V float voltage of the LTC3555
be set by the VCLPROG servo voltage and the resistor on
and LTC3555-1.
CLPROG according to the following expression:
Ideal Diode from BAT to VOUT
VCLPROG
IVBUS = IVBUSQ + • (hCLPROG + 1)
RCLPROG The LTC3555 family has an internal ideal diode as well as
a controller for an optional external ideal diode. The ideal
Figure 1 shows the range of possible voltages at VOUT as diode controller is always on and will respond quickly
a function of battery voltage. whenever VOUT drops below BAT.

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 LTC3555/LTC3555-X
OPERATION
If the load current increases beyond the power allowed at BAT. The resistance of the internal ideal diode is approxi-
from the switching regulator, additional power will be mately 180mΩ. If this is sufficient for the application, then
pulled from the battery via the ideal diode. Furthermore, no external components are necessary. However, if more
if power to VBUS (USB or wall power) is removed, then all conductance is needed, an external P-channel MOSFET
of the application power will be provided by the battery transistor can be added from BAT to VOUT.
via the ideal diode. The transition from input power to When an external P-channel MOSFET transistor is pres-
battery power at VOUT will be quick enough to allow only ent, the GATE pin of the LTC3555 family drives its gate for
the 10µF capacitor to keep VOUT from drooping. The ideal automatic ideal diode control. The source of the external
diode consists of a precision amplifier that enables a large P-channel MOSFET should be connected to VOUT and the
on-chip P-channel MOSFET transistor whenever the voltage drain should be connected to BAT. Capable of driving a
at VOUT is approximately 15mV (VFWD) below the voltage 1nF load, the GATE pin can control an external P-channel
MOSFET transistor having an on-resistance of 40mΩ or
2200 lower.
VISHAY Si2333
2000
OPTIONAL EXTERNAL
1800 IDEAL DIODE Suspend LDO
1600
1400 If the LTC3555 family is configured for USB suspend
CURRENT (mA)

1200
LTC3555
IDEAL DIODE
mode, the switching regulator is disabled and the suspend
1000 LDO provides power to the VOUT pin (presuming there is
800
power available to VBUS). This LDO will prevent the bat-
600 ON
400
SEMICONDUCTOR tery from running down when the portable product has
200
MBRM120LT3
access to a suspended USB port. Regulating at 4.6V, this
0 LDO only becomes active when the switching converter
60 120 180 240 300 360 420 480
0
FORWARD VOLTAGE (mV) (BAT – VOUT)
is disabled (suspended). To remain compliant with the
3555 F02
USB specification, the input to the LDO is current limited
so that it will not exceed the 500µA low power suspend

3.5V TO
TO USB VBUS SW (BAT + 0.3V)
OR WALL 25 26
TO SYSTEM
ADAPTER LOAD
VOUT
PWM AND 24
GATE DRIVE

ISWITCH/ IDEAL
hCLPROG DIODE OPTIONAL
CONSTANT CURRENT
+ GATE EXTERNAL
22
IDEAL DIODE
CONSTANT VOLTAGE – PMOS
BATTERY CHARGER –
15mV +

CLPROG – – 0.3V
2 BAT
+
+
+ +– 23
1.188V 3.6V

AVERAGE INPUT AVERAGE OUTPUT

CURRENT LIMIT VOLTAGE LIMIT
+ SINGLE CELL
CONTROLLER CONTROLLER Li-Ion
3555 F03

Figure 3. PowerPath Block Diagram

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LTC3555/LTC3555-X
OPERATION
specification. If the load on VOUT exceeds the suspend current delivered to the battery will try to reach 1022V/
current limit, the additional current will come from the RPROG. Depending on available input power and external
battery via the ideal diode. load conditions, the battery charger may or may not be
able to charge at the full programmed rate. The external
3.3V Always-On LDO Supply load will always be prioritized over the battery charge
The LTC3555 family includes a low quiescent current low current. The USB current limit programming will always
dropout regulator that is always powered. This LDO can be be observed and only additional power will be available to
used to provide power to a system pushbutton controller, charge the battery. When system loads are light, battery
standby microcontroller or real time clock. Designed to charge current will be maximized.
deliver up to 25mA, the always-on LDO requires at least
Charge Termination
a 1µF low impedance ceramic bypass capacitor for com-
pensation. The LDO is powered from VOUT , and therefore The battery charger has a built-in safety timer. When the
will enter dropout at loads less than 25mA as VOUT falls voltage on the battery reaches the pre-programmed float
near 3.3V. If the LDO3V3 output is not used, it should be voltage, the battery charger will regulate the battery volt-
disabled by connecting it to VOUT. age and the charge current will decrease naturally. Once
the battery charger detects that the battery has reached
VBUS Undervoltage Lockout (UVLO) the float voltage, the four hour safety timer is started.
An internal undervoltage lockout circuit monitors VBUS and After the safety timer expires, charging of the battery will
keeps the PowerPath switching regulator off until VBUS discontinue and no more current will be delivered.
rises above 4.30V and is about 200mV above the battery Automatic Recharge
voltage. Hysteresis on the UVLO turns off the regulator if
VBUS drops below 4.00V or to within 50mV of BAT. When After the battery charger terminates, it will remain off
this happens, system power at VOUT will be drawn from drawing only microamperes of current from the battery.
the battery via the ideal diode. If the portable product remains in this state long enough,
the battery will eventually self discharge. To ensure that
Battery Charger the battery is always topped off, a charge cycle will auto-
matically begin when the battery voltage falls below the
The LTC3555 family includes a constant-current/ recharge threshold which is typically 100mV less than
constant-voltage battery charger with automatic recharge, the charger’s float voltage. In the event that the safety
automatic termination by safety timer, low voltage trickle timer is running when the battery voltage falls below the
charging, bad cell detection and thermistor sensor input recharge threshold, it will reset back to zero. To prevent
for out-of-temperature charge pausing. brief excursions below the recharge threshold from reset-
ting the safety timer, the battery voltage must be below
Battery Preconditioning
the recharge threshold for more than 1.3ms. The charge
When a battery charge cycle begins, the battery charger cycle and safety timer will also restart if the VBUS UVLO
first determines if the battery is deeply discharged. If the cycles low and then high (e.g., VBUS is removed and then
battery voltage is below VTRKL, typically 2.85V, an automatic replaced), or if the battery charger is cycled on and off
trickle charge feature sets the battery charge current to by the I2C port.
10% of the programmed value. If the low voltage persists
for more than 1/2 hour, the battery charger automatically Charge Current
terminates and indicates via the CHRG pin that the battery The charge current is programmed using a single resis-
was unresponsive. tor from PROG to ground. 1/1022th of the battery charge
Once the battery voltage is above 2.85V, the battery charger current is sent to PROG which will attempt to servo to
begins charging in full power constant-current mode. The 1.000V. Thus, the battery charge current will try to reach
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 LTC3555/LTC3555-X
OPERATION
1022 times the current in the PROG pin. The program duty cycles are disparate enough to make an LED appear
resistor and the charge current are calculated using the to be on or off thus giving the appearance of “blinking”.
following equations: Each of the two faults has its own unique “blink” rate for
1022V 1022V human recognition as well as two unique duty cycles for
RPROG = , ICHG = machine recognition.
ICHG RPROG
In either the constant-current or constant-voltage charging The CHRG pin does not respond to the C/10 threshold if
modes, the voltage at the PROG pin will be proportional to the LTC3555 family is in VBUS current limit. This prevents
the actual charge current delivered to the battery. There- false end-of-charge indications due to insufficient power
fore, the actual charge current can be determined at any available to the battery charger.
time by monitoring the PROG pin voltage and using the Table 1 illustrates the four possible states of the CHRG
following equation: pin when the battery charger is active.
VPROG Table 1. CHRG Signal
IBAT = • 1022
RPROG MODULATION
STATUS FREQUENCY (BLINK) FREQUENCY DUTY CYCLES
In many cases, the actual battery charge current, IBAT, will Charging 0Hz 0Hz (Lo-Z) 100%
be lower than ICHG due to limited input power available
Not Charging 0Hz 0Hz (Hi-Z) 0%
and prioritization with the system load drawn from VOUT.
NTC Fault 35kHz 1.5Hz at 50% 6.25% to 93.75%
Bad Battery 35kHz 6.1Hz at 50% 12.5% to 87.5%
Charge Status Indication
The CHRG pin indicates the status of the battery charger. An NTC fault is represented by a 35kHz pulse train whose
Four possible states are represented by CHRG which in- duty cycle varies between 6.25% and 93.75% at a 1.5Hz
clude charging, not charging, unresponsive battery, and rate. A human will easily recognize the 1.5Hz rate as a
battery temperature out of range. “slow” blinking which indicates the out-of-range battery
temperature while a microprocessor will be able to decode
The signal at the CHRG pin can be easily recognized as either the 6.25% or 93.75% duty cycles as an NTC fault.
one of the above four states by either a human or a mi-
croprocessor. An open-drain output, the CHRG pin can If a battery is found to be unresponsive to charging (i.e.,
drive an indicator LED through a current limiting resistor its voltage remains below 2.85V for 1/2 hour), the CHRG
for human interfacing or simply a pull-up resistor for pin gives the battery fault indication. For this fault, a human
microprocessor interfacing. would easily recognize the frantic 6.1Hz “fast” blink of the
LED while a microprocessor would be able to decode either
To make the CHRG pin easily recognized by both humans the 12.5% or 87.5% duty cycles as a bad battery fault.
and microprocessors, the pin is either low for charging,
high for not charging, or it is switched at high frequency Note that the LTC3555 family is a three terminal PowerPath
(35kHz) to indicate the two possible faults, unresponsive product where system load is always prioritized over battery
battery and battery temperature out of range. charging. Due to excessive system load, there may not be
sufficient power to charge the battery beyond the trickle
When charging begins, CHRG is pulled low and remains charge threshold voltage within the bad battery timeout
low for the duration of a normal charge cycle. When period. In this case, the battery charger will falsely indicate
charging is complete, i.e., the BAT pin reaches the float a bad battery. System software may then reduce the load
voltage and the charge current has dropped to one tenth and reset the battery charger to try again.
of the programmed value, the CHRG pin is released (Hi-Z).
If a fault occurs, the pin is switched at 35kHz. While Although very improbable, it is possible that a duty cycle
switching, its duty cycle is modulated between a low reading could be taken at the bright-dim transition (low
and high value at a very low frequency. The low and high duty cycle to high duty cycle). When this happens the
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LTC3555/LTC3555-X
OPERATION
duty cycle reading will be precisely 50%. If the duty cycle than worst-case conditions with the assurance that the
reading is 50%, system software should disqualify it and battery charger will automatically reduce the current in
take a new duty cycle reading. worst-case conditions.

NTC Thermistor I2C Interface

The battery temperature is measured by placing a nega- The LTC3555 family may receive commands from a host
tive temperature coefficient (NTC) thermistor close to the (master) using the standard I2C 2-wire interface. The Timing
battery pack. Diagram shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
To use this feature, connect the NTC thermistor, RNTC,
between the NTC pin and ground and a resistor, RNOM, when the bus is not in use. External pull-up resistors or
from VBUS to the NTC pin. RNOM should be a 1% resistor current sources, such as the LTC1694 I2C accelerator, are
required on these lines. The LTC3555 family is a receive-
with a value equal to the value of the chosen NTC therm-
only slave device. The I2C control signals, SDA and SCL
istor at 25°C (R25). For applications requiring greater
are scaled internally to the DVCC supply. DVCC should be
than 750mA of charging current, a 10k NTC thermistor is
connected to the same power supply as the microcontroller
recommended due to increased interference.
generating the I2C signals.
The LTC3555 family will pause charging when the
The I2C port has an undervoltage lockout on the DVCC
resistance of the NTC thermistor drops to 0.54 times
pin. When DVCC is below approximately 1V, the I2C serial
the value of R25 or approximately 5.4k. For a Vishay
port is cleared and switching regulators 2 and 3 are set
“Curve 1” thermistor, this corresponds to approximately
to full scale.
40°C. If the battery charger is in constant voltage (float)
mode, the safety timer also pauses until the thermistor Bus Speed
indicates a return to a valid temperature. As the tempera-
ture drops, the resistance of the NTC thermistor rises. The The I2C port is designed to be operated at speeds of up
LTC3555 family is also designed to pause charging when to 400kHz. It has built-in timing delays to ensure correct
the value of the NTC thermistor increases to 3.25 times operation when addressed from an I2C compliant master
the value of R25. For Vishay “Curve 1” this resistance, device. It also contains input filters designed to suppress
32.5k, corresponds to approximately 0°C. The hot and cold glitches should the bus become corrupted.
comparators each have approximately 3°C of hysteresis
to prevent oscillation about the trip point. Grounding the Start and Stop Conditions
NTC pin disables the NTC charge pausing function. A bus-master signals the beginning of a communication to
a slave device by transmitting a START condition. A START
Thermal Regulation condition is generated by transitioning SDA from high
To optimize charging time, an internal thermal feedback to low while SCL is high. When the master has finished
loop may automatically decrease the programmed charge communicating with the slave, it issues a STOP condition
current. This will occur if the die temperature rises to by transitioning SDA from low to high while SCL is high.
approximately 110°C. Thermal regulation protects the
LTC3555 family from excessive temperature due to high Byte Format
power operation or high ambient thermal conditions and Each byte sent to the LTC3555 family must be eight bits
allows the user to push the limits of the power handling long followed by an extra clock cycle for the acknowledge
capability with a given circuit board design without risk of bit to be returned by the LTC3555 family. The data should be
damaging the part or external components. The benefit of sent to the LTC3555 family most significant bit (MSB) first.
the LTC3555 family thermal regulation loop is that charge
current can be set according to actual conditions rather
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OPERATION
Table 2. I2C Serial Port Mapping
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
Switching Regulator 2 Switching Regulator 3 Disable Switching Enable Enable Enable Input Current
Voltage (See Table 4) Voltage (See Table 4) Battery Regulator Regulator Regulator Regulator Limit
Charger Modes 1 2 3 (See Table 3)
(See Table 5)

Table 3. USB Current Limit Settings Acknowledge

B1 B0
(ILIM1) (ILIM0) USB SETTING The acknowledge signal is used for handshaking between
0 0 1x Mode (USB 100mA Limit) the master and the slave. An acknowledge (active low)
0 1 10x Mode (Wall 1A Limit) generated by the slave (LTC3555 family) lets the master
1 0 Suspend know that the latest byte of information was received.
1 1 5x Mode (USB 500mA Limit) The acknowledge related clock pulse is generated by the
master. The master releases the SDA line (high) during
the acknowledge clock cycle. The slave-receiver must pull
Table 4. Switching Regulator Servo Voltage
down the SDA line during the acknowledge clock pulse
A7 A6 A5 A4 Switching Regulator 2 Servo Voltage
so that it remains a stable low during the high period of
A3 A2 A1 A0 Switching Regulator 3 Servo Voltage
this clock pulse.
0 0 0 0 0.425V
0 0 0 1 0.450V Slave Address
0 0 1 0 0.475V
The LTC3555 family responds to only one 7-bit address
0 0 1 1 0.500V
which has been factory programmed to 0001001. The
0 1 0 0 0.525V
eighth bit of the address byte (R/W) must be 0 for the
0 1 0 1 0.550V
LTC3555 family to recognize the address since it is a write
0 1 1 0 0.575V
only device. This effectively forces the address to be eight
0 1 1 1 0.600V
bits long where the least significant bit of the address is
1 0 0 0 0.625V 0. If the correct seven bit address is given but the R/W bit
1 0 0 1 0.650V is 1, the LTC3555 family will not respond.
1 0 1 0 0.675V
1 0 1 1 0.700V Bus Write Operation
1 1 0 0 0.725V
The master initiates communication with the LTC3555
1 1 0 1 0.750V
family with a START condition and a 7-bit address followed
1 1 1 0 0.775V
by the write bit R/W = 0. If the address matches that of the
1 1 1 1 0.800V
LTC3555 family, the LTC3555 family returns an acknowl-
edge. The master should then deliver the most significant
Table 5. General Purpose Switching Regulator Modes data byte. Again the LTC3555 family acknowledges and
B6 B5 the cycle is repeated for a total of one address byte and
(SDA)* (SCL)* Switching Regulator Mode two data bytes. Each data byte is transferred to an internal
0 0 Pulse Skip holding latch upon the return of an acknowledge. After both
0 1 Forced Burst Mode Operation data bytes have been transferred to the LTC3555 family,
1 0 LDO Mode the master may terminate the communication with a STOP
1 1 Burst Mode Operation condition. Alternatively, a REPEAT-START condition can be
*SDA and SCL take on this context only when DVCC = 0V. initiated by the master and another chip on the I2C bus
can be addressed. This cycle can continue indefinitely and
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LTC3555/LTC3555-X
OPERATION
the LTC3555 family will remember the last input of valid remains low impedance until regulator 3 reaches 92% of
data that it received. Once all chips on the bus have been its regulation value. A 230ms delay is included to allow a
addressed and sent valid data, a global STOP condition can system microcontroller ample time to reset itself. RST3
be sent and the LTC3555 family will update its command may be used as a power-on reset to the microprocessor
latch with the data that it had received. powered by regulator 3 or may be used to enable regulators
In certain circumstances the data on the I2C bus may 1 and/or 2 for supply sequencing. RST3 is an open-drain
become corrupted. In these cases the LTC3555 family output and requires a pull-up resistor to the output volt-
responds appropriately by preserving only the last set of age of regulator 3 or another appropriate power source.
complete data that it has received. For example, assume
General Purpose Step-Down Switching Regulators
the LTC3555 family has been successfully addressed and is
receiving data when a STOP condition mistakenly occurs. The LTC3555 family contains three general purpose
The LTC3555 family will ignore this STOP condition and 2.25MHz step-down constant-frequency current mode
will not respond until a new START condition, correct ad- switching regulators. Two regulators provide up to 400mA
dress, new set of data and STOP condition are transmitted. and a third switching regulator can produce up to 1A.
All three switching regulators can be programmed for a
Likewise, with only one exception, if the LTC3555 family was
minimum output voltage of 0.8V and can be used to power
previously addressed and sent valid data but not updated
a microcontroller core, microcontroller I/O, memory, disk
with a STOP, it will respond to any STOP that appears on
drive or other logic circuitry. Two of the switching regulators
the bus, independent of the number of REPEAT-STARTS
have I2C programmable set-points for on-the-fly power
that have occurred. If a REPEAT-START is given and the
savings. All three converters support 100% duty cycle
LTC3555 family successfully acknowledges its address and
operation (low dropout mode) when their input voltage
first byte, it will not respond to a STOP until both bytes
drops very close to their output voltage. To suit a variety
of the new data have been received and acknowledged.
of applications, selectable mode functions can be used
Disabling the I2C Port to trade-off noise for efficiency. Four modes are available
to control the operation of the LTC3555 family’s general
The I2C serial port can be disabled by grounding the DVCC purpose switching regulators. At moderate to heavy loads,
pin. In this mode, control automatically passes to the in- the pulse skip mode provides the least noise switching
dividual logic input pins EN1, EN2, EN3, ILIM0, ILIM1, SDA solution. At lighter loads, either Burst Mode operation,
and SCL. Some functionality is not available in this mode forced Burst Mode operation or LDO mode may be selected.
such as the programmability of switching regulators 2 The switching regulators include soft-start to limit inrush
and 3’s output voltage and the battery charger disable current when powering on, short-circuit current protection
feature. In this mode, both of the programmable switching and switch node slew limiting circuitry to reduce radiated
regulators have a fixed servo voltage of 0.8V. EMI. No external compensation components are required.
Because the SDA and SCL pins have no other context when The operating mode of the regulators may be set by either
DVCC is grounded, these pins are re-mapped to control I2C control or by manual control of the SDA and SCL pins
the switching regulator mode bits B5 and B6. SCL maps if the I2C port is not used. Each converter may be individu-
to B5 and SDA maps to B6. ally enabled by either their external control pins EN1, EN2,
EN3 or by the I2C port. Switching regulators 2 and 3 have
RST3 Pin individual programmable feedback servo voltages via I2C
control. The switching regulator input supplies VIN1, VIN2
The RST3 pin is an open-drain output used to indicate that
and VIN3 will generally be connected to the system load
switching regulator 3 has reached its final voltage. RST3
pin VOUT.

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OPERATION
Step-Down Switching Regulator Output Voltage latch which causes the main P-channel MOSFET switch to
Programming turn off and the N-channel MOSFET synchronous rectifier
All three switching regulators can be programmed for to turn on. The N-channel MOSFET synchronous rectifier
output voltages greater than 0.8V. Switching regulators 2 turns off at the end of the 2.25MHz cycle or if the current
and 3 have I2C programmable set-points while regulator 1 through the N-channel MOSFET synchronous rectifier
has a single fixed set-point. The full-scale output voltage for drops to zero. Using this method of operation, the error
each switching regulator is programmed using a resistor amplifier adjusts the peak inductor current to deliver the
divider from the switching regulator output connected to required output power. All necessary compensation is
the feedback pins (FB1, FB2 and FB3) such that: internal to the switching regulator requiring only a single
ceramic output capacitor for stability. At light loads in PWM
⎛ R1 ⎞ mode, the inductor current may reach zero on each pulse
VOUTX = VFBX ⎜ + 1⎟
⎝ R2 ⎠ which will turn off the N-channel MOSFET synchronous
rectifier. In this case, the switch node (SW) goes high
where VFBX ranges from 0.425V to 0.8V for switching impedance and the switch node voltage will “ring”. This
regulators 2 and 3 and VFBX is fixed at 0.8V for switching is discontinuous mode operation, and is normal behavior
regulator 1. See Figure 4 for a switching regulator. At very light loads in pulse skip
mode, the switching regulators will automatically skip
VINx L
pulses as needed to maintain output regulation.
SWx VOUTx
LTC3555/ At high duty cycles (VOUTx > VINx /2) it is possible for the
CFB R1 COUT
LTC3555-X
FBx
inductor current to reverse, causing the regulator to operate
R2
continuously at light loads. This is normal and regulation is
GND maintained, but the supply current will increase to several
3555 F04
milliamperes due to continuous switching.
Figure 4. Buck Converter Application Circuit
In forced Burst Mode operation, the switching regulators
Typical values for R1 are in the range of 40k to 1M. The use a constant current algorithm to control the inductor
capacitor CFB cancels the pole created by feedback resis- current. By controlling the inductor current directly and
tors and the input capacitance of the FB pin and also helps using a hysteretic control loop, both noise and switching
to improve transient response for output voltages much losses are minimized. In this mode output power is limited.
greater than 0.8V. A variety of capacitor sizes can be used While in forced Burst Mode operation, the output capacitor
for CFB but a value of 10pF is recommended for most ap- is charged to a voltage slightly higher than the regulation
plications. Experimentation with capacitor sizes between point. The step-down converter then goes into sleep mode,
2pF and 22pF may yield improved transient response. during which the output capacitor provides the load cur-
rent. In sleep mode, most of the regulator’s circuitry is
Step-Down Switching Regulator Operating Modes powered down, helping conserve battery power. When the
output voltage drops below a pre-determined value, the
The LTC3555 family’s general purpose switching regulators switching regulator circuitry is powered on and another
include four possible operating modes to meet the noise/ burst cycle begins. The duration for which the regulator
power needs of a variety of applications. operates in sleep mode depends on the load current. The
In pulse skip mode, an internal latch is set at the start of sleep time decreases as the load current increases. The
every cycle which turns on the main P-channel MOSFET maximum output current in forced Burst Mode operation is
switch. During each cycle, a current comparator compares about 100mA for switching regulators 1 and 2, and about
the peak inductor current to the output of an error amplifier. 250mA for switching regulator 3. The step-down switching
The output of the current comparator resets the internal regulators will not enter sleep mode if the maximum output
current is exceeded in forced Burst Mode operation and
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LTC3555/LTC3555-X
OPERATION
the output will drop out of regulation. Forced Burst Mode the switching regulator input supply leaving only a few
operation provides a significant improvement in efficiency nanoamperes of leakage current. The step-down switch-
at light loads at the expense of higher output ripple when ing regulator outputs are individually pulled to ground
compared to pulse skip mode. For many noise-sensitive through a 10k resistor on the switch pins (SW1-SW3)
systems, forced Burst Mode operation might be undesirable when in shutdown.
at certain times (i.e., during a transmit or receive cycle
of a wireless device), but highly desirable at others (i.e., General Purpose Switching Regulator Dropout
when the device is in low power standby mode). The I2C Operation
port can be used to enable or disable forced Burst Mode It is possible for a switching regulator’s input voltage,
operation at any time, offering both low noise and low VINx, to approach its programmed output voltage (e.g., a
power operation when they are needed. battery voltage of 3.4V with a programmed output voltage
In Burst Mode operation, the switching regulator automati- of 3.3V). When this happens, the PMOS switch duty cycle
cally switches between fixed frequency PWM operation and increases until it is turned on continuously at 100%. In this
hysteretic control as a function of the load current. At light dropout condition, the respective output voltage equals the
loads, the regulators operate in hysteretic mode in much regulator’s input voltage minus the voltage drops across
the same way as described for the forced Burst Mode the internal P-channel MOSFET and the inductor.
operation. Burst Mode operation provides slightly less
output ripple at the expense of slightly lower efficiency than Step-Down Switching Regulator Soft-Start Operation
forced Burst Mode operation. At heavy loads the switch- Soft-start is accomplished by gradually increasing the
ing regulator operates in the same manner as pulse skip peak inductor current for each switching regulator over
operation at high loads. For applications that can tolerate a 500μs period. This allows each output to rise slowly,
some output ripple at low output currents, Burst Mode helping minimize the battery surge current. A soft-start
operation provides better efficiency than pulse skip at light cycle occurs whenever a given switching regulator is
loads while still providing the full specified output current enabled, or after a fault condition has occurred (thermal
of the switching regulator. shutdown or UVLO). A soft-start cycle is not triggered by
Finally, the switching regulators have an LDO mode that changing operating modes. This allows seamless output
gives a DC option for regulating their output voltages. In operation when transitioning between forced Burst Mode,
LDO mode, the switching regulators are converted to linear Burst Mode, pulse skip mode or LDO operation.
regulators and deliver continuous power from their SWx
pins through their respective inductors. This mode gives Step-Down Switching Regulator Switching Slew Rate
the lowest possible output noise as well as low quiescent Control
current at light loads. The step-down switching regulators contain new patent
The step-down switching regulators allow mode transition pending circuitry to limit the slew rate of the switch nodes
on the fly, providing seamless transition between modes (SWx). This new circuitry is designed to transition the
even under load. This allows the user to switch back and switch nodes over a period of a couple of nanoseconds,
forth between modes to reduce output ripple or increase significantly reducing radiated EMI and conducted supply
low current efficiency as needed. noise.

Step-Down Switching Regulator in Shutdown Low Supply Operation

The step-down switching regulators are in shutdown when The LTC3555 family incorporates an undervoltage lockout
not enabled for operation. In shutdown, all circuitry in circuit on VOUT which shuts down the general purpose
the step-down switching regulator is disconnected from switching regulators when VOUT drops below VOUTUVLO.
This UVLO prevents unstable operation.
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APPLICATIONS INFORMATION
CLPROG Resistor and Capacitor The LTC3555 family includes a current-reversal com-
parator which monitors inductor current and disables the
As described in the High Efficiency Switching PowerPath
synchronous rectifier as current approaches zero. This
Controller section, the resistor on the CLPROG pin deter-
comparator will minimize the effect of current reversal
mines the average input current limit when the switching
on the average input current measurement. For some low
regulator is set to either the 1x mode (USB 100mA), the
inductance values, however, the inductor current may still
5x mode (USB 500mA) or the 10x mode. The input cur-
reverse slightly. This value depends on the speed of the
rent will be comprised of two components, the current
comparator in relation to the slope of the current wave-
that is used to drive VOUT and the quiescent current of the
form, given by VL/L. VL is the voltage across the inductor
switching regulator. To ensure that the USB specification
(approximately –VOUT) and L is the inductance value.
is strictly met, both components of input current should
be considered. The Electrical Characteristics table gives An inductance value of 3.3μH is a good starting value. The
values for quiescent currents in either setting as well as ripple will be small enough for the regulator to remain in
current limit programming accuracy. To get as close to continuous conduction at 100mA average VBUS current.
the 500mA or 100mA specifications as possible, a 1% At lighter loads the current-reversal comparator will dis-
resistor should be used. Recall that able the synchronous rectifier for currents slightly above
0mA. As the inductance is reduced from this value, the
IVBUS = IVBUSQ + VCLPROG/RCLPPROG • (hCLPROG +1)
LTC3555 family will enter discontinuous conduction mode
An averaging capacitor or an R-C combination is required at progressively higher loads. Ripple at VOUT will increase
in parallel with the CLPROG resistor so that the switching directly proportionally to the magnitude of inductor ripple.
regulator can determine the average input current. This Transient response, however, will improve. The current
network also provides the dominant pole for the feedback mode controller controls inductor current to exactly the
loop when current limit is reached. To ensure stability, amount required by the load to keep VOUT in regulation. A
the capacitor on CLPROG should be 0.47µF or larger. transient load step requires the inductor current to change
Alternatively, faster transient response may be achieved to a new level. Since inductor current cannot change instan-
with 0.1µF in series with 8.2Ω. taneously, the capacitance on VOUT delivers or absorbs the
Choosing the PowerPath Inductor difference in current until the inductor current can change
to meet the new load demand. A smaller inductor changes
Because the average input current circuit does not measure its current more quickly for a given voltage drive than a
reverse current (i.e., current from SW to VBUS), current larger inductor, resulting in faster transient response. A
reversal in the inductor at light loads will contribute an larger inductor will reduce output ripple and current ripple,
error to the average VBUS current measurement. The error but at the expense of reduced transient performance and
is conservative in that if the current reverses, the voltage a physically larger inductor package size. For this reason
at CLPROG will be higher than what would represent the a larger CVOUT will be required for larger inductor sizes.
actual average input current drawn. The current available
for battery charging plus system load is thus reduced but The input regulator has an instantaneous peak current
the USB specification will not be violated. clamp to prevent the inductor from saturating during tran-
sient load or start-up conditions. The clamp is designed
This reduction in available VBUS current will happen when so that it does not interfere with normal operation at high
the peak-peak inductor ripple is greater than twice the loads and reasonable inductor ripple. It is intended to pre-
average current limit setting. For example, if the average vent inductor current runaway in case of a shorted output.
current limit is set to 100mA, the peak-peak ripple should
not exceed 200mA. If the input current is less than 100mA, The DC winding resistance and AC core losses of the in-
the measurement accuracy may be reduced. However, this ductor will affect efficiency, and therefore available output
will not affect the average current loop since it will not be power. These effects are difficult to characterize and vary
in regulation.
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by application. Some inductors that may be suitable for their rated voltage and temperature ranges. Y5V ceramic
this application are listed in Table 6. capacitors have the highest packing density, but must be
Table 6. Recommended Inductors
used with caution because of their extreme non-linear
MAX MAX characteristic of capacitance verse voltage. The actual
INDUCTOR L IDC DCR SIZE in mm in-circuit capacitance of a ceramic capacitor should be
TYPE (µH) (A) (Ω) (L × W × H) MANUFACTURER measured with a small AC signal as is expected in-circuit.
LPS4018 3.3 2.2 0.08 3.9 × 3.9 × 1.7 Coilcraft
www.coilcraft.com
Many vendors specify the capacitance versus voltage with
D53LC 3.3 2.26 0.034 5×5×3 Toko a 1VRMS AC test signal and as a result, overstate the ca-
DB318C 3.3 1.55 0.070 3.8 × 3.8 × 1.8 www.toko.com pacitance that the capacitor will present in the application.
WE-TPC 3.3 1.95 0.065 4.8 × 4.8 × 1.8 Wurth Elektronik Using similar operating conditions as the application, the
Type M1 www.we-online.com
user must measure or request from the vendor the actual
CDRH6D12 3.3 2.2 0.0625 6.7 × 6.7 × 1.5 Sumida
CDRH6D38 3.3 3.5 0.020 7×7×4 www.sumida.com capacitance to determine if the selected capacitor meets
the minimum capacitance that the application requires.
VBUS and VOUT Bypass Capacitors
General Purpose Switching Regulator Inductor
The style and value of capacitors used with the LTC3555 Selection
family determine several important parameters such as
regulator control-loop stability and input voltage ripple. Many different sizes and shapes of inductors are avail-
Because the LTC3555 family uses a step-down switching able from numerous manufacturers. Choosing the right
power supply from VBUS to VOUT, its input current wave- inductor from such a large selection of devices can be
form contains high frequency components. It is strongly overwhelming, but following a few basic guidelines will
recommended that a low equivalent series resistance (ESR) make the selection process much simpler.
multilayer ceramic capacitor be used to bypass VBUS. The general purpose step-down converters are designed
Tantalum and aluminum capacitors are not recommended to work with inductors in the range of 2.2µH to 10µH. For
because of their high ESR. The value of the capacitor on most applications a 4.7µH inductor is suggested for the
VBUS directly controls the amount of input ripple for a lower power switching regulators 1 and 2 and 2.2µH is
given load current. Increasing the size of this capacitor recommended for the more powerful switching regula-
will reduce the input ripple. tor 3. Larger value inductors reduce ripple current which
To prevent large VOUT voltage steps during transient load improves output ripple voltage. Lower value inductors result
conditions, it is also recommended that a ceramic capaci- in higher ripple current and improved transient response
tor be used to bypass VOUT. The output capacitor is used time. To maximize efficiency, choose an inductor with a
in the compensation of the switching regulator. At least low DC resistance. For a 1.2V output, efficiency is reduced
4μF of actual capacitance with low ESR are required on about 2% for 100mΩ series resistance at 400mA load cur-
VOUT. Additional capacitance will improve load transient rent, and about 2% for 300mΩ series resistance at 100mA
performance and stability. load current. Choose an inductor with a DC current rating
at least 1.5 times larger than the maximum load current to
Multilayer ceramic chip capacitors typically have excep- ensure that the inductor does not saturate during normal
tional ESR performance. MLCCs combined with a tight operation. If output short circuit is a possible condition,
board layout and an unbroken ground plane will yield very the inductor should be rated to handle the maximum peak
good performance and low EMI emissions. current specified for the step-down converters.
There are several types of ceramic capacitors available, Different core materials and shapes will change the size/
each having considerably different characteristics. For current and price/current relationship of an inductor. Toroid
example, X7R ceramic capacitors have the best voltage and or shielded pot cores in ferrite or Permalloy materials are
temperature stability. X5R ceramic capacitors have appar- small and don’t radiate much energy, but generally cost
ently higher packing density but poorer performance over more than powdered iron core inductors with similar
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 LTC3555/LTC3555-X
APPLICATIONS INFORMATION
electrical characteristics. Inductors that are very thin or General Purpose Switching Regulator Input/Output
have a very small volume typically have much higher core Capacitor Selection
and DCR losses, and will not give the best efficiency. The
Low ESR (equivalent series resistance) MLCC capacitors
choice of which style inductor to use often depends more
should be used at both switching regulator outputs as well
on the price vs size, performance and any radiated EMI
as at each switching regulator input supply (VINX). Only X5R
requirements than on what the LTC3555 family requires
or X7R ceramic capacitors should be used because they
to operate.
retain their capacitance over wider voltage and temperature
The inductor value also has an effect on forced Burst ranges than other ceramic types. A 10μF output capaci-
Mode and Burst Mode operations. Lower inductor values tor is sufficient for most applications. For good transient
will cause the Burst and forced Burst Mode switching response and stability the output capacitor should retain
frequencies to increase. at least 4μF of capacitance over operating temperature
Table 7 shows several inductors that work well with the and bias voltage. Each switching regulator input supply
LTC3555 family’s general purpose regulators. These in- should be bypassed with a 1μF capacitor. Consult with
ductors offer a good compromise in current rating, DCR capacitor manufacturers for detailed information on their
and physical size. Consult each manufacturer for detailed selection and specifications of ceramic capacitors. Many
information on their entire selection of inductors. manufacturers now offer very thin (<1mm tall) ceramic
capacitors ideal for use in height-restricted designs. Table
Table 7. Recommended Inductors 8 shows a list of several ceramic capacitor manufacturers.
INDUCTOR L MAX MAX SIZE in mm
TYPE (µH) IDC (A) DCR (Ω) (L × W × H) MANUFACTURER Table 8. Recommended Ceramic Capacitor Manufacturers
DE2818C 4.7 1.25 0.072 3.0 × 2.8 × 1.8 Toko AVX www.avxcorp.com
3.3 1.45 0.053 3.0 × 2.8 × 1.8 www.toko.com
D312C 4.7 0.79 0.24 3.6 × 3.6 × 1.2 Murata www.murata.com
3.3 0.90 0.20 3.6 × 3.6 × 1.2 Taiyo Yuden www.t-yuden.com
2.2 1.14 0.14 3.6 × 3.6 × 1.2
DE2812C 4.7 1.2 0.13* 3.0 × 2.8 × 1.2 Vishay Siliconix www.vishay.com
3.3 1.4 0.10* 3.0 × 2.8 × 1.2 TDK www.tdk.com
2.0 1.8 0.067* 3.0 × 2.8 × 1.2
CDRH3D16 4.7 0.9 0.11 4 × 4 × 1.8 Sumida Over-Programming the Battery Charger
3.3 1.1 0.085 4 × 4 × 1.8 www.sumida.
2.2 1.2 0.072 4 × 4 × 1.8 com The USB high power specification allows for up to 2.5W to
CDRH2D11 4.7 0.5 0.17 3.2 × 3.2 × 1.2
3.3 0.6 0.123 3.2 × 3.2 × 1.2 be drawn from the USB port (5V × 500mA). The PowerPath
2.2 0.78 0.098 3.2 × 3.2 × 1.2 switching regulator transforms the voltage at VBUS to just
CLS4D09 4.7 0.75 0.19 4.9 × 4.9 × 1
above the voltage at BAT with high efficiency, while limiting
SD3118 4.7 1.3 0.162 3.1 × 3.1 × 1.8 Cooper
3.3 1.59 0.113 3.1 × 3.1 × 1.8 www.cooperet. power to less than the amount programmed at CLPROG.
2.2 2.0 0.074 3.1 × 3.1 × 1.8 com In some cases the battery charger may be programmed
SD3112 4.7 0.8 0.246 3.1 × 3.1 × 1.2 (with the PROG pin) to deliver the maximum safe charging
3.3 0.97 0.165 3.1 × 3.1 × 1.2
2.2 1.12 0.14 3.1 × 3.1 × 1.2 current without regard to the USB specifications. If there
SD12 4.7 1.29 0.117* 5.2 × 5.2 × 1.2 is insufficient current available to charge the battery at the
3.3 1.42 0.104* 5.2 × 5.2 × 1.2
2.2 1.80 0.075* 5.2 × 5.2 × 1.2
programmed rate, the PowerPath regulator will reduce
SD10 4.7 1.08 0.153* 5.2 × 5.2 × 1.0 charge current until the system load on VOUT is satisfied
3.3 1.31 0.108* 5.2 × 5.2 × 1.0 and the VBUS current limit is satisfied. Programming the
2.2 1.65 0.091* 5.2 × 5.2 × 1.0
LPS3015 4.7 1.1 0.2 3.0 × 3.0 × 1.5 Coil Craft
battery charger for more current than is available will not
3.3 1.3 0.13 3.0 × 3.0 × 1.5 www.coilcraft. cause the average input current limit to be violated. It will
2.2 1.5 0.11 3.0 × 3.0 × 1.5 com merely allow the battery charger to make use of all available
*Typical DCR power to charge the battery as quickly as possible, and
with minimal power dissipation within the battery charger.
3555fe

For more information www.linear.com/LTC3555 27

LTC3555/LTC3555-X
APPLICATIONS INFORMATION
Alternate NTC Thermistors and Biasing VBUS VBUS LTC3555/LTC3555-X
NTC BLOCK

The LTC3555 family provides temperature qualified charg- RNOM

0.765 • VBUS
–
ing if a grounded thermistor and a bias resistor are con- 10k
TOO_COLD
NTC
nected to NTC. By using a bias resistor whose value is equal 3 +
to the room temperature resistance of the thermistor (R25)
the upper and lower temperatures are pre-programmed
RNTC
T
10k –
to approximately 40°C and 0°C, respectively (assuming 0.349 • VBUS
TOO_HOT

a Vishay “Curve 1” thermistor). +

The upper and lower temperature thresholds can be ad- +

justed by either a modification of the bias resistor value NTC_ENABLE

or by adding a second adjustment resistor to the circuit. 0.1V –

If only the bias resistor is adjusted, then either the upper 3555 F05a

or the lower threshold can be modified but not both. The (5a)
other trip point will be determined by the characteristics
of the thermistor. Using the bias resistor in addition to an VBUS VBUS LTC3555/LTC3555-X

adjustment resistor, both the upper and the lower tempera- NTC BLOCK

ture trip points can be independently programmed with RNOM

10.5k
0.765 • VBUS
–
the constraint that the difference between the upper and NTC TOO_COLD
+
lower temperature thresholds cannot decrease. Examples 3

of each technique are given below. R1

1.27k –
NTC thermistors have temperature characteristics which TOO_HOT
0.349 • VBUS
are indicated on resistance-temperature conversion tables. R
T NTC
+
10k
The Vishay-Dale thermistor NTHS0603N011-N1002F, used
in the following examples, has a nominal value of 10k +
and follows the Vishay “Curve 1” resistance-temperature NTC_ENABLE
0.1V –
characteristic.
In the explanation below, the following notation is used.
3555 F05b

(5b)
R25 = Value of the Thermistor at 25°C Figure 5. NTC Circuits
RNTC|COLD = Value of thermistor at the cold trip point
RNTC|HOT
RNTC|HOT = Value of the thermistor at the hot trip point • VBUS = 0.349 • VBUS
RNOM + RNTC|HOT
αCOLD = Ratio of RNTC|COLD to R25
and the cold trip point is set when:
αHOT = Ratio of RNTC|HOT to R25
RNTC|COLD
RNOM = Primary thermistor bias resistor (see Figure 5a) • VBUS = 0.765 • VBUS
RNOM + RNTC|COLD
R1 = Optional temperature range adjustment resistor
(see Figure 5b) Solving these equations for RNTC|COLD and RNTC|HOT
results in the following:
The trip points for the LTC3555 family’s temperature
qualification are internally programmed at 0.349 • VBUS for RNTC|HOT = 0.536 • RNOM
the hot threshold and 0.765 • VBUS for the cold threshold. and
Therefore, the hot trip point is set when: RNTC|COLD = 3.25 • RNOM
3555fe

28 For more information www.linear.com/LTC3555

 LTC3555/LTC3555-X
APPLICATIONS INFORMATION
By setting RNOM equal to R25, the above equations result R1 = 0.536 • 10.5k – 0.4368 • 10k = 1.26k
in αHOT = 0.536 and αCOLD = 3.25. Referencing these ratios
the nearest 1% value is 1.27k. The final circuit is shown
to the Vishay Resistance-Temperature Curve 1 chart gives
in Figure 5b and results in an upper trip point of 45°C and
a hot trip point of about 40°C and a cold trip point of about
a lower trip point of 0°C.
0°C. The difference between the hot and cold trip points
is approximately 40°C. USB Inrush Limiting
By using a bias resistor, RNOM, different in value from R25, When a USB cable is plugged into a portable product,
the hot and cold trip points can be moved in either direction. the inductance of the cable and the high-Q ceramic input
The temperature span will change somewhat due to the non- capacitor form an L-C resonant circuit. If the cable does
linear behavior of the thermistor. The following equations can not have adequate mutual coupling or if there is not much
be used to easily calculate a new value for the bias resistor: impedance in the cable, it is possible for the voltage at
αHOT the input of the product to reach as high as twice the
RNOM = • R25 USB voltage (~10V) before it settles out. In fact, due to
0.536
α the high voltage coefficient of many ceramic capacitors, a
RNOM = COLD • R25 nonlinearity, the voltage may even exceed twice the USB
3.25
voltage. To prevent excessive voltage from damaging the
LTC3555 family during a hot insertion, it is best to have
where αHOT and αCOLD are the resistance ratios at the a low voltage coefficient capacitor at the VBUS pin to the
desired hot and cold trip points. Note that these equations LTC3555 family. This is achievable by selecting an MLCC
are linked. Therefore, only one of the two trip points can capacitor that has a higher voltage rating than that required
be chosen, the other is determined by the default ratios for the application. For example, a 16V, X5R, 10µF capaci-
designed in the IC. Consider an example where a 60°C tor in a 1206 case would be a better choice than a 6.3V,
hot trip point is desired. X5R, 10µF capacitor in a smaller 0805 case.
From the Vishay Curve 1 R-T characteristics, αHOT is 0.2488 Alternatively, the following soft connect circuit (Figure 6)
at 60°C. Using the above equation, RNOM should be set to can be employed. In this circuit, capacitor C1 holds MP1
4.64k. With this value of RNOM, the cold trip point is about off when the cable is first connected. Eventually C1 begins
16°C. Notice that the span is now 44°C rather than the to charge up to the USB input voltage applying increasing
previous 40°C. This is due to the decrease in “temperature gate support to MP1. The long time constant of R1 and
gain” of the thermistor as absolute temperature increases. C1 prevent the current from building up in the cable too
The upper and lower temperature trip points can be inde- fast thus dampening out any resonant overshoot.
pendently programmed by using an additional bias resistor
as shown in Figure 5b. The following formulas can be used Printed Circuit Board Layout Considerations
to compute the values of RNOM and R1: In order to be able to deliver maximum current under all
α – αHOT conditions, it is critical that the Exposed Pad on the back-
RNOM = COLD • R25 side of the LTC3555 family package be soldered to the PC
2.714
R1= 0.536 • RNOM – αHOT • R25 board ground. Failure to make thermal contact between
the Exposed Pad on the backside of the package and the
For example, to set the trip points to 0°C and 45°C with copper board will result in higher thermal resistances.
a Vishay Curve 1 thermistor choose: Furthermore, due to its high frequency switching circuitry,
3.266 – 0.4368 it is imperative that the input capacitors, inductors and
RNOM = • 10k = 10.42k output capacitors be as close to the LTC3555 family as
2.714
possible and that there be an unbroken ground plane under
the nearest 1% value is 10.5k: the IC and all of its external high frequency components.
3555fe

For more information www.linear.com/LTC3555 29

LTC3555/LTC3555-X
APPLICATIONS INFORMATION
MP1
Si2333
VBUS
C1
5V USB 100nF
LTC3555/
INPUT C2
USB CABLE LTC3555-X
R1 10µF
40k
GND
3555 F06
3555 F07

Figure 6. USB Soft Connect Circuit

High frequency currents, such as the VBUS, VIN1, VIN2 Figure 7. Higher Frequency Ground Currents Follow Their
and VIN3 currents on the LTC3555 family, tend to find Incident Path. Slices in the Ground Plane Cause High Voltage
their way along the ground plane in a myriad of paths and Increased Emissions
ranging from directly back to a mirror path beneath the Battery Charger Stability Considerations
incident path on the top of the board. If there are slits or
cuts in the ground plane due to other traces on that layer, The LTC3555 family’s battery charger contains both a
the current will be forced to go around the slits. If high constant-voltage and a constant-current control loop. The
frequency currents are not allowed to flow back through constant-voltage loop is stable without any compensation
their natural least-area path, excessive voltage will build when a battery is connected with low impedance leads.
up and radiated emissions will occur. There should be a Excessive lead length, however, may add enough series
group of vias under the grounded backside of the pack- inductance to require a bypass capacitor of at least 1µF
age leading directly down to an internal ground plane. To from BAT to GND. Furthermore, when the battery is dis-
minimize parasitic inductance, the ground plane should connected, a 100µF MLCC capacitor in series with a 0.3Ω
be on the second layer of the PC board. resistor from BAT to GND is required to prevent oscillation.

The GATE pin for the external ideal diode controller has High value, low ESR multilayer ceramic chip capacitors
extremely limited drive current. Care must be taken to reduce the constant-voltage loop phase margin, possibly
minimize leakage to adjacent PC board traces. 100nA of resulting in instability. Ceramic capacitors up to 22µF
leakage from this pin will introduce an offset to the 15mV may be used in parallel with a battery, but larger ceramics
ideal diode of approximately 10mV. To minimize leakage, should be decoupled with 0.2Ω to 1Ω of series resistance.
the trace can be guarded on the PC board by surrounding In constant-current mode, the PROG pin is in the feed-
it with VOUT connected metal, which should generally be back loop rather than the battery voltage. Because of the
less that one volt higher than GATE. additional pole created by any PROG pin capacitance,
When laying out the printed circuit board, the following capacitance on this pin must be kept to a minimum. With
checklist should be used to ensure proper operation of no additional capacitance on the PROG pin, the battery
the LTC3555 family. charger is stable with program resistor values as high
as 25k. However, additional capacitance on this node
1. Are the capacitors at VBUS, VIN1, VIN2 and VIN3 as close reduces the maximum allowed program resistor. The pole
as possible to the LTC3555? These capacitors provide frequency at the PROG pin should be kept above 100kHz.
the AC current to the internal power MOSFETs and their Therefore, if the PROG pin has a parasitic capacitance,
drivers. Minimizing inductance from these capacitors CPROG, the following equation should be used to calculate
to the LTC3555 is a top priority. the maximum resistance value for RPROG:
2. Are COUT and L1 closely connected? The (–) plate of 1
COUT returns current to the GND plane. RPROG ≤
2π • 100kHz • CPROG
3. Keep sensitive components away from the SW pins.

3555fe

30 For more information www.linear.com/LTC3555

 LTC3555/LTC3555-X
TYPICAL APPLICATION
Watchdog Microcontroller Operation

L1
3.3µH
USB/WALL 25 26 TO OTHER
VBUS SW
4.5V TO 5.5V C1 24 LOADS
10k VOUT
10µF
3 22 510Ω
NTC GATE MP1 C2
20 23 22µF
PROG BAT
T 2
2k CLPROG 29 Li-Ion RED
8.2Ω GND
0.1µF 3k
21
CHRG
L2
4.7µH 3.3V
17 400mA
SW1 MEMORY
1.02M
19 10pF
LDO3V3 FB1
8
1µF DVCC 1µF
324k 10µF
LTC3555/
LTC3555-X
18
VIN1
PUSH BUTTON L3
MICROCONTROLLER 1.61V TO 3.03V
4.7µH
6 400mA
SW2 I/O
1.02M
4 10pF
FB2
2 9,10
I 2C 365k 10µF 1µF
MICROPROCESSOR

C1: MURATA GRM21BR61A106KE19

5
C2: TDK C2012X5R0J226M VIN2
L1: COILCRAFT LPS4018-332LM L4
2µH 0.8V TO 1.51V
L2, L3: TOKO 1098AS-4R7M
12 1A
L4: TOKO 1098AS-2R0M SW3 CORE
MP1: SILICONIX Si2333
715k POR
16 14 10pF
EN1 FB3
7
EN2 806k 22µF 2.2µF 10k
13
EN3
27 11
ILIM0 VIN3
28 15
ILIM1 RST3 3555 TA02

3555fe

For more information www.linear.com/LTC3555 31

LTC3555/LTC3555-X
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3555#packaging for the most recent package drawings.

UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)

0.70 ±0.05

4.50 ±0.05
3.10 ±0.05

2.50 REF
2.65 ±0.05
3.65 ±0.05

PACKAGE OUTLINE

0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH
2.50 REF R = 0.20 OR 0.35
R = 0.05 R = 0.115 × 45° CHAMFER
4.00 ±0.10 0.75 ±0.05
TYP TYP
(2 SIDES) 27 28

0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6) 1

5.00 ±0.10
3.50 REF
(2 SIDES)

3.65 ±0.10
2.65 ±0.10

(UFD28) QFN 0816 REV C

0.200 REF 0.25 ±0.05

0.00 – 0.05 0.50 BSC
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

3555fe

32 For more information www.linear.com/LTC3555

 LTC3555/LTC3555-X
REVISION HISTORY (Revision history begins at Rev E)

REV DATE DESCRIPTION PAGE NUMBER

E 11/16 Changed conditions in Absolute Maximum Ratings section for ILIMX and ENx 2

3555fe

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection information
of its circuits www.linear.com/LTC3555
as described herein will not infringe on existing patent rights. 33
LTC3555/LTC3555-X
TYPICAL APPLICATION
Push Button Start with Automatic Sequencing, Reverse Input Voltage Protection and 10 Second Push and Hold Hard Shutdown

USB MP1 25 17
VBUS SW1 MEMORY
CONNECTOR

19
FB1
8
DVCC
0.1µF
15
RST3
1 7
LDO3V3 EN2 CORE
1µF 12
4.7k 1k SW3
LTC3555/
LTC3555-X
14
FB3
1M 13
EN3
MN1
SDA
10µF 9,10 2
I2C SCL
16 I/O
10µF EN1
6
SW2
10k 27
ILIM0
28 4
ILIM1 FB2
SEND I2C CODE: “0x12FF04”
ONCE POWER IS DETECTED
MN1: 2N7002
MP1: SILICONIX Si2333DS
3555 TA03

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3555fe

34 Linear Technology Corporation

LT 1116 REV E • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LTC3555
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3555  LINEAR TECHNOLOGY CORPORATION 2007