bq24020,, bq24022,, bq24023

bq24024, bq24025, bq24026

bq24027
www.ti.com
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

SINGLE-CHIP, LI-ION AND LI-POL CHARGER IC WITH AUTONOMOUS USB-PORT AND

AC-ADAPTER SUPPLY MANAGEMENT (bqTINY™-II)
1FEATURES
• Small 3 mm × 3 mm MLP Package
2
DESCRIPTION
• Charges and powers Systems from Either AC The bqTINY-II series are highly-integrated, flexible
Adapter or USB With Autonomous Li-Ion linear charge and system power management
power-Source Selection devices for space-limited charger applications. In a
single monolithic device, the bqTINY-II offers
• Integrated USB Control With Selectable 100
integrated USB-port and ac-adapter supply
mA and 500 mA Charge Rates management with autonomous power-source
• Ideal for Low-Dropout Charger Designs for selection, power-FET and current-sensor interfaces,
Single-Cell Li-Ion or Li-pol Packs in Space high-accuracy current and voltage regulation, charge
Limited portable applications status, and charge termination.
• Integrated power FET and Current Sensor for The bqTINY-II automatically selects the USB-port or
Up to 1-A Charge applications From AC the ac-adapter as the power source for the system. In
Adapter the USB configuration, the host can select from two
• Precharge Conditioning With Safety Timer preset charge rates of 100 mA or 500 mA. In the
ac-adapter configuration, an external resistor sets the
• power Good (AC Adapter Present) Status system or charge current.
Output
The bqTINY-II charges the battery in three phases:
• Optional Battery Temperature Monitoring
conditioning, constant current, and constant voltage.
Before and During Charge Charge is terminated based on minimum current. An
• Automatic Sleep Mode for Low-power internal charge timer provides a backup safety for
Consumption charge termination. The bqTINY-II automatically
restarts the charge if the battery voltage falls below
APPLICATIONS an internal threshold. The bqTINY-II automatically
• PDAs, MP3 Players enters sleep mode when both supplies are removed.
• Digital Cameras
• Internet appliances
• Smartphones

VDC PACK+ BATTERY PACK

bq24020DRC
AC
ADAPTER +
1 AC OUT 10 SYSTEM
GND PACK−

VBUS 2 USB TS 9 SYSTEM

INTERFACE
3 STAT1 CE 8

USB
4 STAT2 ISET2 7
PORT GND
RSET
5 VSS ISET1 6
D+
D− UDG−02184

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 bqTINY is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas Copyright © 2002–2007, Texas Instruments Incorporated
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
bq24020,, bq24022,, bq24023
bq24024, bq24025, bq24026
bq24027 www.ti.com
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION CONTINUED
Different versions of the bqTINY-II offer many additional features. These include a temperature-sensor input for
detecting hot or cold battery packs, a power-good output (PG) indicating the presence of input power, a TTL-level
charge-enable input (CE) used to disable or enable the charge process, and a TTL-level timer and taper-detect
enable input (TTE) used to disable or enable the fast-charge timer and charge termination.

ORDERING INFORMATION
CHARGE
OPTIONAL FAST-CHARGE TAPER USB TAPER PART
TJ REGULATION MARKINGS
FUNCTIONS (1) TIMER (Hours) TIMER THRESHOLD NUMBER(2)
VOLTAGE (V)(1)
4.2 CE and TS 5 Yes 10% of ISET1 Level bq24020DRCR AZS
4.2 PG and CE 5 Yes 10% of ISET1 Level bq24022DRCR AZU
4.2 CE and TTE 5 Yes 10% of ISET1 Level bq24023DRCR AZV
– 40°C 4.2 TTE and TS 5 Yes 10% of ISET1 Level bq24024DRCR AZW
to
4.2 CE and TS 7 Yes 10% of ISET1 Level bq24025DRCR AZX
125°C
10% of selected
4.2 TE and TS 7 No bq24026DRCR ANR
USB charge rate
10% of selected
4.2 PG and CE 7 No bq24027DRCR ANS
USB charge rate

(1) The DRC package is available taped and reeled only in quantities of 3,000 devices per reel.

Dissipation Ratings
PACKAGE θJA TA < 40°C POWER RATING DERATING FACTOR ABOVE TA = 25°C
DRC (1) 46.87 °C/W 1.5 W 0.021 W/°C

(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is
connected to the ground plane by a 2×3 via matrix.

ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
bq24020, bq24022, UNIT
bq24023, bq24024
bq24025, bq24026
bq24027
Input voltage (2) AC, CE, ISET1, ISET2, OUT, PG, STAT1, STAT2, TE, TS, TTE, USB –0.3 to 7.0 V
Output sink/source current STAT1, STAT2, PG 15 mA
Output current TS 200 µA
Output current OUT 1.5 A
Operating free-air temperature range, TA
–40 to 125
Junction temperature range, TJ °C
Storage temperature, Tstg –65 to 150

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to VSS.

2 Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated

Product Folder Link(s): bq24020 bq24022 bq24023 bq24024 bq24025 bq24026 bq24027
 bq24020,, bq24022,, bq24023
bq24024, bq24025, bq24026
www.ti.com
bq24027
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage (from AC input), VCC 4.5 6.5 V
Supply voltage (from USB input), VCC 4.35 6.5 V
Operating junction temperature range, TJ –40 125 °C

ELECTRICAL CHARACTERISTICS
over 0°C ≤ TJ ≤ 125°C and recommended supply voltage, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CURRENT
ICC(VCC) VCC current VCC > VCC(min) 1.2 2.0 mA
ICC(SLP) Sleep current Sum of currents into OUT pin, VCC < V(SLP) 2 5
ICC(STBY) Standby current CE = High 0°C ≤TJ ≤ 85°C 1 150
IIB(OUT) Input current on OUT pin Charge DONE VCC > VCC(MIN) 5
µA
IIB(CE) Input current on CE pin 1
IIB(TTE) Input bias current on TTE pin 1
IIB(TE) Input bias current on TE pin 1
VOLTAGE REGULATION VO(REG) + V(DO-MAX) ≤ VCC , I(TERM) < IO(OUT) ≤ 1 A
VO(REG) Output voltage, 4.20 V
TA = 25°C –0.35% 0.35%
Voltage regulation accuracy
–1% 1%
VO(OUT) = VO(REG) IO(OUT) = 1A 350 500
V(DO) AC dropout voltage (V(AC)–V(OUT))
VO(REG) + V(DO-MAX)) ≤ VCC
VO(OUT) = VO(REG) ISET2 = High 350 500
mV
USB dropout voltage VO(REG) + V(DO-MAX)) ≤ VCC
V(DO)
(V(USB) – V(OUT)) VO(OUT) = VO(REG) ISET2 = Low 60 100
VO(REG) + V(DO-MAX)) ≤ VCC
CURRENT REGULATION
VI(OUT) > V(LOWV) VCC ≥ 4.5 V 50 1000
IO(OUT) AC output current range (1)
VI(AC) – VI(OUT) > V(DO-MAX)
VCC(MIN) ≥ 4.5 V VI(OUT) > V(LOWV) 80 100
mA
VUSB – VI(OUT) > V(DO-MAX) ISET2 = Low
IO(OUT) USB output current range
VCC(MIN) ≥ 4.5 V VI(OUT) > V(LOWV) 400 500
VUSB – VI(OUT) > V(DO-MAX) ISET2 = High
Voltage on ISET1 pin, VCC ≥ 4.5 V, VIN ≥ 4.5 V, 2.463 2.500 2.538
V(SET) Output current set voltage V
VI(OUT) > V(LOWV), VIN – VI(OUT) > V(DO-MAX)
50 mA ≤ IO(OUT) ≤ 1 A 307 322 337
K(SET) Output current set factor 10 mA ≤ IO(OUT) < 50 mA 296 320 346
1 mA ≤ IO(OUT) < 10 mA 246 320 416

ǒK(SET) Ǔ
V(SET)
IO(OUT) +
RSET
(1)

Copyright © 2002–2007, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Link(s): bq24020 bq24022 bq24023 bq24024 bq24025 bq24026 bq24027
bq24020,, bq24022,, bq24023
bq24024, bq24025, bq24026
bq24027 www.ti.com
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

ELECTRICAL CHARACTERISTICS (continued)

over 0°C ≤ TJ ≤ 125°C and recommended supply voltage, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PRECHARGE AND SHORT-CIRCUIT CURRENT REGULATION
Precharge to fast-charge Voltage on OUT pin 2.8 3.0 3.2
V(LOWV) V
transition threshold
Deglitch time for fast-charge to VCC(MIN) ≥ 4.5 V, tFALL = 100 ns, 10 mV 250 375 500
ms
precharge transition overdrive, VI(OUT) decreasing below threshold
(2)
IO(PRECHG) Precharge range 0 V < VI(OUT) < V(LOWV), t < t(PRECHG) 5 100 mA
Voltage on ISET1 pin VO(REG) = 4.2 V 240 255 270
V(PRECHG) Precharge set voltage mV
0 V < VI(OUT) > V(LOWV), t < t(PRECHG)
CHARGE TAPER AND TERMINATION DETECTION
I(TAPER) Charge taper detection range (3) VI(OUT) > V(RCH), t < t(TAPER) 5 100
USB-100 charge taper VI(OUT) > V(RCH), ISET2 = Low 6.5 9 11
bq24026
detection level mA
USB-500 charge taper VI(OUT) > V(RCH), ISET2 = High 32 44 55
bq24026
detection level
Voltage on ISET1 pin, VO(REG) = 4.2 V, 235 250 265
V(TAPER) Charge taper detection set voltage
VI(OUT) > V(RCH), t < t(TAPER)
mV
Charge termination detection Voltage on ISET1 pin, VO(REG) = 4.2 V, 11 18 25
V(TERM)
set voltage (4) VI(OUT) > V(RCH)
VCC(MIN) ≥ 4.5 V, tFALL = 100 ns charging 250 375 500
t(TPRDET) Deglitch time for TAPER detection current increasing or decreasing above and
below, 10 mV overdrive ms
Deglitch time for VCC(MIN) ≥ 4.5 V, tFALL = 100 ns charging 250 375 500
t(TRMDET)
termination detection current decreasing below, 10 mV overdrive
TEMPERATURE SENSE COMPARATOR
V(HTF) High-voltage threshold PTC thermistor 2.475 2.500 2.525
V
V(LTF) Low-voltage threshold PTC thermistor 0.485 0.500 0.515
I(TS) Current source 96 102 108 µA
t(DEGL) Deglitch time for temperature fault 250 375 500 ms

ǒK(SET) V(PRECHG) Ǔ
IO(PRECHG) +
RSET
(2)
ǒK(SET) V(TAPER) Ǔ
IO(TAPER) +
(3) R SET
ǒK(SET) V(TERM) Ǔ
IO(TERM) +
(4) RSET

4 Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated

Product Folder Link(s): bq24020 bq24022 bq24023 bq24024 bq24025 bq24026 bq24027
 bq24020,, bq24022,, bq24023
bq24024, bq24025, bq24026
www.ti.com
bq24027
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

ELECTRICAL CHARACTERISTICS (continued)

over 0°C ≤ TJ ≤ 125°C and recommended supply voltage, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BATTERY RECHARGE THRESHOLD
VO(REG) VO(REG) VO(REG)
VRCH Recharge threshold V
– 0.115 –0.10 – 0.085
VCC(MIN) ≥ 4.5 V, tFALL = 100 ns decreasing
t(DEGL) Deglitch time for recharge detect below or increasing above threshold, 250 375 500 ms
10 mV overdrive
STAT1, STAT2, and PG OUTPUTS
VOL Low-level output saturation voltage IO = 5 mA 0.25 V
ISET2, CHARGE ENABLE (CE), TIMER AND TERMINATION ENABLE (TTE), AND TIMER ENABLE (TE) INPUTS
VIL Low-level input voltage IIL = 10 µA 0 0.4
V
VIH High-level input voltage IIL = 20 µA 1.4
CE, TE or TTE low-level –1
IIL
input current
CE, TE or TTE high-level 1
IIH
input current µA
IIL ISET2 low-level input current IISET2 = 0 –20
IIH ISET2 high-level input current IISET2 = VCC 40
IIH ISET2 high-Z input current 1 V
TIMERS
t(PRECHG) Precharge time 1,584 1,800 2,016
bq24020
bq24022
t(TAPER) Taper time bq24023 1,584 1,800 2,016
bq24024
bq24025
bq24020 s
bq24022
15,840 18,000 20,160
bq24023
t(CHG) Charge time bq24024
bq24025
bq24026 22,176 25,200 28,224
bq24027
I(FAULT) Timer fault recovery current 200 µA
SLEEP COMPARATOR
VCC ≤
Sleep-mode entry
V(SLP) 2.3 V ≤ VI(OUT) ≤ VO(REG) VI(OUT)
threshold voltage
+80 mV
V
VCC ≥
Sleep mode exit
V(SLPEXIT) 2.3 V ≤ VI(OUT) ≤ VO(REG) VI(OUT)
threshold voltage
+190mV
AC and USB decreasing below threshold,
Sleep mode deglitch time 250 375 500 ms
tFALL = 100 ns, 10 mV overdrive
THERMAL SHUTDOWN THRESHOLDS
T(SHTDWN) Thermal trip threshold 165
°C
Thermal hysteresis 15
UNDERVOLTAGE LOCKOUT
V(UVLO) Undervoltage lockout Decreasing VCC 2.4 2.5 2.6 V
Hysteresis 27 mV

Copyright © 2002–2007, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Link(s): bq24020 bq24022 bq24023 bq24024 bq24025 bq24026 bq24027
bq24020,, bq24022,, bq24023
bq24024, bq24025, bq24026
bq24027 www.ti.com
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

DRC PACKAGE DRC PACKAGE

(TOP VIEW) (TOP VIEW)
VSS STAT2 STAT1 USB AC VSS STAT2 STAT1 USB AC

5 4 3 2 1 5 4 3 2 1

bq24020DRC
bq24025DRC bq24022DRC

6 7 8 9 10 6 7 8 9 10

ISET1 ISET2 CE TS OUT ISET1 ISET2 PG CE OUT

DRC PACKAGE DRC PACKAGE

(TOP VIEW) (TOP VIEW)
VSS STAT2 STAT1 USB AC VSS STAT2 STAT1 USB AC

5 4 3 2 1 5 4 3 2 1

bq24023DRC
bq24024DRC

6 7 8 9 10 6 7 8 9 10

ISET1 ISET2 CE TTE OUT ISET1 ISET2 TTE TS OUT

DRC PACKAGE DRC PACKAGE

(TOP VIEW) (TOP VIEW)
VSS STAT2 STAT1 USB AC VSS STAT2 STAT1 USB AC

5 4 3 2 1 5 4 3 2 1

bq24026DRC bq24027DRC

6 7 8 9 10 6 7 8 9 10
ISET1 ISET2 TE TS OUT ISET1 ISET2 PG CE OUT

6 Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated

Product Folder Link(s): bq24020 bq24022 bq24023 bq24024 bq24025 bq24026 bq24027
 bq24020,, bq24022,, bq24023
bq24024, bq24025, bq24026
www.ti.com
bq24027
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

Terminal Functions
TERMINAL
NAME bq24020 bq24022 I/O DESCRIPTION
bq24023 bq24024 bq24026
bq24025 bq24027
AC 1 1 1 1 1 I AC charge input voltage
CE 8 9 8 - - I Charge enable input (active low)
Charge current set point for AC input and precharge and taper
ISET1 6 6 6 6 6 I
set point for both AC and USB
Charge current set point for USB port (high=500 mA, low=100
ISET2 7 7 7 7 7 I
mA, hi-z = disable USB charge)
OUT 10 10 10 10 10 O Charge current output
PG - 8 - - - O powergood status output (active low)
STAT1 3 3 3 3 3 O Charge status output 1 (open-drain)
STAT2 4 4 4 4 4 O Charge status output 2 (open-drain)
TE - - - - 8 I Timer enable input (active low)
TS 9 - - 9 9 I Temperature sense input
TTE - - 9 8 - I Timer and termination enable input (active low)
USB 2 2 2 2 2 I USB charge input voltage
VSS 5 5 5 5 5 - Ground input
There is an internal electrical connection between the exposed
thermal pad and VSS pin of the device. The exposed thermal
Exposed
pad must be connected to the same potential as the VSS pin
Thermal pad pad pad pad pad -
on the printed circuit board. Do not use the thermal pad as
Pad
the primary ground input for the device. VSS pin must be
connected to ground at all times

Copyright © 2002–2007, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Link(s): bq24020 bq24022 bq24023 bq24024 bq24025 bq24026 bq24027
bq24020,, bq24022,, bq24023
bq24024, bq24025, bq24026
bq24027 www.ti.com
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

FUNCTIONAL BLOCK DIAGRAM

VI(AC) AC
AC OUT
VI(OUT)
VI(OUT) +
VI(REG)
VI(USB) ISET1
USB VI(ISET)
sensefet
VI(SET)
+
REF
BIAS USB
AND AC/USB
UVLO
VI(ISET-USB) V(SET) AC/USB
CHG
ENABLE sensefet

VO(REG)
sensefet

UVLO

VI(ISET-USB)
V(HTF) * 100 mA/500 mA
I(TS)
SUSPEND
THERMAL
TS
SHUTDOWN AC/USB
*
CHG ENABLE
V(LTF)
500 mA/ 100 mA
CE

VI(OUT) * SLEEP (AC) VBAT ISET1

VI(AC)

VI(OUT) * SLEEP (USB) PRECHARGE

(C/10)
VI(USB) CHARGE
TTE CONTROL,
OR TIMER, 500 mA/ 100 mA
TE VO(REG) AND
DISPLAY ISET2
VI(OUT) * RECHARGE LOGIC USB CHARGE

VI(OUT) PG
* PRECHARGE

VI(SET)
VI(SET) * TAPER STAT1
t(TAPER) TIMER

VI(SET) * TERM
STAT2

VSS

* SIGNAL DEGLITCHED UDG−02185

8 Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated

Product Folder Link(s): bq24020 bq24022 bq24023 bq24024 bq24025 bq24026 bq24027
 bq24020,, bq24022,, bq24023
bq24024, bq24025, bq24026
www.ti.com
bq24027
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

TYPICAL CHARACTERISTICS
AC DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
450
IO(OUT) = 1000 mA
400

350

IO(OUT) = 750 mA
Dropout Voltage − mV 300

250
IO(OUT) = 500 mA
200

150
IO(OUT) = 250 mA
100

50

0
0 50 100 150
TJ − Junction Temperature − _C
Figure 1.

The bqTINY-II supports a precision Li-Ion, Li-pol charging system suitable for single-cell packs. Figure 3 shows a
typical charge profile, application circuit and Figure 4 shows an operational flow chart.

Regulation Pre-Conditioning Current Regulation Voltage Regulation

Voltage Phase Phase and Charge Termination Phase

Regulation
Current

Minimum Charge
Charge
Charge Voltage
Complete
Voltage

Charge
Pre-Conditioning Current
and Taper Detect

t(PRECHG) t(CHG)

Figure 2. Typical Charging Profile

Copyright © 2002–2007, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Link(s): bq24020 bq24022 bq24023 bq24024 bq24025 bq24026 bq24027
bq24020,, bq24022,, bq24023
bq24024, bq24025, bq24026
bq24027 www.ti.com
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

FUNCTIONAL DESCRIPTION

AC ADAPTER bq24023DRC
PACK+ SYSTEM
VDC 1 AC OUT 10

GND 0.1 µF +

PACK− SYSTEM
D+ INTERFACE
D−
VBUS 2 USB TTE 9

3 STAT1 CE 8

4 STAT2 ISET2 7
GND
5 VSS ISET1 6
USB PORT
RSET

UDG−02184

Figure 3. Typical Application Circuit

10 Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated

Product Folder Link(s): bq24020 bq24022 bq24023 bq24024 bq24025 bq24026 bq24027
 bq24020,, bq24022,, bq24023
bq24024, bq24025, bq24026
www.ti.com
bq24027
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

POR

SLEEP MODE
Vcc > VI(OUT)
No
checked at all times Indicate SLEEP
MODE

Yes

Regulate
IO(PRECHG)
VI(OUT)<V(LOWV) Reset and Start
Yes
t (PRECHG) timer Indicate Charge-
In-Progress

No

Reset all timers,

Start t (CHG) timer

Regulate Current
or Voltage
Indicate Charge-
In-Progress
No VI(OUT)<V(LOWV)

Yes
Yes

t(PRECHG)
No
Expired?

t (CHG) Expired?

Yes
No
Yes

Fault Condition
Yes VI(OUT) <V(LOWV)

Indicate Fault

No

I(TERM)
detection?
VI(OUT)> V(RCH)?

No Yes
No No
t(TAPER)
Expired?
(1)
I(TAPER) Enable I (FAULT)
detection? Yes current
No
No

Yes Yes VI(OUT) > V(RCH)?

Turn off charge

Yes
Indicate DONE
Yes
Disable I(FAULT)
current
No

VI(OUT) < V(RCH)

?

(1) t(TAPER) does not apply to bq24026/7

Figure 4. Operational Flow Chart

Copyright © 2002–2007, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Link(s): bq24020 bq24022 bq24023 bq24024 bq24025 bq24026 bq24027
bq24020,, bq24022,, bq24023
bq24024, bq24025, bq24026
bq24027 www.ti.com
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

AUTONOMOUS POWER SOURCE SELECTION

As default, the bqTINY-II attempts to charge from the AC input. If AC input is not present, the USB is selected. If
both inputs are available, the AC adapter has the priority. See for details.
AC > BATTERY

AC MODE USB MODE

AC < BATTERY
UDG−02187
USB > BATTERY

Figure 5. Typical Charging Profile

TEMPERATURE QUALIFICATION (bq24020, bq24024, bq24025, and bq24026 only)

The bqTINY-II continuously monitors battery temperature by measuring the voltage between the TS and VSS
pins. An internal current source provides the bias for common 10-kΩ negative-temperature coefficient thermistors
(NTC) (see Figure 6). The device compares the voltage on the TS pin with the internal V(LTF) and V(HTF)
thresholds to determine if charging is allowed. If a temperature outside the V(LTF) and V(HTF) thresholds is
detected, the device immediately suspends the charge by turning off the power FET and holding the timer value
(i.e. timers are NOT reset). Charge is resumed when the temperature returns within the normal range.
The allowed temperature range for a 103AT-type thermistor is 0°C to 45°C. However the user may modify these
thresholds by adding two external resistors. See Figure 7.

BATTERY PRE-CONDITIONING
If the battery voltage falls below the V(LOWV) threshold during a charge cycle, the bqTINY-II applies a precharge
current, IO(PRECHG), to the battery. This feature revives deeply discharged cells. The resistor connected between
the ISET1 and VSS, RSET, determines the precharge rate. The V(PRECHG) and K(SET) parameters are specified in
the specifications table. Note that this applies to both AC and USB charging.
V (PRECGH) K (SET)
I O (PRECHG)
RSET (1)
The bqTINY-II activates a safety timer, t(PRECHG), during the conditioning phase. If V(LOWV) threshold is not
reached within the timer period, the bqTINY-II turns off the charger and asserts a FAULT code on the STATx
pins. Please refer to the TIMER FAULT RECOVERY section for additional details.

bqTINYII PACK+ bqTINYII PACK+

+ +
PACK− ITS PACK−
ITS
TS TS RT1 NTC
NTC TEMP
TEMP 9
9
LTF LTF
BATTERY VLTF BATTERY
VLTF
PACK RT2 PACK
VHTF VHTF
HTF HTF

UDG−02186 UDG−02188

Figure 6. Temperature Sensing Configuration Figure 7. Temperature Sensing Thresholds

12 Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated

Product Folder Link(s): bq24020 bq24022 bq24023 bq24024 bq24025 bq24026 bq24027
 bq24020,, bq24022,, bq24023
bq24024, bq24025, bq24026
www.ti.com
bq24027
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

BATTERY CHARGE CURRENT

The bqTINY-II offers on-chip current regulation with a programmable set point. The resistor connected between
the ISET1 and VSS, RSET, determines the AC charge rate. The V(SET) and K(SET) parameters are specified in the
specifications table.
ǒK(SET) Ǔ
V(SET)
IO(OUT) +
RSET
(2)
When charging from a USB port, the host controller has the option of selecting either a 100-mA or a 500-mA
charge rate using the ISET2 pin. A low-level signal sets the current at 100 mA, and a high-level signal sets the
current at 500 mA. A high-Z input disables USB charging

BATTERY VOLTAGE REGULATION

The voltage regulation feedback is through the OUT pin. This input is tied directly to the positive side of the
battery pack. The bqTINY-II monitors the battery-pack voltage between the OUT and VSS pins. When the battery
voltage rises to the VO(REG) threshold, the voltage-regulation phase begins and the charging current begins to
taper down.
As a safety backup, the bqTINY-II also monitors the charge time. If the charge is not terminated within the time
period specified by t(CHG), the bqTINY-II turns off the charger and asserts a FAULT code on the STATx pins.
Please refer to the TIMER FAULT RECOVERY section for additional details.

CHARGE TAPER DETECTION, TERMINATION AND RECHARGE

The bqTINY-II monitors the charging current during the voltage-regulation phase. When the taper threshold,
I(TAPER), is detected, the bqTINY-II initiates the taper timer, t(TAPER). Charge is terminated after the timer expires.
The resistor connected between the ISET1 and VSS, RSET, determines the taper detection level. The V(TAPER) and
K(SET) parameters are specified in the specifications table. Note that this applies to both AC and USB charging.
V(TAPER) K(SET)
I (TAPER) +
RSET (3)
The bqTINY-II resets the taper timer if the charge current rises above the taper threshold, I(TAPER).
In addition to taper-current detection, the bqTINY-II terminates charge if the charge current falls below the I(TERM)
threshold. This feature allows quick recognition of a battery-removal condition, or insertion of a fully charged
battery. Note that the charge timer and taper timer are bypassed for this feature. The resistor connected between
the ISET1 and VSS, RSET, determines the taper detection level. The V(TERM) and K(SET) parameters are specified in
the specifications table. Note that this applies to both AC and USB charging.
V(TERM) K(SET)
I (TERM) +
R SET (4)
After charge termination, the bqTINY-II re-starts the charge when the voltage on the OUT pin falls below the
V(RCH) threshold. This feature keeps the battery at full capacity at all times.

Note ON bq24026 AND bq24027

The bq24026 and bq24027 monitor the charging current during the voltage-regulation phase. Once the taper
threshold, I(TAPER), is detected, the bq24026/27 terminates the charge. There is no taper timer (t(TAPER)) for this
version.
The resistor connected between the ISET1 and VSS, RSET, determines the taper-detect level for AC input. For
USB charge, taper level is fixed at 10% of the 100- or 500-mA charge rate.
Also note that there is I(TERM) detection in the bq24026 and the bq24027.

SLEEP MODE
The bqTINY-II enters low-power sleep mode if both AC and USB are removed from the circuit. This feature
prevents draining the battery in the absence of input supply.

Copyright © 2002–2007, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Link(s): bq24020 bq24022 bq24023 bq24024 bq24025 bq24026 bq24027
bq24020,, bq24022,, bq24023
bq24024, bq24025, bq24026
bq24027 www.ti.com
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

CHARGE STATUS OUTPUTS

The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in the following table.
These status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the
open-drain transistor is turned off.

Table 1. Status Pins Summary (1)

CHARGE STATE STAT1 STAT2
Precharge in progress ON ON
Fast charge in progress ON OFF
Charge done OFF ON
Charge suspend (temperature) OFF OFF
Timer fault OFF OFF
Sleep mode OFF OFF

(1) OFF means the open-drain output transistor on the STAT1 and STAT2 pins is in an off state.

PG OUTPUT
The open-drain PG (power Good) indicates when the AC adapter is present. The output turns ON when a valid
voltage is detected. This output is turned off in the sleep mode. The PG pin can be used to drive an LED or to
communicate to the host processor.

CE INPUT (CHARGE ENABLE)

The CE digital input is used to disable or enable the charge process. A low-level signal on this pin enables the
charge. A high-level signal disables the charge, and places the device in a low-power mode. A high-to-low
transition on this pin also resets all timers and timer fault conditions. Note that this applies to both AC and USB
charging.

TTE INPUT (TIMER AND TERMINATION ENABLE)

The TTE digital input is used to disable or enable the fast-charge timer and charge-taper detection. A low-level
signal on this pin enables the fast-charge timer and taper timer, and a high-level signal disables this feature.
Note that this applies to both AC and USB charging.

THERMAL SHUTDOWN AND PROTECTION

The bqTINY-II monitors the junction temperature, TJ, and suspends charging if TJ exceeds T(SHTDWN). Charging
resumes when TJ falls approximately 15°C below T(SHTDWN).

TE INPUT (TIMER ENABLED)

The TE digital input is used to disable or enable the fast-charge timer. A low-level signal on this pin enables the
fast-charge timer and a high-level signal disables this feature.
Note that this applies to both AC and USB charging.

14 Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated

Product Folder Link(s): bq24020 bq24022 bq24023 bq24024 bq24025 bq24026 bq24027
 bq24020,, bq24022,, bq24023
bq24024, bq24025, bq24026
www.ti.com
bq24027
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

TIMER FAULT RECOVERY

As shown in Figure 4, the bqTINY-II provides a recovery method to deal with timer-fault conditions. The following
discussion summarizes this method:
Condition #1: The charge voltage is above the recharge threshold (V(RCH)), and a timeout fault occurs
Recovery method: bqTINY-II waits for the battery voltage to fall below the recharge threshold. This could
happen as a result of a load on the battery, self-discharge or battery removal. When the battery voltage falls
below the recharge threshold, the bqTINY-II clears the fault and starts a new charge cycle. Toggling POR, CE, or
TTE also clears the fault.
Condition #2: The charge voltage is below the recharge threshold (V(RCH)), and a timeout fault occurs
Recovery method: In this scenario, the bqTINY-II applies the I(FAULT) current. This small current is used to detect
a battery-removal condition and remains on as long as the battery voltage stays below the recharge threshold. If
the battery voltage goes above the recharge threshold, then the bqTINY-II disables the I(FAULT) current and
executes the recovery method described for condition #1. When the battery voltage falls below the recharge
threshold, the bqTINY-II clears the fault and starts a new charge cycle. Toggling POR, CE, or TTE also clears
the fault.

APPLICATION INFORMATION

THERMAL CONSIDERATIONS
The bqTINY-II is packaged in a thermally enhanced MLP package. The package includes a thermal pad to
provide an effective thermal contact between the device and the printed circuit board (PCB). Full PCB design
guidelines for this package are provided in the application note entitled, QFN/SON PCB Attachment Application
Note (TI Literature Number SLUA271).
The most common measure of package thermal performance is thermal impedance (θJA) measured (or modeled)
from the device junction to the air surrounding the package surface (ambient). The mathematical expression for
θJA is:
T * TA
q JA + J
P (5)
Where:
• TJ = device junction temperature
• TA = ambient temperature
• P = device power dissipation
Factors that can greatly influence the measurement and calculation of θJA include:
• whether or not the device is board mounted
• trace size, composition, thickness, and geometry
• orientation of the device (horizontal or vertical)
• volume of the ambient air surrounding the device under test and airflow_lus549
• whether other surfaces are in close proximity to the device being tested
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal power
FET. It can be calculated from the following equation:
ǒ
P + V IN * V I(BAT) Ǔ I O(OUT)
(6)
Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. See Figure 2.

PCB LAYOUT CONSIDERATIONS

It is important to pay special attention to the PCB layout. The following provides some guidelines:

Copyright © 2002–2007, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Link(s): bq24020 bq24022 bq24023 bq24024 bq24025 bq24026 bq24027
bq24020,, bq24022,, bq24023
bq24024, bq24025, bq24026
bq24027 www.ti.com
SLUS549E – DECEMBER 2002 – REVISED NOVEMBER 2007

• To obtain optimal performance, the decoupling capacitor from VCC to VSS and the output filter capacitors from
OUT to VSS should be placed as close as possible to the bqTINY, with short trace runs to both signal and
VSS pins.
• All low-current VSS connections should be kept separate from the high-current charge or discharge paths from
the battery. Use a single-point ground technique incorporating both the small-signal ground path and the
power-ground path.
• The BAT pin is the voltage feedback to the device. It should be connected with its trace as close to the
battery pack as possible.
• The high-current charge paths into IN and from the OUT pins must be sized appropriately for the maximum
charge current in order to avoid voltage drops in these traces.
• The bqTINY-II is packaged in a thermally-enhanced MLP package. The package includes a thermal pad to
provide an effective thermal contact between the device and the printed circuit board (PCB). Full PCB design
guidelines for this package are provided in the application note entitled: QFN/SON PCB Attachment
Application Note (TI Literature No. SLUA271).

16 Submit Documentation Feedback Copyright © 2002–2007, Texas Instruments Incorporated

Product Folder Link(s): bq24020 bq24022 bq24023 bq24024 bq24025 bq24026 bq24027
 PACKAGE OPTION ADDENDUM

www.ti.com 2-May-2025

PACKAGING INFORMATION

Orderable Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
part number (1) (2) (3) Ball material Peak reflow (6)
(4) (5)

BQ24020DRCR Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 AZS
BQ24022DRCR Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 AZU
BQ24023DRCR Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 85 AZV
BQ24024DRCR Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 AZW
BQ24025DRCR Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 85 AZX
BQ24026DRCR Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 85 ANR
BQ24027DRCR Obsolete Production VSON (DRC) | 10 - - Call TI Call TI -40 to 85 ANS

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without
limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available
for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the
finish value exceeds the maximum column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per
JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the
previous line and the two combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 2-May-2025

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Feb-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ24020DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ24022DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ24023DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ24024DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ24025DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
BQ24026DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Feb-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ24020DRCR VSON DRC 10 3000 367.0 367.0 35.0
BQ24022DRCR VSON DRC 10 3000 367.0 367.0 35.0
BQ24023DRCR VSON DRC 10 3000 367.0 367.0 35.0
BQ24024DRCR VSON DRC 10 3000 367.0 367.0 35.0
BQ24025DRCR VSON DRC 10 3000 367.0 367.0 35.0
BQ24026DRCR VSON DRC 10 3000 367.0 367.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
DRC 10 VSON - 1 mm max height
3 x 3, 0.5 mm pitch PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4226193/A

www.ti.com
 PACKAGE OUTLINE
DRC0010J SCALE 4.000
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

3.1 B
A
2.9

PIN 1 INDEX AREA

3.1
2.9

1.0 C
0.8

SEATING PLANE
0.05
0.00 0.08 C

1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED 4X (0.25)
THERMAL PAD

5 6

2X 11 SYMM
2
2.4 0.1

10
1
8X 0.5 0.30
10X
0.18
PIN 1 ID SYMM
0.1 C A B
(OPTIONAL)
0.5 0.05 C
10X
0.3

4218878/B 07/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
DRC0010J VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(1.65)
(0.5)

10X (0.6)

1
10

10X (0.24)
11
SYMM (2.4)
(3.4)

(0.95)
8X (0.5)

5 6

(R0.05) TYP

( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:20X

0.07 MIN
0.07 MAX EXPOSED METAL ALL AROUND
ALL AROUND
EXPOSED METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4218878/B 07/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
DRC0010J VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

2X (1.5)
(0.5)
SYMM
EXPOSED METAL
11 TYP

10X (0.6)
1
10
(1.53)
10X (0.24) 2X
(1.06)

SYMM

(0.63)

8X (0.5)

6
5

(R0.05) TYP
4X (0.34)

4X (0.25)
(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 11:

80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X

4218878/B 07/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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