bq29330

www.ti.com SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012

2-SERIES, 3-SERIES, AND 4-SERIES CELL LITHIUM-ION OR

LITHIUM-POLYMER BATTERY PROTECTION AFE
Check for Samples: bq29330

1FEATURES
• 2-Series, 3-Series, or 4-Series Cell Protection • NMOS FET Drive for Charge and Discharge
Control FETs
• Can Directly Interface with the bq803x-Based • Host Control can Initiate Sleep and Ship Power
Gas Gauge Family Modes
• Watchdog and POR for the Host • Integrated 2.5-V, 16-mA LDO
• Provides Individual Cell Voltages and Battery • Integrated 3.3-V, 25-mA LDO
Voltage to Battery Management Host • Supply Voltage Range from 4.5 V to 28 V
• Capable of Operation With 5-mΩ Sense • Low Supply Current of 100 μA Typical
Resistor Integrated Cell Balancing Drive
• I2C Compatible User Interface Allows Access APPLICATIONS
to Battery Information • Notebook Computers
• Programmable Threshold and Delay for • Medical and Test Equipment
Overload Short Circuit in Discharge and Short
• Instrumentation and Measurement Systems
Circuit in Charge

DESCRIPTION
The bq29330 is a 2-series, 3-series, and 4-series cell lithium-ion battery pack full-protection analog front end
(AFE) IC that incorporates a 2.5-V, 16-mA and 3.3-V, 25-mA low dropout regulator (LDO). The bq29330 also
integrates an I2C-compatible interface to extract battery parameters such as battery voltage, individual cell
voltages, and control output status. Other parameters such as current protection thresholds and delays can also
be programmed into the bq29330 to increase the flexibility of the battery management system.

SYSTEM DIAGRAM

Discharge / Charge /
Precharge FETs

Fuse

Pack +

16 Dig GPIO & Peripherals 2.5 V LDO + Nch FET Drive Precharge
8 Dig GPIO or Analog GPI Reset (Charge Pumps) Control
Reset

Internal 32.768 kHz Watchdog &

Oscillator and PLL
Only Protection Timing
SMBus
HDQ
UART System Interface I2 C System Interface
Host Interface UART
& Data Management

RAM Configuration, Status

Cell Balancing Drive

2K Bytes of 2K Bytes
Voltage Translation
Cell, Bat and Pack

Data Flash of RAM and Control Registers

TOUT and LEDOUT

6K x 22 24K x 22 Program
T1 Power Support
Mask ROM Flash

Standard Delta-Sigma A-to-D Converter Analog Output Drive

2-Tier Overcurrent
Integrating Delta-Sigma A-to-D Converter
Protection

Pack –

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
bq29330
SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)
The bq29330 provides safety protection for overload, short circuit in charge, and short circuit in discharge
conditions and can also provide cell overvoltage, battery overvoltage and battery undervoltage protection with the
battery management host. In overload, short circuit in charge and short circuit in discharge conditions, the
bq29330 turns off the FET drive autonomously, depending on the internal configuration setting. The
communications interface allows the host to observe and control the status of the bq29330, enable cell
balancing, enter different power modes, set current protection levels, and set the blanking delay times.
Cell balancing of each cell can be performed via a cell bypass path integrated into the bq29330, which can be
enabled via the internal control register accessible via the I2C-compatible interface. The maximum bypass current
is set via an external series resistor and internal FET on resistance (typ. 400 Ω).

ORDERING INFORMATION (1)

PACKAGE
TA (2)
TSSOP(DBT) QFN(RSM) (2)
–40°C to 110°C bq29330DBT bq29330RSM

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) The bq29330 can be ordered in tape and reel by adding the suffix R to the orderable part number, i.e., bq29330DBTR.

SPACER

THERMAL INFORMATION
bq29330
(1)
THERMAL METRIC TSSOP (DBT) QFN (RSM) UNITS
30 PINS 32 PINS
θJA, High K Junction-to-ambient thermal resistance 81.4 37.4
θJC(top) Junction-to-case(top) thermal resistance 16.2 30.6
θJB Junction-to-board thermal resistance 34.1 7.7
°C/W
ψJT Junction-to-top characterization parameter 0.4 0.4
ψJB Junction-to-board characterization parameter 33.6 7.5
θJC(bottom) Junction-to-case(bottom) thermal resistance N/A 2.6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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PACKAGE OPTION PIN DIAGRAMS

TSSOP PACKAGE RSM PACKAGE
(TOP VIEW) (TOP VIEW)

XALERT
SDATA
CELL+
CELL-
1 30 XALERT

XRST
CELL-

SCLK
REG
VSS
CELL+ 2 29 SDATA
REG 3 28 SCLK

31
32

30

29

28

27

26

25
VSS 4 27 NC SRN 1 24
WDI
XRST 5 26 WDI NC 2 23 TOUT
SRN 6 25 TOUT SRP 3 22 LEDOUT
SRP 7 24 LEDOUT VC5 4 21 VSS
VC5 8 23 VSS VC4 5 20
NC
VC4 9 22 PMS VC3 6 19
PMS
21
VC2 7 18 GPOD
VC3 10 GPOD
VC1 8 17
ZVCHG
VC2 11 20 ZVCHG

10

12

13

14

15

16
11
9
VC1 12 19 VCC

CHG

DSG
NC

NC

NC

VCC
BAT

PACK
BAT 13 18 NC
CHG 14 17 PACK
NC 15 16 DSG

PIN FUNCTIONS
PIN
DESCRIPTION
NAME DBT NO. RSM NO.
CELL– 1 28 Output of scaled value of the measured cell voltage.
CELL+ 2 29 Output of scaled value of the measured cell voltage.
REG 3 30 Integrated 2.5-V regulator output
VSS 4, 23 31,21 Power supply ground
XRST 5 32 Active-low output
SRN 6 1 Current sense terminal
Current sense positive terminal when charging relative to SRN; current sense negative terminal when
SRP 7 3
discharging relative to SRN
VC5 8 4 Sense voltage input terminal for most negative cell; balance current input for least positive cell.
Sense voltage input terminal for least positive cell, balance current input for least positive cell, and return
VC4 9 5
balance current for third most positive cell.
Sense voltage input terminal for third most positive cell, balance current input for third most positive cell,
VC3 10 6
and return balance current for second most positive cell.
Sense voltage input terminal for second most positive cell, balance current input for second most
VC2 11 7
positive cell, and return balance current for most positive cell.
Sense voltage input terminal for most positive cell, balance current input for most positive cell, and
VC1 12 8
battery stack measurement input
BAT 13 9 Device power supply input
CHG 14 11 Charge pump, charge N-CH FET gate drive
DSG 16 13 Charge pump output, discharge N-CH FET gate drive
PACK 17 15 PACK positive terminal and alternative power source
VCC 19 16 Power supply voltage
ZVCHG 20 17 Connect the precharge P-CH FET drive here
GPOD 21 18 NCH FET open-drain output
PMS 22 19 Determines CHG output state on POR
LEDOUT 24 22 3.3-V output for LED display power supply
TOUT 25 23 Provides thermistor bias current

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PIN FUNCTIONS (continued)

PIN
DESCRIPTION
NAME DBT NO. RSM NO.
Digital input that provides the timing clock for the OC and SC delays and also acts as the watchdog
WDI 26 24
clock.
SCLK 28 25 Open-drain serial interface clock with internal 10-kΩ pullup to VREG
SDATA 29 26 Open-drain bidirectional serial interface data with internal 10-kΩ pullup to VREG
Open-drain output used to indicate status register changes. With internal 100-kΩ
XALERT 30 27
pullup to VREG
2, 10, 12,
NC 15,18,27 Not electrically connected to the IC
14, 20

FUNCTIONAL BLOCK DIAGRAM

GG VDD GG RST

PACK–

RZVCHG

PACK+

2nd
C Protection
REG

DSG CHG REG RST

PACK ZVCHG VCC
GG LED
INPUT
LEDOUT
CHG_ON

NCH GATE FET ZVCHG_ON

GATE DRIVER 3.3-V LDO C
DSG_ON 2.5-V LDO LED
PMS DRIVER LOGIC
POR
BAT

VC1
CELL 4
VC2

POWER CELL 3
32 kHz INPUT WDI WATCHDOG CELL VC3
TIMER MODE SELECTION
FROM GG CELL1..4
CELL 2
SHIP_ON CIRCUIT VC4
SLEEP_ON SWITCHES
CELL 1
VC5
REGISTERS
STATUS
SERIAL INTERFACE

SDATA OUTPUT CTL

GG INTERFACE
STATE CTL CELL+
SDATA FUNCTION CTL 0.975V
CELL SEL CELL VOLTAGE C GG ANALOG
GG INTERFACE BAT/25
CELL– CELL
OLV PACK/25 TRANSLATION INPUT
SCLK SCLK OLD
R
SCC TOUT THERM GG TS
DRIVE
SCD INPUT
CONTROL C
XALERT OVERLOAD
- THERM
ALERT TO GG COMPARATOR GND
OVERCURRENT THERMISTOR
OPEN DRAIN GPOD OPEN
DRAIN SRP
OUTPUT DELAY
OUTPUT SHORT CIRCUIT R
COMPARATOR SNS
SRN
SHORT_CIRCUIT

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SAFETY STATE DIAGRAM

LEGEND:
UVLO = Undervoltage Lock Out

KEY: No Power Supply

Disabled = OFF and cannot be changed via firmware
Enabled= Can be changed by firmware

Power Supply to PACK

Power Supply to PACK

UVLO Mode
CHG: OFF Ship Mode
DSG: OFF
ZVCHG: OFF CHG: OFF
VREG: OFF DSG: OFF
RST: HIGH ZVCHG: OFF
I2 C: Disabled VREG/VLED: OFF/OFF
Current Protection: Disabled I2 C: Disabled
VCELL: Disabled Current Protection: Disabled
Watchdog: Disabled VCELL: Disabled
Therm, Output: Disabled Watchdog: Disabled
Therm, Output: Disabled

Internal
Internal VLED> 2.4 V VLED < 2.3 V
Firmware Command
& No Supply to PACK
Firmware
Normal Mode Command
No supply PACK
CHG: ON DSG: OFF
voltage Mode
DSG: ON
DSG: OFF
ZVCHG: OFF
VREG/VLED: 2.5V/3.3V
RST: Driven low after tRST
I2 C: Enabled Firmware
Firmware
Current Protection: Enabled Command
Command
32 kHz Resumes VCELL: Enabled
Watchdog: Enabled
FirmwareCommand
Therm, Output: Enabled
Sleep Mode
Firmware CHG: OFF
32 kHz Input Halted Command DSG: OFF
and t WTO expired ZVCHG: OFF
VSR > VOL or VSCD for a period of tOL or tSCD VREG/VLED: ON/ON
Firmware Respectively, or VSR > VSCC for a period I2 C: Enabled
Command Current Protection: Enabled
of tSCC
VCELL: Enabled
WTO Mode Watchdog: Enabled
Current Protection Mode Therm, Output: Disabled
CHG: OFF CHG: OFF
DSG: OFF DSG: OFF
ZVCHG: OFF 32 kHz Input Halted ZVCHG: OFF
VREG/VLED: 2.5 V/3.3 V and tWTO expired VREG/VLED: 2.5 V/3.3 V
RST: Pulsed I2 C: Enabled
I2 C: Enabled Current Protection: Enabled
Current Protection: Enabled VCELL: Enabled
VCELL: Enabled Watchdog: Enabled
Watchdog: Enabled Therm, Output: Enabled
Therm, Output: Enabled

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted) (1) (2)

bq29330 UNIT
Supply voltage range (VCC, BAT) –0.3 to 34
(VC1, VC2, VC3, VC4, PACK, PMS) –0.3 to 34
(VC5) –0.3 to 1.0
(SRP, SRN) –1.0 to 1.0
Input voltage range
(VC1 to VC2, VC2 to VC3, VC3 to VC4, VC4 –0.3 to 8.5
to VC5)
(WDI, SCLK, SDATA) –0.3 to 8.5 V
(DSG,CHG) –0.3 to BAT
(ZVCHG) –0.3 to 34
(GPOD) –0.3 to 34
Output voltage range
(TOUT, SDATA, CELL, XALERT, XRST, –0.3 to 7
LEDOUT)
(CELL+) –0.3 to 7
Current for cell balancing 10 mA
Storage temperature range, Tstg –65 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground of this device except VCn–VC(n+1), where n=1, 2, 3, 4 cell voltage.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT
Supply voltage ( VCC, BAT) 4.5 25 V
VI(STARTUP) Start up voltage (VCC, BAT) 5.5 V
VC1, VC2, VC3, VC4 0 VDD
VC5 0 0.5
VI Input voltage range SRP, SRN –0.5 0.5 V
VCn – VC(n+1), (n=1, 2, 3, 4 ) 0 5.0
PACK, PMS 25
VIH 0.8×REG REG
Logic level input voltage SCLK, SDATA, WDI V
VIL 0 0.2×REG
VO Output voltage GPOD 25 V
XALERT, SDATA, XRST REG
VO Output voltage range V
CELL+, CELL– 0.975
External 2.5-V REG capacitor CREG 1.0 μF
External LEDOUT capacitor CLED 2.2 μF
Extend CELL output capacitor CCELL 0.1 μF
IOL GPOD 1 mA
RPACK 1 kΩ
Input frequency WDI 32.768 kHz
WDI high time 2 μs
Operating temperature –25 85 °C
TA
Functional temperature –40 110 °C

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ELECTRICAL CHARACTERISTICS
SUPPLY CURRENT, TA = 25°C, CREG = 1 μF, CL = 2.2 μF, VCC or BAT = 14 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
No load at REG, LEDOUT, TOUT, XALERT, SCLK, SDATA, TA = 25°C 140 190 μA
ZVCHG= off, WDI = 32 kHz
ICC1 Supply Current 1 TA = –40°C
VMEN = on, VC5 = VC4 = VC3 = VC2 = VC1 = 0 V 220 μA
select VC5 = VC4 = 0 V to 110°C

No load at REG, LEDOUT TOUT,

TA = –40°C
ICC2 Supply Current 2 XALERT, SCLK, SDATA. ZVCHG = off, WDI = 32 kHz, 105 185 μA
to 110°C
VMEN = off
CHG, DSG and ZVCHG = off, TA = –40°C
I(SLEEP) Sleep current 30 50 μA
REG = on, VMEN = off, WDI no clock, SLEEP = 1 to 110°C
CHG, DSG and ZVCHG = off,
TA = –40°C
I(SHUTDOWN) Shutdown mode REG = off, VMEN = off, WDI no clock, 0.1 1 μA
to 110°C
VPACK = 0 V, VC1 = VC2 = VC3 = VC4 = 3.5 V
2.5 V LDO, TA = 25°C, CREG = 1 μF, CL = 2.2 μF, VCC or BAT = 14 V, IOUT 33 = 0 mA (unless otherwise noted)
Regulator output 4.5 V < VCC or BAT ≤ 25 V, IOUT25 ≤ 16 mA TA = –40°C V
V(REG) 2.41 2.5 2.59
voltage to 110°C
Regulator output VCC or BAT = 14 V, IOUT25 = 2 mA
TA = –40°C
ΔV(EGTEMP) change with ±0.2%
to 110°C
temperature
ΔV(REGLINE) Line regulation 5.4 V ≤ VCC or BAT ≤ 25 V, IOUT25 = 2 mA TA = 25°C 3 10 mV
VCC or BAT = 14 V, 0.2 mA ≤ IOUT25 ≤ 2 mA TA = 25°C 7 15 mV
ΔV(REGLOAD) Load regulation
VCC or BAT = 14 V, 0.2 mA ≤ IOUT25 ≤ 16 mA TA = 25°C 15 50 mV
VCC or BAT = 14 V, REG = 2 V TA = 25°C 16 75
I(REGMAX) Current limit mA
VCC or BAT = 14 V, REG = 0 V TA = 25°C 5 45
3.3 V LED, TA = 25°C, CREG = 1.0 μF , CL = 2.2 μF, VCC or BAT = 14 V, IOUT25 = 0 mA (unless otherwise noted)

Regulator output 4.5 V < VCC or BAT ≤ 25 V, IOUT33 ≤ 10 mA TA = –40°C 3 3.3 3.6
VO(LED) V
voltage 6.5 V < VCC or BAT ≤ 25 V, IOUT33 ≤ 25 mA to 110°C 3 3.3 3.6
Regulator output VCC or BAT = 14 V, IOUT33 = 2 mA
TA = –40°C
ΔV(LEDEMP) change with ±0.2%
to 110°C
temperature
ΔV(LEDLINE) Line regulation 5.4 V ≤ VCC or BAT ≤ 25 V, IOUT33 = 2 mA TA = 25°C 3 10 mV
VCC or BAT = 14 V, 0.2 mA ≤ IOUT33 ≤ 2 mA 7 15
ΔV(LEDLOAD) Load regulation TA = 25°C mV
VCC or BAT = 14 V, 0.2 mA ≤ IOUT33 ≤ 25 mA 40 100
VCC or BAT = 14 V, REG = 3 V 25 125
I(LEDMAX) Current limit TA = 25°C mA
VCC or BAT = 14 V, REG = 0 V 12 50
THERMISTOR DRIVE, TA = 25°C, CREG = 1 μF, CL = 2.2 μF, VCC or BAT = 14 V (unless otherwise noted)
VTOUT ITOUT = 0 mA 2.4 2.6 V
TOUT Pass-element ITOUT = –1 mA at TOUT pin, TA = –40°C
RDS(ON) 50 100 Ω
series resistance RDS(ON) = [VREG – VOUT (TOUT)] / 1 mA to 110°C
SHUTDOWN WAKE, TA = 25°C, CREG = 1 μF, CL = 2.2 μF, VCC or BAT = 14 V (unless otherwise noted)
PACK Exit shutdown VCC or BAT = 14 V, PACK = 1.4 V
VSTARTUP 1 μA
threshold
POR, TA = 25°C, CREG = 1 μF, CL = 2.2 μF, VCC or BAT = 14 V (unless otherwise noted)
VPOR VREGTH– –3% 1.8 3% V
Hysteresis
50 150 250 mV
(Vregth+ – Vregth–)

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ELECTRICAL CHARACTERISTICS (Continued)

CELL VOLTAGE MONITOR, TA = 25°C, CREG = 1 μF, CL = 2.2 μF, VCC or BAT = 14 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCn – VCn+1 = 0 V, 8 V ≤ VDD ≤ 25 V 0.950 0.975 1
V(CELLOUT) V
VCn – VCn+1 = 4.5 V, 8 V ≤ VDD ≤ 25 V 0.275 0.3 0.325
(1)
REF Mode , 8 V ≤ VDD ≤ 25 V –1% 0.975 1% V
CELL output
Mode
PACK –2% PACK/18 2% V
[Register Address = 0x03, b1(PACK) = 1, b0( VMEN) = 1]
Mode
BAT –2% BAT/18 2% V
[Register Address = 0X03, b6(BAT) = 1, b0 ( VMEN) = 1]
CMRR Common mode rejection CELL max to CELL min 40 dB
V(CELLSLEW) CELL output rise Min to Max 10% to 90% 9 ms
K = {CELL output (VC5 = 0 V, VC4 = 4.5 V)
0.147 0.150 0.153
–CELL output (VC5 = VC4 = 0 V)} / 4.5
K CELL scale factor
K = {CELL output (VC2 = 13.5 V, VC1 = 18 V)
0.147 0.150 0.153
–CELL output (VC2 = VC1 = 13.5 V)} / 4.5
I(VCELLOUT) Drive current VCn– VCn+1 = 0 V , Vcell = 0 V, TA = –40° to 110° 12 18 μA
CELL output offset error CELL output (VC2 = 18 V, VC1 = 18 V)
VICR –1 mV
–CELL output (VC2 = VC1 = 0 V)
R(BAL) Cell balance internal resistance RDS(ON) for internal FET switch at VDS = 2 V –50% 400 50% Ω

(1) Register Address = 0x04, b2(CAL0) = b3(CAL1) = 1, Register Address = 0x03, b0(VMEN) = 1

CURRENT PROTECTION DETECTION, TA = 25°C, CREG = 1 μF, CL = 2.2 μF, VCC or BAT = 14 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RSNS = 0 –50 –205
V(OLT) OL detection threshold voltage range, typical (1) mV
RSNS = 1 –25 –102.5
RSNS = 0 –5
ΔV(OLT) OL detection threshold voltage program step mV
RSNS = 1 –2.5

SCC detection threshold voltage range, typical RSNS = 0 100 475

V(SCCT) (2) mV
RSNS = 1 RSNS is set in 50 237.5
RSNS = 0 FUNCTION_CTL register 25
ΔV(SCCT) SCC detection threshold voltage program step mV
RSNS = 1 12.5

SCD detection threshold voltage range, RSNS = 0 –100 –475

V(SCDT) mV
typical (3) RSNS = 1 –50 –237.5
RSNS = 0 –25
ΔV(SCDT) SCD detection threshold voltage program step mV
RSNS = 1 –12.5
VOL = –25 mV (typ) –15 –25 –35
VOL(acr) OL detection threshold voltage accuracy(1) VOL = –100 mV (typ) (RSNS = 0,1) –90 –100 –110 mV
VOL = –205 mV (typ) –185 –205 –225
VSCC = 50 mV (typ) 30 50 70
V(SCC_acr) SCC detection threshold voltage accuracy(2) VSCC = 200 mV (typ) (RSNS = 0,1) 180 200 220 mV
VSCC = 475 mV (typ) 428 475 523
VSCD = –50 mV (typ) –30 –50 –70
V(SCD_acr) SCD detection threshold voltage accuracy(3) VSCD = –200 mV (typ) (RSNS = 0,1) –180 –200 –220 mV
VSCD = –475 mV (typ) –426 –475 –523

(1) See OLV register for setting detection threshold

(2) See SCC register for setting detection threshold
(3) See SCD register for setting detection threshold

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ELECTRICAL CHARACTERISTICS (Continued)

FET DRIVE CIRCUIT, TA = 25°C, CREG = 1 μF, CL = 2.2 μF, VCC or BAT = 14 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO(FETOND) = V(DSG) – Vpack TA = 25°C 7.5 12 15.5
VGS connect 10 MΩ V
Output voltage, charge, TA = –40°C to 110°C 8 12 16
VO(FETON)
and discharge FETs on VO(FETONC) = V(CHG) – VBAT TA = 25°C 7.5 12 15.5
VGS connect 10 MΩ V
TA = –40°C to 110°C 8 12 16
V(ZCHG) ZVCHG clamp voltage BAT = 4.5 V 3.3 3.5 3.7 V
VFETOND = VDSG – 0.2
VO(FETOF Output voltage, charge, Vpack V
F) and discharge FETs off
VFETONC = VCHG – VBAT 0.2
V(CHG): Vpack ≥ Vpack + 4 V 400 1000
tr Rise time CL = 4700 pF μs
V(DSG): VBAT ≥ VBAT + 4 V 400 1000
V(CHG): Vpack + VCHG (FETON) ≥ pack + 1 V 40 200
tf Fall time CL = 4700 pF μs
V(DSG): VC1 + VDSG (FETON) ≥ VC1 + 1 V 40 200
LOGIC, TA = 25°C, CREG = 1 μF, CL = 2.2 μF, VCC or BAT = 14 V (unless otherwise noted)
XALERT 60 100 200
R(PUP) Internal pullup resistance SDATA, SCLK TA = –40°C to 110°C 6 10 20 kΩ
XRST 1 3 6
XALERT 0.2
SDATA, IOUT = 200 μA 0.4
Low Logic level output GPOD, IOUT = 50 μA 0.6
VOL TA = –40°C to 110°C V
voltage
VCC or BAT = 7 V, 0.4
VREG = 1.5 V,
XRST, IOUT = 200 μA
VIH SCLK (hysteresis input) Hysteresis 450 mV

AC ELECTRICAL CHARACTERISTICS
TA = 25°C, CREG = 1 μF, CL = 2.2 μF, VCC or BAT = 14 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tWDTINT WDT start up detect time 250 500 1000 ms
tWDWT WDT detect time 50 100 150 μs
tRST XRST Active high time 100 250 560 μs

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AC TIMING REQUIREMENTS (I2C compatible serial interface)

TA = 25°C, CREG = 1 μF, VCC or BAT = 14 V (unless otherwise noted)
PARAMETER MIN MAX UNIT
tr SCLK, SDATA rise time 1000 ns
tf SCLK, SDATA fall time 300 ns
tw(H) SCLK pulse width high 4 μs
tw(L) SCLK pulse width low 4.7 μs
tsu(STA) Setup time for start condition 4.7 μs
th(STA) Start condition hold time after which first clock pulse is generated 4 μs
tsu(DAT) Data setup time 250 ns
th(DAT) Data hold time 0 μs
tsu(STOP) Setup time for Stop condition 4 μs
tsu(BUF) Time the bus must be free before new transmission can start 4.7 μs
tv Clock low to data out valid 900 ns
th(CH) Data out hold time after clock low 10 ns
fSCL Clock frequency 0 100 kHz

tsu(STA) tw(H) tw(L) tf tr

SCLK

tr tf

SDATA Start Stop

Condition SDA SDA
Input Change Condition
th(ch)
th(STA) th(DAT) tsu(DAT)

SCLK 1 2 3 7 8 9

MSB ACK
SDATA
Start Condition tv

tsu(STOP)
SCLK 1 2 3 7 8 9 tsu(BUF)

SDATA MSB ACK

Stop Condition

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FUNCTIONAL DESCRIPTION

LOW DROP OUTPUT REGULATOR (LEDOUT)

The inputs for this regulator can be derived from the VCC or BAT terminals. The output is a fixed voltage of
typically 3.3 V with the minimum output capacitance for stable operation of 2.2 μF and is also internally current
limited. This output is used for LED drive, power supply source for REG (2.5 V) and bq29330 internal circuit.
During normal operation, the regulator limits output current to typically 50 mA. Until the internal regulator circuit is
correctly powered, the DSG and CHG FET drives are low (FETs = OFF).

LOW DROP OUTPUT REGULATOR (REG)

The inputs for this regulator can be derived from the LED (3.3 V). The output is typically 2.5 V with the minimum
output capacitance for stable operation of 1 μF and is also internally current limited. During normal operation, the
regulator limits output current to typically 50 mA.

INITIALIZATION
From a shutdown situation, the bq29330 requires a voltage greater that start-up voltage (VSTARTUP) applied to the
PACK pin to enable its integrated regulator and provide the regulators power source. Once the REG output is
stable, the power source of the regulator is switched to VCC.
After the regulator has started, it then continues to operate through the VCC input. If the VCC input is below the
minimum operating range, then the bq29330 will not operate if the supply to the PACK input is removed.
If the voltage at VLED falls below about 2.3 V, the internal circuit turns off the FETs and disables all controllable
functions including the REG, LEDOUT, and TOUT outputs.
The initial state of the CHG and DSG FET drive is low (OFF) and the ZVCHG FET drive is low (ON).

OVERLOAD DETECTION
The overload detection is used to detect abnormal currents in the discharge direction. This feature is used to
protect the pass FETs, cells, and any other inline components from excessive discharge current conditions. The
detection circuit also incorporates a blanking delay before driving the control for the pass FETs to the OFF state.
The overload sense voltage is set in the OLV register, and delay time is set in the OLD register. The thresholds
can be individually programmed from 50 mV to 205 mV in 5-mV steps with the default being 50 mV.
If the RSNS bit in the FUNCTION_CTL register is set to 1, then the voltage threshold, programmable step size,
and hysteresis is divided by 2.

SHORT CIRCUIT IN CHARGE AND SHORT CIRCUIT IN DISCHARGE DETECTION

The short current circuit in charge and short circuit in discharge detections are used to detect severe abnormal
current in the charge and discharge directions, respectively. This safety feature is used to protect the pass FETs,
cells, and any other inline components from excessive current conditions. The detection circuit also incorporates
a blanking delay before driving the control for the pass FETs to the OFF state. The short circuit in charge
threshold and delay time are set in the SCC register. The short circuit in discharge threshold and delay time are
set in the SCD register. The short-circuit thresholds can be programmed from 100 mV to 475 mV in 25-mV steps.
If the RSNS bit in the FUNCTION_CTL register is set to 1, then the voltage threshold, programmable step size,
and hysteresis is divided by 2.

OVERLOAD, SHORT CIRCUIT IN CHARGE AND SHORT CIRCUIT IN DISCHARGE DELAY

The overload delay (default = 1 ms) allows the system to momentarily accept a high current condition without
disconnecting the supply to the load. The delay time can be increased via the OLD register which can be
programmed for a range of 1 ms to 31 ms with 2-ms steps.
The short circuit in charge and short circuit in discharge delays (default = 0 μs) are programmable in the SCC
and SCD registers, respectively. These registers can be programmed from 0 μs to 915 μs with 61-μs steps.

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OVERLOAD, SHORT CIRCUIT IN CHARGE AND SHORT CIRCUIT IN DISCHARGE RESPONSE

When an overload, short circuit in charge, or short circuit in discharge fault is detected, the FETs are turned off.
The STATUS (b0…b3) register reports the details of overload, short circuit in charge or short-circuit discharge.
The respective STATUS (b0…b3) bits are set to 1 and the XALERT output is triggered. This condition is latched
until the STATE_CONTROL (b7) is set and then reset. If a FET is turned on after resetting STATE_CONTROL
(b0) and the error condition is still present on the system, then the device again enters the protection response
state.

2-, 3-, or 4-CELL CONFIGURATION

In a 2-cell configuration, VC1 and VC2 are shorted to VC3. In a 3-cell configuration, VC1 is shorted to VC2.

CELL VOLTAGE
The cell voltage is translated to allow a system host to measure individual series elements of the battery. The
series element voltage is translated to a GND-based voltage equal to 0.15 ±0.003 of the series element voltage.
This provides a range from 0 to 4.5 V. The translation output is presented between CELL+ and CELL– pins of
the bq29330 and is inversely proportional to the input using the following equation.
Where, V(CELLOUT) = –K × V(CELLIN) + 0.975 (V)
Programming CELL_SEL (b1, b0) selects the individual series element. The CELL_SEL (b3, b2) selects the
voltage monitor mode, cell monitor, offset, etc.

CALIBRATION OF CELL VOLTAGE MONITOR AMPLIFIER GAIN

The cell voltage monitor amplifier has an offset, and to increase accuracy, this can be calibrated.
The following procedure shows how to measure and calculate the offset as an example.

Step 1
Set CAL1=1, CAL0=1, VMEN=1.
VREF is trimmed to 0.975 V within ±1%; measuring VREF eliminates its error.
Measure internal reference voltage VREF from VCELL directly.
VREF = measured reference voltage

Step 2
Set CAL1=0, CAL0=1, CELL1=0, CELL0=0, VMEN=1.
The output voltage includes the offset and represented by:
VOUT(4-5) = VREF + (1 + K) × VOS (V)
Where K = CELL Scaling Factor
VOS = Offset voltage at input of the internal operational amplifier

Step 3
Set CAL1=1, CAL0=0, CELL1=0, CELL0=0, VMEN=1.
Measure scaled REF voltage through VCELL amplifier.
The output voltage includes the scale factor error and offset and is represented by:
V(OUTR) = VREF + (1 + K) × VOS – K × VREF (V)

Step 4
Calculate (VOUT(4-5) –V(OUTR)) / VREF.
The result is the actual scaling factor, KACT and is represented by:
KACT = (VOUT(4-5) –V(OUTR)) / VREF = (VREF + (1 + K) × VOS) – (VREF + (1 + K) × VOS – K ×
VREF)/VREF = K × VREF/VREF = K

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Step 5
Calculate the actual offset value where:
VOS(ACT) = (V(OUTR) – VREF) / (1 + KACT)

Step 6
Calibrated cell voltage is calculated by:
VCn – VC(n+1) = { VREF + (1 + KACT ) × VOS(ACT) – V(CELLOUT)}/KACT = {VOUT(4-5) – V(CELLOUT)}/KACT

To seek greater accuracy, it is better to measure VOS(ACT) for each cell voltage.
Set CAL1=0, CAL0=0, CELL1=0, CELL0=1, VMEN=1.
Set CAL1=0, CAL0=0, CELL1=1, CELL0=0, VMEN=1.
Set CAL1=0, CAL0=0, CELL1=1, CELL0=1, VMEN=1.
Measure VOUT(3-4), VOUT(2-3), VOUT(1-2),
VC4 – VC5 = {VOUT(4-5) – V(CELLOUT)}/KACT
VC3 – VC4 = {VOUT(3-4) – V(CELLOUT)}/KACT
VC2 – VC3 = {VOUT(2-3) – V(CELLOUT)}/KACT
VC1 – VC2 = {VOUT(1-2) – V(CELLOUT)}/KACT

BATTERY PACK AND BATTERY STACK MEASUREMENTS

The PACK (battery pack) and VC1 (battery stack) inputs can be translated to the CELL+, CELL– outputs of the
bq29330 through control bits in the FUNCTION_CONTROL register. If PACK is set, then the input at the PACK
is divided by 18 and presented at the CELL+, CELL– outputs. If the BAT bit is set, then the input to VC1 is
divided by 18 and presented at the CELL+, CELL– outputs. If setting both bits at the same time, VC1 is
presented at the CELL+, CELL– outputs.

CELL BALANCE CONTROL

The cell balance control allows a small bypass path to be controlled for any one series element. The purpose of
this bypass path is to reduce the current into any one cell during charging to bring the series elements to the
same voltage. Series resistors placed between the input pins and the positive series element nodes control the
bypass current value. Individual series element selection is made using bits 4 through 7 of CELL_SEL register.
Series input resistors between 500 Ω and 1 kΩ are recommended for effective cell balancing.

XALERT (XALERT)
XALERT is driven Low, when WDF, OL, SCC, or SCD OC are detected. To clear XALERT, toggle (from 0, set to
1, then reset to 0) STATE_CONTROL, LTCLR (bit 7), then read the STATUS register.

THERMISTOR DRIVE CIRCUIT (TOUT)

The TOUT pin can be enabled to drive a thermistor from REG. The typical thermistor resistance is 10 kΩ at
25°C. The default state for this is OFF to conserve power. The maximum output impedance is 100 Ω. TOUT is
enabled in FUNCTION_CONTROL register (bit 3).

GENERAL PURPOSE OPEN DRAIN DRIVE CIRCUIT (GPOD)

The General Purpose Open Drain output has 1-mA current source drive with a maximum output voltage of 25 V.
The OD output is enabled or disabled by OUTPUT_CONTROL register (bit 4) and has a default state of OFF.

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LATCH CLEAR (LTCLR)

When a protection fault occurs, the state is latched. To clear the fault flag, toggle (from 0, set 1, then reset to 0)
the LTCLR bit in the STATE_CONTROL register (bit 7). The OL, SCC, SCD, and WDF bits are unlatched by this
function. The FETs can now be controlled by programming the OUTPUT_CONTROL register, and the XALERT
output can be cleared by reading the STATUS register.
Fault Timeout STATUS Register
Expired Read

FET Control Access

by Host

Fault Flag Set

LTCLR Bit

XALERT Output

Figure 1. LTCLR and XLAERT Clear Timing

POR and WATCHDOG RESET (XRST)

The XRST pin is activated by activation of the REG output. This holds the host in reset for the duration of the
tRST period, allowing the VREG to stabilize before the host is released from reset. When the regulator power is
down, XRST is active below the regulator’s voltage of 1.8 V. Also, when a watchdog fault is detected, the XRST
is also activated to ensure a valid reset of the battery management host.

VREGTH+

REG Output VREGTH-

tRST
RST Output

Figure 2. XRST Timing Chart – Power Up and Power Down

WATCHDOG INPUT (WDI)

The WDI input is required as a time base for delay timing when determining fault detection and is used as part of
the system watchdog.
Initially, the watchdog monitors the host oscillator start-up; if there is no response from the host within tWDINT of
tRST expiring, then the bq29330 turns CHG, DSG, and ZVCHG FETs off. It then activates the XRST output in an
attempt to reset the host.
Once the watchdog has been started during this wake-up period, it monitors the host for an oscillation stop
condition which is defined as a period of tWDWT where no clock input is received. If an oscillator stop condition is
identified, then the watchdog turns the CHG, DSG, and ZVCHG FETs off. The bq29330 then activates the XRST
output in an attempt to reset the host.

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If the host clock oscillation is started after the reset, the bq29330 still has the WDF flag set until it is cleared. See
the LTCLR section for further details on clearing the fault flags.
During Sleep mode, the watchdog function is not disabled.

REG Output

tDWTINIT(500 ms) tDWTINIT(500 ms)

REG Output

tRST

WDI Input

XALERT

CHG, DSG, and

FET Control ZVCHG = OFF
Access by Host

WDRST = L

REG Output

tDWTINIT(500 ms) tDWTINIT(500 ms)

REG Output

tRST tRST tRST

WDI Input

XALERT

CHG, DSG, and

FET Control
ZVCHG = OFF
Access by Host

WDRST = H

Figure 3. Watchdog Timing Chart – WDI Fault at Start-up

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REG Output
Normal Operation tWDWT tDWTINIT(500 ms) tDWTINIT(500 ms)

REG Output

tRST

WDI Input

XALERT

CHG, DSG, and

FET Control
ZVCHG = OFF
Access by Host

WDRST = L

REG Output
Normal Operation tWDWT tDWTINIT(500 ms) tDWTINIT(500 ms)

REG Output

tRST tRST tRST

WDI Input

XALERT

FET Control CHG, DSG, and

Access by Host ZVCHG = OFF

WDRST = H

Figure 4. Watchdog Timing Chart – WDI Fault After Startup

DSG and CHG NCH FET DRIVER CONTROL

The bq29330 drives either the DSG or CHG FET off if an OL, SCC, or SCD safety threshold is breached
depending on the current direction. The host can force any FET on or off only if the bq29330 integrated
protection control allows.
The default-state of the FET drive is off. A host can control the FET drive by programming OUTPUT_CONTROL
(b2...b0), where b0 is used to control the discharge FET, b1 is used to control the charge FET, and b2 is used to
control the ZVCHG FET. These controls are only valid when not in the initialized state. The CHG drive FET can
be powered by PACK and the DSG FET can be powered by BAT.
When the bq29330 powers down, the NCH FET drivers power down to GND causing the FETs to turn off.

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PRECHARGE AND 0 V CHARGING

The bq29330 supports both a charger that has a precharge mode and one that does not. The bq29330 also
supports charging even when the battery falls to 0 V. In order to charge, the charge FET (CHG) must be turned
on to create a current path. When the VBAT is ~0 V, the V(PACK) is as low as the battery voltage. In this case, the
supply voltage for the device is too low to operate.

POWER MODES
The bq29330 has three power modes, normal, sleep, and ship. The following table outlines the operational
functions during these power modes.

Table 1. Outlines the Operational Functions

POWER TO ENTER POWER MODE TO EXIT POWER MODE MODE DESCRIPTION
MODE
Normal STATE_CONTROL, SLEEP( b0) = 0 and The battery is in normal operation with protection,
STATE_CONTROL, SHIP ( b1) = 0 power management and battery monitoring
functions available and operating.
The supply current of this mode varies as the host
can enable and disable various power
management features.
Sleep STATE_CONTROL, SLEEP( b0) = 1 and STATE_CONTROL, CHG, DSG, and ZVCHG OFF, OL, SCC, and SCD
STATE_CONTROL, SHIP ( b1) = 0 SLEEP( b0) = 0 function is disabled.
Cell AMP, GPOD , CELL BAL, and WDF is not
disabled
Ship STATE_CONTROL, SHIP ( b1) = 1 Supply voltage to PACK The bq29330 is completely shut down as in the
and supply at the PACK < VWAKE Supply sleep mode. In addition, the REG output is
disabled, I2C interface is powered down, and
memory is not valid.

VOLTAGE BASED EXIT FROM SHUTDOWN

If a voltage greater than VSTARTUP is applied to the PACK pin, then the bq29330 exits shutdown and enters
normal mode.

COMMUNICATIONS
The I2C-compatible serial communications provides read and write access to the bq29330 data area. The data is
clocked via separate data (SDATA) and clock (SCLK) pins. The bq29330 acts as a slave device and does not
generate clock pulses. Communication to the bq29330 can be provided from GPIO pins or an I2C supporting port
of a host system controller. The slave address for the bq29330 is 7 bits, and the value is 0100 000 (0x20).

(MSB) I2C Address +R/W bit (LSB)

(MSB) I2C Address (0x20) (LSB)
Write 0 1 0 0 0 0 0 0
Read 1

The bq29330 does NOT have the following functions compatible with the I2C specification.
• The bq29330 is always regarded as a slave.
• The bq29330 does not support the General Code of the I2C specification, and therefore will not return an ACK
but may return a NACK.
• The bq29330 does not support the Address Auto Increment, which allows continuous reading and writing.
• The bq29330 will allow data to be written or read from the same location without re-sending the location
address.

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SCLK …
… … …

SDATA A6 A5 A4 … A0 R/W ACK R7 R6 R5 … R0 ACK D7 D6 D5 … D0 ACK

0 0 0 0
Start Slave Address Register Address Data Stop

Note: Slave = bq29330

Figure 5. I2C-Bus Write to bq29330

SCLK … … … …

SDATA A6 A5 … A0 R/W ACK R7 R6 … R0 ACK A6 A0 R/W ACK D7 D6 … D0 NACK

0 0 0 1 0
Start Start Slave Drives Master
Slave Address Register Address Slave Address Stop
The Data Drives
NACK and
Note: Slave = bq29330 Stop

Figure 6. I2C-Bus Read from bq29330: Protocol A

SCLK … … … …

SDATA A6 A5 … A0 R/W ACK R7 R6 … R0 ACK A6 A5 … A0 R/W ACK D7 … D0 NACK

0 Master
Slave Drives Drives
Start Slave Register Address Stop Start Slave Address The Data Stop
NACK and
Stop
Note: Slave = bq29330

Figure 7. I2C-Bus Read from bq29330: Protocol B

REGISTER MAP
The bq29330 has nine addressable registers. These registers provide status, control, and configuration
information for the battery protection system.

NAME ADDR TYPE DESCRIPTION

STATUS 0x00 R Status register
OUTPUT_CONTROL 0x01 R/W Output pin control from system host and external pin status
STATE_CONTROL 0x02 R/W State control
FUNCTION_CONTROL 0x03 R/W Function control
CELL _SEL 0x04 R/W Battery cell select for cell translation and balance bypass and select mode for calibration
OLV 0x05 R/W Overload voltage threshold
OLD 0x06 R/W Overload delay time
SCC 0x07 R/W Short circuit in charge current threshold voltage and delay
SCD 0x08 R/W Short circuit in discharge current threshold voltage and delay

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BIT MAP
NAME ADDR TYPE
B7 B6 B5 B4 B3 B2 B1 B0
STATUS 0x00 R 0 0 0 ZV WDF OL SCC SCD
OUTPUT_ CONTROL 0x01 R/W 0 0 PMS_CHG GPOD XZV CHG DSG LTCLR
STATE_ CONTROL 0x02 R/W 0 0 0 RSNS WDRST WDDIS SHIP SLEEP
FUNCTION_ CONTROL 0x03 R/W 0 0 0 0 TOUT BAT PACK VMEN
CELL _SEL 0x04 R/W CB3 CB2 CB1 CB0 CAL1 CAL0 CELL1 CELL0
OLV 0x05 R/W 0 0 0 OLV4 OLV3 OLV2 OLV1 OLV0
OLD 0x06 R/W 0 0 0 0 OLD3 OLD2 OLD1 OLD0
SCC 0x07 R/W SCCD3 SCCD2 SCCD1 SCCD0 SCCV3 SCCV2 SCCV1 SCCV0
SCD 0x08 R/W SCDD3 SCDD2 SCDD1 SCDD0 SCDV3 SCDV2 SCDV1 SCDV0

STATUS: Status register

STATUS REGISTER (0x00)
7 6 5 4 3 2 1 0
0 0 0 ZV WDF OL SCC SCD

The STATUS register provides information about the current state of the bq29330.

STATUS b0 (SCD): This bit indicates a short circuit in discharge condition.

0= Voltage below the short circuit in discharge threshold (default).
1= Voltage greater than or equal to the short circuit in discharge threshold.
STATUS b1 (SCC): This bit indicates a short circuit in charge condition in the charge direction.
0= Voltage below the short circuit in charge threshold (default).
1= Voltage greater than or equal to the short circuit in charge threshold.
STATUS b2 (OL): This bit indicates an overload condition.
0= Voltage less than or equal to the overload threshold (default).
1= Voltage greater than overload threshold.
STATUS b3 (WDF): This bit indicates a watchdog fault condition has occurred.
0= 32-kHz oscillation is normal (default).
1= 32-kHz oscillation stopped or not started, and the watchdog has timed out.
STATUS b4 (ZV): This bit indicates ZVCHG output is clamped.
0= ZVCHG pin is not clamped (default).
1= ZVCHG pin is clamped.
STATUS b5, b6, b7: Reserved

OUTPUT_CONTROL : Output control register

OUTPUT_CONTROL REGISTER (0x01)
7 6 5 4 3 2 1 0
0 0 PMS_CHG GPOD XZV CHG DSG LTCLR

The OUTPUT_CONTROL register controls the outputs of the bq29330 and can show the state of the external pin
corresponding to the control.

OUTPUT_ CONTROL b0 (LTCLR): When a fault is latched, this bit releases the fault latch when toggled from 0
to 1 and back to 0 (default =0).
0= (default)
0->1 ->0 clears the fault latches, allowing STATUS to be cleared on its next read.

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OUTPUT_ CONTROL b1 (DSG): This bit controls the external discharge FET.
0= Discharge FET is off and is controlled by the system host (default).
1= Discharge FET is on, and the bq29330 is in normal operating mode.
OUTPUT_ CONTROL b2 (CHG): This bit controls the external charge FET.
0= Charge FET is off, and is controlled by the system host (default).
1= Charge FET is on, and the bq29330 is in normal operating mode.
OUTPUT_CONTROL b3(ZV): This bit enables or disables the precharge function.
0= ZVCHG FET is on, and is controlled by the system host (default).
1= ZVCHG FET is off, and the bq29330 is in normal operating mode.
OUTPUT_CONTROL b4 (GPOD): This bit enables or disables the GPOD output.
0= GPOD is high impedance (default).
1= GPOD output is active (GND).
OUTPUT_CONTROL b5 (PMS_CHG): This bit enables the CHG output for 0-V charge, when PMS terminal is
connected to Pack.
0= CHG FET is off (When PMS = GND, default).
1= CHG FET is on by connecting CHG and PACK terminal. (When PMS = PACK, default).

STATE_CONTROL : State control register

STATE_CONTROL REGISTER (0x02)
7 6 5 4 3 2 1 0
0 0 0 RSNS WDRST WDDIS SHIP SLEEP

The STATE_CTL register controls the outputs of the bq29330 and can be used to clear certain states.

STATE_CONTROL b0 (SLEEP): This bit is used to enter the sleep power mode.
0= bq29330 exits sleep mode (default).
1= bq29330 enters the sleep mode.
STATE_CONTROL b1 (SHIP): This bit is used to enter the ship power mode when Pack supply voltage is not
applied.
0= bq29330 is in normal mode (default).
1= bq29330 enters ship mode when pack voltage is removed.
STATE_CONTROL b2 (WDDIS): This bit is used to enable the watchdog timer.
0= Watchdog timer is enabled (default).
1= Watchdog timer is disabled.
STATE_CONTROL b3 (WDRST): This bit is used to enable the reset for GC, when watchdog timer is active.
0= Reset output is disabled, when watchdog timer is active (default).
1= 2 Times reset output is enabled, when watchdog timer is active.
STATE_CONTROL b4 (RSNS): This bit sets the OL, SCC, and SCD thresholds into a range suitable for a low
sense resistor value by dividing the OLV, SCCV, and SCDV selected voltage thresholds by 2.
0= Current protection voltage threshold as programmed (default)
1= Current protection voltage thresholds divided by 2 as programmed
STATE_CONTROL b6..7 (0): These bits are not used and should be set to 0.

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FUNCTION_CONTROL : Function control register

FUNCTION_CTL REGISTER (0x03)
7 6 5 4 3 2 1 0
0 0 0 0 TOUT BAT PACK VMEN

The FUNCTION_CONTROL register enables and disables features of the bq29330.

FUNCTION_CONTROL b0 (VMEN): This bit enables or disables the cell and battery voltage monitoring
function.
0= Disable voltage monitoring (default). CELL output is pulled down to GND level.
1= Enable voltage monitoring
FUNCTION_CONTROL b1 (PACK): This bit is used to translate the PACK input to the CELL+, CELL– pins
when VMEN = 1. The PACK input voltage is divided by 18 and is presented on CELL+, CELL– pins regardless
of the CELL_SEL register settings.
0= CELL_SEL (b0, b1) settings determine CELL+, CELL– output when VMEN = 1(default).
1= PACK input translated to CELL output regardless of CELL_SEL (b0, b1) selection when VMEN=1
FUNCTION_CTL b2 (BAT): This bit is used to translate the BAT input to the CELL+, CELL– pins when
VMEN=1. The VC5 input voltage is divided by 18 and is presented on CELL+, CELL– regardless of the
CELL_SEL register settings.
0= CELL_SEL (b0, b1) settings determine CELL+, CELL– output when VMEN = 1(default).
1= BAT input translated to CELL+, CELL– output regardless of CELL_SEL (b0, b1) selection when
VMEN = 1
This bit priority is higher than PACK(b1).
FUNCTION_CONTROL b3 (TOUT): This bit controls the power to the thermistor.
0= Thermistor power is off (default).
1= Thermistor power is on.

CELL_SEL : Cell select register

CELL_SEL REGISTER (0x04)
7 6 5 4 3 2 1 0
CB3 CB2 CB1 CB0 CAL1 CAL0 CELL1 CELL0

This register determines cell selection for voltage measurement and translation, cell balancing, and the
operational mode of the cell voltage monitoring.

CELL_SEL b0–b1 (CELL0–CELL1): These two bits select the series cell for voltage measurement translation.

CELL1 CELL0 SELECTED CELL

0 0 VC4–VC5, Bottom series element (default)
0 1 VC4–VC3, Second lowest series element
1 0 VC3–VC2, Second highest series element
1 1 VC1–VC2, Top series element

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CELL_SEL b2–b3 (CAL1, CAL0): These bits determine the mode of the voltage monitor block

CAL1 CAL0 SELECTED MODE

0 0 Cell translation for selected cell (default)
0 1 Offset measurement for selected cell
1 0 Monitor the VREF value for gain calibration
Monitor the VREF directly value for gain calibration,
1 1
bypassing the translation circuit

CELL_SEL b4–b7 (CB0 – CB3): These 4 bits select the series cell for cell balance bypass path.
CELL_SEL b4 (CB0): This bit enables or disables the bottom series cell balance charge bypass path.
0= Disable bottom series cell balance charge bypass path (default)
1= Enable bottom series cell balance charge bypass path
CELL_SEL b5 (CB1): This bit enables or disables the second lowest series cell balance charge bypass path.
0= Disable series cell balance charge bypass path (default)
1= Enable series cell balance charge bypass path
CELL_SEL b6 (CB2): This bit enables or disables the second highest cell balance charge bypass path.
0= Disable series cell balance charge bypass path (default)
1= Enable series cell balance charge bypass path
CELL_SEL b7 (CB3): This bit enables or disables the highest series cell balance charge bypass path.
0= Disable series cell balance charge bypass path (default)
1= Enable series cell balance charge bypass path

OLV: Overload Voltage threshold register

OLV REGISTER (0x05)
7 6 5 4 3 2 1 0
0 0 0 OLV4 OLV3 OLV2 OLV1 OLV0

OLV (b4–b0): These four bits select the value of the overload threshold with a default of 0000.
OLV (b5–b7): These bits are not used and should be set to 0.

OLV (b4–b0) configuration bits with corresponding voltage threshold (1)

0x00 –0.050 V 0x08 –0.090 V 0x10 –0.130 V 0x18 –0.170 V
0x01 –0.055 V 0x09 –0.095 V 0x11 –0.135 V 0x19 –0.175 V
0x02 –0.060 V 0x0a –0.100 V 0x12 –0.140 V 0x1a –0.180 V
0x03 –0.065 V 0x0b –0.105 V 0x13 –0.145 V 0x1b –0.185 V
0x04 –0.070 V 0x0c –0.110 V 0x14 –0.150 V 0x1c –0.190 V
0x05 –0.075 V 0x0d –0.115 V 0x15 –0.155 V 0x1d –0.195 V
0x06 –0.080 V 0x0e –0.120 V 0x16 –0.160 V 0x1e –0.200 V
0x07 –0.085 V 0x0f –0.125 V 0x17 –0.165 V 0x1f –0.205 V

(1) If RSNS bit is FUNCTION_CONTROL = 1, then the corresponding voltage threshold is divided by 2.

22 Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated

Product Folder Link(s): bq29330

 bq29330
www.ti.com SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012

OLD: Overload Delay time configuration register

OLD REGISTER (0x07)
7 6 5 4 3 2 1 0
0 0 0 0 OLD3 OLD2 OLD1 OLD0

OLD(b3–b0): These four bits select the value of the delay time for overload with a default of 0000.
0x00 1 ms 0x04 9 ms 0x08 17 ms 0x0c 25 ms
0x01 3 ms 0x05 11 ms 0x09 19 ms 0x0d 27 ms
0x02 5 ms 0x06 13 ms 0x0a 21 ms 0x0e 29 ms
0x03 7 ms 0x07 15 ms 0x0b 23 ms 0x0f 31 ms

SCC : Short Circuit In Charge configuration register

SCC REGISTER (0x08)
7 6 5 4 3 2 1 0
SCCD3 SCCD2 SCCD1 SCCD0 SCCV3 SCCV2 SCCV1 SCCV0

This register selects the short circuit in charge voltage threshold and delay.
SCCV (b3–b0) : These lower nibble bits select the value of the short circuit in charge voltage threshold with 0000 as the default. (1)
0x00 0.100 V 0x04 0.200 V 0x08 0.300 V 0x0c 0.400 V
0x01 0.125 V 0x05 0.225 V 0x09 0.325 V 0x0d 0.425 V
0x02 0.150 V 0x06 0.250 V 0x0a 0.350 V 0x0e 0.450 V
0x03 0.175 V 0x07 0.275 V 0x0b 0.375 V 0x0f 0.475 V

(1) If RSNS bit is FUNCTION_CTL = 1, then the corresponding voltage threshold is divided by 2.

SCCD (b7–b4): These upper nibble bits select the value of the short circuit in charge delay time. Exceeding the short circuit in charge
voltage threshold for longer than this period turns off the CHG and DSG outputs. 0000 is the default.
0x00 0 μs 0x04 244 μs 0x08 488 μs 0x0c 732 μs
0x01 61 μs 0x05 305 μs 0x09 549 μs 0x0d 793 μs
0x02 122 μs 0x06 366 μs 0x0a 610 μs 0x0e 854 μs
0x03 183 μs 0x07 427 μs 0x0b 671 μs 0x0f 915 μs

SCD : Short Circuit In Discharge configuration register

SCD REGISTER (0x08)
7 6 5 4 3 2 1 0
SCDD3 SCDD2 SCDD1 SCDD0 SCDV3 SCDV2 SCDV1 SCDV0

This register selects the short circuit in discharge voltage threshold and delay.
SCDV(b3–b0) : These lower nibble bits select the value of the short circuit in discharge voltage threshold with 0000 as the default. (1)
0x00 –0.100 V 0x04 –0.200 V 0x08 –0.300 V 0x0c –0.400 V
0x01 –0.125 V 0x05 –0.225 V 0x09 –0.325 V 0x0d –0.425 V
0x02 –0.150 V 0x06 –0.250 V 0x0a –0.350 V 0x0e –0.450 V
0x03 –0.175 V 0x07 –0.275 V 0x0b –0.375 V 0x0f –0.475 V

(1) If RSNS bit is FUNCTION_CTL = 1, then the corresponding voltage threshold is divided by 2.

SCCD (b7–b4): These upper nibble bits select the value of the short circuit in charge delay time. Exceeding the Short Circuit in charge
voltage threshold for longer than this period will turn off the CHG and DSG outputs. 0000 is the default.
0x00 0 μs 0x04 244 μs 0x08 488 μs 0x0c 732 μs
0x01 61 μs 0x05 305 μs 0x09 549 μs 0x0d 793 μs
0x02 122 μs 0x06 366 μs 0x0a 610 μs 0x0e 854 μs
0x03 183 μs 0x07 427 μs 0x0b 671 μs 0x0f 915 μs

Copyright © 2005–2012, Texas Instruments Incorporated Submit Documentation Feedback 23

Product Folder Link(s): bq29330
bq29330
SLUS673E – SEPTEMBER 2005 – REVISED MARCH 2012 www.ti.com

REVISION HISTORY

Changes from Original (September 2005) to Revision A Page

• Changed package name From: SSOP(DBT) To: TSSOP(DBT) in the Ordering Information Table .................................... 2
• Changed the SCLK pin description From: Open-drain bi-directional serial interface clock with internal 10-kΩ pullup
to VREG To: Open-drain serial interface clock with internal 10-kΩ pullup to VREG ................................................................. 4
• Changed Supply Current 2 From: XALERT, SCLK, SDATA. ZVCHG = off, Input WDI, To: XALERT, SCLK, SDATA.
ZVCHG = off, WDI = 32 kHz, ................................................................................................................................................ 7
• Changed Calibration of Cell Voltage Monitor Amplifier Gain, Step 3 - From: Set CAL1=1, CAL0=1, CELL1=0,
CELL0=0, VMEN=1. To: Set CAL1=1, CAL0=0, CELL1=0, CELL0=0, VMEN=1. ............................................................. 12

Changes from Revision A (December 2005) to Revision B Page

• Deleted the QFN(RHB) package from the Ordering Information Table, the Package Option Pin Diagrams, and the
Pin Functions table. .............................................................................................................................................................. 2

Changes from Revision B (August 2006) to Revision C Page

• Changed BAT Pin description From: Charge pump, charge N-CH FET gate drive To: Device power supply input ............ 3
• Changed ELECTRICAL CHARACTERISTICS - CURRENT PROTECTION DETECTION section - positive and
negative values were not properly displayed. ....................................................................................................................... 8
• Changed Figure 3 - Watchdog Timing Chart – WDI Fault at Start-up ................................................................................ 15
• Added Figure 4 - Watchdog Timing Chart – WDI Fault After Startup ................................................................................ 16

Changes from Revision C (March 2009) to Revision D Page

• Added the RSM package to the Ordering Information Table ............................................................................................... 2

• Added the RSM pin out package illustration. ........................................................................................................................ 3

Changes from Revision D (July 2009) to Revision E Page

• Changed the device numbers in the Ordering Information Table From: bq29330ADBT and bq29330ARSM To:
bq29330DBT and bq29330RSM ........................................................................................................................................... 2
• Added Thermal Information .................................................................................................................................................. 2
• Changed the AC Timing Requiremenst Table, fSCL - Clock frequency MAX value From: 400 kHz To: 100 kHz ............... 10

24 Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated

Product Folder Link(s): bq29330

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

BQ29330DBT ACTIVE TSSOP DBT 30 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 110 29330

BQ29330DBTG4 ACTIVE TSSOP DBT 30 60 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 110 29330

BQ29330DBTR ACTIVE TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 110 29330

BQ29330DBTRG4 ACTIVE TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 110 29330

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ29330DBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Feb-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ29330DBTR TSSOP DBT 30 2000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBT0030A SCALE 2.000
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
C
6.55 TYP
A 6.25
0.1 C
PIN 1 INDEX AREA
28X 0.5
30
1

2X
7.85 7.15
7.75
NOTE 3

15
16
30X 0.23
0.17
4.5 1.2 MAX
B
4.3 0.1 C A B
NOTE 4

0.25
GAGE PLANE
0.15
0.05

(0.15) TYP
SEE DETAIL A 0.75
0 -8 0.50
DETAIL A
A 20

TYPICAL

4220214/A 05/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBT0030A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

30X (1.5) SYMM

1 (R0.05) TYP

30X (0.3) 30

30X (0.5)
SYMM

15 16

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220214/A 05/2020
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBT0030A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

30X (1.5) SYMM

(R0.05) TYP
1
30X (0.3) 30

30X (0.5)
SYMM

15 16

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220214/A 05/2020
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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