1.
Introductions
1.1. Basic Function and Design Goals
1.1.1. Basis Function
Provide gain to minimize noise contributed by subsequent blocks
Contribute as low noise as possible
Provide high linearity
Provide 50 ohm input impedance
Low power dissipation
1.1.2. Design Goals
Simultaneous Noise and Input Matching
Any given amount of power dissipation
17
2. Fundamental of Low Noise Amplifier
2.1. Noise Figure and Noise Factor
2.2. Power Gain
18
2.3. Linearity
19
3. Low Noise Amplifier Design Techniques
3.1. Classical Noise Optimization Technique
20
21
22
3.2. Simultaneous Noise and Input Matching Technique
3.2.1. Circuits Topology
23
3.2.2. Noise Parameters
24
25
26
27
3.2.3. Design Process
The following steps describe the procedure how to design LNA based on cascode
topology. Since there is no guideline how to choose the cascode transistor to obtain
the best performances such as NF, Power gain, and Linearity. Assume that the size of
cascode transistor is chosen to be equal to the input transistor. And also assume that
the gate bias of the cascode transistor is Vdd.
1) Choose VGS
a) Setup Environment
In the library named as LNA example, open new cell view named as Choose
VGS. Based on the knowledge conducted in the “Basis cadence lecture”,
build the circuit as below.
28
• Highlight input port and modify it as
Typing in
here
29
• Highlight Output port and modify it as
Typing in
here
30
• From the schematic window select: Tool- Analog Environment
• On the Analog Circuit Design Environment, Click Setup-Model libraries
Typing in here
31
• In the Model Library File and Section fields typing as following
Model Library File Section (opt.)
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt_3v
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt_na
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt_3vna
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt_m
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt_3m
/data1/RACS/DC_project/Tsmc18/models/mm018.scs ees
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt_bip
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt_bip3
/data1/RACS/DC_project/Tsmc18/models/mm018.scs dio
/data1/RACS/DC_project/Tsmc18/models/rf018.scs tt_rfmos
/data1/RACS/DC_project/Tsmc18/models/ResModel.scs res_t
You can Click Browse and go up to the directory, which contain the model
library of the technology you would like to use. Or instructors will introduce
the path of model library
• Notice: After you finish typing one section, press Add icon. If you
make some mistakes, you can delete by click Delete icon
32
• On the Analog Environment Window, Click Variable-Copy from cell view.
Analog Environment window looks like
• Click edit variable icon on the right hand side
The following window will appear.
• Highlight VGS and typing its primary value (any value)
33
Typing in
here
• On the Analog Circuit Design Environment, select Analyses – Choose.
The window will appear as
• On the choosing Analyses window, highlight DC simulator and modify
the field as
34
• Click Apply icon.
• Choose SP Simulator, the window appear as
35
• Modify your window to become as follows
36
Typing in here
Highlight
Typing in here
Click here and place cursor
on Output and Input ports
on the schematic
• Click OK
37
b) Run simulation
• Click Netlist and Run icon
• After simulation is finished you can see the window looks like
c) Plotting Results
• In the Simulation window, select Results → Direct Plot → Main Form.
38
• The window will appears as
• On the SP-Parameters Result Form, do following
39
• Highlight Append for Plot Mode
• Highlight Gmax for Function
• Highlight Rectangular for Plot Type
• Highlight dB10 for Modifier
• Click Plot
• Choose NFmin for Function
• Highlight Rectangular for Plot Type
• Highlight dB10 for Modifier
• Click Plot
Gmax
NFmi
From above figures, we can determine the value of Vgs that gives the minimum
40
NF and maximum available gain. As can be seen in this figure, we choose Vgs =
840 mV.
2) Choose Size of Transistor
Choose the size of transistor by simulating Γopt = 50 Ω factor
a) Setup environment
We can set the multiplier factor of transistor as a variable and do the simulation
to find the optimum value. But in this process the multiplier cannot be a variable
therefore we have to do some simulation steps to find the optimum value of
multiplier factor.
Setting the simulation window as
• Setting Vgs = 840 mV.
• Modify SP simulator as below.
41
Highligh
Typing in
• Click OK
b) Run Simulation
• Click Run simulation icon
c) Plotting Results
• After simulation finish click Results → Main For → S-parameters.
• On the S-Parameter Results window do following
• Choose Gmin (Optimum noise Reflection Coefficient) for Function
• Choose Z-Smith for Plot Type
42
• Click Plot
Place cursor
to find the
43
Another way to see the result
• On the Analog Circuit Design Environment, do following
• Highlight ZP (Z parameters) for Function
• Highlight Rectangular for Plot Type
• Highlight Real for Modifier
• Click Z11 we can see the results as below
44
Place cursor to find the real
Z11 at 5.25 GHz
On the Schematic window do following
• Highlight NMOS transistor by press Q
• On the properties window, change multiplier = 2.
Typing in
• Press OK
45
• Press Save and Check icon
Run simulation and plot result (do the same steps as previous)
Place cursor to
find the value at
5.25 GHz
• Do the same step to plot the Z11
46
• Do the same above steps for multiplier = 3, you obtain the result as
Place cursor
to find the
47
• Do the same above steps for multiplier = 4, you obtain the result as
Place cursor to
find the value at
5.25 GHz
As can be seen from above figures, when multiplier factor = 3, the real part of
Gmin = 1.
48
3) Choose Ls (Inductor Degeneration)
This step is to choose the value of Ls that makes the real part of S11 = 1
a) Setup Environment
• In the schematic window, insert new inductor as below
New
• A new inductor has inductance value as Ls
• On the Analog Circuit Design Environment do the following
Select Variables – Copy From Cell View
Setting primary value of Ls (any value)
49
Modify SP simulation looks like
• Click OK
• Now your Circuit Design Environment looks like
50
b) Run Simulation
Click Netlist and Run icon
c) Plotting Results
After finish simulation, select Results → Direct Plot → Main Form
On the S-Parameter Results window do following
• Highlight SP (S parameters) for Function
• Highlight Z-Smith for Plot Type
51
Click S11, you can see the result as below
Choose the value of
From this figure, you obtain the value of Ls = 0.28 nH
52
4) Choose the series gate inductance
a) Setup environment
• Insert new inductor which has the inductance value = Lg.
• On the Analog Circuit Design Environment, do the following
• Change the value of Ls = 0.28 nH.
• Select Variable – Copy From Cell View.
• Set the primary value of Lg (any value)
• In the Analog Circuit Design Environment, double click on the SP
simulation and modify as
53
• Click OK
• Now the Analog Circuit Design Environment becomes as below
54
b) Run Simulation
• Click Nestlist and Run icon
c) Plotting Results
• After finish simulation, select Results → Direct Plot → Main Form S-
parameters.
• On the S-Parameter Results window do following
• Highlight SP (S parameters) for Function
• Highlight Z-Smith for Plot Type
55
• Click S11, you can see the result as below
Choose the value of
Lg at this point
56
5) Output Matching: Choose load inductance and load resistance
a) Setup environment
On the Schematic Window do following steps
• Change the value of the load resistor to become R1
• Chang the value of the load inductor to become L1
On the Analog Circuit Design Environment do following
• Click Variables Copy From Cell View
• Set the primary value of L1 and R1 (any value)
• The Analog Design Environment look like
• Double Click on the SP simulator and modify it as
57
Select Tools – Parametric Analysis, the following window appears
58
Modify the window as below
b) Run Simulation
• On the Parametric Analysis window, select Analysis – Start
c) Plotting Results
• After simulation is finished, Plotting result
On the Analog Circuit Design Environment, choose: Results → Direct Plot →
Main Form S-parameters, the SP-Parameters window will appear
• Highlight SP for Function
• Highlight Z-Smith for Plot Type
• Click S22 button
59
Choose 1 of
You can choose 1 of the ten values that is shown in above figure, however,
you should consider about the maximum available gain at each value.
• On the Analog Circuit Design Environment, plotting Gmax as the
function of R1 and L1
60
Based on above figure, assume that you decide to design LNA has gain
around 18, so result shows the value of R1 = 300 Ohm.
See in the Smith chart, when the R1 = 300 Ohm L1 = 2.8 nH
6) Output Matching: choose output capacitance
a) Setup environment
On the schematic window, highlight capacitor named C1 and setting its
capacitance value = C1.
On the Analog Circuit Design Environment, do following
• Select Variable – Copy From Cell View.
• Set the primary value of C1 (any value)
• Change the value of L1 = 2.8 nH (this result is obtained in the
previous simulation step)
• On the Analog Circuit Design Environment window, double click on
the SP simulation and modify as
61
Now your Analog Circuit Design Environment looks like below
62
b) Run simulation
Click Netlist and Run icon
c) Plotting result
After finish simulation, select Results → Direct Plot → Main Form S
Parameters
On the S-Parameter Results window do following
• Highlight SP for Function
• Highlight Z-Smith for Plot Type
63
Click S22 button, you can see the result as below
Choose
7) Running S-Parameters and NF Simulation
a) Setup Environment
On the Analog Circuit Design Environment window, do following
• Change the value of C1 = 238 fF
• Double click on SP simulator and modify it as
Click OK
64
Now the Analog Circuit Design Environment looks like below
b) Run simulation
Click The Netlist and Run icon to run the simulation
c) Plotting Results
Plot S parameters:
On the Analog Design Environment window
Click Results Direct Plot Main Form S Parameters
Modify Direct Plot Form window as follows
65
Click on S11, S22, S21, and S12 separately, the results are shown as follows
S21
S11
S22 S12
66
As can be seen in above Fig., the value of S11 is high because the limitation of
the isolation between output and input. However, the value of S11 = 15 dB, it
can be accepted. If the value of S11 is higher than –15dB, the designer might
have to do some simulation steps.
Keep the output matching as the condition which is found at step (5) &
(6)
Find the value of Ls as the step (3).
Find the value of Lg as the step (4)
Plot NF and NFmin of LNA
On the Direct Plot Form
Highline NFmin (or NF) at the function field
Highline dB10 for Modified
67
68
The results are shown as follows
As can be in above Figures, the value of the NF is slightly higher than NFmin of
the given topology. The reason is the size of the input transistor cannot be
chosen properly.
(See the choosing transistor size step, step (2))
8) Linearity simulation (IIP3 and 1 dB compression Point)
a) Setup environment
On the schematic window, highlight input Port and modify it as
69
• On the Analog Circuit Design Environment do following
• Select Variable – Copy From Cell View
• Setting the primary value of rf_freq and rf_pwr to be 5.25 G and –40
• Select Analyses – Choose
• Highlight PSS and modify it as below
70
Highlight PAC on the Choosing Analyses window an modify it as
Click OK on the Choosing Analyses window.
71
• Your Analog Circuits Design Environment looks like
b) Run simulation
To run SP analysis, click Netlist and Run icon
Look in the output log file to be sure the simulation is completed
successfully.
c) Plotting Results
Plotting 1 dB compression point
In the simulation window, choose Results → main Plot → PSS. The
Waveform window and PSS results form appear.
In the PSS results, highlight PSS for Analysis Type
In the PSS results, highlight Compression point for Function
72
Highlight Variable Sweep for circuit input power
73
Place cursor in the schematic window and click on the output port.
Plotting IIP3
• On the Analog Circuit Design Environment window, choose: Results →
Direct Plot → PSS. The waveform window and the PSS results appear
• Highlight PAC and modify it as
74
• Place cursor on the output port in the schematic window, you will see
the result as
75
If we choose the Extrapolation value is –20, then we obtain the following Fig.
76
77
3.3. Power Constrained Noise Optimization Technique
78
79
3.4. Power-Constrained Simultaneous Noise and Input
Matching Technique
80
81
82
83
84
1) Power Constrained
Assume that we design LNA consuming 1 mW under supply voltage of 1.8 V.
1.1) Setup Environment
Draw Circuit as below
Modify Input Port and Output Port as follows
Input Port Output Port
85
From the schematic window select: Tool- Analog Environment
On the Analog Circuit Design Environment, Click Setup-Model libraries
Typing in here
86
In the Model Library File and Section fields typing as follows
Model Library File Section (opt.)
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt_3v
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt_na
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt_3vna
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt_m
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt_3m
/data1/RACS/DC_project/Tsmc18/models/mm018.scs ees
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt_bip
/data1/RACS/DC_project/Tsmc18/models/mm018.scs tt_bip3
/data1/RACS/DC_project/Tsmc18/models/mm018.scs dio
/data1/RACS/DC_project/Tsmc18/models/rf018.scs tt_rfmos
/data1/RACS/DC_project/Tsmc18/models/ResModel.scs res_t
You can Click Browse and go up to the directory, which contain the model
library of the technology you would like to use. Or instructors will introduce
the path of model library
• Notice: After you finish typing one section, press Add icon. If you
make some mistakes, you can delete by click Delete icon
• On the Analog Environment Window, Click Variable-Copy from cell view.
87
Analog Environment window looks like
Choose Variable Copy From Cell View, Analog Environment window
becomes
On the Analog Environment Window, Click Analysis-Choose, following
windown will appear
88
Choose DC analysis
Click on Save DC Operating Point
Make sure that Enable icon is on
1.2. Run Simulation
• Click Netlist and Run icon
1.3. Plot Results
From Analog Design Enviroment Windown, Click, Results Annotate DC Node
Voltage /DC Operating Points
89
We can see the DC current dissipation of the circuit
2) Choose the extral capacitor
a) Setup Inviroment
From the previous step, we choose the value of VGS is equal to 620 mV
Insert one additional capacitor in parallel with Gate-Source capacitor of
input transistor. The LNA schematic now becomes as folows
90
Highline this additional capacitor and modify it as follows
Typing in
here
From Analog Design Inviroment, click Analysis Choose, the Choosing
Analyses windown will appear, then modify it as follows
91
Click Apply and OK , then the Analog Design Enviroment windown becomes
as follows
92
From above Fig., we can choose the value of Cex = 210f in order to obtain
the Real value of Γopt equal to 1.
Insert inductive degeneration
93
94
Zoom in
95
Choose Ls = 1.4n
Insert series gate inductor
96
97
Choose Lg = 107 nH
98
Highlight the output inductor and typing in the inductance field as L1
99
Highlight the output resistor and typing in the resistance field as L1
On the Analog Design Enviroment, click Variable Copy from cell view, and
then typing the primalry value of L1 and R1 (any value).
The Analog Design Enviroment windown becomes
100
101
Choose R1 = 400 ohm, L1 = 26 nH
Highline output capacitance
102
103
Analog Design Environment becomes
Choose C1 = 1.3 pF
Run S-Parmeters Simulation
104
Analog Design Environment becomes
105
106
Stability factor
107
1. Image Rejection LNA
1.1 Circuit Descriptions
108
109
110
Overall NF of LNA/Filter is
⎧ ⎧⎡ ⎛ ⎞ ⎤
2
⎫⎫
⎪ ⎪ ⎢1 + s C gs ( Lg + Ls ) ⎜ 1+ | c | α
δ
⎟ ⎥ ⎪⎪
2
⎪ ⎪⎪ ⎢⎣ ⎝ 5γ ⎠ ⎥⎦ ⎪⎪ ⎪
⎪γ g ⋅ ⎨ ⎬⎪
1 ⎪ d0 ⎪ 2
⎪ ⎪⎬
F1 = 1 + 2 ⋅ ⎨ 2⎛ δ ⎞
g m Rs ⎪ ⎪ − ( sC gs Rs ) ⎜ 1+ | c | α ⎟ ⎪⎪
⎪⎩ ⎝ 5 γ ⎠ ⎭⎪ ⎪
⎪
⎪ αδ ⎪
( ) ( ) ( )
2
−
⎪⎩ 5 1 − | c |2
g m sC gs Rs
2
− sL 2
g ⎪⎭
Note that the impedance of the filter at the frequency of
the pole is high enough Ftotal = F1
111
112
1.2 Circuit Implementation
1.2.1 Setup Environment
Assume that we design the image rejection LNA operating at 5 GHz with the image signal equal
to 5.5 Ghz Based on Eq. We can calculate the value of each component of the image
rejection circuit as follows:
L1 (image rejection filter) = 2.2 nH, C1 (Image Rejection Filter) = 100f, C3 (Image Rejection
Filter) = 300f
Build the circuit as follows
10K ohm
Bias Circuit
• The model of bond-wire is shown in below
113
• The model of bond pad power is shown in below
• The model of bond pad shield is shown in below
Size of bias transistor
114
The way to find the value of input and output matching are the same as the Low
Noise Amplifier 1: Theory. However, the step to determine the value of Ls is
different because now the degeneration inductor is made by bonding wire
instead of using onchip inductor.
Sweep the value of Ls
115
Finally, we obtain the value of each component as follows
Ls = 0.3m, Lg = 2.5 nH, Ld (output inductance) = 2.3 nH, Rd (Output
resistance) = 250 ohm
Cd (Ouput capacitance = 1443 fF
1.2.2 Run S-parameters simulation
116
1.2.3 Plot Results
1) S-Parameters
117
2) NF and NFmin
1.2.4. Check Linearity
118
1.2.5. Plot Results
1) 1dB compression point
2) IIP3
119
2. Gain Enhancement Technique Using Positive
Feedback
2.2.1 Circuit Descriptions
The positive feedback is realized by Cf
This phenomenon can be understood by another point of view as
the form of oscillator. Cgs1, Cf, and M1 constitute an oscillator
topology with inductive termination at the output.
The gain of amplifier without Cf is given by
1 1
Av = g m1Qin = Geff (5.1)
Gtot Gtot
120
• gm is the transconductance of M1,
• Qin is the quality factor of the input circuit
• Geff is the effective transconductance of the amplifier
• Gtot is the total transconductance at the drain of M2 and is
dominated by the equivalent parallel conductance of the
inductor (GP).
1
GP = (5.2)
QL2 RLo
• RLo is the series resistance of the inductor
Low QL lead to high GP high Gtot Limit the Av of the amplifier
From (5.1) Gain of amplifier can be improved by larger Geff or
larger Lo larger power consumption or an impracticably larger
value for the inductor
The Q of the amplifier without Cf is given by
1 Ctot
Q= (5.3)
Gtot Lo
• Ctot is the total capacitance at the drain of M2.
From (5.2) and (5.3): Low QL will also limit the Q of amplifier
Assume that ω << g m 2 / ( Cgs 2 + C f ) , from Fig.-b, the negative
conductance (GN) is generated by Cf is
121
ω 2Cgs 2 ( CN + Cgd 2 )
GN = (5.4)
gm2
The total conductance now is given by
Gtot = GP − GN (5.5)
From (5.5) by using Cf, the total conductance is reduced
improve gain of LNA
Note that no additional active is used therefore no more DC
power dissipated and no noise contributed.
The limit to amount of feedback is governed by stability
consideration. To ensure the stability condition, Gtol must always
positive.
122
2.2.2 Ciruit Implementation
2.2.1 Setup Environment
The value of component of matching network: Ls = 530 mm, Lg = 2.6 nH
The value of output matching network: L1, R1 va C1 are:
123
2.2.2 Runsimulation
124
Insert additional capacitor connected to drain and source terminal of the
cascode transistor
125
• Highline this capacitor and as set its capacitance as variable Cf
On the Anallog Design Inviroment windown, invisible PSS and PAC analyses by
doing as follows
Anallog Design Inviroment windown becomes
126
Click Variable Copy from cell view
Click tool the Parametric Analysis windown will appear. After that we modify it as follows
127
Click Analysis Start in order to run the simulation. After simulation, Plot S21, and K-factor we
can obtain results as follows
K factor
Considering the value of K factor choose value of Cf.
128
