AFE7950

SBASA41D – FEBRUARY 2021 – REVISED JUNE 2023

AFE7950 4T6R RF Sampling AFE with 12 GSPS DACs and 3 GSPS ADCs
The TX signal paths support interpolation and digital
1 Features up conversion options that deliver up to 1200 MHz
• Request full data sheet of signal bandwidth for four TX or 2400 MHz for two
• Quad RF sampling 12-GSPS transmit DACs TX. The output of the DUCs drives a 12-GSPS DAC
• Quad RF sampling 3-GSPS receive ADCs (digital to analog converter) with a mixed mode output
• Dual RF sampling 3-GSPS feedback (auxilliary option to enhance 2nd Nyquist operation. The DAC
RX) ADCs output includes a variable gain amplifier (TX DSA)
• Maximum RF signal bandwidth: with 40-dB range and 1-dB analog and 0.125-dB
– 4TX or 2FB: 1200 MHz or 2TX: 2400 MHz digital steps.
– RX): 1200 MHz (no FB), 600 MHz (with FB) Package Information
• RF frequency range:
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
– TX: 600MHz - 12GHz
AFE7950 FC-BGA 17 mm × 17 mm
– RX/FB: 600MHz -12GHz
• Digital step attenuators (DSA): (1) For more information, see Mechanical, Packaging, and
– TX: 40 dB range, 0.125-dB steps Orderable Information.
(2) The package size (length × width) is a nominal value and
– RX or FB: 25 dB range, 0.5-dB steps includes pins, where applicable.
• Single or dual-band DUC or DDCs for TX and RX
• 16x NCOs per TX or RX and FB
• Optional Internal PLL or VCO for DAC or ADC
clocks or external clock at DAC or ADC sample
rate
• SerDes data interface:
– JESD204B and JESD204C compatible
– 8 SerDes transceivers up to 29.5 Gbps
– Subclass 1 multi-device synchronization
• Package: 17-mm × 17-mm FCBGA, 0.8-mm pitch
2 Applications
• Radar
• Seeker front end
• Defense radio
• Tactical communications infrastructure
• Wireless communications test
3 Description
The AFE7950 is a high performance, wide
bandwidth multi-channel transceiver, integrating four
RF sampling transmitter chains, four RF sampling
receiver chains and two RF sampling feedback chains
(six RF sampling ADCs total). With operation up to
12 GHz, this device enables direct RF sampling in
the L, S, C and X-band frequency ranges without
the need for additional frequency conversions stages.
This improvement in density and flexibility enables
high-channel-count, multi-mission systems.
Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AFE7950
SBASA41D – FEBRUARY 2021 – REVISED JUNE 2023 www.ti.com

Table of Contents
1 Features............................................................................1 6.8 Digital Electrical Characteristics................................19
2 Applications..................................................................... 1 6.9 Power Supply Electrical Characteristics................... 20
3 Description.......................................................................1 6.10 Timing Requirements.............................................. 26
4 Description (continued).................................................. 3 6.11 Switching Characteristics........................................ 27
5 Revision History.............................................................. 3 6.12 Typical Characteristics............................................ 28
6 Specifications.................................................................. 4 7 Device and Documentation Support..........................125
6.1 Absolute Maximum Ratings........................................ 4 7.1 Receiving Notification of Documentation Updates..125
6.2 ESD Ratings............................................................... 4 7.2 Support Resources................................................. 125
6.3 Recommended Operating Conditions.........................5 7.3 Trademarks............................................................. 125
6.4 Thermal Information....................................................5 7.4 Electrostatic Discharge Caution..............................125
6.5 Transmitter Electrical Characteristics..........................6 7.5 Glossary..................................................................125
6.6 RF ADC Electrical Characteristics............................ 13 8 Mechanical, Packaging, and Orderable Information 125
6.7 PLL/VCO/Clock Electrical Characteristics................ 17

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4 Description (continued)
Each receiver chain includes a 25-dB range DSA (Digital Step Attenuator), followed by a 3-GSPS ADC (analog-
to-digital converter). Each receiver channel has an analog peak power detector and various digital power
detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for
device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200 MHz
for four RX without FB paths or 600 MHz with two FB paths (1200 MHz BW each).

5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from July 12, 2022 to June 12, 2023 (from Revision C (July 2022) to Revision D (June
2023)) Page
• Changed the Packaging Information table to include note 2.............................................................................. 1
• Changed IIH and IIL units to µA......................................................................................................................... 19
• Removed dither from conditions....................................................................................................................... 28
• Changed captions to read 1.8 GHz in 1.8 GHz section and removed dither from conditions...........................36
• Removed dither from conditions....................................................................................................................... 42
• Changed 0TX to 1TX in plot notes and removed dither from conditions and dither plot.................................. 50
• Removed dither from conditions....................................................................................................................... 55
• Changed 0TX - 3TX to 1TX - 4TX in plot legends............................................................................................ 63
• Removed TX dither plot and TX dither in conditions........................................................................................ 63
• Removed dither from conditions....................................................................................................................... 73
• Changed 0RX - 3RX to 1RX - 4RX in plot captions and notes.......................................................................100

Changes from March 9, 2022 to July 12, 2022 (from Revision B (March 2022) to Revision C
(July 2022)) Page
• Removed dither from conditions....................................................................................................................... 28
• Changed captions to read 1.8 GHz in 1.8 GHz section and removed dither from conditions...........................36
• Removed dither from conditions....................................................................................................................... 42
• Changed 0TX to 1TX in plot notes and removed dither from conditions and dither plot.................................. 50
• Removed dither from conditions....................................................................................................................... 55
• Changed 0TX - 3TX to 1TX - 4TX in plot legends............................................................................................ 63
• Removed TX dither plot and TX dither in conditions........................................................................................ 63
• Removed dither from conditions....................................................................................................................... 73
• Changed 0RX - 3RX to 1RX - 4RX in plot captions and notes.......................................................................100

Changes from Revision A (August 2021) to Revision B (March 2022) Page

• Added Feature to Request the full data sheet....................................................................................................1
• Added the Specification tables to the data sheet................................................................................................4

Changes from Revision * (February 2021) to Revision A (August 2021) Page

• Changed the data sheet status From: Advanced Information To: Production data............................................ 1

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
DVDD0P9, VDDT0P9 –0.3 1.2 V
VDD1P2RX, VDD1P2TXCLK, VDD1P2TXENC, VDD1P2PLL,
VDD1P2PLLCLKREF, VDD1P2FB, VDD1P2FBCML, –0.3 1.4 V
Supply Voltage
VDD1P2RXCML
Range
VDD1P8RX, VDD1P8RXCLK, VDD1P8TX, VDD1P8TXDAC,
VDD1P8TXENC, VDD1P8PLL, VDD1P8PLLVCO, VDD1P8FB, –0.5 2.1 V
VDD1P8FBCLK, VDD1P8GPIO, VDDA1P8
{1/2/3/4}RXIN+/- –0.5 VDDRX1P8+0.3 V
1FBIN+/-, 2FB+/- –0.5 VDDFB1P8+0.3 V
{1/2/3/4}TXOUT+/- –0.5 VDDTX1P8+0.3 V
REFCLK+/-, SYSREF+/- –0.3 1.4 V
{1:8}SRX+/- –0.3 1.4 V
Pin Volatge
Range {1:8}STX+/- –0.3 1.4 V
GPIO{B/C/D/E}x, SPICLK, SPISDIO, SPISDO, SPISEN, RESETZ, VDD1P8GPIO +
–0.5 V
BISTB0, BISTB1 0.3
VDDCLK1P8 +
IFORCE, VSENSE –0.3 V
0.3
SRDAMUX1, SRDAMUX2 –0.3 VDDA1P8+0.3 V
Peak Input
any input 20 mA
Current
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/
1000
JEDEC JS-001, all pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per ANSI/ESDA/
150
JEDEC JS-002, all pins

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
DVDD0P9, VDDT0P9 Supply voltage 0.9V 0.9 0.925 0.95 V
VDD1P2{RX/TXCLK/TXENC/FB/PLL/
Supply voltage 1.2V 1.15 1.2 1.25 V
PLLCLKREF/FBCML/RXCML}
VDD1P8{RX/RXCLK/TX/TXDAC/
TXENC/PLL/PLLVCO/FB/FBCLK/ Supply voltage 1.8V 1.75 1.8 1.85 V
GPIO}, VDDA1P8
TA Ambient temperature –40 85 °C
Operating Junction Temperature 110(1) °C
TJ
Maximum Operating Junction Temperature 125 °C

(1) Prolonged use at or above this junction temperature can increase the device failure-in-time (FIT) rate. Refer to SBAA403 application
note for additional details

6.4 Thermal Information

AFE7950
THERMAL METRIC(1) ABJ or ALK (FC-BGA) UNIT
400 PINS
RθJA Junction-to-ambient thermal resistance 16.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.42 °C/W
RθJB Junction-to-board thermal resistance 4.85 °C/W
ΨJT Junction-to-top characterization parameter 0.12 °C/W
ΨJB Junction-to-board characterization parameter 4.6 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Transmitter Electrical Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS
below 6GHz and 1474.56MSPS above 6GHz, fDAC = 11796.48MSPS; PLL clock mode below 6GHz output frequency and
External clock mode above 6GHz output frequency; interleave mode for 1st Nyquist, non-interleave mix mode for 2nd Nyquist,
nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 16.22Gbps; TX clock dither enabled,
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DACRES DAC resolution 14 bits
fDAC = 12 GSPS, 1st Nyquist 600 6000
fDAC = 12 GSPS, 2nd Nyquist 6000 12000
fDAC = 9 GSPS, 1st Nyquist 600 4500
fRFout RF output frequency range MHz
fDAC = 9 GSPS, 2nd Nyquist 4500 9000
fDAC = 6 GSPS, 1st Nyquist 600 3000
fDAC =6 GSPS, 2nd Nyquist 3000 6000
fout = 850 MHz, fDAC = 5898.24 MSPS,
4.2 dBm
-0.5dBFS
fout = 1800 MHz, fDAC = 5898.24
4.6 dBm
MSPS, -0.5dBFS
fout = 2600 MHz, fDAC = 8847.36
4.0 dBm
MSPS, -0.5dBFS
fout = 3500 MHz, -0.5dBFS 3.9 dBm
fout = 4900 MHz, -0.5dBFS 3.1 dBm
Max Full Scale Output Power, max fout = 3500 MHz, fDAC = 5898.24
Pmax_FS 1.0 dBm
gain 1 tone, at device pins MSPS, -0.5dBFS, straight mode
fout = 4900 MHz, fDAC = 5898.24
0.1 dBm
MSPS, -0.5dBFS, straight mode
fout = 4900 MHz, fDAC = 8847.36
-0.7 dBm
MSPS, -0.5dBFS, straight mode
fout = 8100 MHz, -0.1dBFS, mixed
-2.8 dBm
mode
fout = 9600 MHz, -0.1dBFS, mixed
-4.3 dBm
mode
RTERM Output termination resistor Default setting 50 Ω
ATTrange DSA Attenuation range 40 dB
DSA Analog Attenuation step 1.0 dB
ATTstep DSA Attenuation step accuracy (DNL) 0 < Atten < 40dB, before calibration ±0.2 dB
DSA Attenuation step accuracy (DNL) 0 < Atten < 40dB, after calibration ±0.1 dB
fout = 850MHz(2) ±1 deg
fout = 1800MHz(2) ±1 deg
fout =2600MHz(2) ±1
DSA Gain Steps Phase accuracy, any deg
ATTphase-err fout = 3500MHz(2) ±1
8dB range
fout = 4900MHz(2) ±1 deg
fout = 8100MHz(2) ±2 deg
fout = 9600MHz(2) ±2 deg
any 20MHz 0.1
Gflat Gain flatness dB
600MHz BW, Fout < 4.9G 1.2

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6.5 Transmitter Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS
below 6GHz and 1474.56MSPS above 6GHz, fDAC = 11796.48MSPS; PLL clock mode below 6GHz output frequency and
External clock mode above 6GHz output frequency; interleave mode for 1st Nyquist, non-interleave mix mode for 2nd Nyquist,
nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 16.22Gbps; TX clock dither enabled,
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fout = 850MHz, -7dBFS each tone -66 dBc
fout = 1800MHz, -7dBFS each tone -63 dBc
fout = 2600MHz, -7dBFS each tone -62 dBc
fout = 3500MHz, -7dBFS each tone -61 dBc
fout = 4900MHz, -7dBFS each tone -57 dBc
fout = 8100MHz, -7dBFS each tone -55 dBc

3rd Order Intermodulation distortion, 2 fout = 9600MHz, -7dBFS each tone -52 dBc
IMD3
tones at fIF±10 MHz fout = 850MHz, -13dBFS each tone -74.4 dBc
fout = 1800MHz, -13dBFS each tone -71.1 dBc
fout = 2600MHz, -13dBFS each tone -73 dBc
fout = 3500MHz, -13dBFS each tone -72 dBc
fout = 4900MHz, -13dBFS each tone -67.8 dBc
fout = 8100MHz, -13dBFS each tone -64 dBc
fout = 9600MHz, -13dBFS each tone -68 dBc
fout = 850 MHz 50.8 dBc
fout = 1800 MHz 51.9 dBc
Spurious Free Dynamic Range (within
SFDR fout = 2600 MHz 42 dBc
Nyquist zone)
fout = 3500 MHz 44 dBc
fout= 4900 MHz 46.1 dBc
fDAC = 5898.24MSPS, interleave mode -51.9 dBc
fDAC = 8847.36 MSPS, interleave
-46.0 dBc
fS/2 - fOUT Interleaving Image mode
fDAC = 11796.48MSPS, interleave
-41 dBc
mode
fout = 850 MHz -49 dBc
fout = 1800 MHz -53 dBc
fout = 2600 MHz -50 dBc
fout = 3500 MHz -48 dBc
fout= 4900 MHz -47 dBc
fout= 8100 MHz -50 dBc

2nd Harmonic Distortion (within fout= 9600 MHz -53 dBc

HD2
Nyquist zone) fout = 850 MHz, AOUT=-12dBFS -60 dBc
fout = 1800 MHz, AOUT=-12dBFS -64 dBc
fout = 2600 MHz, AOUT=-12dBFS -45 dBc
fout = 3500 MHz, AOUT=-12dBFS -57 dBc
fout= 4900 MHz, AOUT=-12dBFS -58 dBc
fout= 8100 MHz, AOUT=-12dBFS -60 dBc
fout= 9600 MHz, AOUT=-12dBFS -62 dBc

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6.5 Transmitter Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS
below 6GHz and 1474.56MSPS above 6GHz, fDAC = 11796.48MSPS; PLL clock mode below 6GHz output frequency and
External clock mode above 6GHz output frequency; interleave mode for 1st Nyquist, non-interleave mix mode for 2nd Nyquist,
nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 16.22Gbps; TX clock dither enabled,
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fout = 850 MHz -62 dBc
fout = 1800 MHz -55 dBc
fout = 2600 MHz -57 dBc
fout = 3500 MHz -60 dBc
fout= 4900 MHz -54 dBc
fout= 8100 MHz -54 dBc

3rd Harmonic Distortion (within fout= 9600 MHz -56 dBc

HD3
Nyquist zone) fout = 850 MHz, AOUT=-12dBFS -80 dBc
fout = 1800 MHz, AOUT=-12dBFS -79 dBc
fout = 2600 MHz, AOUT=-12dBFS -77 dBc
fout = 3500 MHz, AOUT=-12dBFS -77 dBc
fout= 4900 MHz, AOUT=-12dBFS -78 dBc
fout= 8100 MHz, AOUT=-12dBFS -82 dBc
fout= 9600 MHz, AOUT=-12dBFS -80 dBc
fout = 850 MHz -81 dBc
fout = 1800 MHz -88 dBc
fout = 2600 MHz -86 dBc
fout = 3500 MHz -79 dBc
fout= 4900 MHz -86 dBc
fout= 8100 MHz -87 dBc

Harmonic Distortion n >= 4 (within fout= 9600 MHz -85 dBc

HDn, n >= 4
Nyquist zone) fout = 850 MHz, AOUT=-12dBFS -93 dBc
fout = 1800 MHz, AOUT=-12dBFS -98 dBc
fout = 2600 MHz, AOUT=-12dBFS -84 dBc
fout = 3500 MHz, AOUT=-12dBFS -87 dBc
fout= 4900 MHz, AOUT=-12dBFS -87 dBc
fout= 8100 MHz, AOUT=-12dBFS -87 dBc
fout= 9600 MHz, AOUT=-12dBFS -87 dBc
fout = 850 MHz 68.5 dBc
fout = 1800 MHz 79.4 dBc
fout = 2600 MHz 77 dBc
SFDR +/- 250 Spurious Free Dynamic Range within
fout = 3500 MHz 75 dBc
MHz +/- 250 MHz
fout= 4900 MHz 76 dBc
fout= 8100 MHz 61 dBc
fout= 9600 MHz 64 dBc
fDAC = 5898.24MSPS -64 dBFS
fS/4 Fixed Spur fDAC = 8847.36MSPS -75 dBFS
fDAC = 11796.48MSPS -67 dBFS
fDAC = 5898.24MSPS -49 dBFS
fS/2 Fixed Spur fDAC = 8847.36MSPS -48 dBFS
fDAC = 11796.48 MSPS -48 dBFS

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6.5 Transmitter Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS
below 6GHz and 1474.56MSPS above 6GHz, fDAC = 11796.48MSPS; PLL clock mode below 6GHz output frequency and
External clock mode above 6GHz output frequency; interleave mode for 1st Nyquist, non-interleave mix mode for 2nd Nyquist,
nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 16.22Gbps; TX clock dither enabled,
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
2nd Nyquist, fDAC = 5898.24MSPS -76 dBFS
3*fS/4 Fixed Spur 2nd Nyquist, fDAC = 8847.36MSPS -89 dBFS
2nd Nyquist, fDAC = 11796.48MSPS -63 dBFS
Atten=0dB, Pout=-13dBFs -68.5 dBc

ACPR - 1 carrier, LTE 20MHz E-TM1.1 Atten=20dB,Pout=-13dBFs -67.2 dBc

ACPR1xcarr
carrier fout = 0.85 GHz Atten=28dB,Pout=-13dBFs -64.5 dBc
Atten=39dB, Pout=-13dBFs -53.9 dBc
Atten=0dB,Pout=-13dBFs -70.7 dBc

ACPR - 1 carrier, LTE 20MHz E-TM1.1 Atten=20dB, Pout=-13dBFs -68.3 dBc

ACPR1xcarr
carrier fout = 1.8425 GHz Atten=28dB, Pout=-13dBFs -62.9 dBc
Atten=39dB, Pout=-13dBFs -52.0 dBc
Atten=0dB, Pout=-13dBFs -71 dBc

ACPR - 1 carrier, LTE 20MHz E-TM1.1 Atten=20dB, Pout=-13dBFs -68 dBc

ACPR1xcarr
carrier fout = 2.6 GHz Atten=28dB, Pout=-13dBFs -62 dBc
Atten=39dB, Pout=-13dBFs -51.3 dBc
Atten=0dB, Pout=-13dBFs -70 dBc

ACPR - 1 carrier, LTE 20MHz E-TM1.1 Atten=20dB, Pout=-13dBFs -67 dBc

ACPR1xcarr
carrier fout = 3.5 GHz Atten=28dB, Pout=-13dBFs -60 dBc
Atten=39dB, Pout=-13dBFs -49.8 dBc
Atten=0dB, Pout=-13dBFs -68.8 dBc

ACPR - 1 carrier, LTE 20MHz E-TM1.1 Atten=20dB, Pout=-13dBFs -65.9 dBc

ACPR1xcarr
carrier fout = 4.9 GHz Atten=28dB, Pout=-13dBFs -60.6 dBc
Atten=39dB, Pout=-13dBFs -49.5 dBc
Atten=0dB, Pout=-13dBFs -65 dBc

ACPR - 1 carrier, NR 100MHz E- Atten=20dB, Pout=-13dBFs -62 dBc

ACPR1xcarr
TM1.1 carrier fout = 2.6 GHz Atten=20dB, Pout=-13dBFs -55 dBc
Atten=39dB,Pout=-13dBFs -44.3 dBc
Atten=0dB, Pout=-13dBFs -64 dBc

ACPR - 1 carrier, NR 100MHz E- Atten=20dB, Pout=-13dBFs -59 dBc

ACPR1xcarr
TM1.1 carrier fout = 3.5 GHz Atten=28dB, Pout=-13dBFs -52 dBc
Atten=39dB, Pout=-13dBFs -41.1 dBc
Atten=0dB, Pout=-13dBFs -64.1 dBc

ACPR - 1 carrier, NR 100MHz E- Atten=20dB, Pout=-13dBFs -60.4 dBc

ACPR1xcarr
TM1.1 carrier fout = 4.9 GHz Atten=28dB, Pout=-13dBFs -53.5 dBc
Atten=39dB, Pout=-13dBFs -42.5 dBc
Atten=0dB, Pout=-13dBFs -58 dBc

ACPR - 1 carrier, NR 100MHz E- Atten=20dB, Pout=-13dBFs -53 dBc

ACPR1xcarr
TM1.1 carrier fout = 8.1 GHz Atten=28dB, Pout=-13dBFs -46 dBc
Atten=39dB, Pout=-13dBFs -36 dBc

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6.5 Transmitter Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS
below 6GHz and 1474.56MSPS above 6GHz, fDAC = 11796.48MSPS; PLL clock mode below 6GHz output frequency and
External clock mode above 6GHz output frequency; interleave mode for 1st Nyquist, non-interleave mix mode for 2nd Nyquist,
nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 16.22Gbps; TX clock dither enabled,
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Atten=0dB, Pout=-13dBFs -57 dBc

ACPR - 1 carrier, NR 100MHz E- Atten=20dB, Pout=-13dBFs -50 dBc

ACPR1xcarr
TM1.1 carrier fout = 9.6 GHz Atten=28dB, Pout=-13dBFs -42 dBc
Atten=39dB, Pout=-13dBFs -31 dBc
Fout =0.85 GHz, POUT=-13dBFs 0.2 %
Fout =1.8425 GHz, POUT=-13dBFs 0.3 %
Error Vector Magnitude, 1x 20MHz E-
EVM Fout =2.6 GHz, POUT=-13dBFs 0.28 %
TM3.1/3.1a, no ref. clock noise
Fout =3.5 GHz, POUT=-13dBFs 0.38 %
Fout =4.9 GHz, POUT=-13dBFs 0.4 %
Atten=0dB, fDAC = 5898.24MSPS, dBFS/
-157.6
Pout=-13dBFs Hz
Atten=20dB, fDAC = 5898.24MSPS, dBFS/
-153.3
Noise Spectral Density 20MHz offset Pout=-13dBFs Hz
NSDdBFS
fOUT = 0.85 GHz Atten=28dB, fDAC = 5898.24MSPS, dBFS/
-147.9
Pout=-13dBFs Hz
Atten=39dB, fDAC = 5898.24MSPS, dBFS/
-136.9
Pout=-13dBFs Hz
Atten=0dB, fDAC = 5898.24MSPS, dBFS/
-158.4
Pout=-13dBFs Hz
Atten=20dB, fDAC = 5898.24MSPS, dBFS/
-152.2
Noise Spectral Density 20MHz offset Pout=-13dBFs Hz
NSDdBFS
fOUT = 1.8 GHz Atten=28dB, fDAC = 5898.24MSPS, dBFS/
-145.6
Pout=-13dBFs Hz
Atten=39dB, fDAC = 5898.24MSPS, dBFS/
-134.6
Pout=-13dBFs Hz
Atten=0dB, fDAC = 8847.36MSPS, dBFS/
-157
Pout=-13dBFs Hz
Atten=20dB, fDAC = 8847.36MSPS, dBFS/
-151
Noise Spectral Density 20MHz offset Pout=-13dBFs Hz
NSDdBFS
fOUT = 2.6 GHz Atten=28dB, fDAC = 8847.36MSPS, dBFS/
-144
Pout=-13dBFs Hz
Atten=39dB, fDAC = 8847.36MSPS, dBFS/
-133.0
Pout=-13dBFs Hz
dBFS/
Atten=0dB, Pout=-13dBFs -158
Hz
dBFS/
Atten=20dB, Pout=-13dBFs -150
Noise Spectral Density 20MHz offset Hz
NSDdBFS
Fout =3.5 GHz dBFS/
Atten=28dB, Pout=-13dBFs -143
Hz
dBFS/
Atten=39dB, Pout=-13dBFs -131.8
Hz

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6.5 Transmitter Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS
below 6GHz and 1474.56MSPS above 6GHz, fDAC = 11796.48MSPS; PLL clock mode below 6GHz output frequency and
External clock mode above 6GHz output frequency; interleave mode for 1st Nyquist, non-interleave mix mode for 2nd Nyquist,
nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 16.22Gbps; TX clock dither enabled,
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
dBFS/
Atten=0dB, Pout=-13dBFs -155.5
Hz
dBFS/
Atten=20dB, Pout=-13dBFs -147.8
Noise Spectral Density 20MHz offset Hz
NSDdBFS
Fout =4.9 GHz dBFS/
Atten=28dB, Pout=-13dBFs -140.8
Hz
dBFS/
Atten=39dB, Pout=-13dBFs -129.6
Hz
dBFS/
Atten=0dB, Pout=-13dBFs -153
Hz
dBFS/
Atten=20dB, Pout=-13dBFs -147
Noise Spectral Density 50MHz offset Hz
NSDdBFS
Fout =8.1 GHz dBFS/
Atten=28dB, Pout=-13dBFs -140
Hz
dBFS/
Atten=39dB, Pout=-13dBFs -129
Hz
dBFS/
Atten=0dB, Pout=-13dBFs -152
Hz
dBFS/
Atten=20dB, Pout=-13dBFs -147
Noise Spectral Density 50MHz offset Hz
NSDdBFS
Fout =9.6 GHz dBFS/
Atten=28dB, Pout=-13dBFs -140
Hz
dBFS/
Atten=39dB, Pout=-13dBFs -129
Hz
Output Return Loss, <6GHz, +/- fc *
with matching -17 dB
10%
S22
Output Return Loss, >8GHz, +/- fc *
with matching -10 dB
10%
fout = 900 MHz, fDAC = 8847.36MSPS,
-49 dB
straight mode
fout = 1850 MHz, fDAC =
-59 dB
8847.36MSPS, straight mode
fout = 2600 MHz, fDAC =
-65 dB
8847.36MSPS, straight mode
fout = 3500 MHz, fDAC =
-66 dB
8847.36MSPS, straight mode
fout= 4900 MHz, fDAC =
Near Channel: -60 dB
8847.36MSPS, straight mode
Isolation 1TXOUT to 2TXOUT or 3TXOUT to
4TXOUT(1) fout = 900 MHz, fDAC = 8847.36MSPS,
-90 dB
straight mode
fout = 1850 MHz, fDAC =
-91 dB
8847.36MSPS, straight mode
fout = 2600 MHz, fDAC =
-93 dB
8847.36MSPS, straight mode
fout = 3500 MHz, fDAC =
-94 dB
8847.36MSPS, straight mode
fout= 4900 MHz, fDAC =
-83 dB
8847.36MSPS, straight mode

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6.5 Transmitter Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS
below 6GHz and 1474.56MSPS above 6GHz, fDAC = 11796.48MSPS; PLL clock mode below 6GHz output frequency and
External clock mode above 6GHz output frequency; interleave mode for 1st Nyquist, non-interleave mix mode for 2nd Nyquist,
nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 16.22Gbps; TX clock dither enabled,
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fout = 9.6GHz, fOFFSET = 100Hz -88 dBc/Hz
fout = 9.6GHz, fOFFSET = 1kHz -102 dBc/Hz
fout = 9.6GHz, fOFFSET = 10kHz -110 dBc/Hz
Additive Phase Noise External Clock
PNTXADD fout = 9.6GHz, fOFFSET = 100kHz -123 dBc/Hz
Mode(3)
fout = 9.6GHz, fOFFSET = 1MHz -136 dBc/Hz
fout = 9.6GHz, fOFFSET = 10MHz -143 dBc/Hz
fout = 9.6GHz, fOFFSET = 100MHz -146 dBc/Hz

(1) Measured with differential 50 ohm across TxP/M. The DC bias to 1.8V to each TxP/M at each pin remains and is not removed. Other
external components on the TX paths are disconnected.
(2) After DSA calibration procedure
(3) Single side band, input clock phase noise subtracted.

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6.6 RF ADC Electrical Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; RX Output Rate = 491.52MSPS
below 6GHz input frequency and 1474.56MSPS above 6GHz input frequency, fADC = 2949.12MSPS; PLL clock mode with
fREF = 491.52MHz below 6GHz input frequency and External clock mode with fCLK = 11796.48MHz above 6GHz input
frequency; nominal power supplies; DSA Setting = 4dB below 6GHz and 3dB above 6GHz; SerDes rate =24.33Gbps; unless
otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADCRES ADC resolution 14 bits
FRFin RF input frequency range 600 12000 MHz
fIN = 830 MHz, DSA=0dB -2.9 dBm
fIN = 1760 MHz, DSA=0dB -2.8 dBm
fIN = 2610 MHz, DSA=0dB -1.8 dBm
Min Full scale input power, at device
PFS_CW,min fIN = 3610 MHz, DSA=0dB -0.4 dBm
pins (1)
fIN = 4910 MHz, DSA=0dB 0.1 dBm
fIN = 8150 MHz, DSA=0dB 2.1 dBm
fIN = 9610 MHz, DSA=0dB 4.3 dBm
fIN = 830 MHz, DSA = 20dB 16.7 dBm
fIN = 1760 MHz, DSA = 20dB 17.0 dBm
fIN = 2610 MHz, DSA = 20dB 18 dBm
MAX Full scale input power - reliability
PFS_CW,MAX fIN = 3610 MHz, DSA = 20dB 18.5 dBm
limited, at device pins
fIN = 4910 MHz, DSA = 20dB 19.3 dBm
fIN = 8150 MHz, DSA = 20dB 21.3 dBm
fIN = 9610 MHz, DSA = 20dB 23.5 dBm
S11 Input Return Loss with matching network -12.0 dB
ATTrange DSA Attenuation range 25.0 dB
DSA Attenuation step 0.5 dB
Delta=Gatt(X)-Gatt(X-1),
DSA Attenuation step accuracy ±0.1 dB
Fin=3610MHz, after calibration
ATTstep DSA Gain Steps Phase accuracy
Fin=3610MHz, after calibration ±0.9 deg
any 8dB range
DSA Gain Steps Phase accuracy
Fin=4910MHz, after calibration ±1.8 deg
any 8dB range
fIN = 830 MHz, DSA = 3dB(3) -155.2 dBFS/Hz
fIN = 1760 MHz, DSA = 3dB(3) -155.0 dBFS/Hz
fIN = 2610 MHz, DSA = 3dB(3) -154.4 dBFS/Hz
fIN = 3610 MHz, DSA = 3dB(3) -154.1 dBFS/Hz
fIN = 4910 MHz, DSA = 3dB(3) -155.1 dBFS/Hz
fIN = 8150 MHz, DSA = 3dB(3) -150 dBFS/Hz

Noise Density fIN = 9610 MHz, DSA = 3dB(3) -151 dBFS/Hz

NSD
(small signal) fIN = 830 MHz, 3<=Atten<=22 -156.0 dBFS/Hz
fIN = 1760 MHz, 3<=Atten<=25 -155.8 dBFS/Hz
fIN = 2610 MHz, 3<=Atten<=25 -155.7 dBFS/Hz
fIN = 3610 MHz, 3<=Atten<=25 -155.4 dBFS/Hz
fIN = 4910 MHz, 3<=Atten<=25 -155.8 dBFS/Hz
fIN = 8150 MHz, 3<=Atten<=25 -152.5 dBFS/Hz
fIN = 9610 MHz, 3<=Atten<=25 -152.5 dBFS/Hz

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6.6 RF ADC Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; RX Output Rate = 491.52MSPS
below 6GHz input frequency and 1474.56MSPS above 6GHz input frequency, fADC = 2949.12MSPS; PLL clock mode with
fREF = 491.52MHz below 6GHz input frequency and External clock mode with fCLK = 11796.48MHz above 6GHz input
frequency; nominal power supplies; DSA Setting = 4dB below 6GHz and 3dB above 6GHz; SerDes rate =24.33Gbps; unless
otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fIN = 830 MHz 19.1 dB
fIN = 1760 MHz 19.0 dB
fIN = 2610 MHz 20.9 dB
Noise Figure min
NFmin fIN = 3610 MHz 22.8 dB
DSA Atten=0 - 3dB
fIN = 4910 MHz 22.4 dB
fIN = 8150 MHz 27.3 dB
fIN = 9610 MHz 30 dB
fIN = 830 MHz(4) 20.0 dB
fIN = 1760 MHz(4) 20.6 dB
fIN = 2610 MHz(4) 21.9 dB
Noise Figure
NF fIN = 3610 MHz(4) 23.5 dB
DSA Atten=4dB
fIN = 4910 MHz(4) 22.3 dB
fIN = 8150 MHz(4) 27.9 dB
fIN = 9610 MHz(4) 30.7 dB
fIN = 830 MHz 34.7 dB
fIN = 1760 MHz 35.2 dB
fIN = 2610 MHz 36.0 dB
Noise Figure
NFmax fIN = 3610 MHz 37.3 dB
DSA Atten=20dB
fIN = 4910 MHz 37.6 dB
fIN = 8150 MHz 42.8 dB
fIN = 9610 MHz 45 dB
fIN = 840 MHz, 3<=Atten<=12 -82.4 dBc
fIN = 1770 MHz, 3<=Atten<=12 -84.1 dBc
fIN = 2610 MHz, 3<=Atten<=12 -74 dBc
3rd order intermodulation 2 tones at at fIN = 3610 MHz, 3<=Atten<=12 -77 dBc
IMD3 fIN ± 10MHz
fIN = 4920 MHz, 3<=Atten<=12 -75.9 dBc
-7dBFS each tone
fIN = 8150 MHz, 3<=Atten<=12,
-55 dBc
25MHz tone spacing
fIN = 9610 MHz, 3<=Atten<=12,
-60 dBc
25MHz tone spacing
fIN = 830 MHz 88.2 dBFS
fIN = 1760 MHz 80.6 dBFS
fIN = 2610 MHz 88 dBFS
Spurious Free Dynamic Range
SFDR within output bandwidth, AIN = -3 fIN = 3610 MHz 84 dBFS
dBFS
fIN = 4910 MHz 78.9 dBFS
fIN = 8150 MHz 78 dBFS
fIN = 9610 MHz 71 dBFS

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6.6 RF ADC Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; RX Output Rate = 491.52MSPS
below 6GHz input frequency and 1474.56MSPS above 6GHz input frequency, fADC = 2949.12MSPS; PLL clock mode with
fREF = 491.52MHz below 6GHz input frequency and External clock mode with fCLK = 11796.48MHz above 6GHz input
frequency; nominal power supplies; DSA Setting = 4dB below 6GHz and 3dB above 6GHz; SerDes rate =24.33Gbps; unless
otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fIN = 830 MHz -85.5 dBFS
fIN = 1760 MHz -90.5 dBFS
fIN = 2610 MHz -88 dBFS
2nd Harmonic Distortion
HD2 fIN = 3610 MHz -87 dBFS
AIN = -3 dBFS(2)
fIN = 4910 MHz -84.2 dBFS
fIN = 8150 MHz -70 dBFS
fIN = 9610 MHz -70 dBFS
fIN = 830 MHz -80.2 dBFS
fIN = 1760 MHz -85.3 dBFS
fIN = 2610 MHz -86 dBFS
3rd Harmonic Distortion
HD3 fIN = 3610 MHz -78 dBFS
AIN = -3 dBFS
fIN = 4910 MHz -75.4 dBFS
fIN = 8150 MHz -70 dBFS
fIN = 9610 MHz -70 dBFS
fIN = 830 MHz -88.2 dBFS
fIN = 1760 MHz -80.6 dBFS
fIN = 2610 MHz -88 dBFS
SFDR excl. HD2 and HD3
HDn, n>3 fIN = 3610 MHz -84 dBFS
AIN = -3 dBFS
fIN = 4910 MHz -81.7 dBFS
fIN = 8150 MHz -78 dBFS
fIN = 9610 MHz -78 dBFS
fIN = 830 MHz 89.2 dBFS
fIN = 1760 MHz 88.8 dBFS
fIN = 2610 MHz 95 dBFS
Spurious Free Dynamic Range
SFDR AIN = -13 dBFS fIN = 3610 MHz 90 dBFS
0<=Atten<=16
fIN = 4910 MHz 89.8 dBFS
fIN = 8150 MHz 83 dBFS
fIN = 9610 MHz 80 dBFS
fIN = 830 MHz, with board trim -79.0 dBFS
fIN = 1760 MHz, with board trim -101.6 dBFS
fIN = 2610 MHz, with board trim -100 dBFS
2nd Harmonic Distortion
HD2 AIN = -13 dBFS fIN = 3610 MHz, with board trim -101 dBFS
0<=Atten<=16
fIN = 4910 MHz, with board trim -99.1 dBFS
fIN = 8150 MHz, with board trim -107 dBFS
fIN = 9610 MHz, with board trim -107 dBFS

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6.6 RF ADC Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; RX Output Rate = 491.52MSPS
below 6GHz input frequency and 1474.56MSPS above 6GHz input frequency, fADC = 2949.12MSPS; PLL clock mode with
fREF = 491.52MHz below 6GHz input frequency and External clock mode with fCLK = 11796.48MHz above 6GHz input
frequency; nominal power supplies; DSA Setting = 4dB below 6GHz and 3dB above 6GHz; SerDes rate =24.33Gbps; unless
otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fIN = 830 MHz -95.4 dBFS
fIN = 1760 MHz -95.2 dBFS
fIN = 2610 MHz -98 dBFS
3rd Harmonic Distortion
HD3 AIN = -13 dBFS fIN = 3610 MHz -97 dBFS
0<=Atten<=16
fIN = 4910 MHz -94 dBFS
fIN = 8150 MHz -100 dBFS
fIN = 9610 MHz -102 dBFS
fIN = 830 MHz -89.2 dBFS
fIN = 1760 MHz -88.8 dBFS
fIN = 2610 MHz -95 dBFS
SFDR excl. HD2 and HD3
HDn, n>3 AIN = -13 dBFS fIN = 3610 MHz -90 dBFS
0<=Atten<=16
fIN = 4910 MHz -90 dBFS
fIN = 8150 MHz -83 dBFS
fIN = 9610 MHz -80 dBFS
fIN = 830 MHz -76.6 dBc
fIN = 1760 MHz -70.9 dBc
Near Channel: fIN = 2610 MHz -73.5 dBc
1RXIN to 2RXIN
RX-RX Isolation fIN = 3610 MHz -76.9 dBc
3RXIN to 4RXIN
fIN = 4910 MHz -65.3 dBc
fIN = 8150 MHz -64 dBc
fIN = 9610 MHz -60 dBc
fIN = 830 MHz -84.3 dBc
fIN = 1760 MHz -87.7 dBc
fIN = 2610 MHz -85 dBc
Near Channel:
TX-FB Isolation 2TXOUT to 1FBIN fIN = 3610 MHz -75 dBc
4TXOUT to 2FBIN
fIN = 4910 MHz -81.5 dBc
fIN = 8150 MHz -71 dBc
fIN = 9610 MHz -69 dBc
fIN = 830 MHz -85.9 dBc
fIN = 1760 MHz -86.9 dBc
fIN = 2610 MHz -91 dBc
Far Channel:
TX-RX Isolation 2TXOUT to 1RXIN fIN = 3610 MHz -83 dBc
4TXOUT to 3RXIN
fIN = 4910 MHz -81.9 dBc
fIN = 8150 MHz -68 dBc
fIN = 9610 MHz -68 dBc

(1) The input fullscale at minimum attenuation can be reduce by adding a digital gain range to the DSA, extending the useful range of the
DSA. The noise figure remains constant over the digital gain range.
(2) NLE correction of HD2
(3) From DSA = 3dB down to 0dB, NSD increases 1dB per DSA dB
(4) NF increase 1dB per DSA 1dB above DSA = 3dB

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6.7 PLL/VCO/Clock Electrical Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; Reference clock input frequency
491.52MHz (unless otherwise noted), fDAC = fVCO, fOUT = fDAC/4, normalized to fVCO.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCO1 min frequency 7.2 GHz
fVCO1
VCO1 max frequency 7.68 GHz
VCO2 min frequency 8.8 GHz
fVCO2
VCO2 max frequency 9.1 GHz
VCO3 min frequency 9.7 GHz
fVCO3
VCO3 max frequency 10.24 GHz
VCO4 min frequency 11.6 GHz
fVCO4
VCO4 max frequency 12.08 GHz
DIVDAC DAC sample rate divider 1, 2 or 3
DIVFBAD ADC sample rate divider from DAC 1, 2, 3, 4,
C sample rate 6 or 8
DIVRXAD 1, 2, 3, 4,
ADC sample rate divider
C 6 or 8
600kHz -113 dBc/Hz
800kHz -116 dBc/Hz

Closed Loop Phase Noise FPLL = 1MHz -119 dBc/Hz

11.79848 GHz FREF=491.52MHz 1.8MHz -125 dBc/Hz
5MHz -133 dBc/Hz
50MHz –141 dBc/Hz
600kHz -114 dBc/Hz
800kHz –118 dBc/Hz

Closed Loop Phase Noise FPLL=8.84736 1MHz –120 dBc/Hz

GHz FREF=491.52MHz 1.8MHz –127 dBc/Hz
5MHz –135 dBc/Hz
50MHz –142 dBc/Hz
PNVCO
600kHz –113 dBc/Hz
800kHz –116 dBc/Hz

Closed Loop Phase Noise FPLL= 9.8403 1MHz –119 dBc/Hz

GHz FREF=491.52MHz 1.8MHz –125 dBc/Hz
5MHz –134 dBc/Hz
50MHz –140 dBc/Hz
600kHz –116 dBc/Hz
800kHz –119 dBc/Hz

Closed Loop Phase Noise FPLL= 1MHz –122 dBc/Hz

7.86432GHz FREF=491.52MHz 1.8MHz –127 dBc/Hz
5MHz –136 dBc/Hz
50MHz –143 dBc/Hz
fPLL=11.79848 GHz, [1KHz, 100MHz] -43.4 dBc/Hz
Frms Clock PLL integrated phase error(1) fPLL=8.8536 GHz, [1KHz, 100MHz] -47.6 dBc/Hz
fPLL=9.8304 GHz, [1KHz, 100MHz] -46.2 dBc/Hz
fPFD PFD frequency 100 500 MHz
PNpll_flat Normalized PLL flat Noise fVCO = 11796.48MHz –226.5 dBc/Hz
FREF Input Clock frequency 0.1 12 GHz
VSS Input Clock level 0.6 1.8 Vppdiff

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6.7 PLL/VCO/Clock Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; Reference clock input frequency
491.52MHz (unless otherwise noted), fDAC = fVCO, fOUT = fDAC/4, normalized to fVCO.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC
Coupling Coupling
Only
Parallel resistance 100 Ω
REFCLK input impedance(2)
Parallel capacitance 0.5 pF

(1) Single Sideband, not including the reference clock contribution

(2) Refer to S11 data available from TI for impedance vs frequency

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6.8 Digital Electrical Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CML SerDes Inputs [8:1]SRX+/-
VSRDIFF SerDes Receiver Input Amplitude differential 100 1200 mVpp
VSRCOM SerDes Input Common Mode 0.4 0.5 0.6 V
SerDes Internal Differential
ZSRdiff 100 Ω
Termination(1)
Full rate mode 19 29.5 Gbps
FSerDes SerDes Bit Rate Half rate mode 9.5 16.25 Gbps
Quarter rate mode 4.75 8.125 Gbps
Insertion Loss Tolerance(2) Serdes supply = 1.8V 25 dB
TJ Total Jitter Tolerance 0.42 UI
CML SerDes Outputs [8:1]STX+/-
VSTDIFF SerDes Transmitter Output Amplitude differential 500 1000 mVpp
VSTCOM SerDes Output Common Mode 0.4 0.45 0.55 V
ZSTdiff SerDes Output Impedance 100 Ω
TRF Output rise and fall time 20-80% 8 ps
TEQS Equalization range 7 dB
TTJ Output total jitter 0.21 UI
CMOS I/O: GPIO{B/C/D/E}x, SPICLK, SPISDIO, SPISDO, SPISEN, RESETZ, BISTB0, BISTB1
0.6×VDD1
VIH High-Level Input Voltage V
P8GPIO
0.4×VDD1
VIL Low-Level Input Voltage V
P8GPIO
IIH High-Level Input Current –250 250 µA
IIL Low-Level Input Current –250 250 µA
CL CMOS input capacitance 2 pF
VDD1P8G
VOH High-Level Ouput Voltage V
PIO–0.2
VOL Low-Level Output Voltage 0.2 V
Differential Inputs: SYSREF+/- Mode A
PLL
Clock
ClockMODE
Mode
Only
FSYSREFMAX SYSREF Input Frequency Maximum 40 MHz
VSWINGSRMAX SYSREF Input Swing Maximum 1.8 Vppdiff(3)
VSWINGSRMIN SYSREF Input Swing Minimum fREF < 500MHz 0.3 Vppdiff(3)
VSWINGSRMIN SYSREF Input Swing Minimum fREF > 500MHz 0.6 Vppdiff(3)
SYSREF Input Common Mode Voltage
VCOMSRMAX 0.8 V
Maximum
SYSREF Input Common Mode Voltage
VCOMSRMIN 0.6 V
Minimum
ZT Input termination differential 100 (1) Ω
CL Input capacitance Each pin to GND 0.5 pF
LVDS Inputs: 0SYNCIN+/- and 1SYNCIN+/-
VICOM Input Common Voltage 1.2 V
VID Differential Input Voltage swing 450 Vppdiff(3)
ZT Input termination differential 100 Ω

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6.8 Digital Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVDS Outputs: 0SYNCOUT+/- and 1SYNCOUT+/-
VOCOM Output Common Voltage 1.2 V
VOD Differential Output Voltage swing 500 Vppdiff(3)
ZT Internal Termination 100 Ω

(1) SYSREF termination is programmable between 100Ω, 150Ω and 300Ω

(2) Loss tolerance is bump to bump from STX to SRX
(3) Vppdiff is the difference between the maximum differential voltage (positive value) and minimum differential voltage (negative value).

6.9 Power Supply Electrical Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS,
fDAC = 8847.36MSPS interleave mode; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation
=0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Group 3A: VDD1P8FB + VDD1P8RX +
948.2 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 533.7 mA
VDD1P8GPIO + VDDA1P8
Group 3C: VDD1P8PLL + Mode 1: 4T2F - FDD FB 100% on, no RX
TX/FB Rate: 491.52 Msps Single Band: 77.3 mA
VDD1P8PLLVCO
12x Int, FB 6x Dec fDAC = 5898.24 SPS
Group 2A: VDD1P2FB + VDD1P2RX fADC = 2949.12MSPS fTX = 1.85 GHz 299.4 mA
Group 2B: VDD1P2TXCLK + 64/66 coding, 16.22Gbps TX: 4-8-4-1, FB:
2-4-4-1 804.5 mA
IVDD1P2 VDD1P2TXENC
Group 2C: VDD1P2FBCML +
49.1 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2041.3 mA
Pdiss Power Dissipation 6027.1 mW
Group 3A: VDD1P8FB + VDD1P8RX +
820.4 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 735.2 mA
VDD1P8GPIO + VDDA1P8 Mode 2: 4T4R - TDD 1F shared with
Group 3C: VDD1P8PLL + RX TX 75%, RX 25%, FB 75% Dual
Band: 12x Int, FB 6x Dec, RX 24x 74.4 mA
VDD1P8PLLVCO
Dec TX/FB Rate 491.52 Msps RX Rate
Group 2A: VDD1P2FB + VDD1P2RX 122.88 Msps fDAC = 8847.36MSPS fADC 289.0 mA
Group 2B: VDD1P2TXCLK + = 2949.12MSPS fOUT=fIN= 1.9, 2.6 GHz
64/66 coding, 16.22Gbps TX: 8-16-4-1, 822.0 mA
IVDD1P2 VDD1P2TXENC
FB: 2-4-4-1, RX: 2-16-16-1
Group 2C: VDD1P2FBCML +
45.6 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2263.8 mA
Pdiss Power Dissipation 6359.2 mW

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6.9 Power Supply Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS,
fDAC = 8847.36MSPS interleave mode; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation
=0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Group 3A: VDD1P8FB + VDD1P8RX +
1668.6 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 965.1 mA
VDD1P8GPIO + VDDA1P8 Mode 3: 4T4R2F - FDD FB 100% on TX
Group 3C: VDD1P8PLL + Dual Band: 12x Int, FB 6x Dec RX Dual
Band: RX 24x TX/FB Rate 491.52 Msps 77.6 mA
VDD1P8PLLVCO
RX Rate 122.88 Msps fDAC = 11796.48
Group 2A: VDD1P2FB + VDD1P2RX MSPS fADC = 2949.12 MSPS fTX = 1.85 893.4 mA
Group 2B: VDD1P2TXCLK + + 2.15 GHz fRX = 1.75 + 1.88 GHz
64/66 coding, 16.22Gbps TX: 8-16-4-1, 879.5 mA
IVDD1P2 VDD1P2TXENC
FB: 2-4-4-1, RX: 2-16-16-1
Group 2C: VDD1P2FBCML +
50.7 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 3826.9 mA
Pdiss Power Dissipation 10513.0 mW
Group 3A: VDD1P8FB + VDD1P8RX +
1611.5 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 694.5 mA
VDD1P8GPIO + VDDA1P8 Mode 4: 4T4R2F - FDD FB 100% on 7.5
Group 3C: VDD1P8PLL + GSPS DAC, 2.5 GSPS ADC Single Band:
15x Int, FB 5x Dec Dual Band: RX 20x 72.8 mA
VDD1P8PLLVCO
TX/FB Rate 491.52 Msps RX Rate 122.88
Group 2A: VDD1P2FB + VDD1P2RX Msps fDAC = 7372.8 MSPS fADC = 2457.6 768.5 mA
Group 2B: VDD1P2TXCLK + MSPS fTX = 1.85 + 2.15 GHz fRX = 1.75
+ 1.88 GHz 64/66 coding, 16.22Gbps TX: 940.5 mA
IVDD1P2 VDD1P2TXENC
4-8-4-1, FB: 2-4-4-1, RX: 2-16-16-1
Group 2C: VDD1P2FBCML +
45.5 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 3000.5 mA
Pdiss Power Dissipation 9087.4 mW
Group 3A: VDD1P8FB + VDD1P8RX +
821.8 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 808.5 mA
VDD1P8GPIO + VDDA1P8 Mode 5: 4T4R - TDD 1F shared with
Group 3C: VDD1P8PLL + RX TX 75%, RX 25%, FB 75% Single
Band: 12x Int, FB 3x Dec, RX 6x Dec 77.4 mA
VDD1P8PLLVCO
TX/FB Rate = 983.04 Msps RX Rate
Group 2A: VDD1P2FB + VDD1P2RX 491.52 Msps fDAC = 11796.48 MSPS fADC 289.5 mA
Group 2B: VDD1P2TXCLK + = 2949.12 MSPS fTX = 3.5 GHz fRX
=3.5 GHz 64/66 coding, 16.22Gbps TX: 682.0 mA
IVDD1P2 VDD1P2TXENC
8-8-2-1, FB: 4-4-4-2, RX: 4-8-4-1
Group 2C: VDD1P2FBCML +
49.0 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2123.3 mA
Pdiss Power Dissipation 6209.3 mW

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6.9 Power Supply Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS,
fDAC = 8847.36MSPS interleave mode; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation
=0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Group 3A: VDD1P8FB + VDD1P8RX +
658.1 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 431.1 mA
VDD1P8GPIO + VDDA1P8
Group 3C: VDD1P8PLL + Mode 7a: TDD 4T1FB (RX iin Standby)
TX 9G and FB 3G -16bit: 368.64M; DSA 75.3 mA
VDD1P8PLLVCO
= 6dB, non-interleave mode
Group 2A: VDD1P2FB + VDD1P2RX RX 3G : 368.64M. 16 bit, Standby 189.2 mA
Group 2B: VDD1P2TXCLK + Serdes: 25gbps) -> 2 lanes for Rx/FB
(lane shared) and 2lanes for Tx 1041.1 mA
IVDD1P2 VDD1P2TXENC
Group 2C: VDD1P2FBCML +
39.0 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2208.7 mA
Pdiss Power Dissipation 5607.0 mW
Group 3A: VDD1P8FB + VDD1P8RX +
789.5 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 471.3 mA
VDD1P8GPIO + VDDA1P8
Group 3C: VDD1P8PLL + Mode 7b: TDD 4R (TX in Standby)
TX 9G and FB 3G -16bit: 368.64M; DSA 73.4 mA
VDD1P8PLLVCO
= 6dB, , non-interleave mode, Standby
Group 2A: VDD1P2FB + VDD1P2RX RX 3G : 368.64M. 16 bit 599.3 mA
Group 2B: VDD1P2TXCLK + Serdes: 25gbps) -> 2 lanes for Rx/FB
(lane shared) and 2lanes for Tx 169.6 mA
IVDD1P2 VDD1P2TXENC
Group 2C: VDD1P2FBCML +
39.1 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 1645.3 mA
Pdiss Power Dissipation 4851.9 mW
Group 3A: VDD1P8FB + VDD1P8RX +
IVDD1P8 691.0 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 441.2 mA
VDD1P8GPIO + VDDA1P8
Group 3C: VDD1P8PLL + Mode 7c: TDD 4T4R1FB
IVDD1P8 TX 9G and FB 3G -16bit: 368.64M; DSA 74.8 mA
VDD1P8PLLVCO
= 6dB, , non-interleave mode, 75% on
IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX RX 3G : 368.64M. 16 bit 25% on 291.7 mA
Group 2B: VDD1P2TXCLK + Serdes: 25gbps) -> 2 lanes for Rx/FB
IVDD1P2 (lane shared) and 2lanes for Tx 823.2 mA
VDD1P2TXENC
Group 2C: VDD1P2FBCML +
IVDD1P2 39.0 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2067.9 mA
Pdiss Power Dissipation 5418.2 mW

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6.9 Power Supply Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS,
fDAC = 8847.36MSPS interleave mode; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation
=0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Group 3A: VDD1P8FB + VDD1P8RX +
IVDD1P8 1283.8 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 752.0 mA
VDD1P8GPIO + VDDA1P8
Group 3C: VDD1P8PLL + Mode 7d: FDD 4T4R1FB
IVDD1P8 TX 9G and FB 3G -16bit: 368.64M; DSA 74.6 mA
VDD1P8PLLVCO
= 6dB, , non-interleave mode,
IVDD1P2 Group 2A: VDD1P2FB + VDD1P2RX RX 3G : 368.64M. 16 bit 750.5 mA
Group 2B: VDD1P2TXCLK + Serdes: 25gbps) -> 2 lanes for Rx/FB
IVDD1P2 (lane shared) and 2lanes for Tx 1077.6 mA
VDD1P2TXENC
Group 2C: VDD1P2FBCML +
IVDD1P2 47.7 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2695.5 mA
Pdiss Power Dissipation 8475.5 mW
Group 3A: VDD1P8FB + VDD1P8RX +
20.3 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 292.8 mA
VDD1P8GPIO + VDDA1P8
Group 3C: VDD1P8PLL +
12.6 mA
VDD1P8PLLVCO
Mode 8: same configuration as mode 7,
Group 2A: VDD1P2FB + VDD1P2RX Sleep Mode. SLEEP pin is pull high. 4.6 mA
Group 2B: VDD1P2TXCLK +
54.3 mA
IVDD1P2 VDD1P2TXENC
Group 2C: VDD1P2FBCML +
15.3 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 313.1 mA
Pdiss Power Dissipation 956.8 mW
Group 3A: VDD1P8FB + VDD1P8RX +
1593.2 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 840.6 mA
VDD1P8GPIO + VDDA1P8 Mode 9: 4T4R2F - FDD FB 100% on TX
Group 3C: VDD1P8PLL + Single Band: 24x Int, FB 12x Dec RX
Single Band: RX 24x TX/FB Rate 245.76 77.3 mA
VDD1P8PLLVCO
Msps RX Rate 122.88 Msps fDAC =
Group 2A: VDD1P2FB + VDD1P2RX 5898.24 MSPS fADC = 2949.12 MSPS fTX 905.0 mA
Group 2B: VDD1P2TXCLK + = 0.85 GHz fRX = 0.8 GHz 8/10 coding,
9.8304Gbps TX: 4-8-4-1, FB: 2-4-4-1, RX: 817.7 mA
IVDD1P2 VDD1P2TXENC
2-8-8-1
Group 2C: VDD1P2FBCML +
52.1 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2405.2 mA
Pdiss Power Dissipation 8814.3 mW

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6.9 Power Supply Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS,
fDAC = 8847.36MSPS interleave mode; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation
=0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Group 3A: VDD1P8FB + VDD1P8RX +
1626.2 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 976.4 mA
VDD1P8GPIO + VDDA1P8 Mode 10: 4T4R2F - FDD FB 100% on
Group 3C: VDD1P8PLL + TX Single Band: 18x Int, FB 6x Dec RX
Single Band: RX 12x TX/FB Rate 491.52 74.6 mA
VDD1P8PLLVCO
Msps RX Rate 245.76 Msps fDAC =
Group 2A: VDD1P2FB + VDD1P2RX 8847.36 MSPS fADC = 2949.12 MSPS fTX 902.7 mA
Group 2B: VDD1P2TXCLK + = 1.85 GHz fRX = 1.75 GHz 8/10 coding,
9.8304Gbps TX: 8-8-2-1, FB: 4-4-2-1, RX: 1111.9 mA
IVDD1P2 VDD1P2TXENC
4-8-4-1
Group 2C: VDD1P2FBCML +
48.0 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 3578.9 mA
Pdiss Power Dissipation 10515.0 mW
Group 3A: VDD1P8FB + VDD1P8RX +
800 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 840 mA
VDD1P8GPIO + VDDA1P8
Group 3C: VDD1P8PLL + Mode 11a: TDD 4T1FB (RX in Standby)
Single Band: 8x Int, FB 2x Dec, RX uses 73 mA
VDD1P8PLLVCO
FB TX/FB/RX Rate = 1474.56 Msps fDAC
Group 2A: VDD1P2FB + VDD1P2RX = 11796.48 MSPS fADC = 2949.12 MSPS 190 mA
Group 2B: VDD1P2TXCLK + fTX = fRX = 8 GHz 64/66 coding, 24.33
Gbps TX: 8-8-2-1, FB/RX: 4-4-4-2 1440 mA
IVDD1P2 VDD1P2TXENC
Group 2C: VDD1P2FBCML +
75 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 3070 mA
Pdiss Power Dissipation 8010 mW
Group 3A: VDD1P8FB + VDD1P8RX +
750 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 890 mA
VDD1P8GPIO + VDDA1P8
Group 3C: VDD1P8PLL + Mode 11b: TDD 4R (TX in Standby)
Single Band: 8x Int, FB 2x Dec, RX uses 72 mA
VDD1P8PLLVCO
FB TX/FB/RX Rate = 1474.56 Msps fDAC
Group 2A: VDD1P2FB + VDD1P2RX = 11796.48 MSPS fADC = 2949.12 MSPS 610 mA
Group 2B: VDD1P2TXCLK + fTX = fRX = 8 GHz 64/66 coding, 24.33
Gbps TX: 8-8-2-1, FB/RX: 4-4-4-2 280 mA
IVDD1P2 VDD1P2TXENC
Group 2C: VDD1P2FBCML +
72 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2360 mA
Pdiss Power Dissipation 6460 mW

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6.9 Power Supply Electrical Characteristics (continued)

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS,
fDAC = 8847.36MSPS interleave mode; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation
=0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Group 3A: VDD1P8FB + VDD1P8RX +
790 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 850 mA
VDD1P8GPIO + VDDA1P8
Mode 11c: TDD 4T4R1FB average
Group 3C: VDD1P8PLL + TX/FB: 75%, RX 25% 73 mA
VDD1P8PLLVCO Single Band: 8x Int, FB 2x Dec, RX uses
Group 2A: VDD1P2FB + VDD1P2RX FB TX/FB/RX Rate = 1474.56 Msps fDAC 300 mA
= 11796.48 MSPS fADC = 2949.12 MSPS
Group 2B: VDD1P2TXCLK + fTX = fRX = 8 GHz 64/66 coding, 24.33 1150 mA
IVDD1P2 VDD1P2TXENC Gbps TX: 8-8-2-1, FB/RX: 4-4-4-2
Group 2C: VDD1P2FBCML +
75 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 2890 mA
Pdiss Power Dissipation 7620 mW
Group 3A: VDD1P8FB + VDD1P8RX +
1260 mA
VDD1P8TX
Group 3B: VDD1P8FBCLK +
IVDD1P8 VDD1P8RXCLK + VDD1P8TXDAC+ 940 mA
VDD1P8GPIO + VDDA1P8
Group 3C: VDD1P8PLL + Mode 11d: FDD 4T4R
Single Band: 8x Int, RX uses FB 73 mA
VDD1P8PLLVCO
TX/FB/RX Rate = 1474.56 Msps fDAC =
Group 2A: VDD1P2FB + VDD1P2RX 11796.48 MSPS fADC = 2949.12 MSPS 630 mA
Group 2B: VDD1P2TXCLK + fTX = fRX = 8 GHz 64/66 coding, 24.33
Gbps TX: 8-8-2-1, FB/RX: 4-4-4-2 1480 mA
IVDD1P2 VDD1P2TXENC
Group 2C: VDD1P2FBCML +
78 mA
VDD1P2RXCML + VDD1P2PLLCLKREF
IVDD0P9 Group 1A: DVDD0P9 + VDDT0P9 4200 mA
Pdiss Power Dissipation 10640 mW

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6.10 Timing Requirements

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS,
fDAC = 8847.36MSPS; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate
= 24.33Gbps; unless otherwise noted.
MIN NOM MAX UNIT
Timing: SYSREF+/-
ts(SYSREF) Setup Time, SYSREF+/- Valid to Rising Edge of CLK+/- 50 ps
th(SYSREF) Hold Time, SYSREF+/- Valid after Rising Edge of CLK+/- 50 ps
Timing: Serial ports
ts(SENB) Setup Time, SENB to Rising Edge of SCLK 15 ns
th(SENB) Hold Time, SENB after last Rising Edge of SCLK (1) 5 + tSCLK ns
ts(SDIO) Setup Time, SDIO valid to Rising Edge of SCLK 15 ns
th(SDIO) Hold Time, SDIO valid after Rising Edge of SCLK 5 ns
t(SCLK)_W Minimum SCLK period: registers write 25 ns
t(SCLK)_R Minimum SCLK period: registers read 50 ns
Minimum Data Output delay after Falling Edge of SCLK 0 ns
td(data_out)
Maximum Data Output delay after Falling Edge of SCLK 15 ns
tRESET Minimum RESETZ Pulse Width 1 ms

(1) SDEN\\ need to be held one more extra clock cycle with the last SCLK edge

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6.11 Switching Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS,
fDAC = 8847.36MSPS; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate
= 24.33Gbps; unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TX Channel Latency
SerDes Receiver Analog Delay Full rate 2.8 ns
LMFSHd=2-8-8-1, 368.64 MSPS input
rate, 24x Interpolation, Serdes rate = 152
16.22Gbps (JESD204C)
LMFSHd=8-16-4-1, 491.52 MSPS 24x
Interpolation, Serdes rate = 16.22Gbps 176
(JESD204C) interface
tJESDTX JESD to TX output Latency clock
LMFSHd=4-16-8-1, 245.76 MSPS 48x cycles(1)
Interpolation, Serdes rate = 16.22Gbps 124
(JESD204C)
LMFSHd=2-16-16-1, 122.88 MSPS 96x
Interpolation, Serdes rate = 16.22Gbps 97
(JESD204C)
RX Channel Latency
SerDes Transmitter Analog Delay 3.6 ns
LMFS=2-16-16-1, 122.88 MSPS, 24x
Decimation, Serdes rate = 16.22Gbps 92
(JESD204C)
LMFS=4-16-8-1, 245.76 MSPS, 12x interface
tJESDRX RX input to JESD output Latency Decimation, Serdes rate = 16.22Gbps 108 clock
(JESD204C) cycles(1)
LMFS=4-8-4-1, 491.52 MSPS, 6x
Decimation, Serdes rate = 16.22Gbps 153
(JESD204C)
FB Channel Latency
SerDes Transmitter Analog Delay 3.6 ns
LMFS=1-2-8-1, 368.64 MSPS, 8x
151 interface
Decimation
tJESDFB FB input to JESD output Latency clock
LMFS=2-4-4-1, 491.52 MSPS, 6x cycles(1)
177
Decimation

(1) Interface clock cycles is the period of the digital interface sample rate, e.g. 1GSPS = 1ns.

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6.12 Typical Characteristics

6.12.1 TX Typical Characteristics 800 MHz
Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
7 6.5

6 6

5 5.5
Output Full Scale (dBm)

Output Full Scale (dBm)

4 5

3 4.5

2 4

1 fDAC=5898.24MSPS, straight mode

3.5
fDAC=5898.24MSPS, interleave mode fdac=5898.24MSPS, straight mode
0 fDAC=8847.36MSPS, straight mode 3 fdac=5898.24MSPS, interleaved mode
fDAC=8847.36MSPS, interleave mode fdac=8847.36MSPS, straight mode
-1 fDAC=11796.48MSPS, straight mode 2.5 fdac=8847.36MSPS, interleaved mode
fDAC=11796.48MSPS, interleave mode fdac=11796.48MSPS, interleaved mode
-2 2
600 750 900 1050 1200 1350 1500 -40 -15 10 35 60 85 105
Output Frequency (MHz) Temperature (Cq)
including PCB and cable losses, Aout = -0.5dFBS, DSA = 0, including PCB and cable losses, Aout = -0.5dFBS, DSA = 0,
0.8 GHz matching 0.8 GHz matching
Figure 6-1. TX Output Fullscale vs Output Frequency Figure 6-2. TX Output Fullscale vs Temperature
5 Uncalibrated Differential Gain Error (dB) 0.05
1TX
0 2TX 0.04
3TX 0.03
-5 4TX
Output Power (dBm)

0.02
-10 0.01
-15 0

-20 -0.01
-0.02
-25 1TX
-0.03 2TX
-30 -0.04 3TX
4TX
-35 -0.05
0 5 10 15 20 25 30 35 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 11796.48 MSPS, interleave mode, Aout = -0.5dFBS, fDAC=5898.24MSPS, interleave mode, matching at 0.8 GHz
matching 0.8 GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA
. Setting) + 1
Figure 6-3. TX Output Power vs DSA Setting and Channel at Figure 6-4. TX Uncalibrated Differential Gain Error vs DSA
0.85 GHz Setting and Channel at 0.85 GHz
0.05 0.35
1TX
Uncalibrated Integrated Gain Error (dB)
Calibrated Differential Gain Error (dB)

0.04 2TX 0.3

0.03 3TX
4TX
0.02 0.25

0.01
0.2
0
0.15
-0.01
-0.02 0.1
1TX
-0.03 2TX
0.05 3TX
-0.04
4TX
-0.05 0
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC=5898.24MSPS, interleave mode, matching at 0.8 GHz fDAC=5898.24MSPS, interleave mode, matching at 0.8 GHz
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA
Setting) + 1 Setting = 0) + DSA Settings
Figure 6-5. TX Calibrated Differential Gain Error vs DSA Setting Figure 6-6. TX Uncalibrated Integrated Gain Error vs DSA
and Channel at 0.85 GHz Setting and Channel at 0.85 GHz

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6.12.1 TX Typical Characteristics 800 MHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.1 0.05

Uncalibrated Differential Gain Error (dB)

1TX
Calibrated Integrated Gain Error (dB)

2TX 0.04
0.08 3TX 0.03
4TX
0.02
0.06
0.01
0.04 0
-0.01
0.02
-0.02
-0.03 -40 qC
0
-0.04 25 qC
105 qC
-0.02 -0.05
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC=5898.24MSPS, interleave mode, matching at 0.8 GHz fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz
Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA
Setting = 0) + DSA Setting Setting) + 1
Figure 6-7. TX Calibrated Integrated Gain Error vs DSA Setting Figure 6-8. TX Uncalibrated Differential Gain Error vs DSA
and Channel at 0.85 GHz Setting and Temperature at 0.85 GHz
0.03 0.5
-40 qC
Uncalibrated Integrated Gain Error (dB)
Calibrated Differential Gain Error (dB)

0.45
0.02 25 qC
0.4 105 qC
0.01 0.35
0 0.3
0.25
-0.01
0.2
-0.02 0.15

-0.03 0.1
-40 qC 0.05
-0.04 25 qC
0
105 qC
-0.05 -0.05
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA
Setting) + 1 Setting = 0) + DSA Setting
Figure 6-9. TX Calibrated Differential Gain Error vs DSA Setting Figure 6-10. TX Uncalibrated Integrated Gain Error vs DSA
and Temperature at 0.85 GHz Setting and Temperature at 0.85 GHz
0.1 0.02
Uncalibrated Differential Phase Error (deg)

-40 qC
Calibrated Integrated Gain Error (dB)

0.08 25 qC
105 qC
0.01
0.06

0.04
0
0.02

0
-0.01 1TX
2TX
-0.02 3TX
4TX
-0.04 -0.02
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz
Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Differential Phase Error = PhaseOUT(DSA Setting – 1) –
Setting = 0) + DSA Setting PhaseOUT(DSA Setting)
Figure 6-11. TX Calibrated Integrated Gain Error vs DSA Setting Figure 6-12. TX Uncalibrated Differential Phase Error vs DSA
and Temperature at 0.85 GHz Setting and Channel at 0.85 GHz

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6.12.1 TX Typical Characteristics 800 MHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.25 0.2

Uncalibrated Integrated Phase Error (deg)

Calibrated Differential Phase Error (deg)

0.2
0.15
0.15
0.1
0.05
0 0.1
-0.05
-0.1
0.05
-0.15
-0.2 1TX 3TX 1TX 3TX
2TX 4TX 2TX 4TX
-0.25 0
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz
Differential Phase Error = PhaseOUT(DSA Setting – 1) – Integrated Phase Error = PhaseOUT(DSA Setting) –
PhaseOUT(DSA Setting) PhaseOUT(DSA Setting = 0)
Phase DNL spike may occur at any DSA setting. .
Figure 6-13. TX Calibrated Differential Phase Error vs DSA Figure 6-14. TX Uncalibrated Integrated Phase Error vs DSA
Setting and Channel at 0.85 GHz Setting and Channel at 0.85 GHz
0.2 0.02
Uncalibrated Differential Phase Error (deg)
Calibrated Integrated Phase Error (deg)

0.15
0.1
0.01
0.05
0
-0.05
0
-0.1
-0.15
-0.2 -0.01
-0.25 -40qC
1TX 3TX 25qC
-0.3 105qC
2TX 4TX
-0.02
-0.35
0 4 8 12 16 20 24 28 32 36 40
0 4 8 12 16 20 24 28 32 36 40
DSA (dB)
DSA (dB)

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz
Integrated Phase Error = PhaseOUT(DSA Setting) – Differential Phase Error = PhaseOUT(DSA Setting – 1) –
PhaseOUT(DSA Setting = 0) PhaseOUT(DSA Setting) + 1

Figure 6-15. TX Calibrated Integrated Phase Error vs DSA Figure 6-16. TX Uncalibrated Differential Phase Error vs DSA
Setting and Channel at 0.85 GHz Setting and Temperature at 0.85 GHz

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6.12.1 TX Typical Characteristics 800 MHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.02 0.2

Uncalibrated Integrated Phase Error (deg)

-40qC 105qC
Calibrated Differential Phase Error (deg)

0.18
25qC
0.16
0.01
0.14
0.12
0.1
0
0.08
0.06
-0.01 0.04
-40qC 0.02
25qC
105qC 0
-0.02
-0.02
0 4 8 12 16 20 24 28 32 36 40
0 4 8 12 16 20 24 28 32 36 40
DSA (dB)
DSA (dB)
fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz, fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz
channel with the median variation over DSA setting at 25°C Integrated Phase Error = PhaseOUT(DSA Setting) –
Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting = 0)
PhaseOUT(DSA Setting) + 1 .
Figure 6-17. TX Calibrated Differential Phase Error vs DSA Figure 6-18. TX Uncalibrated Integrated Phase Error vs DSA
Setting and Temperature at 0.85 GHz Setting and Temperature at 0.85 GHz
0 -134
1TX
Calibrated Integrated Phase Error (deg)

2TX
-0.05 3TX
-139
4TX
Noise (dBFS/Hz)

-0.1
-144
-0.15
-149
-0.2

-154
-0.25
-40qC 105qC
25qC
-0.3 -159
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz,
Integrated Phase Error = PhaseOUT(DSA Setting) – POUT = –13 dBFS
PhaseOUT(DSA Setting = 0) .
Figure 6-19. TX Calibrated Integrated Phase Error vs DSA Figure 6-20. TX Output Noise vs Channel and Attenuation at
Setting and Temperature at 0.85 GHz 0.85 GHz
-65 -70
1TX -71
-70 2TX
3TX -72
4TX -73
-75
-74
IMD3 (dBc)
IMD3 (dBc)

-80 -75
-76
-85 -77
-78
-90
-79 1TX
-80 2TX
-95 3TX
-81 4TX
-100 -82
0 4 8 12 16 20 24 28 32 36 40 0 40 80 120 160 200 240 280 320 360 400
DSA (dB) Tone Spacing (MHz)

fDAC = 11796.48MSPS, interleave mode, fCENTER = 0.85 GHz, fDAC = 5898.24MSPS, straight mode, fCENTER = 0.85 GHz,
matching at 0.8 GHz, –13 dBFS each tone matching at 0.8 GHz, –13 dBFS each tone
Figure 6-21. TX IMD3 vs DSA Setting at 0.85 GHz Figure 6-22. TX IMD3 vs Tone Spacing and Channel at 0.85 GHz

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6.12.1 TX Typical Characteristics 800 MHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
-71 -71
-72 1TX -72
2TX -73
-73 3TX
4TX -74
-74
-75
-75 -76
IMD3 (dBc)

IMD3 (dBc)
-76 -77
-77 -78
-78 -79
-79 -80
-81
-80 1TX
-82
-81 2TX
-83 3TX
-82 -84 4TX
-83 -85
0 40 80 120 160 200 240 280 320 360 400 0 40 80 120 160 200 240 280 320 360 400
Tone Spacing (MHz) Tone Spacing (MHz)

fDAC = 8847.36MSPS, straight mode, fCENTER = 0.85 GHz, fDAC = 11796.48MSPS, interleave mode, fCENTER = 0.85 GHz,
matching at 0.8 GHz, –13 dBFS each tone matching at 0.8 GHz, –13 dBFS each tone
Figure 6-23. TX IMD3 vs Tone Spacing and Channel at 0.85 GHz Figure 6-24. TX IMD3 vs Tone Spacing and Channel at 0.85 GHz
-70 -73
-40qC -40qC
-71 25qC -74 25qC
-72 105qC 105qC
-75
-73
-76
IMD3 (dBc)

IMD3 (dBc)

-74
-77
-75
-78
-76
-79
-77
-78 -80

-79 -81

-80 -82
0 40 80 120 160 200 240 280 320 360 400 0 40 80 120 160 200 240 280 320 360 400
Tone Spacing (MHz) Tone Spacing (MHz)

fDAC = 5898.24MSPS, straight mode, fCENTER =0.85 GHz, fDAC = 8847.36MSPS, straight mode, fCENTER =0.85 GHz,
matching at 0.8 GHz, –13 dBFS each tone, worst channel matching at 0.8 GHz, –13 dBFS each tone, worst channel
Figure 6-25. TX IMD3 vs Tone Spacing and Temperature at 0.85 Figure 6-26. TX IMD3 vs Tone Spacing and Temperature at 0.85
GHz GHz
-72 -60
-73
-65
-74
-75 -70

-76 -75
IMD3 (dBc)

IMD3 (dBc)

-77
-80
-78
-79 -85
-80 -90 1TX
-81 -40qC 2TX
25qC -95 3TX
-82
105qC 4TX
-83 -100
0 40 80 120 160 200 240 280 320 360 400 -37 -34 -31 -28 -25 -22 -19 -16 -13 -10 -7
Tone Spacing (MHz) Pout/tone (dBFS)

fDAC = 11796.48MSPS, straight mode, fCENTER =0.85 GHz, fDAC = 5898.24MSPS, straight mode, fCENTER = 0.85 GHz,
matching at 0.8 GHz, –13 dBFS each tone, worst channel fSPACING = 20 MHz, matching at 0.8 GHz
Figure 6-27. TX IMD3 vs Tone Spacing and Temperature at 0.85 Figure 6-28. TX IMD3 vs Digital Level at 0.85 GHz
GHz

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6.12.1 TX Typical Characteristics 800 MHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
-60 -60

-65 -65

-70
-70
-75
-75
IMD3 (dBc)

IMD3 (dBc)
-80
-80
-85
-85
-90
-90 1TX 1TX
-95
2TX 2TX
-95 3TX -100 3TX
4TX 4TX
-100 -105
-37 -34 -31 -28 -25 -22 -19 -16 -13 -10 -7 -37 -34 -31 -28 -25 -22 -19 -16 -13 -10 -7
Pout/tone (dBFS) Pout/tone (dBFS)

fDAC = 8847.36MSPS, straight mode, fCENTER = 0.85 GHz, fDAC = 11796.48MSPS, interleave mode, fCENTER = 0.85 GHz,
fSPACING = 20 MHz, matching at 0.8 GHz fSPACING = 20 MHz, matching at 0.8 GHz
Figure 6-29. TX IMD3 vs Digital Level at 0.85 GHz Figure 6-30. TX IMD3 vs Digital Level at 0.85 GHz
-150
Aout=-30dBFS Aout=-6dBFS
-151 Aout=-20dBFS Aout=-1dBFS
Aout=-12dBFS
-152
Noise (dBFS/Hz)

-153

-154

-155

-156

-157

-158

-159
600 750 900 1050 1200 1350 1500
Output Frequency (MHz)

Matching at 2.6 GHz, Single tone, fDAC = 11.79648GSPS, TM1.1, POUT_RMS = –13 dBFS
interleave mode, 40-MHz offset, DSA = 0dB .

Figure 6-31. TX Single Tone Output Noise vs Frequency and Figure 6-32. TX 20-MHz LTE Output Spectrum at 0.85 GHz
Amplitude at 0.85 GHz
-52 -52
1TX 1TX
-54 2TX -54 2TX
Alternate channel ACPR (dBc)

3TX 3TX
Ajacent channel ACPR (dBc)

-56 4TX -56 4TX

-58 -58

-60 -60

-62 -62

-64 -64

-66 -66

-68 -68

-70 -70
-32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12
Pout (dBFS) Pout(dBFS)

Matching at 0.8 GHz, single carrier 20-MHz BW TM1.1 LTE Matching at 0.8 GHz, single carrier 20-MHz BW TM1.1 LTE
Figure 6-33. TX 20-MHz LTE ACPR vs Digital Level at 0.85 GHz Figure 6-34. TX 20-MHz LTE alt-ACPR vs Digital Level at 0.85
GHz

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6.12.1 TX Typical Characteristics 800 MHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
-52 -51
1TX 1TX
2TX -54 2TX
-55

Alternate channel ACPR (dBc)

3TX 3TX
Ajacent channel ACPR (dBc)

4TX 4TX
-57
-58
-60
-61
-63
-64
-66

-67 -69

-70 -72
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

Matching at 0.8 GHz, single carrier 20-MHz BW TM1.1 LTE Matching at 0.8 GHz, single carrier 20-MHz BW TM1.1 LTE
Figure 6-35. TX 20-MHz LTE ACPR vs DSA at 0.85 GHz Figure 6-36. TX 20-MHz LTE alt-ACPR vs DSA at 0.85 GHz
-55 -55
-60 -60
-65 -65
-70 -70
HD2 (dBFS/Hz)

HD2 (dBFS/Hz)

-75 -75
-80 -80
-85 -85
-90 -90
1TX, -12dBFS 3TX, -12dBFS 1TX, -12dBFS 3TX, -12dBFS
-95 1TX, -6dBFS 3TX, -6dBFS -95 1TX, -6dBFS 3TX, -6dBFS
-100 2TX, -12dBFS 4TX, -12dBFS -100 2TX, -12dBFS 4TX, -12dBFS
2TX, -6dBFS 4TX, -6dBFS 2TX, -6dBFS 4TX, -6dBFS
-105 -105
600 750 900 1050 1200 1350 1500 600 750 900 1050 1200 1350 1500
Output Frequency (MHz) Output Frequency (MHz)

Matching at 0.8 GHz, fDAC = 5898.24GSPS, straight mode Matching at 0.8 GHz, fDAC = 8847.36GSPS, straight mode
Figure 6-37. TX HD2 vs Digital Amplitude and Output Frequency Figure 6-38. TX HD2 vs Digital Amplitude and Output Frequency
at 0.85 GHz at 0.85 GHz
-55 -55
-60 1TX, -12dBFS 3TX, -12dBFS -60 1TX, -12dBFS 3TX, -12dBFS
1TX, -6dBFS 3TX, -6dBFS 1TX, -6dBFS 3TX, -6dBFS
-65 2TX, -12dBFS 4TX, -12dBFS -65 2TX, -12dBFS 4TX, -12dBFS
-70 2TX, -6dBFS 4TX, -6dBFS -70 2TX, -6dBFS 4TX, -6dBFS
-75 -75
HD3 (dBFS/Hz)

HD3 (dBFS/Hz)

-80 -80
-85 -85
-90 -90
-95 -95
-100 -100
-105 -105
-110 -110
-115 -115
600 750 900 1050 1200 1350 1500 600 750 900 1050 1200 1350 1500
Output Frequency (MHz) Output Frequency (MHz)

Matching at 0.8 GHz, fDAC = 5898.24MSPS, straight mode, Matching at 0.8 GHz, fDAC = 8847.36MSPS, straight mode,
normalized to output power at harmonic frequency normalized to output power at harmonic frequency
Figure 6-39. TX HD3 vs Digital Amplitude and Output Frequency Figure 6-40. TX HD3 vs Digital Amplitude and Output Frequency
at 0.85 GHz at 0.85 GHz

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6.12.1 TX Typical Characteristics 800 MHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0 10
-10 Tone = -6.0dBm 0 Tone = 0dBm
HD2 = -68.7dBm HD2 = -56.4dBm
-20 HD3 = -88.6dBm -10 HD3 = -73.1dBm
-30 IL2 = -75.0dBm -20 IL2 = -70.9dBm
Amplitude (dBm)

Amplitude (dBm)
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80 -80
-90 -90
-100 -100
-110 -110
0 1000 2000 3000 4000 5000 6000 0 1000 2000 3000 4000 5000 6000
Output Frequency (MHz) Output Frequency (MHz)

fDAC = 5898.24MSPS, interleave mode, 0.8 GHz matching, fDAC = 5898.24MSPS, interleave mode, 0.8 GHz matching,
includes PCB and cable losses. ILn = fS/n ± fOUT. includes PCB and cable losses. ILn = fS/n ± fOUT.
Figure 6-41. TX Single Tone (–12 dBFS) Output Spectrum at Figure 6-42. TX Single Tone (–6 dBFS) Output Spectrum at 0.85
0.85 GHz (0-fDAC) GHz (0-fDAC)
10
0 Tone = 5.0dBm
HD2 = -47.7dBm
-10 HD3 = -67.7dBm
-20 IL2 = -65.2dBm
Amplitude (dBm)

-30
-40
-50
-60
-70
-80
-90
-100
-110
0 1000 2000 3000 4000 5000 6000
Output Frequency (MHz)

fDAC = 5898.24MSPS, interleave mode, 0.8 GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT.
Figure 6-43. TX Single Tone (–1 dBFS) Output Spectrum at 0.85 GHz (0-fDAC)

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6.12.2 TX Typical Characteristics at 1.8 GHz

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
3 3.5
2.5 3
2.5
2
2
Output Full Scale (dBm)

Output Full Scale (dBm)

1.5
1.5
1 1
0.5 0.5
0 0
-0.5 -0.5
fDAC=5898.24MSPS, straight mode fdac=5898.24MSPS, straight mode
fDAC=5898.24MSPS, interleave mode -1 fdac=5898.24MSPS, interleave mode
-1
fDAC=8847.36MSPS, straight mode -1.5 fdac=8847.36MSPS, straight mode
-1.5 fDAC=8847.36MSPS, interleave mode fdac=8847.36MSPS, interleave mode
-2
fDAC=11796.48MSPS, straight mode fdac=11796.48MSPS, straight mode
-2 -2.5
fDAC=11796.48MSPS, interleave mode fdac=11796.48MSPS, interleave mode
-2.5 -3
1200 1500 1800 2100 2400 2700 -40 -15 10 35 60 85 105
Output Frequency (MHz) Temperature (Cq)

including PCB and cable losses, Aout = -0.5dFBS, DSA = 0, Aout = -0.5dFBS, matching 1.8 GHz
1.8 GHz matching .
Figure 6-44. TX Output Fullscale vs Output Frequency Figure 6-45. TX Output Power vs Temperature at 1.8 GHz
0.05 0.05
Uncalibrated Differential Gain Error (dB)

Calibrated Differential Gain Error (dB) 1TX 3TX

0.04 0.04 2TX 4TX
0.03 0.03
0.02 0.02
0.01 0.01
0 0
-0.01 -0.01
-0.02 -0.02
1TX
-0.03 2TX -0.03
-0.04 3TX -0.04
4TX
-0.05 -0.05
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC=5898.24MSPS, interleave mode, matching at 1.8 GHz fDAC=5898.24MSPS, interleave mode, matching at 1.8 GHz
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA
Setting) + 1 Setting) + 1
Figure 6-46. TX Uncalibrated Differential Gain Error vs DSA Figure 6-47. TX Calibrated Differential Gain Error vs DSA
Setting and Channel at 1.8 GHz Setting and Channel at 1.8 GHz
0.35 0.06
1TX
Uncalibrated Integrated Gain Error (dB)

Calibrated Integrated Gain Error (dB)

0.3 2TX
0.04 3TX
4TX
0.25
0.02
0.2
0
0.15
-0.02
0.1
1TX
2TX -0.04
0.05 3TX
4TX
0 -0.06
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC=5898.24MSPS, interleave mode, matching at 1.8 GHz fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Integrated Gain Error = POUT(DSA Setting) – POUT(DSA
Setting = 0) + (DSA Setting) Setting = 0) + (DSA Setting)
Figure 6-48. TX Uncalibrated Integrated Gain Error vs DSA Figure 6-49. TX Calibrated Integrated Gain Error vs DSA Setting
Setting and Channel at 1.8 GHz and Channel at 1.8 GHz

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6.12.2 TX Typical Characteristics at 1.8 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.05 0.03
Uncalibrated Differential Gain Error (dB)

Calibrated Differential Gain Error (dB)

0.04 0.02
0.03
0.01
0.02
0.01 0

0 -0.01
-0.01 -0.02
-0.02
-0.03
-0.03 -40 qC -40 qC
-0.04 25 qC -0.04 25 qC
105 qC 105 qC
-0.05 -0.05
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA
Setting) + 1 Setting) + 1
Figure 6-50. TX Uncalibrated Differential Gain Error vs DSA Figure 6-51. TX Calibrated Differential Gain Error vs DSA
Setting and Temperature at 1.8 GHz Setting and Temperature at 1.8 GHz
0.35 0.06
-40 qC -40 qC
Uncalibrated Integrated Gain Error (dB)

Calibrated Integrated Gain Error (dB)

0.3 25 qC 25 qC
105 qC 0.04 105 qC
0.25

0.2 0.02
0.15

0.1 0

0.05
-0.02
0

-0.05 -0.04
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Integrated Gain Error = POUT(DSA Setting) – POUT(DSA
Setting = 0) + (DSA Setting) Setting = 0) + (DSA Setting)
Figure 6-52. TX Uncalibrated Integrated Gain Error vs DSA Figure 6-53. TX Calibrated Integrated Gain Error vs DSA Setting
Setting and Temperature at 1.8 GHz and Temperature at 1.8 GHz
0.05 0.25
Uncalibrated Differential Phase Error (deg)

Calibrated Differential Phase Error (deg)

1TX 3TX
2TX 4TX 0.2
0.04
0.15
0.03 0.1
0.05
0.02
0
0.01
-0.05

0 -0.1
-0.15
-0.01 1TX 3TX
-0.2
2TX 4TX
-0.02 -0.25
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz
Differential Phase Error = PhaseOUT(DSA Setting – 1) – Differential Phase Error = PhaseOUT(DSA Setting – 1) –
PhaseOUT(DSA Setting) PhaseOUT(DSA Setting)
. Phase DNL spike may occur at any DSA setting.
Figure 6-54. TX Uncalibrated Differential Phase Error vs DSA Figure 6-55. TX Calibrated Differential Phase Error vs DSA
Setting and Channel at 1.8 GHz Setting and Channel at 1.8 GHz

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6.12.2 TX Typical Characteristics at 1.8 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.4 0.2
Uncalibrated Integrated Phase Error (deg)

1TX 3TX

Calibrated Integrated Phase Error (deg)

0.35 2TX 4TX 0.1

0
0.3
-0.1
0.25
-0.2
0.2
-0.3
0.15
-0.4
0.1
-0.5
0.05 -0.6 1TX 3TX
2TX 4TX
0 -0.7
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Integrated Phase Error = Phase(DSA Setting) – Phase(DSA
Setting = 0) Setting = 0)
Figure 6-56. TX Uncalibrated Integrated Phase Error vs DSA Figure 6-57. TX Calibrated Integrated Phase Error vs DSA
Setting and Channel at 1.8 GHz Setting and Channel at 1.8 GHz
0.03 0.02
Uncalibrated Differential Phase Error (deg)

Calibrated Differential Phase Error (deg)

0.02
0.01

0.01
0
0

-0.01
-0.01 -40qC -40qC
25qC 25qC
105qC 105qC
-0.02 -0.02
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz,
Differential Phase Error = PhaseOUT(DSA Setting – 1) – channel with the median variation over DSA setting at 25°C
PhaseOUT(DSA Setting) Differential Phase Error = PhaseOUT(DSA Setting – 1) –
. PhaseOUT(DSA Setting)
Figure 6-58. TX Uncalibrated Differential Phase Error vs DSA Figure 6-59. TX Calibrated Differential Phase Error vs DSA
Setting and Temperature at 1.8 GHz Setting and Temperature at 1.8 GHz

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6.12.2 TX Typical Characteristics at 1.8 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.38 0.1
Uncalibrated Integrated Phase Error (deg)

-40qC 105qC

Calibrated Integrated Phase Error (deg)

0.34 25qC 0.05
0.3
0
0.26
0.22 -0.05

0.18 -0.1
0.14 -0.15
0.1
-0.2
0.06
0.02 -0.25 -40qC 105qC
25qC
-0.02 -0.3
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz, fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz,
channel with the median variation over DSA setting at 25°C channel with the median variation over DSA setting at 25°C
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Integrated Phase Error = Phase(DSA Setting) – Phase(DSA
Setting = 0) Setting = 0)
Figure 6-60. TX Uncalibrated Integrated Phase Error vs DSA Figure 6-61. TX Calibrated Integrated Phase Error vs DSA
Setting and Temperature at 1.8 GHz Setting and Temperature at 1.8 GHz
-134 -65
1TX 1TX
2TX 2TX
3TX -70 3TX
-139
4TX 4TX
Noise (dBFS/Hz)

-75
IMD3 (dBc)

-144
-80
-149
-85

-154
-90

-159 -95
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 5898.24MSPS, interleave mode, matching at 1.8 GHz, fDAC = 11796.48MSPS, interleave mode, fCENTER = 1.8 GHz,
POUT = –13 dBFS matching at 1.8 GHz, –13 dBFS each tone
Figure 6-62. TX Output Noise vs Channel and Attenuation at 1.8 Figure 6-63. TX IMD3 vs DSA Setting at 1.8 GHz
GHz
-68 -68
-40qC
-70 25qC
-70 105qC

-72
-72
IMD3 (dBc)

IMD3 (dBc)

-74
-74
-76
-76
-78
1TX
2TX -78
-80 3TX
4TX
-82 -80
0 40 80 120 160 200 240 280 320 360 400 0 40 80 120 160 200 240 280 320 360 400
Tone Spacing (MHz) Tone Spacing (MHz)

fDAC = 11796.48MSPS, interleave mode, fCENTER = 1.8 GHz, fDAC = 11796.48MSPS, interleave mode, fCENTER = 1.8 GHz,
matching at 1.8 GHz, –13 dBFS each tone matching at 1.8 GHz, –13 dBFS each tone, worst channel
Figure 6-64. TX IMD3 vs Tone Spacing and Channel at 1.8 GHz Figure 6-65. TX IMD3 vs Tone Spacing and Temperature at 1.8
GHz

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6.12.2 TX Typical Characteristics at 1.8 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
-60 -146
Aout=-30dBFS Aout=-6dBFS
-65 Aout=-20dBFS Aout=-1dBFS
-148
Aout=-12dBFS
-70
-150

Noise (dBFS/Hz)
-75
IMD3 (dBc)

-80 -152

-85 -154
-90
-156
-95 1TX
2TX
3TX -158
-100
4TX
-105 -160
-37 -34 -31 -28 -25 -22 -19 -16 -13 -10 -7 1200 1350 1500 1650 1800 1950 2100 2250 2400 2550 2700
Pout/tone (dBFS) Output Frequency (MHz)

fDAC = 11796.48MSPS, interleave mode, fCENTER = 1.8 GHz, Matching at 2.6 GHz, Single tone, fDAC = 11.79648GSPS,
fSPACING = 20 MHz, matching at 1.8 GHz interleave mode, 40-MHz offset
Figure 6-66. TX IMD3 vs Digital Level at 1.8 GHz Figure 6-67. TX Single Tone Output Noise vs Frequency and
Amplitude at 1.8 GHz
-54
1TX
-56 2TX
3TX
Ajacent channel ACPR (dBc)

-58 4TX
-60

-62

-64

-66

-68

-70

-72
-32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12
Pout (dBFS)
TM1.1, POUT_RMS = –13 dBFS
Matching at 1.8 GHz, single carrier 20-MHz BW TM1.1 LTE
Figure 6-68. TX 20-MHz LTE Output Spectrum at 1.8425 GHz
Figure 6-69. TX 20-MHz LTE ACPR vs Digital Level at 1.8425
GHz
-55 -51
1TX 1TX
-57 2TX 2TX
-54
Alternate channel ACPR (dBc)

3TX 3TX
Ajacent channel ACPR (dBc)

-59 4TX 4TX

-57
-61

-63 -60

-65 -63
-67
-66
-69
-69
-71

-73 -72
-32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12 0 4 8 12 16 20 24 28 32 36 40
Pout(dBFS) DSA (dB)

Matching at 1.8 GHz, single carrier 20-MHz BW TM1.1 LTE Matching at 1.8 GHz, single carrier 20-MHz BW TM1.1 LTE
Figure 6-70. TX 20-MHz LTE alt-ACPR vs Digital Level at 1.8425 Figure 6-71. TX 20-MHz LTE ACPR vs DSA at 1.8 GHz
GHz

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6.12.2 TX Typical Characteristics at 1.8 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
-49 -55
1TX
-52 2TX
-65
Alternate channel ACPR (dBc)

3TX
-55 4TX
-75

HD2 (dBFS/Hz)
-58

-61 -85

-64
-95
-67 1TX, -12dBFS 3TX, -12dBFS
-105 1TX, -6dBFS 3TX, -6dBFS
-70 2TX, -12dBFS 4TX, -12dBFS
2TX, -6dBFS 4TX, -6dBFS
-73 -115
0 4 8 12 16 20 24 28 32 36 40 1200 1500 1800 2100 2400 2700
DSA (dB) Output Frequency (MHz)

Matching at 1.8 GHz, single carrier 20-MHz BW TM1.1 LTE Matching at 1.8 GHz, fDAC = 11.79648GSPS, interleave mode,
. normalized to output power at harmonic frequency
Figure 6-72. TX 20-MHz LTE alt-ACPR vs DSA at 1.8 GHz Figure 6-73. TX HD2 vs Digital Amplitude and Output Frequency
at 1.8 GHz
-65 0
-10 Tone = -8.4dBm
-75 HD2 = -85.8dBm
-20 HD3 = -86.1dBm
-85 -30 IL2 = -81.3dBm
IL3 = -72.0dBm
Amplitude (dBm)

-40
HD3 (dBFS/Hz)

-95
-50
-105 -60
-70
-115
-80
-125 1TX, -12dBFS 3TX, -12dBFS -90
1TX, -6dBFS 3TX, -6dBFS -100
-135 2TX, -12dBFS 4TX, -12dBFS
2TX, -6dBFS 4TX, -6dBFS -110
-145 0 1000 2000 3000 4000 5000 6000 7000 8000 9000
1200 1350 1500 1650 1800 1950 2100 2250 2400 2550 2700 Output Frequency (MHz)
Output Frequency (MHz)
fDAC = 8847.36MSPS, straight mode, 1.8 GHz matching,
Matching at 1.8 GHz, fDAC = 11.79648GSPS, interleave mode, includes PCB and cable losses. ILn = fS/n ± fOUT and is due to
normalized to output power at harmonic frequency mixing with digital clocks.
Figure 6-74. TX HD3 vs Digital Amplitude and Output Frequency Figure 6-75. TX Single Tone (–12 dBFS) Output Spectrum at 1.8
at 1.8 GHz GHz (0-fDAC)
0 10
-10 Tone = -2.4dBm 0 Tone = 2.6dBm
HD2 = -71.7dBm HD2 = -60.7dBm
-20 HD3 = -74.6dBm -10 HD3 = -57.7dBm
-30 IL2 = -73.9dBm -20 IL2 = -69.0dBm
IL3 = -66.0dBm IL3 = -60.8dBm
Amplitude (dBm)

Amplitude (dBm)

-30
-40
-40
-50
-50
-60
-60
-70
-70
-80 -80
-90 -90
-100 -100
-110 -110
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000
Output Frequency (MHz) Output Frequency (MHz)

fDAC = 8847.36MSPS, straight mode, 1.8 GHz matching, fDAC = 8847.36MSPS, straight mode, 1.8 GHz matching,
includes PCB and cable losses. ILn = fS/n ± fOUT and is due to includes PCB and cable losses. ILn = fS/n ± fOUT and is due to
mixing with digital clocks. mixing with digital clocks.
Figure 6-76. TX Single Tone (–6 dBFS) Output Spectrum at 1.8 Figure 6-77. TX Single Tone (–1 dBFS) Output Spectrum at 1.8
GHz (0-fDAC) GHz (0-fDAC)

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6.12.3 TX Typical Characteristics at 2.6 GHz

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
4 5
1TX
0 2TX
3
3TX
-5 4TX
Fullscale POUT (dBm)

Output Power (dBm)

2
-10

1 -15

-20
0
-25
-1 -30
straight mode
interleave mode -35
-2
2000 2200 2400 2600 2800 3000 3200 -40
Frequency (MHz)
0 5 10 15 20 25 30 35 40
Including PCB and cable losses, Aout = -0.5dBFS, DSA = 0, DSA (dB)

2.6 GHz matching fDAC = 8847.36 MSPS, Aout = -0.5dBFS, matching 2.6 GHz

Figure 6-78. TX Full Scale vs RF Frequency at 11796.48MSPS Figure 6-79. TX Output Power vs DSA Setting and Channel at
2.6 GHz
0.05 0.05
Uncalibrated Differential Gain Error (dB)

1TX 3TX
0.04 Calibrated Differential Gain Error (dB) 0.04 2TX 4TX
0.03 0.03
0.02 0.02
0.01 0.01
0 0
-0.01 -0.01
-0.02 -0.02
1TX
-0.03 2TX -0.03
-0.04 3TX -0.04
4TX
-0.05 -0.05
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC=8847.36MSPS, straight mode, matching at 2.6 GHz fDAC=8847.36MSPS, straight mode, matching at 2.6 GHz
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA
Setting) + 1 Setting) + 1
Figure 6-80. TX Uncalibrated Differential Gain Error vs DSA Figure 6-81. TX Calibrated Differential Gain Error vs DSA
Setting and Channel at 2.6 GHz Setting and Channel at 2.6 GHz
0.45 0.08
1TX
Uncalibrated Integrated Gain Error (dB)

Calibrated Integrated Gain Error (dB)

0.4 2TX
0.06 3TX
0.35 4TX
0.3 0.04

0.25
0.02
0.2

0.15 0

0.1 1TX
2TX -0.02
0.05 3TX
4TX
0 -0.04
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC=8847.36MSPS, straight mode, matching at 2.6 GHz fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Integrated Gain Error = POUT(DSA Setting) – POUT(DSA
Setting = 0) + (DSA Setting) Setting = 0) + (DSA Setting)
Figure 6-82. TX Uncalibrated Integrated Gain Error vs DSA Figure 6-83. TX Calibrated Integrated Gain Error vs DSA Setting
Setting and Channel at 2.6 GHz and Channel at 2.6 GHz

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6.12.3 TX Typical Characteristics at 2.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.05 0.03
Uncalibrated Differential Gain Error (dB)

Calibrated Differential Gain Error (dB)

0.04 0.02
0.03
0.01
0.02
0.01 0

0 -0.01
-0.01 -0.02
-0.02
-0.03
-0.03 -40 qC -40 qC
-0.04 25 qC -0.04 25 qC
105 qC 105 qC
-0.05 -0.05
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz, fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz,
channel with the median variation over DSA setting at 25°C channel with the median variation over DSA setting at 25°C
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA
Setting) + 1 Setting) + 1
Figure 6-84. TX Uncalibrated Differential Gain Error vs DSA Figure 6-85. TX Calibrated Differential Gain Error vs DSA
Setting and Temperature at 2.6 GHz Setting and Temperature at 2.6 GHz
0.4 0.08
-40 qC -40 qC
Uncalibrated Integrated Gain Error (dB)

Calibrated Integrated Gain Error (dB)

0.35 25 qC 25 qC
105 qC 0.06 105 qC
0.3

0.25 0.04

0.2
0.02
0.15

0.1 0

0.05
-0.02
0

-0.05 -0.04
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz, fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz,
channel with the median variation over DSA setting at 25°C channel with the median variation over DSA setting at 25°C
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Integrated Gain Error = POUT(DSA Setting) – POUT(DSA
Setting = 0) + (DSA Setting) Setting = 0) + (DSA Setting)
Figure 6-86. TX Uncalibrated Integrated Gain Error vs DSA Figure 6-87. TX Calibrated Integrated Gain Error vs DSA Setting
Setting and Temperature at 2.6 GHz and Temperature at 2.6 GHz

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6.12.3 TX Typical Characteristics at 2.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.08 0.3
Uncalibrated Differential Phase Error (deg)

Calibrated Differential Phase Error (deg)

1TX 3TX 0.25
0.06 2TX 4TX
0.2
0.04 0.15
0.1
0.02
0.05
0 0
-0.05
-0.02
-0.1
-0.04 -0.15
-0.2
-0.06 1TX 3TX
-0.25 2TX 4TX
-0.08 -0.3
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz
Differential Phase Error = PhaseOUT(DSA Setting – 1) – Differential Phase Error = PhaseOUT(DSA Setting – 1) –
PhaseOUT(DSA Setting) PhaseOUT(DSA Setting)
. Phase DNL spike may occur at any DSA setting.
Figure 6-88. TX Uncalibrated Differential Phase Error vs DSA Figure 6-89. TX Calibrated Differential Phase Error vs DSA
Setting and Channel at 2.6 GHz Setting and Channel at 2.6 GHz
0.2 0.2
Uncalibrated Integrated Phase Error (deg)

Calibrated Integrated Phase Error (deg)

0.15
0.15
0.1
0.1 0.05
0.05 0
-0.05
0
-0.1
-0.05 -0.15

-0.1 -0.2
-0.25
-0.15 1TX 3TX 1TX 3TX
-0.3
2TX 4TX 2TX 4TX
-0.2 -0.35
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Integrated Phase Error = Phase(DSA Setting) – Phase(DSA
Setting = 0) Setting = 0)
Figure 6-90. TX Uncalibrated Integrated Phase Error vs DSA Figure 6-91. TX Calibrated Integrated Phase Error vs DSA
Setting and Channel at 2.6 GHz Setting and Channel at 2.6 GHz

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6.12.3 TX Typical Characteristics at 2.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.04 0.04
Uncalibrated Differential Phase Error (deg)

Calibrated Differential Phase Error (deg)

0.03 0.03
0.02
0.02
0.01
0.01 0
0 -0.01

-0.01 -0.02
-0.03
-0.02
-40 Cq -0.04 -40qC
-0.03 25qC -0.05 25qC
105qC 105qC
-0.04 -0.06
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz, fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz,
channel with the median variation over DSA setting at 25°C channel with the median variation over DSA setting at 25°C
Differential Phase Error = PhaseOUT(DSA Setting – 1) – Differential Phase Error = PhaseOUT(DSA Setting – 1) –
PhaseOUT(DSA Setting) PhaseOUT(DSA Setting)
Figure 6-92. TX Uncalibrated Differential Phase Error vs DSA Figure 6-93. TX Calibrated Differential Phase Error vs DSA
Setting and Temperature at 2.6 GHz Setting and Temperature at 2.6 GHz
0.3 0.3
Uncalibrated Integrated Phase Error (deg)

-40qC -40qC
Calibrated Integrated Phase Error (deg)

0.25 0.25
25qC 25qC
0.2 105qC 0.2 105qC
0.15 0.15
0.1 0.1
0.05 0.05
0 0
-0.05 -0.05
-0.1 -0.1
-0.15 -0.15
-0.2 -0.2
-0.25 -0.25
-0.3 -0.3
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz, fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz,
channel with the medium variation over DSA setting at 25°C channel with the median variation over DSA setting at 25°C
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Integrated Phase Error = Phase(DSA Setting) – Phase(DSA
Setting = 0) Setting = 0)
Figure 6-94. TX Uncalibrated Integrated Phase Error vs DSA Figure 6-95. TX Calibrated Integrated Phase Error vs DSA
Setting and Temperature at 2.6 GHz Setting and Temperature at 2.6 GHz

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6.12.3 TX Typical Characteristics at 2.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
-132 -70
1TX
-135 2TX
3TX -75
-138 4TX
Noise (dBFS/Hz)

-141

IMD3 (dBc)
-80
-144

-147
-85
-150

-153 1TX
-90 2TX
-156 3TX
4TX
-159 -95
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 8847.36MSPS, straight mode, matching at 2.6 GHz, fDAC = 8847.36MSPS, straight mode, fCENTER = 2.6 GHz,
POUT = –13 dBFS matching at 2.6 GHz, –13 dBFS each tone
Figure 6-96. TX Output Noise vs Channel and Attenuation at 2.6 Figure 6-97. TX IMD3 vs DSA Setting at 2.6 GHz
GHz
-60 -60
1TX TA = -40qC
2TX -62 TA = 25qC
3TX -64 TA = 105qC
-65 4TX
-66
IMD3 (dBc)

IMD3 (dBc)

-68
-70 -70
-72
-74
-75
-76
-78
-80 -80
0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400
Tone Spacing (MHz) Tone Spacing (MHz)

fDAC = 8847.36MSPS, straight mode, fCENTER = 2.6 GHz, fDAC = 8847.36MSPS, straight mode, fCENTER = 2.6 GHz,
matching at 2.6 GHz, –13 dBFS each tone matching at 2.6 GHz, –13 dBFS each tone, worst channel.
Figure 6-98. TX IMD3 vs Tone Spacing and Channel at 2.6 GHz Figure 6-99. TX IMD3 vs Tone Spacing and Temperature at 2.6
GHz
-55 -65
-60
-65
-70
-70
-75
-80
IMD3 (dBc)

IMD3 (dBc)

-75
-85
-90
-95 -80
-40qC, straight mode
-100 -40qC, interleaved mode
-105 1TX 25qC, straight mode
2TX -85 25qC, interleaved mode
-110
3TX 105qC, straight mode
-115 4TX 105qC, interleaved mode
-120 -90
-40 -35 -30 -25 -20 -15 -10 -5 0 50 100 150 200 250 300 350 400
POUT/tone (dBFS) Tone Spacing (MHz)

fDAC = 8847.36MSPS, straight mode, fCENTER = 2.6 GHz, fDAC = 8847.36MSPS, straight mode, fCENTER = 2.6 GHz,
fSPACING = 20 MHz, matching at 2.6 GHz matching at 2.6 GHz, –13 dBFS each tone
Figure 6-100. TX IMD3 vs Digital Level at 2.6 GHz Figure 6-101. TX IMD3 vs Tone Spacing and Temperature

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6.12.3 TX Typical Characteristics at 2.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
-148
-149 AOUT=-30dBFS AOUT=-6dBFS
AOUT=-20dBFS AOUT=-1dBFS
-150 AOUT=-12dBFS
Output Noise (dBFS/Hz)

-151
-152
-153
-154
-155
-156
-157
-158
-159
-160
2000 2200 2400 2600 2800 3000 3200 TM1.1, POUT_RMS = –13 dBFS
Output Frequency (MHz)
.
Matching at 2.6 GHz, Single tone, fDAC = 11.79648GSPS,
.
interleave mode, 40-MHz offset
.
Figure 6-102. TX Single Tone Output Noise vs Frequency and
Figure 6-103. TX 20-MHz LTE Output Spectrum at 2.6 GHz (Band
Amplitude at 2.6 GHz
41)
-55 -55
1TX 1TX
2TX 2TX
3TX 3TX
-60 4TX -60 4TX
alt-ACPR (dBc)
ACPR (dBc)

-65 -65

-70 -70

-75 -75
-30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12
Pout (dBFS) Pout (dBFS)

Matching at 2.6 GHz, single carrier 20-MHz BW TM1.1 LTE Matching at 2.6 GHz, single carrier 20-MHz BW TM1.1 LTE
Figure 6-104. TX 20-MHz LTE ACPR vs Digital Level at 2.6 GHz Figure 6-105. TX 20-MHz LTE alt-ACPR vs Digital Level at 2.6
GHz
-51 -51
1TX 1TX
-54 2TX -54 2TX
Alternate channel ACPR (dBc)

3TX 3TX
Ajacent channel ACPR (dBc)

4TX 4TX
-57 -57

-60 -60

-63 -63

-66 -66

-69 -69

-72 -72
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

Matching at 2.6 GHz, single carrier 20-MHz BW TM1.1 LTE Matching at 2.6 GHz, single carrier 20-MHz BW TM1.1 LTE
Figure 6-106. TX 20-MHz LTE ACPR vs DSA at 2.6 GHz Figure 6-107. TX 20-MHz LTE alt-ACPR vs DSA at 2.6 GHz

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6.12.3 TX Typical Characteristics at 2.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
-51 -51
1TX 1TX
-54 2TX -54 2TX

Alternate channel ACPR (dBc)

3TX 3TX
Ajacent channel ACPR (dBc)

4TX 4TX
-57 -57

-60 -60

-63 -63

-66 -66

-69 -69

-72 -72
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

Matching at 2.6 GHz, single carrier 20-MHz BW TM1.1 LTE Matching at 2.6 GHz, single carrier 20-MHz BW TM1.1 LTE
Figure 6-108. TX 20-MHz LTE ACPR vs DSA at 2.6 GHz Figure 6-109. TX 20-MHz LTE alt-ACPR vs DSA at 2.6 GHz
-42 -43
1TX 1TX
-45 2TX -46 2TX
Alternate channel ACPR (dBc)
3TX 3TX
Ajacent channel ACPR (dBc)

-48 4TX -49 4TX

-51 -52

-54 -55

-57 -58

-60 -61

-63 -64

-66 -67
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

Matching at 2.6 GHz, single carrier 100-MHz BW TM1.1 NR Matching at 2.6 GHz, single carrier 100-MHz BW TM1.1 NR
Figure 6-110. TX 100-MHz NR ACPR vs DSA at 2.6 GHz Figure 6-111. TX 100-MHz NR alt-ACPR vs DSA at 2.6 GHz
-40 -50
1TX, -12dBFS 3TX, -12dBFS
-60 1TX, -6dBFS 3TX, -6dBFS
-50 2TX, -12dBFS 4TX, -12dBFS
2TX, -6dBFS 4TX, -6dBFS
-70
-60
HD2 (dBFS)

HD3 (dBFS)

-80
-70
-90
-80
-100
1TX, -12dBFS 3TX, -12dBFS
-90 1TX, -6dBFS 3TX, -6dBFS
2TX, -12dBFS 4TX, -12dBFS -110
2TX, -6dBFS 4TX, -6dBFS
-100 -120
1800 2000 2200 2400 2600 2800 3000 3200 1800 2000 2200 2400 2600 2800 3000 3200
FOUT (MHz) FOUT (MHz)

Matching at 2.6 GHz, fDAC = 11.79648GSPS, interleave mode, Matching at 2.6 GHz, fDAC = 11.79648GSPS, interleave mode,
normalized to output power at harmonic frequency normalized to output power at harmonic frequency
Figure 6-112. TX HD2 vs Digital Amplitude and Output Figure 6-113. TX HD3 vs Digital Amplitude and Output
Frequency at 2.6 GHz Frequency at 2.6 GHz

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6.12.3 TX Typical Characteristics at 2.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled

0 0
-10 Tone=-9.85dBm -10 Tone=-3.9dBm
HD2=-82.2dBm HD2=-66.4dBm
-20 HD3<-90dBm -20 HD3=-81.4dBm
IL2=-69.0dBm IL2=-62.7dBm
-30 IL3=-84.0dBm -30 IL3=-80.1dBm
Amplitude (dBm)

Amplitude (dBm)
-40 -40
-50 -50
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000
Frequency (MHz) Frequency (MHz)
fDAC = 8847.36MSPS, straight mode, 2.6 GHz matching, fDAC = 8847.36MSPS, straight mode, 2.6 GHz matching,
includes PCB and cable losses. ILn = fS/n ± fOUT and is due to includes PCB and cable losses. ILn = fS/n ± fOUT and is due to
mixing with digital clocks. mixing with digital clocks.
Figure 6-114. TX Single Tone (–12 dBFS) Output Spectrum at 2.6 Figure 6-115. TX Single Tone (–6 dBFS) Output Spectrum at 2.6
GHz (0-fDAC) GHz (0-fDAC)
10 70
0 Tone=+1.1dBm 71
HD2=-57.5dBm
-10 HD3=-64.0dBm 72
IL2=-57.7dBm
-20 IL3=-74.3dBm 73
Amplitude (dBm)

IMD3 (dBc)

-30 74

-40 75

-50 76

-60 77

-70 78

-80 79

-90 80
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 MIN TYP MAX
Supply Voltages
Frequency (MHz)
fDAC = 8847.36MSPS, straight mode, 2.6 GHz matching, fDAC = 11796.48MSPS, interleave mode, 2.6 GHz matching.
includes PCB and cable losses. ILn = fS/n ± fOUT and is due to 40-MHz offset from tone. Output Power = –13 dBFS. All
mixing with digital clocks. supplies simultaneously at MIN, TYP, or MAX voltages.

Figure 6-116. TX Single Tone (–1 dBFS) Output Spectrum at 2.6 Figure 6-117. TX IMD3 vs Supply Voltage at 2.6 GHz
GHz (0-fDAC)

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6.12.4 TX Typical Characteristics at 3.5 GHz

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled

5 5
fDAC=8847.36, straight mode 1TX
4 fDAC=11796.48, straight mode 0 2TX
fDAC=8847.36, interleave mode 3TX
3 -5 4TX
fDAC=11796.48, interleave mode

Output Power (dBm)

Output Power (dBm)

2 -10

1 -15

0 -20

-1 -25

-2 -30

-3 -35

-4 -40
0 5 10 15 20 25 30 35 40
-5 DSA (dB)
2800 3000 3200 3400 3600 3800 4000 4200
Fundamental Frequency (MHz) Aout = -0.5dFBS, 3.5 GHz Matching, included PCB and cable
Aout = -0.5dFBS, 3.5 GHz Matching, included PCB and cable losses
losses Figure 6-119. TX Output Power vs DSA Setting at 3.5 GHz
Figure 6-118. TX Output Power vs Frequency
0.06 0.05
Uncalibrated Differential Gain Error (dB)

1TX 3TX
Calibrated Differential Gain Error (dB)

0.04 2TX 4TX

0.04
0.03
0.02
0.02
0.01
0 0
-0.01
-0.02
-0.02
1TX
2TX -0.03
-0.04
3TX -0.04
4TX
-0.06 -0.05
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

3.5 GHz Matching, included PCB and cable losses 3.5 GHz Matching, included PCB and cable losses
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA
Setting) + 1 Setting) + 1
Figure 6-120. TX Uncalibrated Differential Gain Error vs DSA Figure 6-121. TX Calibrated Differential Gain Error vs DSA
Setting and Channel at 3.5 GHz Setting and Channel at 3.5 GHz

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6.12.4 TX Typical Characteristics at 3.5 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.5 0.04
1TX
Uncalibrated Integrated Gain Error (dB)

Calibrated Integrated Gain Error (dB)

0.45 2TX
0.4 0.02 3TX
4TX
0.35
0.3 0
0.25
0.2 -0.02
0.15
1TX
0.1 2TX -0.04
0.05 3TX
4TX
0 -0.06
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

3.5 GHz Matching, included PCB and cable losses 3.5 GHz Matching, included PCB and cable losses
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Integrated Gain Error = POUT(DSA Setting) – POUT(DSA
Setting = 0) + (DSA Setting) Setting = 0) + (DSA Setting)
Figure 6-122. TX Uncalibrated Integrated Gain Error vs DSA Figure 6-123. TX Calibrated Integrated Gain Error vs DSA
Setting and Channel at 3.5 GHz Setting and Channel at 3.5 GHz
0.08 0.3
Uncalibrated Differential Phase Error (deg)

Calibrated Differential Phase Error (deg)

1TX 3TX
2TX 4TX
0.06 0.2

0.04 0.1

0.02 0

0 -0.1

-0.02 -0.2
1TX 3TX
2TX 4TX
-0.04 -0.3
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

3.5 GHz Matching, included PCB and cable losses 3.5 GHz Matching, included PCB and cable losses
. Phase DNL spike may occur at any DSA setting.
Figure 6-124. TX Uncalibrated Differential Phase Error vs DSA Figure 6-125. TX Calibrated Differential Phase Error vs DSA
Setting and Channel at 3.5 GHz Setting and Channel at 3.5 GHz
0.6 0.2
Uncalibrated Integrated Phase Error (deg)

Calibrated Integrated Phase Error (deg)

0.5 0.1

0
0.4
-0.1
0.3
-0.2
0.2
-0.3

0.1 -0.4
1TX 3TX 1TX 3TX
2TX 4TX 2TX 4TX
0 -0.5
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

3.5 GHz Matching, included PCB and cable losses 3.5 GHz Matching, included PCB and cable losses
Figure 6-126. TX Uncalibrated Integrated Phase Error vs DSA Figure 6-127. TX Calibrated Integrated Phase Error vs DSA
Setting and Channel at 3.5 GHz Setting and Channel at 3.5 GHz

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6.12.4 TX Typical Characteristics at 3.5 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.05 0.03
Uncalibrated Differential Gain Error (dB)

Calibrated Differential Gain Error (dB)

0.04 0.02
0.03
0.01
0.02
0.01 0

0 -0.01
-0.01 -0.02
-0.02
-0.03
-0.03 -40 qC -40 qC
-0.04 25 qC -0.04 25 qC
105 qC 105 qC
-0.05 -0.05
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

3.5 GHz Matching, 1TX 3.5 GHz Matching, 1TX, Calibrated at 25°C
Figure 6-128. TX Uncalibrated Differential Gain Error vs DSA Figure 6-129. TX Calibrated Differential Gain Error vs DSA
Setting and Temperature at 3.5 GHz Setting and Temperature at 3.5 GHz
0.5 0.02
-40 qC
Uncalibrated Integrated Gain Error (dB)

0.45 Calibrated Integrated Gain Error (dB)

25 qC
0.4 105 qC
0.35 0

0.3
0.25
-0.02
0.2
0.15
0.1 -0.04
0.05 -40 qC
25 qC
0
105 qC
-0.05 -0.06
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

3.5 GHz Matching, 1TX 3.5 GHz Matching, 1TX, Calibrated at 25°C
Figure 6-130. TX Uncalibrated Integrated Gain Error vs DSA Figure 6-131. TX Calibrated Integrated Gain Error vs DSA
Setting and Temperature at 3.5 GHz Setting and Temperature at 3.5 GHz
0.08 0.06
Uncalibrated Differential Phase Error (deg)

-40qC
Calibrated Differential Phase Error (deg)

0.06 25qC 0.03

105qC
0
0.04
-0.03
0.02
-0.06
0
-0.09
-0.02
-0.12
-40qC
-0.04 -0.15 25qC
105qC
-0.06 -0.18
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

3.5 GHz Matching, 1TX 3.5 GHz Matching, 1TX, Calibrated at 25°C
Differential Phase Error = PhaseOUT(DSA Setting – 1) – Differential Phase Error = PhaseOUT(DSA Setting – 1) –
PhaseOUT(DSA Setting) PhaseOUT(DSA Setting)
Figure 6-132. TX Uncalibrated Differential Phase Error vs DSA Figure 6-133. TX Calibrated Differential Phase Error vs DSA
setting and Temperature at 3.5 GHz Setting and Temperature at 3.5 GHz

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6.12.4 TX Typical Characteristics at 3.5 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.6 0.1
Uncalibrated Integrated Phase Error (deg)

-40qC -40qC

Calibrated Integrated Phase Error (deg)

0.55
25qC 0.05 25qC
0.5 105qC 105qC
0.45 0
0.4
-0.05
0.35
0.3 -0.1
0.25
-0.15
0.2
0.15 -0.2
0.1
-0.25
0.05
0 -0.3
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

3.5 GHz Matching, 1TX 3.5 GHz Matching, 1TX, Calibrated at 25°C
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Integrated Phase Error = Phase(DSA Setting) – Phase(DSA
Setting=0) Setting = 0)
Figure 6-134. TX Uncalibrated Integrated Phase Error vs DSA Figure 6-135. TX Calibrated Integrated Phase Error vs DSA
Setting and Temperature at 3.5 GHz Setting and Temperature at 3.5 GHz
-130 -66
1TX
2TX
-135 3TX -69
4TX
Noise (dBFS/Hz)

-140 -72
IMD3 (dBc)

-145 -75

-150 -78
1TX
-155 -81 2TX
3TX
4TX
-160 -84
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC=11796.48MSPS, interleave mode, matching at 3.5GHz, 20-MHz tone spacing, 3.5 GHz Matching, –13 dBFS each
Aout = –13 dBFS. tone, included PCB and cable losses
Figure 6-136. TX NSD vs DSA Setting at 3.5 GHz Figure 6-137. TX IMD3 vs DSA Setting at 3.5 GHz
-50
-55
-60
-65
IMD3 (dBc)

-70
-75
-80
-85
1TX
-90 2TX
-95 3TX
4TX
-100
-40 -35 -30 -25 -20 -15 -10 -5
POUT/tone (dBFS)

20-MHz tone spacing, 3.5 GHz Matching

.
3.5 GHz Matching, single carrier 20-MHz BW TM1.1 LTE
Figure 6-138. TX IMD3 vs Digital Amplitude and Channel at 3.5
GHz Figure 6-139. TX 20-MHz LTE Output Spectrum at 3.5 GHz (Band
42)

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6.12.4 TX Typical Characteristics at 3.5 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
-48 -49
1TX 1TX
-51 2TX -52 2TX

Alternate channel ACPR (dBc)

3TX 3TX
Ajacent channel ACPR (dBc)

-54 4TX -55 4TX

-57 -58

-60 -61

-63 -64

-66 -67

-69 -70

-72 -73
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

3.5 GHz Matching, single carrier 20-MHz BW TM1.1 LTE 3.5 GHz Matching, single carrier 20-MHz BW TM1.1 LTE
Figure 6-140. TX 20-MHz LTE ACPR vs DSA Setting at 3.5 GHz Figure 6-141. TX 20-MHz LTE alt-ACPR vs DSA Setting at 3.5
GHz
-55 -55
1TX 1TX
2TX 2TX
Alternate Channel ACPR (dBc)
3TX 3TX
-60 4TX -60 4TX
ACPR (dBc)

-65 -65

-70 -70

-75 -75
-32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12 -32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12
POUT (dBFS) POUT (dBFS)

3.5 GHz Matching, single carrier 20-MHz BW TM1.1 LTE 3.5 GHz Matching, single carrier 20-MHz BW TM1.1 LTE
Figure 6-142. TX 20-MHz LTE ACPR vs Digital Level at 3.5 GHz Figure 6-143. TX 20-MHz LTE alt-ACPR vs Digital Level at 3.5
GHz
-30 -60
1TX, -12dBFS 3TX, -12dBFS
-40 1TX, -6dBFS 3TX, -6dBFS
2TX, -12dBFS 4TX, -12dBFS -70
2TX, -6dBFS 4TX, -6dBFS
-50
-80
HD2 (dBFS)

HD3 (dBFS)

-60
-90
-70
-100
-80
1TX, -12dBFS 3TX, -12dBFS
-110 1TX, -6dBFS 3TX, -6dBFS
-90 2TX, -12dBFS 4TX, -12dBFS
2TX, -6dBFS 4TX, -6dBFS
-100 -120
2800 3000 3200 3400 3600 3800 4000 4200 2800 3000 3200 3400 3600 3800 4000 4200
FOUT (MHz) FOUT (MHz)

Matching at 3.5 GHz, fDAC = 11.79648GSPS, interleave mode, Matching at 3.5 GHz, fDAC = 11.79648GSPS, interleave mode,
normalized to output power at harmonic frequency normalized to output power at harmonic frequency. Dip is due
. to HD3 falling near DC.
Figure 6-144. TX Single Tone HD2 vs Frequency and Digital Figure 6-145. TX Single Tone HD3 vs Frequency and Digital
Level at 3.5 GHz Level at 3.5 GHz

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6.12.4 TX Typical Characteristics at 3.5 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
10 0
0 Tone=0dBm -10 Tone=-4.9dBm
HD2=-52dBm HD2=-63dBm
-10 HD3=-53dBm HD3=-71dBm
-20
-20 IL2=-44dBm IL2=-49dBm
IL3=-85dBm -30 fs/2=-43.6dBm
Amplitude (dBm)

Amplitude (dBm)
-30
Fs/2=-44dBm
-40 -40
-50 -50
-60 -60
-70
-70
-80
-80
-90
-100 -90
-110 -100
0 2000 4000 6000 8000 10000 12000 0 2000 4000 6000 8000 10000 12000
Frequency (MHz) D095
Frequency (MHz) D096

Matching at 3.5 GHz, fDAC = 11.79648GSPS, interleave mode. Matching at 3.5 GHz, fDAC = 11.79648GSPS, interleave mode.
Figure 6-146. TX Single Tone (–1 dBFS) Output Spectrum at 3.5 Figure 6-147. TX Single Tone (–6 dBFS) Output Spectrum at 3.5
GHz (0 - fDAC) GHz (0-fDAC)
0
-10 Tone=-10.9dBm
HD2=-76dBm
-20 HD3=-83dBm
IL2=-54dBm
-30 fs/2=-44dBm
Amplitude (dBm)

-40
-50
-60
-70
-80
-90
-100
0 2000 4000 6000 8000 10000 12000
Frequency (MHz) D098

Matching at 3.5 GHz, fDAC = 11.79648GSPS, interleave mode.

Figure 6-148. TX Single Tone (–12 dBFS) Output Spectrum at 3.5 GHz (0-fDAC)

6.12.5 TX Typical Characteristics at 4.9 GHz

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
2.4 0
2.2 1TX 1TX
2TX -0.2 2TX
2 3TX 3TX
-0.4
4TX 4TX
Output Full Scale (dBm)

Output Full Scale (dBm)

1.8
-0.6
1.6
1.4 -0.8
1.2 -1
1 -1.2
0.8
-1.4
0.6
-1.6
0.4
0.2 -1.8
0 -2
4300 4500 4700 4900 5100 5300 5500 4300 4500 4700 4900 5100 5300 5500
Output Frequency (MHz) Output Frequency (MHz)

Excluding PCB and cable losses, Aout = -0.5dFBS, DSA = 0, Excluding PCB and cable losses, Aout = -0.5dFBS, DSA = 0,
4.9 GHz matching 4.9 GHz matching
Figure 6-149. TX Full Scale vs RF Frequency and Channel at Figure 6-150. TX Full Scale vs RF Frequency and Channel at
11796.48MSPS 5898.24MSPS, Straight Mode, 2nd Nyquist Zone

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6.12.5 TX Typical Characteristics at 4.9 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
2 0.05

Uncalibrated Differential Gain Error (dB)

1TX 0.04
1.6 2TX
3TX 0.03
1.2
4TX
Output Full Scale (dBm)

0.02
0.8
0.01
0.4
0
0 -0.01
-0.4 -0.02
1TX
-0.8 -0.03 2TX
-0.04 3TX
-1.2
4TX
-1.6 -0.05
0 4 8 12 16 20 24 28 32 36 40
-2 DSA (dB)
-45 -20 5 30 55 80 105
Temperature (Cq)
fDAC=11796.48MSPS, interleave mode, matching at 4.9 GHz
fDAC = 11796.48 MSPS, Aout = -0.5dFBS, matching 4.9 GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA
. Setting) + 1

Figure 6-151. TX Output Power vs DSA Setting and Channel at Figure 6-152. TX Uncalibrated Differential Gain Error vs DSA
4.9 GHz Setting and Channel at 4.9 GHz

0.05 0.5
1TX
Uncalibrated Integrated Gain Error (dB)
Calibrated Differential Gain Error (dB)

0.04 2TX 0.45

0.03 3TX 0.4
4TX
0.02 0.35
0.01 0.3
0 0.25
-0.01 0.2
-0.02 0.15
1TX
-0.03 0.1 2TX
-0.04 0.05 3TX
4TX
-0.05 0
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC=11796.48MSPS, interleave mode, matching at 4.9 GHz fDAC=11796.48MSPS, interleave mode, matching at 4.9 GHz
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Integrated Gain Error = POUT(DSA Setting) – POUT(DSA
Setting) + 1 Setting = 0) + (DSA Setting)
Figure 6-153. TX Calibrated Differential Gain Error vs DSA Figure 6-154. TX Uncalibrated Integrated Gain Error vs DSA
Setting and Channel at 4.9 GHz Setting and Channel at 4.9 GHz

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6.12.5 TX Typical Characteristics at 4.9 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.06 0.05
1TX

Uncalibrated Differential Gain Error (dB)

Calibrated Integrated Gain Error (dB)

0.04 2TX 0.04

3TX 0.03
0.02 4TX
0.02
0 0.01
-0.02 0

-0.04 -0.01
-0.02
-0.06
-0.03 -40 qC
-0.08 -0.04 25 qC
105 qC
-0.1 -0.05
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 11796.48MSPS, interleave mode, matching at 4.9 GHz fDAC = 11796.48MSPS, interleaved mode, matching at 4.9
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA GHz
Setting = 0) + (DSA Setting) Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA
. Setting) + 1
Figure 6-155. TX Calibrated Integrated Gain Error vs DSA Figure 6-156. TX Uncalibrated Differential Gain Error vs DSA
Setting and Channel at 4.9 GHz Setting and Temperature at 4.9 GHz
0.03 0.5
-40 qC
Uncalibrated Integrated Gain Error (dB)

0.45
Calibrated Differential Gain Error (dB)

0.02 25 qC
0.4 105 qC
0.01 0.35
0.3
0
0.25
-0.01 0.2

-0.02 0.15
0.1
-0.03
q 0.05
-40 C
-0.04 25 qC 0
105 qC -0.05
-0.05 0 4 8 12 16 20 24 28 32 36 40
0 4 8 12 16 20 24 28 32 36 40 DSA (dB)
DSA (dB)
fDAC = 11796.48MSPS, interleaved mode, matching at 4.9
fDAC = 11796.48MSPS, interleaved mode, matching at 4.9
GHz
GHz
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA
Setting = 0) + (DSA Setting)
Setting) + 1
Figure 6-158. TX Uncalibrated Integrated Gain Error vs DSA
Figure 6-157. TX Calibrated Differential Gain Error vs DSA
Setting and Temperature at 4.9 GHz
Setting and Temperature at 4.9 GHz

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6.12.5 TX Typical Characteristics at 4.9 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.04 0.08

Uncalibrated Differential Phase Error (deg)

-40 qC
Calibrated Integrated Gain Error (dB)

25 qC 0.06
0.02 105 qC
0.04

0 0.02

0
-0.02
-0.02

-0.04 -0.04

-0.06 1TX
-0.06 2TX
-0.08 3TX
4TX
-0.08 -0.1
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9 fDAC = 11796.48MSPS, interleaved mode, matching at 4.9
GHz GHz
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Differential Phase Error = PhaseOUT(DSA Setting – 1) –
Setting = 0) + (DSA Setting) PhaseOUT(DSA Setting)

Figure 6-159. TX Calibrated Integrated Gain Error vs DSA Figure 6-160. TX Uncalibrated Differential Phase Error vs DSA
Setting and Temperature at 4.9 GHz Setting and Channel at 4.9 GHz
0.25 0.8
Uncalibrated Integrated Phase Error (deg)
Calibrated Differential Phase Error (deg)

0.2 0.7
0.15
0.6
0.1
0.05 0.5

0 0.4
-0.05 0.3
-0.1
0.2
-0.15
-0.2 1TX 3TX 0.1 1TX 3TX
2TX 4TX 2TX 4TX
-0.25 0
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9 fDAC = 11796.48MSPS, interleaved mode, matching at 4.9
GHz GHz
Differential Phase Error = PhaseOUT(DSA Setting – 1) – Integrated Phase Error = Phase(DSA Setting) – Phase(DSA
PhaseOUT(DSA Setting) Setting = 0)
Phase DNL spike may occur at any DSA setting. .
Figure 6-161. TX Calibrated Differential Phase Error vs DSA Figure 6-162. TX Uncalibrated Integrated Phase Error vs DSA
Setting and Channel at 4.9 GHz Setting and Channel at 4.9 GHz

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6.12.5 TX Typical Characteristics at 4.9 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.25 0.08

Uncalibrated Differential Phase Error (deg)

Calibrated Integrated Phase Error (deg)

0.2
0.06
0.15
0.04
0.1
0.05 0.02
0
0
-0.05
-0.02
-0.1
-0.15 -0.04
-0.2
-0.06
-0.25 -40qC
1TX 3TX -0.08 25qC
-0.3 2TX 4TX 105qC
-0.35 -0.1
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9 fDAC = 11796.48MSPS, interleaved mode, matching at 4.9
GHz GHz
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Differential Phase Error = PhaseOUT(DSA Setting – 1) –
Setting = 0) PhaseOUT(DSA Setting)
Figure 6-163. TX Calibrated Integrated Phase Error vs DSA Figure 6-164. TX Uncalibrated Differential Phase Error vs DSA
Setting and Channel at 4.9 GHz Setting and Temperature at 4.9 GHz
0.1 Uncalibrated Integrated Phase Error (deg) 0.8
Calibrated Differential Phase Error (deg)

0.08 0.7
0.06
0.6
0.04
0.02 0.5

0 0.4
-0.02 0.3
-0.04
0.2
-0.06 -40qC
-0.08 25qC 0.1 -40qC 105qC
105qC 25qC
-0.1 0
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9 fDAC = 11796.48MSPS, interleaved mode, matching at 4.9
GHz GHz
Differential Phase Error = PhaseOUT(DSA Setting – 1) – Integrated Phase Error = Phase(DSA Setting) – Phase(DSA
PhaseOUT(DSA Setting) Setting = 0)
Figure 6-165. TX Calibrated Differential Phase Error vs DSA Figure 6-166. TX Uncalibrated Integrated Phase Error vs DSA
Setting and Temperature at 4.9 GHz Setting and Temperature at 4.9 GHz

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6.12.5 TX Typical Characteristics at 4.9 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
0.2 -128
-40qC 105qC 1TX
Calibrated Integrated Phase Error (deg)

25qC 2TX
0.1 -133 3TX
4TX

Noise (dBFS/Hz)
0 -138

-0.1 -143

-0.2 -148

-0.3 -153

-158
-0.4
0 4 8 12 16 20 24 28 32 36 40
0 4 8 12 16 20 24 28 32 36 40
DSA (dB)
DSA (dB)

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9 fDAC = 11796.48MSPS, interleaved mode, matching at 4.9
GHz, channel with the median variation over DSA setting at GHz, POUT = –13 dBFS
25°C .
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA .
Setting = 0) .

Figure 6-167. TX Calibrated Integrated Phase Error vs DSA Figure 6-168. TX Output Noise vs Channel and Attenuation at
Setting and Temperature at 4.9 GHz 2.6 GHz

-65 -64
1TX 1TX
2TX 2TX
-70 3TX -65 3TX
4TX 4TX
-75 -66
IMD3 (dBc)

IMD3 (dBc)

-80 -67

-85 -68

-90 -69

-95 -70
0 4 8 12 16 20 24 28 32 36 40 0 40 80 120 160 200 240 280 320 360 400
DSA (dB) Tone Spacing (MHz)

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9 fDAC = 11796.48MSPS, interleaved mode, matching at 4.9
GHz, fCENTER = 4.9GHz, -13 dBFS each tone GHz, fCENTER = 4.9GHz, –13 dBFS each tone
Figure 6-169. TX IMD3 vs DSA Setting at 4.9 GHz Figure 6-170. TX IMD3 vs Tone Spacing and Channel at 4.9 GHz
-64 -55
-40 qC 1TX
25 qC -60 2TX
-65 105 qC 3TX
-65 4TX
-66
-70
IMD3 (dBc)

IMD3 (dBc)

-67 -75

-80
-68
-85
-69
-90

-70 -95
0 40 80 120 160 200 240 280 320 360 400 -37 -34 -31 -28 -25 -22 -19 -16 -13 -10 -7
Tone Spacing (MHz) Pout/tone (dBFS)

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9 fDAC = 11796.48MSPS, interleaved mode, matching at 4.9
GHz, fCENTER = 4.9GHz, –13 dBFS each tone, worst channel GHz, fCENTER = 4.9GHz, fSPACING = 20 MHz
Figure 6-171. TX IMD3 vs Tone Spacing and Temperature at 4.9 Figure 6-172. TX IMD3 vs Digital Level at 4.9 GHz
GHz

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6.12.5 TX Typical Characteristics at 4.9 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
-139
Ain=-30dBFS
-141 Ain=-20dBFS
-143 Ain=-12dBFS
Ain=-6dBFS
-145 Ain=-1dBFS
Noise (dBFS/Hz)

-147
-149
-151
-153
-155
-157
-159
4300 4500 4700 4900 5100 5300 5500
Output Frequency (MHz)

Matching at 4.9 GHz, Single tone, fDAC = 11.79648GSPS, TM1.1, POUT_RMS = –13 dBFS
interleave mode, 40-MHz offset, DSA=0dB .

Figure 6-173. TX Single Tone Output Noise vs Frequency and Figure 6-174. TX 20-MHz LTE Output Spectrum at 4.9 GHz
Amplitude at 4.9 GHz
-52 -54
1TX 1TX
-54 2TX -56 2TX
Alternate channel ACPR (dBc)

3TX 3TX
Ajacent channel ACPR (dBc)

-56 4TX -58 4TX

-58 -60

-60 -62

-62 -64

-64 -66

-66 -68

-68 -70

-70 -72
-32 -29 -26 -23 -20 -17 -14 -12 -32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -12
Pout(dBFS) Pout (dBFS)

Matching at 4.9 GHz, single carrier 20-MHz BW TM1.1 LTE Matching at 4.9 GHz, single carrier 20-MHz BW TM1.1 LTE
Figure 6-175. TX 20-MHz LTE ACPR vs Digital Level at 4.9 GHz Figure 6-176. TX 20-MHz LTE alt-ACPR vs Digital Level at 4.9
GHz
-41 -48
1TX 1TX
-44 2TX -51 2TX
Alternate channel ACPR (dBc)

3TX 3TX
Ajacent channel ACPR (dBc)

-47 4TX -54 4TX

-50 -57

-53 -60

-56 -63

-59 -66

-62 -69

-65 -72
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA (dB) DSA (dB)

Matching at 4.9 GHz, single carrier 20-MHz BW TM1.1 LTE Matching at 4.9 GHz, single carrier 20-MHz BW TM1.1 LTE
Figure 6-177. TX 20-MHz LTE ACPR vs DSA at 4.9 GHz Figure 6-178. TX 20-MHz LTE alt-ACPR vs DSA at 4.9 GHz

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6.12.5 TX Typical Characteristics at 4.9 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz,
AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled
-55 -60
-60 -65
-70
-65
-75
-70
-80
HD2 (dBFS/Hz)

HD3 (dBFS/Hz)
-75 -85
-80 -90
-85 -95
-100
-90
1TX, -12dBFS 3TX, -12dBFS -105 1TX, -12dBFS 3TX, -12dBFS
-95 1TX, -6dBFS 3TX, -6dBFS 1TX, -6dBFS 3TX, -6dBFS
-110
-100 2TX, -12dBFS 4TX, -12dBFS 2TX, -12dBFS 4TX, -12dBFS
2TX, -6dBFS 4TX, -6dBFS -115 2TX, -6dBFS 4TX, -6dBFS
-105 -120
4300 4500 4700 4900 5100 5300 5500 4300 4500 4700 4900 5100 5300 5500
Output Frequency (MHz) Output Frequency (MHz)

Matching at 4.9 GHz, fDAC = 11.79648GSPS, interleave mode, Matching at 4.9 GHz, fDAC = 11.79648GSPS, interleave mode,
normalized to output power at harmonic frequency normalized to output power at harmonic frequency
Figure 6-179. TX HD2 vs Digital Amplitude and Output Figure 6-180. TX HD3 vs Digital Amplitude and Output
Frequency at 4.9 GHz Frequency at 4.9 GHz
0 0
-10 Tone = -11.5dBm -10 Tone = -5.5dBm
HD2 = -70.5dBm HD2 = -58.7dBm
-20 HD3 = -86.3dBm -20 HD3 = -68.8dBm
-30 IL2 = -89.3dBm -30 IL2 = -75.6dBm
Fs/2 = -54.2dBm Fs/2 = -54.2dBm
Amplitude (dBm)

Amplitude (dBm)

-40 -40
-50 -50
-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110
0 2000 4000 6000 8000 10000 12000 0 2000 4000 6000 8000 10000 12000
Output Frequency (MHz) Output Frequency (MHz)
fDAC = 11796.48MSPS, interleave mode, 4.9 GHz matching, fDAC = 11796.48MSPS, interleave mode, 4.9 GHz matching,
includes PCB and cable losses. ILn = fS/n ± fOUT. includes PCB and cable losses. ILn = fS/n ± fOUT.
Figure 6-181. TX Single Tone (–12 dBFS) Output Spectrum at Figure 6-182. TX Single Tone (–6 dBFS) Output Spectrum at 4.9
4.9 GHz (0-fDAC) GHz (0-fDAC)
10
0 Tone = -0.5dBm
HD2 = -48.1dBm
-10 HD3 = -52.2dBm
-20 IL2 = -69.9dBm
Fs/2 = -54.7dBm
Amplitude (dBm)

-30
-40
-50
-60
-70
-80
-90
-100
-110
0 2000 4000 6000 8000 10000 12000
Output Frequency (MHz)

fDAC = 11796.48MSPS, interleave mode, 4.9 GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT.
Figure 6-183. TX Single Tone (–1 dBFS) Output Spectrum at 4.9 GHz (0-fDAC)

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6.12.6 TX Typical Characteristics at 8.1 GHz

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 8.1 GHz matching

0 0
1TX 1TX
-1 2TX -5 2TX
-2 3TX 3TX
4TX -10 4TX
Output Power (dBm)

Output Power (dBm)

-3
-15
-4
-20
-5
-25
-6
-7 -30

-8 -35

-9 -40
-10 -45
7200 7400 7600 7800 8000 8200 8400 8600 8800 9000 0 5 10 15 20 25 30 35 40
Output Frequency (MHz) DSA Setting (dB)
includes PCB and cable losses. includes PCB and cable losses.
Figure 6-184. TX Output Power vs Frequency at 8.11 GHz Figure 6-185. TX Output Power vs DSA Setting at 8.11 GHz
Uncalibrated Amplitude Differential Nonlinearity (dB)

0
1TX 0.1
-1 2TX
3TX 0.08
-2
4TX 0.06
Output Power (dBm)

-3
0.04
-4
0.02
-5
0
-6
-0.02
-7
-0.04
-8 1TX
-0.06 2TX
-9 3TX
-0.08
-10 4TX
-40 -20 0 20 40 60 80 100 120 -0.1
Temperature (C) 0 4 8 12 16 20 24 28 32 36 40
DSA Setting (dB)
includes PCB and cable losses.
.
Figure 6-186. TX Output Power vs Temperature at 8.11 GHz
Figure 6-187. TX DSA Uncalibrated Amplitude Differential
Nonlinearity at 8.11 GHz
Uncalibrated Amplitude Differential Nonlinearity (dB)
Calibrated Amplitude Differential Nonlinearity (dB)

0.1 0.1
0.08 0.08
0.06 0.06
0.04 0.04
0.02 0.02

0 0

-0.02 -0.02

-0.04 -0.04
1TX -0.06
-0.06 2TX -40C
3TX -0.08 25C
-0.08 110C
4TX
-0.1 -0.1
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA Setting (dB) DSA Setting (dB)

Figure 6-188. TX DSA Calibrated Amplitude Differential Figure 6-189. TX DSA Uncalibrated Amplitude Differential
Nonlinearity at 8.11 GHz Nonlinearity at 8.11 GHz

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6.12.6 TX Typical Characteristics at 8.1 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 8.1 GHz matching
Calibrated Amplitude Differential Nonlinearity (dB)

0.1
0.08
0.06
0.04
0.02
0
-0.02
-0.04
-0.06 -40C
-0.08 25C
110C
-0.1
0 4 8 12 16 20 24 28 32 36 40
DSA Setting (dB)
.
Figure 6-191. TX DSA Uncalibrated Amplitude Integrated
Figure 6-190. TX DSA Calibrated Amplitude Differential Nonlinearity at 8.11 GHz
Nonlinearity at 8.11 GHz
UnCalibrated Amplitude Integrated Nonlinearity (dB)

Uncalibrated Amplitude Integrated Nonlinearity (dB)

1 1

0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0 0

-0.2 -0.2

-0.4 -0.4
1TX -0.6
-0.6 2TX -40C
3TX -0.8 25C
-0.8 110C
4TX
-1
-1
0 4 8 12 16 20 24 28 32 36 40
0 4 8 12 16 20 24 28 32 36 40
DSA Setting (dB)
DSA Setting (dB)
Figure 6-193. TX DSA Uncalibrated Amplitude Integrated
Figure 6-192. TX DSA Calibrated Amplitude Integrated
Nonlinearity at 8.11 GHz
Nonlinearity at 8.11 GHz
UnCalibrated Phase Differential Nonlinearity (deg)

0.5
1TX
0.4 2TX
0.3 3TX
4TX
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0 4 8 12 16 20 24 28 32 36 40
DSA Setting (dB)
Figure 6-194. TX DSA Calibrated Amplitude Integrated
Nonlinearity at 8.11 GHz Figure 6-195. TX DSA Uncalibrated Phase Differential
Nonlinearity at 8.11 GHz

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6.12.6 TX Typical Characteristics at 8.1 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 8.1 GHz matching
Calibrated Phase Differential Nonlinearity (deg)

Uncalibrated Phase Differential Nonlinearity (deg)

0.5 0.5
1TX -40C
0.4 2TX 0.4 25C
0.3 3TX 0.3 110C
4TX
0.2 0.2

0.1 0.1

0 0

-0.1 -0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5
-0.5 0 4 8 12 16 20 24 28 32 36 40
0 4 8 12 16 20 24 28 32 36 40 DSA Setting (dB)
DSA Setting (dB)
.
Figure 6-196. TX DSA Calibrated Phase Differential Nonlinearity
at 8.11 GHz Figure 6-197. TX DSA Uncalibrated Phase Differntial
Uncalibrated Phase Integrated Nonlinearity (deg) Nonlinearity at 8.11 GHz
Calibrated Phase Differential Nonlinearity (deg)

0.5
2
-40C
0.4 25C
1TX
110C 1.5 2TX
0.3 3TX
0.2 1 4TX

0.1
0.5
0
0
-0.1
-0.2 -0.5
-0.3
-1
-0.4
-1.5
-0.5
0 4 8 12 16 20 24 28 32 36 40
DSA Setting (dB) -2
0 4 8 12 16 20 24 28 32 36 40
. DSA Setting (dB)
Figure 6-198. TX DSA Calibrated Phase Differential Nonlinearity Figure 6-199. TX DSA Uncalibrated Phase Integrated
at 8.11 GHz Nonlinearity at 8.11 GHz
Calibrated Phase Integrated Nonlinearity (deg)

Uncalibrated Phase Integrated Nonlinearity (dB)

2 2
-40C
1.5 1.5 25C
110C
1 1

0.5 0.5

0 0

-0.5 -0.5

-1 1TX -1
2TX
-1.5 3TX -1.5
4TX
-2 -2
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
DSA Setting (dB) DSA Setting (dB)

Figure 6-200. TX DSA Calibrated Phase Integrated Nonlinearity Figure 6-201. TX DSA Uncalibrated Phase Integrated
at 8.11 GHz Nonlinearity at 8.11 GHz

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6.12.6 TX Typical Characteristics at 8.1 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 8.1 GHz matching

2 0
Calibrated Phase Integrated Nonlinearity (dB)

1.5
-20
1

Amplitude (dBm)
0.5 -40

0
-60
-0.5

-1 -80
-40C
-1.5 25C
110C -100
-2 0 2000 4000 6000 8000 10000 12000
0 4 8 12 16 20 24 28 32 36 40 Frequency (MHz)
DSA Setting (dB)
–1 dBFS
.
Figure 6-203. TX Single Tone Output Spectrum at 8.11 GHz
Figure 6-202. TX DSA Calibrated Phase Integrated Nonlinearity
at 8.11 GHz
0 0
-10
-20 -20
-30
Amplitude (dBm)
Amplitude (dBm)

-40 -40

-50
-60 -60

-70
-80 -80

-90
-100 -100
7500 7750 8000 8250 8500 8700 0 2000 4000 6000 8000 10000 12000
Frequency (MHz) Frequency (MHz)

–1 dBFS –6 dBFS
Figure 6-204. TX Single Tone Output Spectrum at 8.11 GHz Figure 6-205. TX Single Tone Output Spectrum at 8.11 GHz
0 0
-10
-20 -20
-30
Amplitude (dBm)
Amplitude (dBm)

-40 -40

-50
-60 -60

-70
-80 -80

-90
-100 -100
7500 7750 8000 8250 8500 8700 0 2000 4000 6000 8000 10000 12000
Frequency (MHz) Frequency (MHz)

–6 dBFS –12 dBFS

Figure 6-206. TX Single Tone Output Spectrum at 8.11 GHz Figure 6-207. TX Single Tone Output Spectrum at 8.11 GHz

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6.12.6 TX Typical Characteristics at 8.1 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 8.1 GHz matching

0 0
-10
-20 -20
-30

Amplitude (dBm)
Amplitude (dBm)

-40 -40

-50
-60 -60

-70
-80 -80

-90
-100 -100
7500 7750 8000 8250 8500 8700 0 2000 4000 6000 8000 10000 12000
Frequency (MHz) Frequency (MHz)

–12 dBFS 50-MHz tone spacing, –7 dBFS each tone

Figure 6-208. TX Single Tone Output Spectrum at 8.11 GHz Figure 6-209. TX Dual Tone Output Spectrum at 8.11 GHz
0 0
-10
-20 -20
-30
Amplitude (dBm)
Amplitude (dBm)

-40 -40

-50
-60 -60

-70
-80 -80

-90
-100 -100
7500 7750 8000 8250 8500 8700 0 2000 4000 6000 8000 10000 12000
Frequency (MHz) Frequency (MHz)

50-MHz tone spacing, –7 dBFS each tone 50-MHz tone spacing, –12 dBFS each tone
Figure 6-210. TX Dual Tone Output Spectrum at 8.11 GHz Figure 6-211. TX Dual Tone Output Spectrum at 8.11 GHz
0 0
-10
-20 -20
-30
Amplitude (dBm)
Amplitude (dBm)

-40 -40

-50
-60 -60

-70
-80 -80

-90
-100 -100
7500 7750 8000 8250 8500 8700 0 2000 4000 6000 8000 10000 12000
Frequency (MHz) Frequency (MHz)

50-MHz tone spacing, –12 dBFS each tone 50-MHz tone spacing, –30 dBFS each tone
Figure 6-212. TX Dual Tone Output Spectrum at 8.11 GHz Figure 6-213. TX Dual Tone Output Spectrum at 8.11 GHz

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6.12.6 TX Typical Characteristics at 8.1 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 8.1 GHz matching

0 0
-10
-20 -20
-30

Amplitude (dBm)
Amplitude (dBm)

-40 -40

-50
-60 -60

-70
-80 -80

-90
-100 -100
7500 7750 8000 8250 8500 8700 0 2000 4000 6000 8000 10000 12000
Frequency (MHz) Frequency (MHz)

50-MHz tone spacing, –30 dBFS each tone 50-MHz tone spacing, –60 dBFS each tone
Figure 6-214. TX Dual Tone Output Spectrum at 8.11 GHz Figure 6-215. TX Dual Tone Output Spectrum at 8.11 GHz
0 -40
1TX
-10
-45 2TX
-20 3TX
-50 4TX
-30
Amplitude (dBm)

-40 -55
IMD3 (dBc)

-50
-60
-60
-65
-70
-80 -70
-90
-75
-100
7500 7750 8000 8250 8500 8700 -80
Frequency (MHz) -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
Digital Amplitude per Tone (dBFS)
50-MHz tone spacing, –60 dBFS each tone
. 50-MHz tone spacing

Figure 6-216. TX Dual Tone Output Spectrum at 8.11 GHz Figure 6-217. TX IMD3 vs Digital Amplitude at 8.11 GHz

-40 -40
-40C 1TX, -13dBFS 1TX, -7dBFS
-45 25C -45 2TX, -13dBFS 2TX, -7dBFS
110C 3TX, -13dBFS 3TX, -7dBFS
-50 -50 4TX, -13dBFS 4TX, -7dBFS

-55 -55
IMD3 (dBc)

IMD3 (dBc)

-60 -60

-65 -65

-70 -70

-75 -75
-80 -80
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40
Digital Amplitude per Tone (dBFS)
DSA Setting (dB)
50-MHz tone spacing 50-MHz tone spacing
Figure 6-218. TX IMD3 vs Digital Amplitude at 8.11 GHz Figure 6-219. TX IMD3 vs DSA Setting at 8.11 GHz

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6.12.6 TX Typical Characteristics at 8.1 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 8.1 GHz matching

-40 -60
-13dBFS, -40C -7dBFS, -40C
-45 -13dBFS, 25C -7dBFS, 25C -65
-13dBFS, 110C -7dBFS, 110C
-50 -70

2-tone SFDR (dBFS)

-55 -75
IMD3 (dBc)

-60 -80

-65 -85

-70 -90 1TX

2TX
-75 -95 3TX
4TX
-80 -100
0 5 10 15 20 25 30 35 40 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
DSA Setting (dB) Tone Amplitude (dBFS)

50-MHz tone spacing 50-MHz tone spacing

Figure 6-220. TX IMD3 vs DSA Setting at 8.11 GHz Figure 6-221. TX 2-Tone SFDR vs Digital Amplitude at 8.11 GHz

-140 -140
1TX -40C
-142 2TX -142 25C
NSD at 50MHz Offset (dBFS/Hz)
NSD at 50MHz Offset (dBFS/Hz)

3TX -144 110C

-144
4TX
-146 -146

-148 -148

-150 -150

-152 -152

-154 -154

-156 -156

-158 -158
-160
-160
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0
Digital Amplitude (dBFS)
Digital Amplitude (dBFS)
50-MHz offset
50-MHz offset
Figure 6-223. TX NSD vs Digital Amplitude at 8.11 GHz
Figure 6-222. TX NSD vs Digital Amplitude at 8.11 GHz
-120 -120
1TX, -12dBFS 1TX, -1dBFS -12dBFS, -40C
-125 2TX, -12dBFS 2TX, -1dBFS -125 -12dBFS, 25C
NSD at 50MHz offset (dBFS/Hz)
NSD at 50MHz offset (dBFS/Hz)

3TX, -12dBFS 3TX, -1dBFS -12dBFS, 110C

-130 4TX, -12dBFS 4TX, -1dBFS -130 -1dBFS, -40C
-1dBFS, 25C
-135 -1dBFS, 110C
-135

-140 -140

-145 -145

-150 -150

-155 -155

-160
-160
0 5 10 15 20 25 30 35 40
0 5 10 15 20 25 30 35 40
DSA Setting (dB)
DSA Setting (dB)
50-MHz offset
50-MHz offset
Figure 6-225. TX NSD vs DSA Setting at 8.11 GHz
Figure 6-224. TX NSD vs DSA Setting at 8.11 GHz

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6.12.6 TX Typical Characteristics at 8.1 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 8.1 GHz matching

-33 -33
1TX 1TX
-36 2TX -36 2TX
3TX 3TX
-39 -39 4TX
4TX
-42
-42

ACPR (dBc)
ACPR (dBc)

-45
-45
-48
-48
-51
-51
-54
-54
-57
-57
-60
-60 0 5 10 15 20 25 30 35 40
0 5 10 15 20 25 30 35 40 DSA Setting (dB)
DSA Setting (dB) .
Figure 6-226. TX NR100MHz ACPR vs DSA Setting 8.11 GHz
Figure 6-227. TX NR100MHz alt-ACPR vs DSA Setting 8.11 GHz
8
1TX
NR 100MHz Composite EVM (%rms)

7 2TX
3TX
6 4TX

0
0 5 10 15 20 25 30 35 40
DSA Setting (dB)
Figure 6-228. TX NR100MHz EVM vs DSA Setting 8.11 GHz

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6.12.6 TX Typical Characteristics at 8.1 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 8.1 GHz matching

Figure 6-229. TX 100MHz NR Output Spectrum at 8.11 GHz

Figure 6-230. TX 100MHz NR EVM at 8.11 GHz

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6.12.6 TX Typical Characteristics at 8.1 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (24x interpolation), mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 8.1 GHz matching

Figure 6-231. TX 4x100MHz NR Output Spectrum 8.11 GHz

Figure 6-232. TX 4x100MHz NR Output Spectrum 8.11 GHz

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6.12.7 TX Typical Characteristics at 9.6 GHz

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 1474.56 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 9.6 GHz matching

-4 0
1TX
-5 -1 2TX
-6 -2 3TX
4TX
Output Power (dBm)

Output Power (dBm)

-7 -3
-8 -4
-9 -5
-10 -6
-11 -7
1TX
-12 2TX -8
-13 3TX
4TX -9
-14 -10
8800 9000 9200 9400 9600 9800 10000 10200 10400 -40 -20 0 20 40 60 80 100 120
Output Frequency (MHz) Temperature (C)
Includes PCB and cable losses. Includes PCB and cable losses.
Figure 6-233. TX Output Power vs Frequency at 9.61 GHz Figure 6-234. TX Output Power vs Frequency at 9.61 GHz
Uncalibrated Amplitude Differential Nonlinearity (dB)
0
1TX 0.2
-5 2TX 1TX
-10 3TX 0.15 2TX
4TX 3TX
4TX
Output Power (dBm)

-15 0.1
-20 0.05
-25
0
-30
-0.05
-35
-40 -0.1

-45 -0.15
-50
0 5 10 15 20 25 30 35 40 -0.2
0 2 4 6 8 10 12 14 16 18 20 22 24 26
DSA Setting (dB)
DSA Setting (dB)
Includes PCB and cable losses.
.
Figure 6-235. TX Output Power vs DSA Setting at 9.61 GHz
Figure 6-236. TX DSA Uncalibrated Amplitude Differential
Nonlinearity
Uncalibrated Amplitude Differential Nonlinearity (dB)
Calibrated Amplitude Differential Nonlinearity (dB)

0.2 0.2
1TX
0.15 2TX 0.15
3TX
0.1 4TX 0.1

0.05 0.05

0 0

-0.05 -0.05

-0.1 -0.1
-40C
-0.15 -0.15 25C
110C
-0.2 -0.2
0 2 4 6 8 10 12 14 16 18 20 22 24 26 0 2 4 6 8 10 12 14 16 18 20 22 24 26
DSA Setting (dB) DSA Setting (dB)
Figure 6-237. TX DSA Calibrated Amplitude Differential Figure 6-238. TX DSA Uncalibrated Amplitude Differential
Nonlinearity Nonlinearity

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6.12.7 TX Typical Characteristics at 9.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 1474.56 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 9.6 GHz matching
Calibrated Amplitude Differential Nonlinearity (dB)

0.2

0.15

0.1

0.05

-0.05

-0.1
-40C
-0.15 25C
110C
-0.2
0 2 4 6 8 10 12 14 16 18 20 22 24 26
DSA Setting (dB)
Figure 6-239. TX DSA Calibrated Amplitude Differential Figure 6-240. TX DSA Uncalibrated Amplitude Integrated
Nonlinearity Nonlinearity
Uncalibrated Amplitude Integrated Nonlinearity (dB)
Calibrated Amplitude Integrated Nonlinearity (dB)

1 1
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
-0.2 -0.2
-0.4 -0.4
1TX
-0.6 2TX -0.6 -40C
-0.8 3TX 25C
4TX -0.8
110C
-1 -1
0 2 4 6 8 10 12 14 16 18 20 22 24 26 0 2 4 6 8 10 12 14 16 18 20 22 24 26
DSA Setting (dB) DSA Setting (dB)
Figure 6-241. TX DSA Calibrated Amplitude Integrated Figure 6-242. TX DSA Uncalibrated Amplitude Integrated
Nonlinearity Nonlinearity
Calibrated Amplitude Integrated Nonlinearity (dB)

Uncalibrated Phase Differential Nonlinearity (deg)

1 1
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
-0.2 -0.2
-0.4 -0.4
1TX
-0.6 -40C -0.6 2TX
-0.8 25C -0.8 3TX
110C 4TX
-1 -1
0 2 4 6 8 10 12 14 16 18 20 22 24 26 0 2 4 6 8 10 12 14 16 18 20 22 24 26
DSA Setting (dB) DSA Setting (dB)
Figure 6-243. TX DSA Calibrated Amplitude Integrated Figure 6-244. TX DSA Uncalibrated Phase Differential
Nonlinearity Nonlinearity

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6.12.7 TX Typical Characteristics at 9.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 1474.56 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 9.6 GHz matching
Calibrated Phase Differential Nonlinearity (deg)

Uncalibrated Phase Differential Nonlinearity (deg)

1
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.2
-0.4
-0.4
1TX
-0.6 2TX -0.6 -40C
-0.8 3TX
-0.8 25C
4TX
110C
-1
-1
0 2 4 6 8 10 12 14 16 18 20 22 24 26
0 2 4 6 8 10 12 14 16 18 20 22 24 26
DSA Setting (dB)
DSA Setting (dB)
Figure 6-245. TX DSA Calibrated Phase Differential Nonlinearity Figure 6-246. TX DSA Uncalibrated Phase Differential
Nonlinearity
Calibrated Phase Differential Nonlinearity (deg)

Uncalibrated Phase IntegratedNonlinearity (deg)

1 2
1TX
0.8
1.5 2TX
0.6 3TX
1 4TX
0.4
0.2 0.5

0 0
-0.2
-0.5
-0.4
-1
-0.6 -40C
-0.8 25C -1.5
110C
-1 -2
0 2 4 6 8 10 12 14 16 18 20 22 24 26 0 2 4 6 8 10 12 14 16 18 20 22 24 26
DSA Setting (dB) DSA Setting (dB)
Figure 6-247. TX DSA Calibrated Phase Differential Nonlinearity Figure 6-248. TX DSA Uncalibrated Phase Integrated
Nonlinearity
Calibrated Phase Differential Nonlinearity (deg)

1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6 -40C
-0.8 25C
110C
-1
0 2 4 6 8 10 12 14 16 18 20 22 24 26
DSA Setting (dB)
Figure 6-249. TX DSA Calibrated Phase Integrated Nonlinearity Figure 6-250. TX DSA Uncalibrated Phase Integrated
Nonlinearity

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6.12.7 TX Typical Characteristics at 9.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 1474.56 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 9.6 GHz matching

-40
Calibrated Phase Integrated Nonlinearity (deg)

2
-40C -50
1.5 25C
110C -60
1

IMD3 (dBc or dBFS)

-70
0.5 -80

0 -90
-100
-0.5
-110
-1 1TX (dBc) 1TX (dBFS)
-120 2TX (dBc) 2TX (dBFS)
-1.5 -130 3TX (dBc) 3TX (dBFS)
4TX (dBc) 4TX (dBFS)
-2 -140
0 2 4 6 8 10 12 14 16 18 20 22 24 26 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
DSA Setting (dB) Tone Amplitude (dBFS)

. 50-MHz tone spacing

Figure 6-251. TX DSA Calibrated Amplitude Integrated Figure 6-252. TX IMD3 vs Digital Amplitude at 9.61 GHz
Nonlinearity
-40 -50
-50
-55
-60
-60
IMD3 (dBc or dBFS)

-70
-80 -65
IMD3 (dBc)

-90 -70
-100
-75
-110
-80 -13dBFS, 1TX -7dBFS, 1TX
-120 -40 (C, dBc) -40 (C, dBFS) -13dBFS, 2TX -7dBFS, 2TX
-130 25 (C, dBc) 25 (C, dBFS) -85 -13dBFS, 3TX -7dBFS, 3TX
110 (C, dBc) 110 (C, dBFS) -13dBFS, 4TX -7dBFS, 4TX
-140 -90
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40
Tone Amplitude (dBFS) DSA Setting (dB)
50-MHz tone spacing 50-MHz tone spacing
Figure 6-253. TX IMD3 vs Digital Amplitude at 9.61 GHz Figure 6-254. TX IMD3 vs DSA Setting at 9.61 GHz
-50 -50

-55 -55

-60 -60

-65 -65
IMD3 (dBc)

IMD3 (dBc)

-70 -70

-75 -75

-80 -13dBFS, 1TX -7dBFS, 1TX -80

-13dBFS, 2TX -7dBFS, 2TX -13dBFS, -40C -7dBFS, -40C
-85 -13dBFS, 3TX -7dBFS, 3TX -85 -13dBFS, -25C -7dBFS, 25C
-13dBFS, 4TX -7dBFS, 4TX -13dBFS, 110C -7dBFS, 100C
-90 -90
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
DSA Setting (dB) DSA Setting (dB)
50-MHz tone spacing 50-MHz tone spacing
Figure 6-255. TX IMD3 vs DSA Setting at 9.61 GHz Figure 6-256. TX IMD3 vs DSA Setting at 9.61 GHz

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6.12.7 TX Typical Characteristics at 9.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 1474.56 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 9.6 GHz matching

-60 -50
-62
-55
-64
-66
-60
IMD3 (dBc)

IMD3 (dBc)
-68
-70 -65
-72
-70
-74
1TX
-76 2TX -60dBFS per tone
-75
-78 3TX -30dBFS per tone
4TX -13dBFS per tone
-80 -80
0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000
Tone Spacing (MHz) Tone Spacing (MHz)
Figure 6-257. TX IMD3 vs Tone Spacing at 9.61 GHz Figure 6-258. TX IMD3 vs Tone Spacing at 9.61 GHz
-60 -144
-40C 1TX
-61 25C -145 2TX
-62 110C -146 3TX
4TX
-63 -147
NSD (dBFS/Hz)
IMD3 (dBc)

-64 -148
-65 -149
-66 -150
-67 -151
-68 -152
-69 -153
-70 -154
0 100 200 300 400 500 600 700 800 900 1000 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0
Tone Spacing (MHz) Digital Amplitude (dBFS)
Figure 6-259. TX IMD3 vs Tone Spacing at 9.61 GHz Figure 6-260. TX NSD vs Digital Amplitude at 9.61 GHz
-144
-40C
-145 25C
-146 110C

-147
NSD (dBFS/Hz)

-148
-149
-150
-151
-152
-153
-154
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0
Digital Amplitude (dBFS)
Figure 6-261. TX NSD vs Digital Amplitude at 9.61 GHz Figure 6-262. TX NSD vs DSA Setting at 9.61 GHz

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6.12.7 TX Typical Characteristics at 9.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 1474.56 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 9.6 GHz matching

-120 -120
1TX -40C
2TX 25C
-125 3TX -125 110C
4TX
-130 -130
NSD (dBFS/Hz)

NSD (dBFS/Hz)
-135 -135

-140 -140

-145 -145

-150 -150
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
DSA Setting (dB) DSA Setting (dB)
Figure 6-263. TX NSD vs DSA Setting at 9.61 GHz Figure 6-264. TX NSD vs DSA Setting at 9.61 GHz
-60 0
1TX
-65 2TX
3TX -20
-70 4TX
2-tone SFDR (dBFS)

Amplitude (dBm)

-75 -40

-80
-60
-85

-90
-80
-95
-100
-100
0 2000 4000 6000 8000 10000 12000
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
Frequency (MHz)
Tone Amplitude (dBFS)
Includes PCB and cable losses.
50-MHz tone spacing
Figure 6-266. TX Single Tone Spectrum at 9.61 GHz and -1dBFS
Figure 6-265. TX 2-tone SFDR vs Digital Amplitude at 9.61 GHz
(wideband)
0 0
-10
-20
-20
-30
-40
Amplitude (dBm)

Amplitude (dBm)

-50 -40
-60
-70 -60
-80
-90
-80
-100
-110
-120 -100
9000 9200 9400 9600 9800 10000 10200 0 2000 4000 6000 8000 10000 12000
Frequency (MHz) Frequency (MHz)
Includes PCB and cable losses. Includes PCB and cable losses.
Figure 6-267. TX Single Tone Spectrum at 9.61 GHz and -1dBFS Figure 6-268. TX Single Tone Spectrum at 9.61 GHz and -6dBFS
(1.2GHz BW) (wideband)

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6.12.7 TX Typical Characteristics at 9.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 1474.56 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 9.6 GHz matching

-20

Amplitude (dBm)
-40

-60

-80

-100
0 2000 4000 6000 8000 10000 12000
Frequency (MHz)
Includes PCB and cable losses. Includes PCB and cable losses.
Figure 6-269. TX Single Tone Spectrum at 9.61 GHz and -6dBFS Figure 6-270. TX Single Tone Spectrum at 9.61 GHz and
(1.2GHz BW) -12dBFS (wideband)
0 0
-10
-20
-20
-30
-40
Amplitude (dBm)

Amplitude (dBm)

-50 -40
-60
-70 -60
-80
-90
-80
-100
-110
-120 -100
9000 9200 9400 9600 9800 10000 10200 0 2000 4000 6000 8000 10000 12000
Frequency (MHz) Frequency (MHz)
Includes PCB and cable losses. Includes PCB and cable losses, 50-MHz tone spacing.
Figure 6-271. TX Single Tone Spectrum at 9.61 GHz and Figure 6-272. TX 2-Tone Spectrum at 9.61 GHz and -7dBFS
-12dBFS (1.2GHz BW) (wideband)
0 0
-10
-20
-20
-30
-40
Amplitude (dBm)

Amplitude (dBm)

-50 -40
-60
-70 -60
-80
-90
-80
-100
-110
-120 -100
9000 9200 9400 9600 9800 10000 10200 0 2000 4000 6000 8000 10000 12000
Frequency (MHz) Frequency (MHz)
Includes PCB and cable losses, 50-MHz tone spacing. Includes PCB and cable losses, 50-MHz tone spacing.
Figure 6-273. TX 2-Tone Spectrum at 9.61 GHz and -7dBFS Figure 6-274. TX 2-Tone Spectrum at 9.61 GHz and -13dBFS
(1.2GHz BW) (wideband)

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6.12.7 TX Typical Characteristics at 9.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 1474.56 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 9.6 GHz matching

0 0
-10
-20
-20
-30
-40
Amplitude (dBm)

Amplitude (dBm)
-50 -40
-60
-70 -60
-80
-90
-80
-100
-110
-120 -100
9000 9200 9400 9600 9800 10000 10200 0 2000 4000 6000 8000 10000 12000
Frequency (MHz) Frequency (MHz)
Includes PCB and cable losses, 50-MHz tone spacing. Includes PCB and cable losses, 50-MHz tone spacing.
Figure 6-275. TX 2-Tone Spectrum at 9.61 GHz and -13dBFS Figure 6-276. TX 2-Tone Spectrum at 9.61 GHz and -30dBFS
(1.2GHz BW) Each (wideband)
0 0
-10
-20
-20
-30
-40
Amplitude (dBm)

Amplitude (dBm)

-50 -40
-60
-70 -60
-80
-90
-80
-100
-110
-120 -100
9000 9200 9400 9600 9800 10000 10200 0 2000 4000 6000 8000 10000 12000
Frequency (MHz) Frequency (MHz)
Includes PCB and cable losses, 50-MHz tone spacing. Includes PCB and cable losses, 50-MHz tone spacing.
Figure 6-277. TX 2-Tone Spectrum at 9.61 GHz and -30dBFS Figure 6-278. TX 2-Tone Spectrum at 9.61 GHz and -60dBFS
Each (1.2GHz BW) Each (wideband)
0 -80
-10
-20 -90
Additive Phase Noise (dBc/Hz)

-30
-100
-40
Amplitude (dBm)

-50 -110
-60
-70 -120
-80
-130
-90
-100
-140
-110
-120 -150
9000 9200 9400 9600 9800 10000 10200 102 103 104 105 106 107 108
Frequency (MHz) Offset Frequency (Hz)
Includes PCB and cable losses, 50-MHz tone spacing. Single sideband, external clock mode, input clock phase noise
. removed
Figure 6-279. TX 2-Tone Spectrum at 9.61 GHz and -60dBFS Figure 6-280. TX Additive Phase Noise vs Offset Frequency at
Each (1.2GHz BW) 9.61 GHz

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6.12.7 TX Typical Characteristics at 9.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 1474.56 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 9.6 GHz matching

-25
1TX
-30 2TX
3TX
4TX
NR 100MHz ACPR (dBc)

-35

-40

-45

-50

-55

-60
0 5 10 15 20 25 30 35 40
DSA Setting (dB)
Figure 6-281. TX NR100MHz ACPR vs DSA Setting at 9.61 GHz Figure 6-282. TX NR100MHz alt-ACPR vs DSA Setting at 9.61
GHz
8
1TX
NR 100MHz Composite EVM (%rms)

7 2TX
3TX
6 4TX

0
0 5 10 15 20 25 30 35 40
DSA Setting (dB)
Figure 6-283. TX NR100MHz EVM vs DSA Setting at 9.61 GHz

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6.12.7 TX Typical Characteristics at 9.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 1474.56 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 9.6 GHz matching

Includes PCB and cable losses.

Figure 6-284. TX NR100MHz Output Spectrum at 9.61 GHz

Includes PCB and cable losses.

Figure 6-285. TX 4xNR100MHz Output Spectrum at 9.61 GHz

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6.12.7 TX Typical Characteristics at 9.6 GHz (continued)

Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC =
11796.48MSPS (8x interpolation), Mixed mode, 1st Nyquist zone output, PLL clock mode with fREF = 1474.56 MHz, AOUT
= –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled, 9.6 GHz matching

Note
Includes PCB and cable losses.

Figure 6-286. TX 100MHz NR EVM at 9.61 GHz

6.12.8 RX Typical Characteristics at 800 MHz
Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
0.4 0.13
DSA=4dB DSA=10dB
0.1
0.2 DSA=6dB DSA=12dB
DSA=8dB DSA=14dB 0.07
Relative Input Power (dB)

0 0.04
0.01
Input FS (dB)

-0.2 -0.02
-0.05
-0.4
-0.08
-0.6 -0.11
1RX
-0.14 2RX
-0.8 3RX
-0.17
4RX
-1 -0.2
700 800 900 1000 1100 -40 -30 -20 -10 0 10 20 30 40 50 60 70
Output Frequency (MHz) Temperature (qC)

With 0.8 GHz matching, normalized to 830 MHz With 0.8 GHz matching, normalized to fullscale at 25°C for
. each channel
Figure 6-287. RX In-Band Gain Flatness for Channel 1RX, fIN = Figure 6-288. RX Input Fullscale vs Temperature and Channel at
830 MHz 800MHz

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6.12.8 RX Typical Characteristics at 800 MHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
7 0.3

Uncalibrated Differential Gain Error (dB)

1RX 3RX
6
0.25 2RX 4RX
5
0.2
Input Phase (degree)

4
3 0.15
2
0.1
1
0 0.05
-1
1RX 0
-2 2RX
3RX -0.05
-3
4RX
-4 -0.1
-40 -30 -20 -10 0 10 20 30 40 50 60 70 0 5 10 15 20 25
Temperature (qC) DSA (dB)
With 0.8 GHz matching, normalized to phase at 25°C With 0.8 GHz matching
. Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA
. Setting) + 1
Figure 6-289. RX Input Phase vs Temperature and DSA at fOUT = Figure 6-290. RX Uncalibrated Differential Amplitude Error vs
0.8 GHz DSA Setting at 0.8 GHz
0.03 2.7
1RX 3RX
Uncalibrated Integrated Gain Error (dB)
Calibrated Differential Gain Error (dB)

0.025 2.4
2RX 4RX
0.02
2.1
0.015
1.8
0.01
0.005 1.5
0 1.2
-0.005
0.9
-0.01
0.6 1RX
-0.015 2RX
0.3 3RX
-0.02
4RX
-0.025 0
0 5 10 15 20 25 0 5 10 15 20 25
DSA (dB) DSA (dB)

With 0.8 GHz matching With 0.8 GHz matching

Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA
Setting) + 1 Setting = 0) + (DSA Setting)
Figure 6-291. RX Calibrated Differential Amplitude Error vs DSA Figure 6-292. RX Uncalibrated Integrated Amplitude Error vs
Setting at 0.8 GHz DSA Setting at 0.8 GHz
0.16 0.6
Uncalibrated Differential Phase Error (deg)

1RX 3RX 1RX 3RX

Calibrated Integrated Gain Error (dB)

0.14 2RX 4RX 2RX 4RX

0.12 0.4
0.1
0.08 0.2

0.06
0.04 0

0.02
0 -0.2

-0.02
-0.04 -0.4
0 5 10 15 20 25 0 5 10 15 20 25
DSA (dB) DSA (dB)

With 0.8 GHz matching With 0.8 GHz matching

Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA Differential Phase Error = PhaseIN(DSA Setting – 1) –
Setting = 0) + (DSA Setting) PhaseIN(DSA Setting)

Figure 6-293. RX Calibrated Integrated Amplitude Error vs DSA Figure 6-294. RX Uncalibrated Differential Phase Error vs DSA
Setting at 2.6 GHz Setting at 0.8 GHz

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6.12.8 RX Typical Characteristics at 800 MHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
0.5 1.2

Uncalibrated Integrated Phase Error (deg)

Calibrated Differential Phase Error (deg)

1RX 3RX
0.4 2RX 4RX 0.9
0.3
0.6
0.2
0.3
0.1
0
0
-0.3
-0.1
-0.6
-0.2

-0.3 -0.9 1RX 3RX

2RX 4RX
-0.4 -1.2
0 5 10 15 20 25 0 5 10 15 20 25
DSA (dB) DSA (dB)

With 0.8 GHz matching With 0.8 GHz matching

Differential Phase Error = PhaseIN(DSA Setting – 1) – Integrated Phase Error = Phase(DSA Setting) – Phase(DSA
PhaseIN(DSA Setting) Setting = 0)
Figure 6-295. RX Calibrated Differential Phase Error vs DSA Figure 6-296. RX Uncalibrated Integrated Phase Error vs DSA
Setting at 0.8 GHz Setting at 0.8 GHz
0.6 0
1RX 3RX
Calibrated Integrated Phase Error (deg)

-10 SNR = 63.2dBFS

2RX 4RX
0.4 -20
-30
Amplitude (dBFS)

0.2 -40
-50
0 -60
-70
-0.2 -80
-90
-0.4 -100
-110
-0.6 -120
0 5 10 15 20 25 -250 -200 -150 -100 -50 0 50 100 150 200 250
DSA (dB) Output Frequency (MHz)
With 0.8 GHz matching With 0.8 GHz matching, fIN = 840 MHz, AIN= –3 dBFS
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA .
Setting = 0) .
Figure 6-297. RX Calibrated Integrated Phase Error vs DSA Figure 6-298. RX Output FFT at 0.8 GHz
Setting at 0.8 GHz
-153.8 -147
DSA = 4dB -40 qC, DSA = 4dB
-154 -148
DSA = 12dB -40 qC, DSA = 12dB
-154.2 -149 25 qC, DSA = 4dB
25 qC, DSA = 12dB
-154.4 110 qC, DSA = 4dB
-150
Noise (dBFS/Hz)

Noise (dBFS/Hz)

-154.6 110 qC, DSA = 12dB

-151
-154.8
-152
-155
-153
-155.2
-154
-155.4
-155.6 -155

-155.8 -156
-156 -157
-40 -25 -10 5 20 35 50 65 80 95 110 -30 -25 -20 -15 -10 -5 0
Temperature (qC) Input Amplitude (dBFS)

With 0.8 GHz matching, 12.5-MHz offset from tone With 0.8 GHz matching, DSA Setting = 12 dB, 12.5-MHz offset
. from tone
Figure 6-299. RX Noise Spectral Density vs Temperature at 0.8 Figure 6-300. RX Noise Spectral Density vs Input Amplitude and
GHz Temperature at 0.8 GHz

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6.12.8 RX Typical Characteristics at 800 MHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-147 -80
1RX, DSA = 4dB -40 qC
-148 1RX, DSA = 12dB -82 25 qC
-149 2RX, DSA = 4dB 110qC
2RX, DSA = 12dB -84
-150 3RX, DSA = 4dB
Noise (dBFS/Hz)

3RX, DSA = 12dB -86

IMD3 (dBFS)
-151
-88
-152
-90
-153
-92
-154
-155 -94

-156 -96

-157 -98
-30 -25 -20 -15 -10 -5 0 0 2 4 6 8 10 12 14 16
Input Amplitude (dBFS) DSA (dB)

With 0.8 GHz matching, 12.5-MHz offset from tone With 0.8 GHz matching, each tone –7 dBFS, tone spacing =
. 20 MHz
Figure 6-301. RX Noise Spectral Density vs Input Amplitude and Figure 6-302. RX IMD3 vs DSA Setting and Temperature at 0.8
Channel at 0.8 GHz GHz
-90 -86
-40 qC
-92 -90 25 qC
-94 110qC
-94
-96
q -98
-40 C
IMD3 (dBFS)
IMD5 (dBFS)

-98 25 qC -102
-100 110qC
-106
-102
-110
-104
-106 -114

-108 -118

-110 -122
0 2 4 6 8 10 12 14 16 -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6
DSA (dB) Input Amplitude (dBFS)

With 0.8 GHz matching, each tone –7 dBFS, tone spacing = With 0.8 GHz matching, tone spacing = 20 MHz, DSA = 4 dB
20 MHz .
Figure 6-303. RX IMD5 vs DSA Setting and Temperature at 0.8 Figure 6-304. RX IMD3 vs Input Level and Temperature at 0.8
GHz GHz
-85 -85
-40 qC -40 qC
-90 25 qC -90 25 qC
110qC 110qC

-95 -95
IMD3 (dBFS)

IMD5 (dBFS)

-100 -100

-105 -105

-110 -110

-115 -115

-120 -120
-30 -27 -24 -21 -18 -15 -12 -9 -6 -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6
Input Amplitude (dBFS) Input Amplitude (dBFS)

With 0.8 GHz matching, tone spacing = 20 MHz, DSA = 12 dB With 0.8 GHz matching, tone spacing = 20 MHz, DSA = 12 dB
Figure 6-305. RX IMD3 vs Input Level and Temperature at 0.8 Figure 6-306. RX IMD5 vs Input Level and Temperature at 0.8
GHz GHz

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6.12.8 RX Typical Characteristics at 800 MHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-55 -60
1RX 3RX -40qC
-60 2RX 4RX -63 25qC
110qC
-66
-65
-69
-70
HD2 (dBc)

HD2 (dBc)
-72
-75
-75
-80
-78
-85
-81
-90 -84

-95 -87
3 6 9 12 15 18 3 6 9 12 15 18
DSA (dB) DSA (dB)

With 0.8 GHz matching, measured after HD2 trim, DDC With 0.8 GHz matching, measured after HD2 trim, DDC
bypass mode (TI only mode for characterization) bypass mode (TI only mode for characterization)
Figure 6-307. RX HD2 vs DSA Setting and Channel at 0.8 GHz Figure 6-308. RX HD2 vs DSA Setting and Temperature at 0.8
GHz
-61 -69
-40 qC, DSA=4dB 25 qC, DSA=12dB 1RX 3RX
-66 -40 qC, DSA=12dB 110 qC, DSA=4dB 2RX 4RX
25 qC, DSA=4dB 110 qC, DSA=12dB -74
-71
HD2 (dBFS)

HD3 (dBc)

-79
-76

-81
-84

-86
-89
-91

-96 -94
-30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 3 5 7 9 11 13 15 17 18
Input Amplitude (dBFS) DSA (dB)

With 0.8 GHz matching, measured after HD2 trim, DDC With 0.8 GHz matching, DDC bypass mode (TI only mode for
bypass mode (TI only mode for characterization) characterization)
Figure 6-309. RX HD2 vs Input Level and Temperature at 0.8 Figure 6-310. RX HD3 vs DSA Setting and Channel at 0.8 GHz
GHz
-69 -70
-40qC 1RX 3RX
25qC -75 2RX 4RX
-72 110qC
-80

-75 -85
HD3 (dBFS)
HD3 (dBc)

-90
-78
-95

-81 -100

-105
-84
-110

-87 -115
3 6 9 12 15 18 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0
DSA (dB) Input Amplitude (dBFS)

With 0.8 GHz matching, DDC bypass mode (TI only mode for With 0.8 GHz matching, DDC bypass mode (TI only mode for
characterization) characterization)
Figure 6-311. RX HD3 vs DSA Setting and Temperature at 0.8 Figure 6-312. RX HD3 vs Input Level and Channel at 0.8 GHz
GHz

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6.12.8 RX Typical Characteristics at 800 MHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-65 100
-70 1RX 3RX
2RX 4RX
-75

Non HD2/3 SFDR (dBFS)

-80 95
-85
HD3 (dBFS)

-90
-95 90
-100
-105
-110 85
-115 -40 qC, DSA=4dB 25 qC, DSA=12dB
-40 qC, DSA=12dB 110 qC, DSA=4dB
-120 25 qC, DSA=4dB 110 qC, DSA=12dB
-125 80
-30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 0 2 4 6 8 10 12 14 16
Input Amplitude (dBFS) DSA (dB)

With 0.8 GHz matching, DDC bypass mode (TI only mode for With 0.8 GHz matching
characterization) .
Figure 6-313. RX HD3 vs Input Level and Temperature at 0.8 Figure 6-314. RX Non-HD2/3 vs DSA Setting at 0.8 GHz
GHz
-80 -94
1RX 3RX 1RX 3RX
2RX 4RX -96 2RX 4RX
-82
-98
-84
-100
IMD3 (dBFS)

IMD5 (dBFS)

-86 -102

-88 -104

-106
-90
-108
-92
-110

-94 -112
MIN TYP MAX MIN TYP MAX
Supply Voltage Supply Voltages

With 0.8 GHz matching, –7 dBFS each tone, 20-MHz tone With 0.8 GHz matching, –7 dBFS each tone, 20-MHz tone
spacing, all supplies at MIN, TYP, or MAX recommended spacing, all supplies at MIN, TYP, or MAX recommended
operating voltages operating voltages
Figure 6-315. RX IMD3 vs Supply and Channel at 0.8 GHz Figure 6-316. RX IMD5 vs Supply and Channel at 0.8 GHz
-154
-154.2
-154.4
-154.6
NSD (dBFS)

-154.8
-155
-155.2
-155.4
-155.6
-155.8 1RX 3RX
2RX 4RX
-156
MIN TYP MAX
Supply Voltages

With 0.8 GHz matching, 12.5-MHz offset, all supplies at MIN, TYP, or MAX recommended operating voltages
Figure 6-317. RX Noise Spectral Density vs Supply and Channel at 0.8 GHz

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6.12.9 RX Typical Characteristics at 1.75 GHz – 1.9 GHz

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
0.6 0.3
DSA=4dB DSA=10dB
0.4 DSA=6dB DSA=12dB 0.2
DSA=8dB DSA=14dB
Relative Input Power (dB)

0.1
0.2

Input FS (dB)
0
0
-0.1
-0.2
-0.2
-0.4
-0.3 1RX
2RX
-0.6 -0.4 3RX
4RX
-0.8 -0.5
1650 1750 1850 1950 2050 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Output Frequency (MHz) Temperature (qC)

With 1.8 GHz matching, normalized to 1.75 GHz With 1.8 GHz matching, normalized to fullscale at 25°C for
. each channel
Figure 6-318. RX In-Band Gain Flatness, fIN = 1750 MHz Figure 6-319. RX Input Fullscale vs Temperature and Channel at
1.75 GHz
25 0.15

20 Uncalibrated Differential Gain Error (dB) 0.1

15 0.05
Input Phase (degree)

10 0

5 -0.05

0 -0.1

-5 -0.15
-10 1RX -0.2
2RX
-15 3RX -0.25 1RX 3RX
4RX 2RX 4RX
-20 -0.3
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 0 5 10 15 20 25
Temperature (qC) DSA (dB)
With 2.6 GHz matching, normalized to phase at 25°C With 1.8 GHz matching
. Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA
. Setting) + 1
Figure 6-320. RX Input Phase vs Temperature and DSA at fIN = Figure 6-321. RX Uncalibrated Differential Amplitude Error vs
1.75 GHz DSA Setting at 1.75 GHz
0.03 0.1
1RX 3RX
Uncalibrated Integrated Gain Error (dB)
Calibrated Differential Gain Error (dB)

0.025
2RX 4RX -0.1
0.02
0.015 -0.3
0.01
0.005 -0.5

0
-0.7
-0.005
-0.01 -0.9
1RX
-0.015 2RX
-1.1 3RX
-0.02
4RX
-0.025 -1.3
0 5 10 15 20 25 0 5 10 15 20 25
DSA (dB) DSA (dB)

With 1.8 GHz matching With 1.8 GHz matching

Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA
Setting) + 1 Setting = 0) + (DSA Setting)
Figure 6-322. RX Calibrated Differential Amplitude Error vs DSA Figure 6-323. RX Uncalibrated Integrated Amplitude Error vs
Setting at 1.75 GHz DSA Setting at 1.75 GHz

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6.12.9 RX Typical Characteristics at 1.75 GHz – 1.9 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
0.016 1

Uncalibrated Differential Phase Error (deg)

0.014 1RX 3RX
Calibrated Integrated Gain Error (dB)

2RX 4RX
0.012 0.5
0.01
0.008 0
0.006
0.004 -0.5
0.002
0 -1
-0.002
-0.004 -1.5
1RX 3RX
-0.006 2RX 4RX
-0.008 -2
0 5 10 15 20 25 0 5 10 15 20 25
DSA (dB) DSA (dB)

With 1.8 GHz matching With 1.8 GHz matching

Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA Differential Phase Error = PhaseIN(DSA Setting – 1) –
Setting = 0) + (DSA Setting) PhaseIN(DSA Setting)

Figure 6-324. RX Calibrated Integrated Amplitude Error vs DSA Figure 6-325. RX Uncalibrated Differential Phase Error vs DSA
Setting at 1.75 GHz Setting at 1.75 GHz
0.5 1
Uncalibrated Integrated Phase Error (deg)
Calibrated Differential Phase Error (deg)

0
-1
0.2
-2
-3
-0.1 -4
-5
-0.4 -6
-7
1RX -8 1RX
-0.7 2RX 2RX
-9
3RX 3RX
4RX -10 4RX
-1 -11
0 5 10 15 20 25 0 5 10 15 20 25
DSA (dB) DSA (dB)

With 1.8 GHz matching With 1.8 GHz matching

Differential Phase Error = PhaseIN(DSA Setting – 1) – Integrated Phase Error = Phase(DSA Setting) – Phase(DSA
PhaseIN(DSA Setting) Setting = 0)
Figure 6-326. RX Calibrated Differential Phase Error vs DSA Figure 6-327. RX Uncalibrated Integrated Phase Error vs DSA
Setting at 1.75 GHz Setting at 1.75 GHz
1 0
Calibrated Integrated Phase Error (deg)

-10 SNR = 60.9dBFS

-20
0.5
-30
Amplitude (dBFS)

-40
0 -50
-60
-0.5 -70
-80
1RX -90
-1 2RX -100
3RX
4RX -110
-1.5 -120
0 5 10 15 20 25 -250 -200 -150 -100 -50 0 50 100 150 200 250
DSA (dB) Output Frequency (MHz)
With 1.8 GHz matching With 1.8 GHz matching, fIN = 2610 MHz, AIN= –3 dBFS
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA .
Setting = 0) .
Figure 6-328. RX Calibrated Integrated Phase Error vs DSA Figure 6-329. RX Output FFT at 1.75 GHz
Setting at 1.75 GHz

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6.12.9 RX Typical Characteristics at 1.75 GHz – 1.9 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-154.6 -145
-146 -40 qC, DSA = 4dB
-154.8 -40 qC, DSA = 12dB
-147 25 qC, DSA = 4dB
-148 25 qC, DSA = 12dB
-155 110 qC, DSA = 4dB
Noise (dBFS/Hz)

Noise (dBFS/Hz)
-149 110 qC, DSA = 12dB
-155.2 -150
-151
-155.4 -152
-153
-155.6
-154

-155.8 -155
DSA = 4dB
DSA = 12dB -156
-156 -157
-40 -25 -10 5 20 35 50 65 80 95 110 -30 -25 -20 -15 -10 -5 0
Temperature (qC) Input Amplitude (dBFS)

With 1.8 GHz matching, 12.5-MHz offset from tone With 1.8 GHz matching, DSA Setting = 12 dB, 12.5-MHz offset
. from tone
Figure 6-330. RX Noise Spectral Density vs Temperature at 1.75 Figure 6-331. RX Noise Spectral Density vs Input Amplitude and
GHz Temperature at 1.75 GHz
-145 -70
-146 1RX, DSA = 4dB -72 -40 qC
1RX, DSA = 12dB 25 qC
-147 2RX, DSA = 4dB -74 110qC
-148 2RX, DSA = 12dB -76
3RX, DSA = 4dB
Noise (dBFS/Hz)

-149 3RX, DSA = 12dB -78

IMD3 (dBFS)

-150 4RX, DSA = 4dB -80

-151 4RX, DSA = 12dB -82
-152 -84
-153 -86
-154 -88
-155 -90
-156 -92
-157 -94
-30 -25 -20 -15 -10 -5 0 0 2 4 6 8 10 12 14 16 18 20
Input Amplitude (dBFS) DSA (dB)

With 1.8 GHz matching, 12.5-MHz offset from tone With 1.8 GHz matching, each tone –7 dBFS, tone spacing =
. 20 MHz
Figure 6-332. RX Noise Spectral Density vs Input Amplitude and Figure 6-333. RX IMD3 vs DSA Setting and Temperature at 1.75
Channel at 1.75 GHz GHz
-88 -80
-40 qC -40 qC
-92 25 qC -85 25 qC
110qC 110qC
-96 -90

-100 -95
IMD3 (dBFS)

IMD3 (dBFS)

-104 -100

-108 -105

-112 -110

-116 -115

-120 -120

-124 -125
-36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6 -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6
Input Amplitude (dBFS) Input Amplitude (dBFS)

With 1.8 GHz matching, tone spacing = 20 MHz, DSA = 4 dB With 1.8 GHz matching, tone spacing = 20 MHz, DSA = 12 dB
Figure 6-334. RX IMD3 vs Input Level and Temperature at 1.75 Figure 6-335. RX IMD3 vs Input Level and Temperature at 1.75
GHz GHz

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6.12.9 RX Typical Characteristics at 1.75 GHz – 1.9 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-75 -72
1RX 3RX -40qC 110qC
2RX 4RX 25qC
-80 -77

-85 -82
HD2 (dBc)

HD2 (dBc)
-90 -87

-95 -92

-100 -97

-105 -102
3 5 7 9 11 13 15 17 19 3 5 7 9 11 13 15 17 19
DSA (dB) DSA (dB)

With 1.8 GHz matching, fin = 1900MHz, measured after HD2 With 1.8 GHz matching, fin = 1900MHz, measured after HD2
trim, DDC bypass mode (TI only mode for characterization) trim, DDC bypass mode (TI only mode for characterization)
Figure 6-336. RX HD2 vs DSA Setting and Channel at 1.9 GHz Figure 6-337. RX HD2 vs DSA Setting and Temperature at 1.9
GHz
-75 -74
1RX, DSA=4dB 3RX, DSA=4dB -40 qC, DSA=4dB 25 qC, DSA=12dB
-80 1RX, DSA=12dB 3RX, DSA=12dB -79 -40 qC, DSA=12dB 110 qC, DSA=4dB
-85 2RX, DSA=4dB 4RX, DSA = 4dB 25 qC, DSA=4dB 110 qC, DSA=12dB
2RX, DSA=12dB 4RX, DSA = 12dB -84
-90
-89
HD2 (dBFS)

HD2 (dBFS)

-95
-100 -94
-105 -99
-110
-104
-115
-120 -109

-125 -114
-30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0
Input Amplitude (dBFS) Input Amplitude (dBFS)

With 1.8 GHz matching, fin = 1900MHz, measured after HD2 With 1.8 GHz matching, fin = 1900MHz, measured after HD2
trim, DDC bypass mode (TI only mode for characterization) trim, DDC bypass mode (TI only mode for characterization)
Figure 6-338. RX HD2 vs Input Amplitude and Channel at 1.9 Figure 6-339. RX HD2 vs Input Amplitude and Temperature at
GHz 1.9 GHz
-65 -65
1RX 3RX -40qC
-70 2RX 4RX 25qC
-70 110qC
-75
-75
-80
HD3 (dBc)

HD3 (dBc)

-85 -80

-90
-85
-95
-90
-100

-105 -95
3 5 7 9 11 13 15 17 19 3 5 7 9 11 13 15 17 19
DSA (dB) DSA (dB)

With 1.8 GHz matching, fin = 1900MHz, DDC bypass mode (TI With 1.8 GHz matching, fin = 1900MHz, DDC bypass mode (TI
only mode for characterization) only mode for characterization)
Figure 6-340. RX HD3 vs DSA Setting and Channel at 1.9 GHz Figure 6-341. RX HD3 vs DSA Setting and Temperature at 1.9
GHz

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6.12.9 RX Typical Characteristics at 1.75 GHz – 1.9 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-50 -65
1RX, DSA=4dB 3RX, DSA=4dB -40 qC, DSA=4dB 25 qC, DSA=12dB
1RX, DSA=12dB 3RX, DSA=12dB -70 -40 qC, DSA=12dB 110 qC, DSA=4dB
-60
2RX, DSA=4dB 4RX, DSA = 4dB -75 25 qC, DSA=4dB 110 qC, DSA=12dB
2RX, DSA=12dB 4RX, DSA = 12dB
-70 -80
HD3 (dBFS)

HD3 (dBFS)
-85
-80
-90
-90
-95

-100 -100
-105
-110
-110
-120 -115
-30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0
Input Amplitude (dBFS) Input Amplitude (dBFS)

With 1.8 GHz matching, fin = 1900MHz, DDC bypass mode (TI With 1.8 GHz matching, fin = 1900MHz, DDC bypass mode (TI
only mode for characterization) only mode for characterization)
Figure 6-342. RX HD3 vs Input Level and Channel at 1.9 GHz Figure 6-343. RX HD3 vs Input Level and Temperature at 1.9
GHz
95 81
1RX 3RX
80.8 2RX 4RX
90
80.6
Non HD2/3 SFDR (dBFS)
Inband SFDR (dBFS/Hz)

80.4
85
80.2
80 80
79.8
75
79.6
1RX,
2RX 79.4
70
3RX 79.2
4RX
65 79
-30 -25 -20 -15 -10 -5 0 0 2 4 6 8 10 12 14 16
Input Amplitude (dBFS) DSA (dB)

With 1.8 GHz matching, decimated by 3 With 1.8 GHz matching

Figure 6-344. RX In-Band SFDR (±400 MHz) vs Input Amplitude Figure 6-345. RX Non-HD2/3 vs DSA Setting at 1.75 GHz
at 1.75 GHz
-84 -151
1RX 3RX
-86 2RX 4RX -151.5
-88 -152
-90 -152.5
IMD3 (dBFS)

NSD (dBFS)

-92 -153
-94 -153.5
-96 -154
-98 -154.5
-100 -155
-102 -155.5 1RX 3RX
2RX 4RX
-104 -156
MIN TYP MAX MIN TYP MAX
Supply Voltage Supply Voltages

With 1.8 GHz matching, –7 dBFS each tone, 20-MHz tone With 1.8 GHz matching, 12.5-MHz offset, all supplies at MIN,
spacing, all supplies at MIN, TYP, or MAX recommended TYP, or MAX recommended operating voltages
operating voltages .
Figure 6-346. RX IMD3 vs Supply and Channel at 1.75 GHz Figure 6-347. RX Noise Spectral Density vs Supply and Channel
at 1.75 GHz

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6.12.10 RX Typical Characteristics at 2.6 GHz

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
2 2
DSA=4dB
1.5 DSA=6dB 1.5
DSA=8dB
Relative Input Power (dB)

1 DSA=10dB 1
DSA=12dB

Input Fullscale (dB)

0.5 DSA=14dB 0.5

0 0

-0.5 -0.5

-1 -1 1RX
2RX
-1.5 -1.5 3RX
4RX
-2 -2
2350 2400 2450 2500 2550 2600 2650 2700 2750 2800 -40 -20 0 20 40 60 80 100 120
Input Frequency (MHz) Temperature (qC)

With matching, normalized to power at 2.6 GHz for each DSA With 2.6 GHz matching, normalized to fullscale at 25°C for
setting each channel
Figure 6-348. RX Inband Gain Flatness, fIN = 2600 MHz Figure 6-349. RX Input Fullscale vs Temperature and Channel at
2.6 GHz

Uncalibrated Differential Amplitude Error (dB)

40 0.3
1RX 3RX
30 2RX 4RX
0.2
20
Input Phase (degrees)

10
0.1
0
-10 0
-20
-0.1
-30 DSA=0dB DSA=10dB DSA=20dB
DSA=2dB DSA=12dB DSA=22dB
-40 DSA=4dB DSA=14dB DSA=24dB -0.2
-50 DSA=6dB DSA=16dB
DSA=8dB DSA=18dB
-60 -0.3
-40 -20 0 20 40 60 80 100 120 0 2 4 6 8 10 12 14 16 18 20 22 2425
Temperature (qC) DSA Setting (dB)

With 2.6 GHz matching, normalized to phase at 25°C With 2.6 GHz matching
. Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA
. Setting) + 1
Figure 6-350. RX Input Phase vs Temperature and DSA at fOUT = Figure 6-351. RX Uncalibrated Differential Amplitude Error vs
2.6 GHz DSA Setting at 2.6 GHz
0.1 2
Uncalibrated Integrated Amplitude Error (dB)
Calibrated Differential Amplitude Error (dB)

1RX 1RX
0.08 2RX 1.5 2RX
0.06 3RX 3RX
4RX 1 4RX
0.04
0.02 0.5

0 0
-0.02 -0.5
-0.04
-1
-0.06
-0.08 -1.5

-0.1 -2
0 2 4 6 8 10 12 14 16 18 20 22 2425 0 2 4 6 8 10 12 14 16 18 20 22 24
DSA Setting (dB) DSA Setting (dB)

With 2.6 GHz matching With 2.6 GHz matching

Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA
Setting) + 1 Setting = 0) + (DSA Setting)
Figure 6-352. RX Calibrated Differential Amplitude Error vs DSA Figure 6-353. RX Uncalibrated Integrated Amplitude Error vs
Setting at 2.6 GHz DSA Setting at 2.6 GHz

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6.12.10 RX Typical Characteristics at 2.6 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
0.1 3

Uncalibrated Differential Phase Error (deg)

Calibrated Integrated Amplitude Error (dB)

2.5 1RX
0.08 2RX
2 3RX
0.06
1.5 4RX
0.04
1
0.02 0.5
0 0
-0.02 -0.5
-1
-0.04
1RX -1.5
-0.06 2RX -2
-0.08 3RX
4RX -2.5
-0.1 -3
0 2 4 6 8 10 12 14 16 18 20 22 24 0 2 4 6 8 10 12 14 16 18 20 22 24 26
DSA Setting (dB) DSA Setting (dB)

With 2.6 GHz matching With 2.6 GHz matching

Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA Differential Phase Error = PhaseIN(DSA Setting – 1) –
Setting = 0) + (DSA Setting) PhaseIN(DSA Setting)
Figure 6-354. RX Calibrated Integrated Amplitude Error vs DSA Figure 6-355. RX Uncalibrated Differential Phase Error vs DSA
Setting at 2.6 GHz Setting at 2.6 GHz
3 10

Uncalibrated Integrated Phase Error (deg)

Calibrated Differential Phase Error (deg)

2.5 1RX 1RX

2RX 8 2RX
2 3RX 3RX
6
1.5 4RX 4RX
4
1
0.5 2
0 0
-0.5 -2
-1
-4
-1.5
-6
-2
-2.5 -8
-3 -10
0 2 4 6 8 10 12 14 16 18 20 22 24 26 0 2 4 6 8 10 12 14 16 18 20 22 24
DSA Setting (dB) DSA Setting (dB)

With 2.6 GHz matching With 2.6 GHz matching

Differential Phase Error = PhaseIN(DSA Setting – 1) – Integrated Phase Error = Phase(DSA Setting) – Phase(DSA
PhaseIN(DSA Setting) Setting = 0)
Figure 6-356. RX Calibrated Differential Phase Error vs DSA Figure 6-357. RX Uncalibrated Integrated Phase Error vs DSA
Setting at 2.6 GHz Setting at 2.6 GHz
10 0
1RX
Calibrated Integrated Phase Error (deg)

8 -10 SNR=62.5dBFS
2RX
3RX -20
6
4RX -30
4
Amplitude (dBFS)

-40
2 -50
0 -60
-2 -70
-80
-4
-90
-6
-100
-8 -110
-10 -120
0 2 4 6 8 10 12 14 16 18 20 22 24 -250 250
DSA Setting (dB) Frequency (MHz)

With 2.6 GHz matching With 2.6 GHz matching, fIN = 2610 MHz, AIN= –3 dBFS
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA .
Setting = 0) .
Figure 6-358. RX Calibrated Integrated Phase Error vs DSA Figure 6-359. RX Output FFT at 2.6 GHz
Setting at 2.6 GHz

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6.12.10 RX Typical Characteristics at 2.6 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-152 -150
DSA = 4
-152.5 DSA = 12

Noise Spectral Density (dBFS/Hz)

-151
-153
-152
-153.5
NSD (dBFS)

-154 -153

-154.5
-154
-155
-155 -40qC
-155.5 25qC
105qC
-156 -156
-40 -20 0 20 40 60 80 100 120 -30 -25 -20 -15 -10 -5 0
Temperature (qC) Input Amplitude (dBFS)

With 2.6 GHz matching, 12.5-MHz offset from tone With 2.6 GHz matching, DSA Setting = 12 dB, 12.5-MHz offset
. from tone
Figure 6-360. RX Noise Spectral Density vs Temperature at 2.6 Figure 6-361. RX Noise Spectral Density vs Input Amplitude and
GHz Temperature at 2.6 GHz
-146 -60
1RX, DSA=4 3RX, DSA=4 Temp=-40qC
1RX, DSA=12 3RX, DSA=12 Temp=25qC
2RX, DSA=4 4RX, DSA=4 -65 Temp=110qC
-148
2RX, DSA=12 4RX, DSA=12
-70
NSD (dBFS/Hz)

IMD3 (dBFS)
-150
-75
-152
-80

-154
-85

-156 -90
-30 -25 -20 -15 -10 -5 0 0 2 4 6 8 10 12 14 16
Input Amplitude (dBFS) DSA Setting (dB)

With 2.6 GHz matching, 12.5-MHz offset from tone With 2.6 GHz matching, each tone –7 dBFS, tone spacing =
. 20 MHz
Figure 6-362. RX Noise Spectral Density vs Input Amplitude and Figure 6-363. RX IMD3 vs DSA Setting and Temperature at 2.6
Channel at 2.6 GHz GHz
-70 -75
-75 -80
-80 -85
-85 -90
IMD3 (dBFS)

IMD3 (dBFS)

-90 -95
-95 -100
-100 -105
-105 -110
-110 Temp=-40qC -115 Temp=-40qC
-115 Temp=25qC -120 Temp=25qC
Temp=110qC Temp=110qC
-120 -125
-40 -35 -30 -25 -20 -15 -10 -5 0 -40 -35 -30 -25 -20 -15 -10 -5 0
Input Level (dBFS) Input Level (dBFS)

With 2.6 GHz matching, tone spacing = 20 MHz, DSA = 4 dB With 2.6 GHz matching, tone spacing = 20 MHz, DSA = 12 dB
Figure 6-364. RX IMD3 vs Input Level and Temperature at 2.6 Figure 6-365. RX IMD3 vs Input Level and Temperature at 2.6
GHz GHz

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6.12.10 RX Typical Characteristics at 2.6 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-60 -70
Temp=-40qC
-65 -75 Temp=25qC
Temp=110qC
-70 -80

-75 -85

HD2 (dBFS)
HD2 (dBc)

-80 -90

-85 -95

-90 1RX -100

2RX
-95 3RX -105
4RX
-100 -110
2 4 6 8 10 12 14 16 18 20 -30 -25 -20 -15 -10 -5 0
DSA Setting (dB) Input Level (dBFS)

With 2.6 GHz matching, DDC bypass mode (TI only mode for With 2.6 GHz matching, DDC bypass mode (TI only mode for
characterization) characterization)
Figure 6-366. RX HD2 vs DSA Setting and Channel at 2.6 GHz Figure 6-367. RX HD2 vs Input Level and Temperature at 2.6
GHz
-60 -60

-65 -65

-70 -70

-75 -75
HD3 (dBc)

HD3 (dBc)

-80 -80

-85 -85

-90 1RX -90

2RX Temp=-40qC
-95 3RX -95 Temp=-25qC
4RX Temp=110qC
-100 -100
2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 16 18
DSA Setting (dB) DSA Setting (dBc)

With 2.6 GHz matching, DDC bypass mode (TI only mode for With 2.6 GHz matching, DDC bypass mode (TI only mode for
characterization) characterization)
Figure 6-368. RX HD3 vs DSA Setting and Channel at 2.6 GHz Figure 6-369. RX HD3 vs DSA Setting and Temperature at 2.6
GHz
-60 -60
1RX Temp=-40qC
-65 2RX -65 Temp=25qC
-70 3RX -70 Temp=110qC
4RX
-75 -75
HD3 (dBFS)

HD3 (dBFS)

-80 -80
-85 -85
-90 -90
-95 -95
-100 -100
-105 -105
-110 -110
-30 -25 -20 -15 -10 -5 0 -30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS) Input Level (dBFS)

With 2.6 GHz matching, DDC bypass mode (TI only mode for With 2.6 GHz matching, DDC bypass mode (TI only mode for
characterization) characterization)
Figure 6-370. RX HD3 vs Input Level and Channel at 2.6 GHz Figure 6-371. RX HD3 vs Input Level and Temperature at 2.6
GHz

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6.12.10 RX Typical Characteristics at 2.6 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
110 110
1RX
105 2RX 105
3RX
100 4RX 100

In-band SFDR (dBFS)

SFDR (dBFS)

95 95

90 90

85 85

80 80 1RX
2RX
75 75 3RX
4RX
70 70
2500 2525 2550 2575 2600 2625 2650 2675 2700 2500 2525 2550 2575 2600 2625 2650 2675 2700
Input Frequency (MHz) Input Frequency (dBc)

With 2.6 GHz matching With 2.6 GHz matching

Figure 6-372. RX In-Band SFDR (±200 MHz) vs Frequency With Figure 6-373. RX In-Band SFDR (±200 MHz) vs Frequency With
AIN= –1 dBFS at 2.6 GHz AIN= –6 dBFS at 2.6 GHz
110 106
DSA=4
105 104 DSA=12
102
100

In-band SFDR (dBFS)

In-band SFDR (dBFS)

100
95 98
90 96

85 94
92
80 1RX
2RX 90
75 3RX 88
4RX
70 86
2500 2525 2550 2575 2600 2625 2650 2675 2700 -30 -25 -20 -15 -10 -5 0
Input Frequency (MHz) Input Amplitude (dBFS)

With 2.6 GHz matching With 2.6 GHz matching

Figure 6-374. RX In-Band SFDR (±200 MHz) vs Frequency With Figure 6-375. RX In-Band SFDR (±200 MHz) vs Input Amplitude
AIN= –12 dBFS at 2.6 GHz at 2.6 GHz
100 100
-40qC -40qC
98 25qC 98 25qC
96 105qC 96 105qC
In-band SFDR (dBFS)

Inband SFDR (dBFS)

94 94
92 92
90 90
88 88
86 86
84 84
82 82
80 80
-30 -25 -20 -15 -10 -5 0 -30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS) Input Amplitude (dBFS)

With 2.6 GHz matching With 2.6 GHz matching, decimate by 8, DSA Setting = 12 dB
Figure 6-376. RX In-Band SFDR (±200 MHz) vs Input Amplitude Figure 6-377. RX Inband SFDR (±150 MHz) vs Input Amplitude
and Temperature at 2.6 GHz and Temperature at 2.6 GHz

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6.12.10 RX Typical Characteristics at 2.6 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
100 -80
-40qC
25qC -82
95 105qC -84

non-HD2/3 SFDR (dBFS)

In-band SFDR (dBFS)

-86
90
-88

85 -90
-92
80
-94
-96
75
-98

70 -100
-30 -25 -20 -15 -10 -5 0 0 2 4 6 8 10 12 14 16 18
Input Amplitude (dBFS) DSA Setting (dB)

With 2.6 GHz matching, decimate by 4 With 2.6 GHz matching

Figure 6-378. RX In-Band SFDR (±300 MHz) vs Input Amplitude Figure 6-379. RX Non-HD2/3 vs DSA Setting at 2.6 GHz
and Temperature at 2.6 GHz
-70 -150
1RX 1RX
-72 2RX -150.5 2RX
3RX 3RX
-74
4RX -151 4RX
-76
NSD (dBFS/Hz)

-151.5
IMD3 (dBFS)

-78
-80 -152

-82 -152.5

-84 -153
-86
-153.5
-88
-154
-90 MIN TYP MAX
MIN TYP MAX Supply Voltages
Supply Voltages
With 2.6 GHz matching, 12.5-MHz offset, all supplies at MIN,
With 2.6 GHz matching, –7 dBFS each tone, 20-MHz tone
TYP, or MAX recommended operating voltages
spacing, all supplies at MIN, TYP, or MAX recommended
.
operating voltages
Figure 6-381. RX Noise Spectral Density vs Supply and Channel
Figure 6-380. RX IMD3 vs Supply and Channel at 2.6 GHz at 2.6 GHz

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6.12.11 RX Typical Characteristics at 3.5 GHz

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
2 70
DSA=4dB 60
1.5 DSA=6dB 50
DSA=8dB
40
Relative Input Power (dB)

1 DSA=10dB

Input Phase (degrees)

DSA=12dB 30
0.5 DSA=14dB 20
10
0 0
-10
-0.5 -20
-30 DSA=0dB DSA=10dB DSA=20dB
-1 DSA=2dB DSA=12dB DSA=22dB
-40
DSA=4dB DSA=14dB DSA=24dB
-1.5 -50 DSA=6dB DSA=16dB
-60 DSA=8dB DSA=18dB
-2 -70
3400 3450 3500 3550 3600 3650 3700 3750 3800 -30 -10 10 30 50 70 90 110 120
Input Frequency (MHz) Temperature (qC)

With 3.6 GHz matching, normalized to 3.6 GHz With 3.6 GHz matching, normalized to phase at 25°C
Figure 6-382. RX In-Band Gain Flatness, fIN = 3600 MHz Figure 6-383. RX Input Phase vs Temperature at 3.6 GHz
0.5 0.1
-40qC -40qC

Amplitude Differential Nonlinearity (dB)

0.4 25qC 0.08 25qC
Differential Amplitude Error (dB)

0.3 105qC 0.06 105qC

0.2 0.04
0.1 0.02
0 0
-0.1 -0.02
-0.2 -0.04
-0.3 -0.06
-0.4 -0.08
-0.5 -0.1
0 5 10 15 20 25 0 5 10 15 20 25
DSA Setting (dB) DSA Setting (dB)

With 3.6 GHz matching With 3.6 GHz matching

Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA
Setting) + 1 Setting) + 1
Figure 6-384. RX Uncalibrated Differential Amplitude Error vs Figure 6-385. RX Calibrated Differential Amplitude Error vs DSA
DSA Setting at 3.6 GHz Setting at 3.6 GHz
4 1
-40qC
3.5 0.8 25qC
Integrated Amplitude Error (dB)

Integrated Amplitude Error (dB)

3 0.6 105qC

2.5 0.4
2 0.2
1.5 0
1 -0.2
0.5 -0.4
0 -40qC -0.6
-0.5 25qC -0.8
105qC
-1 -1
0 5 10 15 20 25 0 5 10 15 20 25
DSA Setting (dB) DSA Setting (dB)

With 3.6 GHz matching With 3.6 GHz matching

Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA
Setting = 0) + (DSA Setting) Setting = 0) + (DSA Setting)
Figure 6-386. RX Uncalibrated Integrated Amplitude Error vs Figure 6-387. RX Calibrated Integrated Amplitude Error vs DSA
DSA Setting at 3.6 GHz Setting at 3.6 GHz

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6.12.11 RX Typical Characteristics at 3.5 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
2 2.5
-40qC -40qC
1.5 25qC 2 25qC
105qC 1.5 105qC
Differential Phase Error (q)

Differential Phase Error (q)

1
1
0.5 0.5
0 0

-0.5 -0.5
-1
-1
-1.5
-1.5 -2
-2 -2.5
0 5 10 15 20 25 0 5 10 15 20 25
DSA Setting (dB) DSA Setting (dB)

With 3.6 GHz matching With 3.6 GHz matching

Differential Phase Error = PhaseIN(DSA Setting – 1) – Differential Phase Error = PhaseIN(DSA Setting – 1) –
PhaseIN(DSA Setting) PhaseIN(DSA Setting)
Figure 6-388. RX Uncalibrated Phase Error vs DSA Setting at Figure 6-389. RX Calibrated Differential Phase Error vs DSA
3.6 GHz Setting at 3.6 GHz
5 2.5
-40qC
4 2 25qC
Phase Integrated Nonlinearity (q)

3 Integrated Phase Error (q) 1.5 105qC

2 1
1 0.5
0 0
-1 -0.5
-2 -1
-3 -40qC -1.5
-4 25qC -2
105qC
-5 -2.5
0 5 10 15 20 25 0 5 10 15 20 25
DSA Setting (dB) DSA Setting (dB)

With 3.6 GHz matching With 3.6 GHz matching

Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Integrated Phase Error = Phase(DSA Setting) – Phase(DSA
Setting = 0) Setting = 0)
Figure 6-390. RX Uncalibrated Integrated Phase Error vs DSA Figure 6-391. RX Calibrated Integrated Phase Error vs DSA
Setting at 3.6 GHz Setting at 3.6 GHz
0 -60
-10 SNR=62.2dBFS Temp=-40qC
Temp=25qC
-20 -65 Temp=110qC
-30
Amplitude (dBFS)

-40 -70
IMD3 (dBFS)

-50
-60 -75
-70
-80 -80
-90
-100 -85
-110
-120 -90
-250 250 0 2 4 6 8 10 12 14 16
Frequency (MHz) DSA Setting (dB)

With 3.6 GHz matching , fIN = 3610 MHz, AIN = –3 dBFS With 3.5 GHz matching, each tone at –7 dBFS, 20-MHz tone
. spacing
Figure 6-392. RX Output FFT at 3.6 GHz Figure 6-393. RX IMD3 vs DSA Setting and Temperature at 3.6
GHz

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6.12.11 RX Typical Characteristics at 3.5 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-80 -60

-85 -65

-90 -70
IMD3 (dBFS)

-95 -75

HD2 (dBc)
-100 -80

-105 -85

-110 -90 1RX

Temp=-40qC 2RX
-115 Temp=25qC -95 3RX
Temp=110qC 4RX
-120 -100
-40 -35 -30 -25 -20 -15 -10 -5 0 2 4 6 8 10 12 14 16 18 20
DSA Setting (dB) DSA Setting (dB)

With 3.5 GHz matching, 20-MHz tone spacing With 3.5 GHz matching, DDC bypass mode (TI only mode for
. characterization)
Figure 6-394. RX IMD3 vs Input Level and Temperature at 3.6 Figure 6-395. RX HD2 vs DSA Setting and Channel at 3.6 GHz
GHz
-71 -70
-40qC 1RX
-74 25qC -75 2RX
110qC 3RX
-80 4RX
-77

-85
HD2 (dBFS)
HD2 (dBc)

-80
-90
-83
-95
-86
-100
-89
-105
-92
3 6 9 12 15 18 -110
DSA (dB) -30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
With 3.5 GHz matching, DDC bypass mode (TI only mode for
With 3.5 GHz matching, DDC bypass mode (TI only mode for
characterization)
characterization)
Figure 6-396. RX HD2 vs DSA Setting and Temperature at 3.6
Figure 6-397. RX HD2 vs Input Level and Channel at 3.6 GHz
GHz
-70 -60
Temp=-40qC
-75 Temp=25qC -65
Temp=110qC
-80 -70

-85 -75
HD2 (dBFS)

HD3 (dBc)

-90 -80

-95 -85

-100 -90 1RX

2RX
-105 -95 3RX
4RX
-110 -100
-30 -25 -20 -15 -10 -5 0 2 4 6 8 10 12 14 16 18 20
Input Level (dBFS) DSA Setting (dB)

With 3.5 GHz matching, DDC bypass mode (TI only mode for With 3.5 GHz matching, DDC bypass mode (TI only mode for
characterization) characterization)
Figure 6-398. RX HD2 vs Input Level and Temperature at 3.6 Figure 6-399. RX HD3 vs DSA Setting and Channel at 3.6 GHz
GHz

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6.12.11 RX Typical Characteristics at 3.5 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-64 -60
-40qC
25qC -65
-67 110qC
-70
-75

HD3 (dBFS)
HD3 (dBc)

-70 -80
-85
-73
-90
-95
-76 1RX
-100 2RX
-105 3RX
-79 4RX
3 6 9 12 15 18 -110
DSA (dB) -30 -25 -20 -15 -10 -5 0
Input Amplitude (dBFS)
With 3.5 GHz matching, DDC bypass mode (TI only mode for
With 3.5 GHz matching, DDC bypass mode (TI only mode for
characterization)
characterization)
Figure 6-400. RX HD3 vs DSA Setting and Temperature at 3.6
Figure 6-401. RX HD3 vs Input Level and Channel at 3.6 GHz
GHz
-70 -140
Temp=-40qC 1RX, DSA=4dB 3RX, DSA=4dB
-75 Temp=25qC -142 1RX, DSA=12dB 3RX, DSA=12dB

Noise Spectral Density (dBFS)

Temp=110qC -144 2RX, DSA=4dB 4RX, DSA=4dB
-80 2RX, DSA=12dB 4RX, DSA=12dB
-146
-85
HD3 (dBFS)

-148
-90 -150

-95 -152
-154
-100
-156
-105 -158
-110 -160
-30 -25 -20 -15 -10 -5 0 -30 -25 -20 -15 -10 -5 0
Input Level (dBFS) Input Level (dBFS)

With 3.5 GHz matching, DDC bypass mode (TI only mode for With 3.5 GHz matching, 12.5-MHz offset from tone
characterization) .
Figure 6-402. RX HD3 vs Input Level and Temperature at 3.6 Figure 6-403. RX Noise Spectral Density vs Input Level and DSA
GHz Setting at 3.6 GHz
110 90
1RX
105 2RX
3RX 85
4RX
SFDR excl. HD2/3 (dBc)

100
In-band SFDR (dBFS)

80
95

90 75

85
70
80 1RX
65 2RX
75 3RX
4RX
70 60
-30 -25 -20 -15 -10 -5 0 0 2 4 6 8 10 12 14 16 18
Input Amplitude (dBFS) DSA Setting (dB)

With 3.5 GHz matching With 3.5 GHz matching

Figure 6-404. RX In-Band SFDR (±200 MHz) vs Input Level and Figure 6-405. RX SFDR Excluding HD2/3 vs DSA Setting and
Channel at 3.6 GHz Channel at 3.6 GHz

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6.12.11 RX Typical Characteristics at 3.5 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.

-70 -90
1RX
-72 2RX -92
-74 3RX -94
4RX
-76 -96

IMD5 (dBFS)
IMD3 (dBFS)

-78 -98

-80 -100

-82 -102

-84 -104
1RX
-86 -106 2RX
-108 3RX
-88
4RX
-90 -110
MIN TYP MAX MIN TYP MAX
Supply Voltages Supply Voltages

With 3.6 GHz matching, –7 dBFS each tone, 20-MHz tone With 3.6 GHz matching, –7 dBFS each tone, 20-MHz tone
spacing, all supplies at MIN, TYP, or MAX recommended spacing, all supplies at MIN, TYP, or MAX recommended
operating voltages operating voltages

Figure 6-406. RX IMD3 vs Supply Voltage and Channel at 3.6 Figure 6-407. RX IMD5 vs Supply Voltage and Channel at 3.6
GHz GHz

-152
1RX
-152.5 2RX
3RX
-153 4RX
NSD (dBFS/Hz)

-153.5

-154

-154.5

-155

-155.5

-156
MIN TYP MAX
Supply Voltages
With 3.6 GHz matching, tone at –20 dBFS, 12.5-MHz offset frequency, all supplies at MIN, TYP, or MAX recommended operating
voltages
Figure 6-408. RX Noise Spectral Density vs Supply Voltage and Channel at 3.6 GHz

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6.12.12 RX Typical Characteristics at 4.9 GHz

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
0.6 1
DSA=4dB
0.7
0.4 DSA=6dB
DSA=8dB 0.4
Relative Input Power (dB)

DSA=10dB
0.2 DSA=12dB 0.1
DSA=14dB -0.2

Input FS (dB)
0 -0.5
-0.8
-0.2
-1.1
-0.4 -1.4
1RX
-1.7 2RX
-0.6 3RX
-2
4RX
-0.8 -2.3
4700 4800 4900 5000 5100 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Output Frequency (MHz) Temperature (qC)

With matching, normalized to power at 4.9GHz for each DSA With 4.9 GHz matching, normalized to fullscale at 25°C for
setting each channel
Figure 6-409. RX Inband Gain Flatness, fIN = 4900 MHz Figure 6-410. RX Input Fullscale vs Temperature and Channel at
4.9 GHz
65 0.15
55 Uncalibrated Differential Gain Error (dB) 0.1
45
0.05
Input Phase (degree)

35
25 0

15 -0.05
5
-0.1
-5
1RX -0.15 1RX
-15 2RX 2RX
-25 3RX -0.2 3RX
4RX 4RX
-35 -0.25
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 0 5 10 15 20 25
Temperature (qC) DSA (dB)
With 4.9 GHz matching, normalized to phase at 25°C With 4.9 GHz matching
. Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA
. Setting) + 1
Figure 6-411. RX Input Phase vs Temperature and DSA at fOUT = Figure 6-412. RX Uncalibrated Differential Amplitude Error vs
4.9 GHz DSA Setting at 4.9 GHz
0.03 1.2
1RX 3RX 1RX
Uncalibrated Integrated Gain Error (dB)
Calibrated Differential Gain Error (dB)

0.025 1
2RX 4RX 2RX
0.02 3RX
0.8 4RX
0.015
0.6
0.01
0.005 0.4
0 0.2
-0.005
0
-0.01
-0.2
-0.015
-0.02 -0.4

-0.025 -0.6
0 5 10 15 20 25 0 5 10 15 20 25
DSA (dB) DSA (dB)

With 4.9 GHz matching With 4.9 GHz matching

Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA
Setting) + 1 Setting = 0) + (DSA Setting)
Figure 6-413. RX Calibrated Differential Amplitude Error vs DSA Figure 6-414. RX Uncalibrated Integrated Amplitude Error vs
Setting at 4.9 GHz DSA Setting at 4.9 GHz

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6.12.12 RX Typical Characteristics at 4.9 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
0.05 2

Uncalibrated Differential Phase Error (deg)

1RX
Calibrated Integrated Gain Error (dB)

2RX 1.5
0.04
3RX
4RX 1
0.03
0.5
0.02 0

0.01 -0.5

-1
0
-1.5 1RX
2RX
-0.01 -2 3RX
4RX
-0.02 -2.5
0 5 10 15 20 25 0 5 10 15 20 25
DSA (dB) DSA (dB)

With 4.9 GHz matching With 4.9 GHz matching

Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA Differential Phase Error = PhaseIN(DSA Setting – 1) –
Setting = 0) + (DSA Setting) PhaseIN(DSA Setting)

Figure 6-415. RX Calibrated Integrated Amplitude Error vs DSA Figure 6-416. RX Uncalibrated Differential Phase Error vs DSA
Setting at 4.9 GHz Setting at 4.9 GHz
1.5 3
Uncalibrated Integrated Phase Error (deg)
Calibrated Differential Phase Error (deg)

1 2

0.5 1

0 0

-0.5 -1

-1 -2

-1.5 -3

-2 1RX -4 1RX
2RX 2RX
-2.5 3RX -5 3RX
4RX 4RX
-3 -6
0 5 10 15 20 25 0 5 10 15 20 25
DSA (dB) DSA (dB)

With 4.9 GHz matching With 4.9 GHz matching

Differential Phase Error = PhaseIN(DSA Setting – 1) – Integrated Phase Error = Phase(DSA Setting) – Phase(DSA
PhaseIN(DSA Setting) Setting = 0)
Figure 6-417. RX Calibrated Differential Phase Error vs DSA Figure 6-418. RX Uncalibrated Integrated Phase Error vs DSA
Setting at 4.9 GHz Setting at 4.9 GHz
1 0
Calibrated Integrated Phase Error (deg)

-10 SNR = 60dBFS

0.5
-20
0 -30
Amplitude (dBFS)

-40
-0.5
-50
-1 -60
-70
-1.5
-80
-2 1RX -90
2RX -100
-2.5 3RX -110
4RX
-3 -120
0 5 10 15 20 25 -250 -200 -150 -100 -50 0 50 100 150 200 250
DSA (dB) Output Frequency (MHz)

With 4.9 GHz matching With 4.9 GHz matching, fIN = 4910 MHz, AIN= –3 dBFS
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA .
Setting = 0) .

Figure 6-419. RX Calibrated Integrated Phase Error vs DSA Figure 6-420. RX Output FFT at 4.9 GHz
Setting at 4.9 GHz

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6.12.12 RX Typical Characteristics at 4.9 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-154.8 -145
DSA = 4dB -146 -40 qC, DSA = 4dB
DSA = 12dB -40 qC, DSA = 12dB
-155 -147 25 qC, DSA = 4dB
-148 25 qC, DSA = 12dB
110 qC, DSA = 4dB
Noise (dBFS/Hz)

Noise (dBFS/Hz)
-155.2 -149 110 qC, DSA = 12dB
-150
-155.4 -151
-152
-155.6 -153
-154
-155.8 -155
-156
-156 -157
-40 -25 -10 5 20 35 50 65 80 95 110 -30 -25 -20 -15 -10 -5 0
Temperature (qC) Input Amplitude (dBFS)
With 4.9 GHz matching, 12.5-MHz offset from tone With 4.9 GHz matching, DSA Setting = 12 dB, 12.5-MHz offset
. from tone
Figure 6-421. RX Noise Spectral Density vs Temperature at 4.9 Figure 6-422. RX Noise Spectral Density vs Input Amplitude and
GHz Temperature at 4.9 GHz
-145 -64
-146 1RX, DSA = 4dB -40 qC
1RX, DSA = 12dB 25 qC
-147 2RX, DSA = 4dB -69 110qC
-148 2RX, DSA = 12dB
3RX, DSA = 4dB
Noise (dBFS/Hz)

-149 3RX, DSA = 12dB -74

IMD3 (dBFS)

-150 4RX, DSA = 4dB

-151 4RX, DSA = 12dB -79
-152
-153 -84
-154
-155 -89
-156
-157 -94
-30 -25 -20 -15 -10 -5 0 0 2 4 6 8 10 12 14 16 18 20
Input Amplitude (dBFS) DSA (dB)

With 4.9 GHz matching, 12.5-MHz offset from tone With 4.9 GHz matching, each tone –7 dBFS, tone spacing =
. 20 MHz
Figure 6-423. RX Noise Spectral Density vs Input Amplitude and Figure 6-424. RX IMD3 vs DSA Setting and Temperature at 4.9
Channel at 4.9 GHz GHz
-80 -75
-40 qC -40 qC
-85 25 qC -80 25 qC
-90 110qC -85 110qC

-95 -90
IMD3 (dBFS)

IMD3 (dBFS)

-100 -95
-105 -100
-110 -105
-115 -110
-120 -115
-125 -120
-130 -125
-36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6 -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6
Input Amplitude (dBFS) Input Amplitude (dBFS)

With 4.9 GHz matching, tone spacing = 20 MHz, DSA = 4 dB With 4.9 GHz matching, tone spacing = 20 MHz, DSA = 12 dB
Figure 6-425. RX IMD3 vs Input Level and Temperature at 4.9 Figure 6-426. RX IMD3 vs Input Level and Temperature at 4.9
GHz GHz

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6.12.12 RX Typical Characteristics at 4.9 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-70 -70
-72 1RX -40qC
2RX -73 25qC
-74 3RX 110qC
-76 4RX -76
-78
-79
HD2 (dBc)

HD2 (dBc)
-80
-82 -82
-84
-85
-86
-88 -88
-90
-91
-92
-94 -94
0 2 4 6 8 10 12 14 16 3 6 9 12 15 18
DSA (dB) DSA (dB)

With 4.9 GHz matching, measured after HD2 trim, DDC With 4.9 GHz matching, measured after HD2 trim, DDC
bypass mode (TI only mode for characterization) bypass mode (TI only mode for characterization)
Figure 6-427. RX HD2 vs DSA Setting and Channel at 4.9 GHz Figure 6-428. RX HD2 vs DSA and Temperature at 4.9 GHz
-72 -62
-75 -40 qC 1RX
25 qC -64 2RX
-78
110qC -66 3RX
-81 4RX
-84 -68
-87
HD2 (dBFS)

HD3 (dBc)

-70
-90
-93 -72
-96
-74
-99
-102 -76
-105 -78
-108
-80
-111
-114 -82
-30 -27 -24 -21 -18 -15 -12 -9 -6 -3 -1 3 5 7 9 11 13 15 17 19
Input Amplitude (dBFS) DSA (dB)

With 4.9 GHz matching, measured after HD2 trim, DDC With 4.9 GHz matching, DDC bypass mode (TI only mode for
bypass mode (TI only mode for characterization) characterization)
Figure 6-429. RX HD2 vs Input Level and Temperature at 4.9 Figure 6-430. RX HD3 vs DSA Setting and Channel at 4.9 GHz
GHz
-62 -65
-40qC 1RX 3RX
25qC -70 2RX 4RX
-65 110qC
-75

-68 -80
HD3 (dBFS)
HD3 (dBc)

-85
-71
-90

-74 -95

-100
-77
-105

-80 -110
3 6 9 12 15 18 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 -1
DSA (dB) Input Amplitude (dBFS)

With 4.9 GHz matching, DDC bypass mode (TI only mode for With 4.9 GHz matching, DDC bypass mode (TI only mode for
characterization) characterization)
Figure 6-431. RX HD3 vs DSA Setting and Temperature at 4.9 Figure 6-432. RX HD3 vs Input Level and Channel at 4.9 GHz
GHz

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6.12.12 RX Typical Characteristics at 4.9 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 491.52MSPS
(decimate by 6), PLL clock mode with fREF = 491.52 MHz, AIN = –3 dBFS, DSA setting = 4 dB.
-66 102
-69 -40 qC 99 1RX
-72 25 qC 2RX
110qC 96 3RX
-75 4RX
93

Inband SFDR (dBFS)

-78
-81 90
HD3 (dBFS)

-84 87
-87 84
-90 81
-93 78
-96
75
-99
-102 72
-105 69
-108 66
-30 -27 -24 -21 -18 -15 -12 -9 -6 -3 -1 -30 -27 -24 -21 -18 -15 -12 -9 -6
Input Amplitude (dBFS) Input Amplitude (dBFS)

With 4.9 GHz matching, DDC bypass mode (TI only mode for With 4.9 GHz matching, decimate by 3
characterization) .
Figure 6-433. RX HD3 vs Input Level and Temperature at 4.9 Figure 6-434. RX In-Band SFDR (±400 MHz) vs Input Amplitude
GHz and Channel at 4.9 GHz
83 -70
1RX 3RX -72 1RX 3RX
82.5 2RX 4RX 2RX 4RX
-74
Non HD2/3 SFDR (dBFS)

82 -76
-78
81.5
IMD3 (dBFS)

-80
-82
81
-84
80.5 -86
-88
80
-90
79.5 -92
-94
79 -96
0 2 4 6 8 10 12 14 16 MIN TYP MAX
DSA (dB) Supply Voltage
With 4.9 GHz matching With 4.9 GHz matching, –7 dBFS each tone, 20-MHz tone
. spacing, all supplies at MIN, TYP, or MAX recommended
. operating voltages
Figure 6-435. RX Non-HD2/3 vs DSA Setting at 4.9 GHz Figure 6-436. RX IMD3 vs Supply and Channel at 4.9 GHz
-151
-151.5
-152
-152.5
NSD (dBFS)

-153
-153.5
-154
-154.5
-155
-155.5 1RX 3RX
2RX 4RX
-156
MIN TYP MAX
Supply Voltages

With 4.9 GHz matching, 12.5-MHz offset, all supplies at MIN, TYP, or MAX recommended operating voltages
Figure 6-437. RX Noise Spectral Density vs Supply and Channel at 4.9 GHz

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6.12.13 RX Typical Characteristics at 8.1GHz

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 1474.56MSPS
(decimate by 2) , External clock mode with fCLK = 11796.48MHz, AIN = –3 dBFS, DSA setting = 3 dB, 8.1GHz matching.
2 2
1 1
0 0
-1 -1
Amplitude (dB)

Amplitude (dB)
-2 -2
-3 -3
-4 -4
-5 -5
1RX DSA = 0dB DSA = 16dB
-6 2RX -6 DSA = 4dB DSA = 20dB
-7 3RX -7 DSA = 8dB DSA = 24dB
4RX DSA = 12dB
-8 -8
7400 7600 7800 8000 8200 8400 8600 8800 7400 7600 7800 8000 8200 8400 8600 8800
Input Frequency (MHz) Input Frequency (MHz)

Normalized to 8.11GHz 1RX and 3RX, Normalized to 8.11GHz

Figure 6-438. RX Amplitude vs Frequency and Channel Figure 6-439. RX Amplitude vs Frequency and DSA Setting
2 0.8

Amplitude Differential Non-linearity (dB)

1 0.6
0
0.4
-1
Amplitude (dB)

0.2
-2
-3 0

-4 -0.2
-5
DSA = 0dB DSA = 16dB -0.4
-6 DSA = 4dB DSA = 20dB no cal, -40C after cal, -40C
DSA = 8dB DSA = 24dB -0.6 no cal, 25C after cal, 25C
-7
DSA = 12dB no cal, 110C after cal, 110C
-8 -0.8
7400 7600 7800 8000 8200 8400 8600 8800 0 2 4 6 8 10 12 14 16 18 20 22 2425
Input Frequency (MHz) DSA Setting (dB)

2RX and 4RX, Normalized to 8.11GHz .

Figure 6-440. RX Amplitude vs Frequency and DSA Setting Figure 6-441. RX Amplitude Differential Nonlinearity at 8.11GHz
5
Phase Differential Non-linearity (degrees)

4
3
2
1
0
-1
-2
-3 no cal, -40C after cal, -40C
-4 no cal, 25C after cal, 25C
no cal, 110C after cal, 110C
-5
0 2 4 6 8 10 12 14 16 18 20 22 2425
DSA Setting (dB)
Figure 6-442. RX Amplitude Integrated Nonlinearity at 8.11GHz Figure 6-443. RX Phase Differential Nonlinearity at 8.11GHz

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6.12.13 RX Typical Characteristics at 8.1GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 1474.56MSPS
(decimate by 2) , External clock mode with fCLK = 11796.48MHz, AIN = –3 dBFS, DSA setting = 3 dB, 8.1GHz matching.
10 -60
no cal, -40C after cal, -40C -40C
8
Phase Differential Non-linearity (dB)

no cal, 25C after cal, 25C 25C

no cal, 110C after cal, 110C -70 110C
6
4
-80

IMD3 (dBFS)
2
0 -90

-2
-100
-4
-6 -110
-8
-10 -120
0 2 4 6 8 10 12 14 16 18 20 22 2425 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0
DSA Setting (dB) Input Amplitude per Tone (dBFS)

. 50MHz tone spacing

Figure 6-444. RX Phase Differential Nonlinearity at 8.11GHz Figure 6-445. RX IMD3 vs Input Amplitude at 8.11GHz
-50
AIN=-13dBFS, -40C AIN=-7.dBFS, -40C
-55 AIN=-13dBFS, 25C AIN=-7dBFS, 25C
-60 AIN=-13dBFS, 110C AIN=-7dBFS, 110C

-65
IMD3 (dBFS)

-70
-75
-80
-85
-90
-95
-100
0 2 4 6 8 10 12 14 16 18 20
DSA Setting (dB)

50MHz tone spacing .

Figure 6-446. RX IMD3 vs DSA Setting at 8.11GHz Figure 6-447. RX IMD3 vs Tone Spacing at 8.11GHz
-144
1RX, DSA = 3dB
-145 1RX, DSA = 12dB
-146 2RX, DSA = 3dB
2RX, DSA = 12dB
-147 3RX, DSA = 3dB
NSD (dBFS/Hz)

3RX, DSA = 12dB

-148 4RX, DSA = 3dB
-149 4RX, DSA = 12dB

-150
-151
-152
-153
-154
. -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0
Input Amplitude (dBFS)
Figure 6-448. RX NSD vs Digital Amplitude at 8.11GHz
Figure 6-449. RX NSD vs Digital Amplitude at 8.11GHz

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6.12.13 RX Typical Characteristics at 8.1GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 1474.56MSPS
(decimate by 2) , External clock mode with fCLK = 11796.48MHz, AIN = –3 dBFS, DSA setting = 3 dB, 8.1GHz matching.
-142
-144

Noise Spectral Density (dBFS/Hz)

-146
-148
-150
-152
-154
AIN=-12dBFS, -40C AIN=-1dBFS, -40C
-156 AIN=-12dBFS, 25C AIN=-1dBFS, 25C
AIN=-12dBFS, 110C AIN=-1dBFS, 110C
-158 AIN=-6dBFS, -40C
-160 AIN=-6dBFS, 25C
AIN=-6dBFS, 110C
-162
0 2 4 6 8 10 12 14 16 18 20
DSA Setting (dB)

. External clock mode

Figure 6-450. RX NSD vs DSA Setting at 8.11GHz Figure 6-451. RX NSD vs DSA Setting at 8.11GHz
-80 -40
-40C AIN=-12dBFS, -40C AIN=-1dBFS, -40C
-85 25C -50 AIN=-12dBFS, 25C AIN=-1dBFS, 25C
110C AIN=-12dBFS, 110C AIN=-1dBFS, 110C
-90 AIN=-6dBFS, -40C
-60 AIN=-6dBFS, 25C
-95 AIN=-6dBFS, 110C
HD2 (dBFS)
HD2 (dBFS)

-70
-100
-80
-105
-90
-110

-115 -100

-120 -110
-60 -50 -40 -30 -20 -10 0 0 2 4 6 8 10 12 14 16 18 20
Input Amplitude (dBFS) DSA Setting (dB)

Figure 6-452. RX HD2 vs Digital Amplitude at 8.11GHz Figure 6-453. RX HD2 vs DSA Setting at 8.11GHz
-80
-40C
-85 25C
110C
-90

-95
HD3 (dBFS)

-100

-105

-110

-115

-120
-60 -50 -40 -30 -20 -10 0
Input Amplitude (dBFS)
Figure 6-454. RX HD3 vs Digital Amplitude at 8.11GHz Figure 6-455. RX HD3 vs DSA Setting at 8.11GHz

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6.12.13 RX Typical Characteristics at 8.1GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 1474.56MSPS
(decimate by 2) , External clock mode with fCLK = 11796.48MHz, AIN = –3 dBFS, DSA setting = 3 dB, 8.1GHz matching.
-72.5 0
-40 C
-75
25 C
-77.5 110 C -20

-80
2-tone SFDR (dBFS)

Amplitude (dBFS)
-40
-82.5
-85
-60
-87.5
-90 -80
-92.5
-95 -100
-97.5
-100 -120
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -750 -500 -250 0 250 500 750
Digital Amplitude per Tone (dBFS) Frequency (MHz)

50MHz Tone Spacing External clock mode

Figure 6-456. RX 2-tone SFDR vs Digital Amplitude at 8.11GHz Figure 6-457. RX Single Tone Output FFT at 8.11GHz, -1dBFS
0 0

-20 -20
Amplitude (dBFS)

Amplitude (dBFS)
-40 -40

-60 -60

-80 -80

-100 -100

-120 -120
-750 -500 -250 0 250 500 750 -750 -500 -250 0 250 500 750
Frequency (MHz) Frequency (MHz)

External clock mode External clock mode

Figure 6-458. RX Single Tone Output FFT at 8.11GHz, -12dBFS Figure 6-459. RX Single Tone Output FFT at 8.11GHz, -30dBFS
0 0

-20 -20
Amplitude (dBFS)

Amplitude (dBFS)

-40 -40

-60 -60

-80 -80

-100 -100

-120 -120
-750 -500 -250 0 250 500 750 -750 -500 -250 0 250 500 750
Frequency (MHz) Frequency (MHz)

External clock mode External clock mode, -7dBFS each tone

Figure 6-460. RX Single Tone Output FFT at 8.11GHz, -60dBFS Figure 6-461. RX Dual Tone Output FFT at 8.11GHz

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6.12.13 RX Typical Characteristics at 8.1GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 1474.56MSPS
(decimate by 2) , External clock mode with fCLK = 11796.48MHz, AIN = –3 dBFS, DSA setting = 3 dB, 8.1GHz matching.
0

-20

Amplitude (dBFS)
-40

-60

-80

-100

-120
-750 -500 -250 0 250 500 750
Frequency (MHz)

External clock mode, -13dBFS each tone External clock mode, -30dBFS each tone
Figure 6-462. RX Dual Tone Output FFT at 8.11GHz Figure 6-463. RX Dual Tone Output FFT at 8.11GHz
0

-20
Amplitude (dBFS)

-40

-60

-80

-100

-120
-750 -500 -250 0 250 500 750
Frequency (MHz)

External clock mode, -60dBFS each tone

Figure 6-464. RX Dual Tone Output FFT at 8.11GHz

6.12.14 RX Typical Characteristics at 9.6 GHz

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 1474.56MSPS
(decimate by 2), External clock mode with fCLK = 11796.48 MHz, AIN = –3 dBFS, DSA setting = 3 dB, 9.6 GHz matching.
2.5 2.5
2 2
1.5 1.5
Input Amplitude (dB)

Input Amplitude (dB)

1 1
0.5 0.5
0 0
-0.5 -0.5 DSA=0dB
DSA=4dB
-1 -1 DSA=8dB
DSA=3dB, 1RX DSA=12dB, 1RX DSA=12dB
-1.5 DSA=3dB, 2RX DSA=12dB, 2RX -1.5 DSA=16dB
-2 DSA=3dB, 3RX DSA=12dB, 3RX -2 DSA=20dB
DSA=3dB, 4RX DSA=12dB, 4RX DSA=24dB
-2.5 -2.5
9000 9200 9400 9600 9800 10000 10200 9000 9200 9400 9600 9800 10000 10200
Input Frequency (MHz) Input Frequency (MHz)

Normalized to 9.6 GHz Normalized to 9.6 GHz

Figure 6-465. RX Input Amplitude vs Frequency Figure 6-466. RX Input Amplitude vs Frequency at 9.6 GHz

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6.12.14 RX Typical Characteristics at 9.6 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 1474.56MSPS
(decimate by 2), External clock mode with fCLK = 11796.48 MHz, AIN = –3 dBFS, DSA setting = 3 dB, 9.6 GHz matching.
0.8 5
Amplitude Differential Non-linearity (dB)

Amplitude Integral Non-linearity (dB)

0.6
3
0.4
2
0.2
1
0 0

-0.2 -1
-2
-0.4
no cal, -40C after cal, -40C -3 no cal, -40C after cal, -40C
-0.6 no cal, 25C after cal, 25C
-4 no cal, 25C after cal, 25C
no cal, 110C after cal, 110C no cal, 110C after cal, 110C
-0.8
-5
0 2 4 6 8 10 12 14 16 18 20 22 2425
0 2 4 6 8 10 12 14 16 18 20 22 2425
DSA Setting (dB)
DSA Setting (dB)
Figure 6-467. RX Amplitude Differential Non-Linearity at 9.6 GHz Figure 6-468. RX Amplitude Integrated Non-linearity at 9.6 GHz
5 10
Phase Differential Non-linearity (degrees)

4 8

Phase Differential Non-linearity (dB)

3 6

2 4

1 2

0 0

-1 -2

-2 -4

-3 -6 no cal, -40C after cal, -40C

no cal, -40C after cal, -40C
no cal, 25C after cal, 25C -8 no cal, 25C after cal, 25C
-4 no cal, 110C after cal, 110C
no cal, 110C after cal, 110C
-5 -10
0 2 4 6 8 10 12 14 16 18 20 22 2425 0 2 4 6 8 10 12 14 16 18 20 22 2425
DSA Setting (dB) DSA Setting (dB)

Figure 6-469. RX Phase Differential Non-linearity at 9.6 GHz Figure 6-470. RX Phase Integrated Non-linearity at 9.6 GHz

-60 -40
-40C AIN=-13dBFS, -40C AIN=-7.dBFS, -40C
25C AIN=-13dBFS, 25C AIN=-7dBFS, 25C
-70 110C -50 AIN=-13dBFS, 110C AIN=-7dBFS, 110C

-80 -60
IMD3 (dBFS)
IMD3 (dBFS)

-90 -70

-100 -80

-110 -90

-120 -100
-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0 2 4 6 8 10 12 14 16 18 20
Input Amplitude per Tone (dBFS) DSA Setting (dB)

. 50MHz tone spacing

Figure 6-471. RX IMD3 vs Digital Amplitude at 9.6 GHz Figure 6-472. RX IMD3 vs DSA Setting at 9.6 GHz

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6.12.14 RX Typical Characteristics at 9.6 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 1474.56MSPS
(decimate by 2), External clock mode with fCLK = 11796.48 MHz, AIN = –3 dBFS, DSA setting = 3 dB, 9.6 GHz matching.
-40 -50
AIN=-13dBFS, -40C AIN=-7.dBFS, -40C AIN=-30dBFS, -40C AIN=-13dBFS, -40C
AIN=-13dBFS, 25C AIN=-7dBFS, 25C -60 AIN=-30dBFS, 25C AIN=-13dBFS, 25C
-50 AIN=-13dBFS, 110C AIN=-7dBFS, 110C AIN=-30dBFS, 110C AIN=-13dBFS, 110C
-70
-60
-80

IMD3 (dBFS)
IMD3 (dBFS)

-70 -90

-100
-80
-110
-90
-120

-100 -130
0 2 4 6 8 10 12 14 16 18 20 0 50 100 150 200 250 300 350 400 450 500
DSA Setting (dB) Tone Spacing (MHz)

50MHz tone spacing 50MHz tone spacing

Figure 6-473. RX IMD3 vs DSA Setting at 9.6 GHz Figure 6-474. RX IMD3 vs Tone Spacing at 9.6 GHz
-144
1RX, -40C 3RX, -40C
-145 1RX, 25C 3RX, 25C
-146 1RX, 110C 3RX, 110C
2RX, -40C 4RX, -40C
-147 2RX, 25C 4RX, 25C
NSD (dBFS/Hz)

2RX, 110C 4RX, 110C

-148
-149
-150
-151
-152
-153
-154
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0
Input Amplitude (dBFS)
Figure 6-475. RX NSD vs Digital Amplitude at 9.6 GHz Figure 6-476. RX NSD vs Digital Amplitude at 9.6 GHz
-140 -80
-40C
-142 25C
-85
Noise Spectral Density (dBFS/Hz)

-144 110C
-90
-146
-95
HD2 (dBFS)

-148
-150 -100
-152
AIN=-12dBFS, -40C AIN=-1dBFS, -40C -105
-154 AIN=-12dBFS, 25C AIN=-1dBFS, 25C
AIN=-12dBFS, 110C AIN=-1dBFS, 110C -110
-156 AIN=-6dBFS, -40C
-158 AIN=-6dBFS, 25C -115
AIN=-6dBFS, 110C
-160 -120
0 2 4 6 8 10 12 14 16 18 20 -60 -50 -40 -30 -20 -10 0
DSA Setting (dB) Input Amplitude (dBFS)
Figure 6-477. RX NSD vs DSA Setting at 9.6 GHz Figure 6-478. RX HD2 vs Digital Level at 9.6 GHz

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6.12.14 RX Typical Characteristics at 9.6 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 1474.56MSPS
(decimate by 2), External clock mode with fCLK = 11796.48 MHz, AIN = –3 dBFS, DSA setting = 3 dB, 9.6 GHz matching.
-40 -50
AIN=-12dBFS, -40C AIN=-1dBFS, -40C -40C
-50 AIN=-12dBFS, 25C AIN=-1dBFS, 25C -60 25C
AIN=-12dBFS, 110C AIN=-1dBFS, 110C 110C
AIN=-6dBFS, -40C
-60 AIN=-6dBFS, 25C -70
AIN=-6dBFS, 110C
HD2 (dBFS)

HD3 (dBFS)
-70 -80

-80 -90

-90 -100

-100 -110

-110 -120
0 2 4 6 8 10 12 14 16 18 20 -60 -50 -40 -30 -20 -10 0
DSA Setting (dB) Input Amplitude (dBFS)
Figure 6-479. RX HD2 vs DSA Setting at 9.6 GHz Figure 6-480. RX HD3 vs Digital Level at 9.6 GHz
0 0
AIN=-12dBFS, -40C AIN=-1dBFS, -40C
-10 AIN=-12dBFS, 25C AIN=-1dBFS, 25C
AIN=-12dBFS, 110C AIN=-1dBFS, 110C -20
-20
AIN=-6dBFS, -40C
-30 AIN=-6dBFS, 25C

Amplitude (dBFS)
-40
AIN=-6dBFS, 110C
HD3 (dBFS)

-40
-50 -60

-60
-80
-70
-80 -100
-90
-100 -120
-750 -500 -250 0 250 500 750
0 2 4 6 8 10 12 14 16 18 20
Frequency [MHz]
DSA Setting (dB)

. –1 dBFS

Figure 6-481. RX HD3 vs DSA Setting at 9.6 GHz Figure 6-482. RX Single Tone Output FFT at 9.61 GHz

0 0

-20 -20
Amplitude (dBFS)
Amplitude (dBFS)

-40 -40

-60 -60

-80 -80

-100 -100

-120 -120
-750 -500 -250 0 250 500 750 -750 -500 -250 0 250 500 750
Frequency [MHz] Frequency (MHz)
–6 dBFS –12 dBFS.
Figure 6-483. RX Single Tone Output FFT at 9.61 GHz Figure 6-484. RX Single Tone Output FFT at 9.61 GHz

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6.12.14 RX Typical Characteristics at 9.6 GHz (continued)

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12 GHz. Default conditions: output sample rate = 1474.56MSPS
(decimate by 2), External clock mode with fCLK = 11796.48 MHz, AIN = –3 dBFS, DSA setting = 3 dB, 9.6 GHz matching.
0

-20

Amplitude (dBFS)
-40

-60

-80

-100

-120
-750 -500 -250 0 250 500 750
Frequency (MHz)

–30 dBFS –60 dBFS

Figure 6-485. RX Single Tone Output FFT at 9.61 GHz Figure 6-486. RX Single Tone Output FFT at 9.61 GHz
0 0

-20 -20
Amplitude (dBFS)

Amplitude (dBFS)
-40 -40

-60 -60

-80 -80

-100 -100

-120 -120
-750 -500 -250 0 250 500 750 -750 -500 -250 0 250 500 750
Frequency (MHz) Frequency (MHz)

9.61 GHz and 9.635 GHz, –7 dBFS each tone 9.61 GHz and 9.635 GHz, –13 dBFS each tone
Figure 6-487. RX Two Tone Output FFT at 9.61 GHz Figure 6-488. RX Two Tone Output FFT at 9.61 GHz
0 0

-20 -20
Amplitude (dBFS)

Amplitude (dBFS)

-40 -40

-60 -60

-80 -80

-100 -100

-120 -120
-750 -500 -250 0 250 500 750 -750 -500 -250 0 250 500 750
Frequency (MHz) Frequency (MHz)

9.61 GHz and 9.635 GHz, –30 dBFS each tone 9.61 GHz and 9.635 GHz, –60 dBFS each tone
Figure 6-489. RX Two Tone Output FFT at 9.61 GHz Figure 6-490. RX Two Tone Output FFT at 9.61 GHz

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6.12.15 PLL and Clock Typical Characteristics

Typical values at TA = +25°C with nominal supplies. Unless otherwise noted, fREF = 491.52 MHz, Phase noise measured at
TX output
-80
fVCO=11796.48MHz
-90 fVCO=8847.36MHz
fVCO=7864.32MHz
-100

Phase Noise (dBc/Hz)

-110

-120

-130

-140

-150

-160
1E+3 1E+4 1E+5 1E+6 1E+7 1E+8
Offset Frequency (Hz)

PLL enabled, fREF = 491.52MSPS, measured at 2TXOUT

Figure 6-492. Phase Noise vs Offset Frequency

measured at TX output, normalized to 12GHz by
and fVCO at fOUT = 2610 MHz
20*log10(12GHz/FOUT)

Figure 6-491. Phase Noise vs Offset Frequency for

PLL and External Clock at 12GHz
-80 -80
25qC fOUT=2610MHz
-90 -40qC fOUT=3510MHz
110qC fOUT=4910MHz
-100 -100
Phase Noise (dBc/Hz)

Phase Noise (dBc/Hz)

-110

-120 -120

-130

-140 -140

-150

-160 -160
1E+3 1E+4 1E+5 1E+6 1E+7 1E+8 1E+3 1E+4 1E+5 1E+6 1E+7 1E+8
Offset Frequency (Hz) Offset Frequency (Hz)

PLL enabled, fVCO = 11796.48 MHz, fREF = 491.52MSPS, PLL enabled, fVCO = 11796.48 MHz, fREF = 491.52MSPS,
measured at 2TXOUT measured at 2TXOUT
Figure 6-493. Phase Noise for 12-GHz VCO vs Figure 6-494. Phase Noise for 12-GHz VCO vs
Offset Frequency and Temperature at fOUT = 1910 Offset Frequency and fOUT at 25°C
MHz
-80 -80
fOUT=2610MHz fOUT=2610MHz
-90 fOUT=3510MHz -90 fOUT=3510MHz
fOUT=4910MHz fOUT=4910MHz
-100 -100
Phase Noise (dBc/Hz)

Phase Noise (dBc/Hz)

-110 -110

-120 -120

-130 -130

-140 -140

-150 -150

-160 -160
1E+3 1E+4 1E+5 1E+6 1E+7 1E+8 1E+3 1E+4 1E+5 1E+6 1E+7 1E+8
Offset Frequency (Hz) Offset Frequency (Hz)

PLL enabled, fVCO = 11796.48 MHz, fREF = 491.52MSPS, PLL enabled, fVCO = 11796.48 MHz, fREF = 491.52MSPS,
measured at 2TXOUT measured at 2TXOUT

Figure 6-495. Phase Noise for 12-GHz VCO vs Figure 6-496. Phase Noise for 12-GHz VCO vs
Offset Frequency and fOUT at –40°C Offset Frequency and fOUT at 110°C

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-80 -40
low CP setting fREF = 122.88MHz
-90 high CP setting -42 fREF = 245.76MHz
mid CP setting fREF = 368.64MHz

Integrated Phase Noise (dBc)

-44
-100 fREF = 491.52MHz
Phase Noise (dBc/Hz)

-46
-110
-48
-120 -50

-130 -52
-54
-140
-56
-150
-58
-160 -60
1E+3 1E+4 1E+5 1E+6 1E+7 1E+8 -40 -20 0 20 40 60 80 100 120
freq_offset(KHz) Temperature (qC)

PLL enabled, fVCO = 11796.48 MHz, fREF = 491.52MSPS, PLL enabled, fVCO = 11796.48 MHz, 1-kHz to 100-MHz,
measured at 2TXOUT single-sided integration bandwidth, measured at 2TXOUT
Figure 6-497. Phase Noise for 12-GHz VCO vs Figure 6-498. Integrated Phase Noise for 12-GHz
Offset Frequency and CP Setting at fOUT = 2.6 GHz VCO vs Temperature and fREF at fOUT = 2.6 GHz
-120 -125
fREF = 122.88MHz
Phase Noise at 600kHz Offset (dBc/Hz)

Phase Noise at 800kHz Offset (dBc/Hz)

-121 fREF = 245.76MHz -126
-122 fREF = 368.64MHz -127
fREF = 491.52MHz
-123 -128
-124 -129
-125 -130
-126 -131
-127 -132
fREF = 122.88MHz
-128 -133 fREF = 245.76MHz
-129 -134 fREF = 368.64MHz
fREF = 491.52MHz
-130 -135
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
Temperature (qC) Temperature (qC)

PLL enabled, fVCO = 11796.48 MHz, measured at 2TXOUT A. PLL enabled, fVCO = 11796.48 MHz, measured at 2TXOUT

Figure 6-499. Phase Noise for 12-GHz VCO at Figure 6-500. Phase Noise for 12-GHz VCO at 800-
600kHz Offset vs Temperature and fREF at fOUT = kHz Offset vs Temperature and fREF at fOUT = 2.6
2.6 GHz GHz
-125 -130
fREF = 122.88MHz fREF = 122.88MHz
Phase Noise at 1.8MHz Offset (dBc/Hz)
Phase Noise at 1MHz Offset (dBc/Hz)

-126 fREF = 245.76MHz -131 fREF = 245.76MHz

-127 fREF = 368.64MHz -132 fREF = 368.64MHz
fREF = 491.52MHz fREF = 491.52MHz
-128 -133
-129 -134
-130 -135
-131 -136
-132 -137
-133 -138
-134 -139
-135 -140
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
Temperature (qC) Temperature (qC)

PLL enabled, fVCO = 11796.48 MHz, measured at 2TXOUT PLL enabled, fVCO = 11796.48 MHz, measured at 2TXOUT

Figure 6-501. Phase Noise for 12-GHz VCO at 1- Figure 6-502. Phase Noise for 12-GHz VCO at 1.8-
MHz Offset vs Temperature and fREF at fOUT = 2.6 MHz Offset vs Temperature and fREF at fOUT = 2.6
GHz GHz

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-140 -150
fREF = 122.88MHz

Phase Noise at 50MHz Offset (dBc/Hz)

Phase Noise at 5MHz Offset (dBc/Hz)
-141 fREF = 245.76MHz -151
-142 fREF = 368.64MHz -152
fREF = 491.52MHz
-143 -153
-144 -154
-145 -155
-146 -156
-147 -157
fREF = 122.88MHz
-148 -158 fREF = 245.76MHz
-149 -159 fREF = 368.64MHz
fREF = 491.52MHz
-150 -160
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
Temperature (qC) Temperature (qC)

PLL enabled, fVCO = 11796.48 MHz, measured at 2TXOUT PLL enabled, fVCO = 11796.48 MHz, measured at 2TXOUT

Figure 6-503. Phase Noise for 12-GHz VCO at 5- Figure 6-504. Phase Noise for 12-GHz VCO at 50-
MHz Offset vs Temperature and fREF at fOUT = 2.6 MHz Offset vs Temperature and fREF at fOUT = 2.6
GHz GHz
-80 -80
25qC fOUT=2610MHz
-90 -40qC -90 fOUT=3510MHz
110qC fOUT=4910MHz
-100 -100
Phase Noise (dBc/Hz)

Phase Noise (dBc/Hz)

-110 -110

-120 -120

-130 -130

-140 -140

-150 -150

-160 -160
1E+3 1E+4 1E+5 1E+6 1E+7 1E+8 1E+3 1E+4 1E+5 1E+6 1E+7 1E+8
Offset Frequency (Hz) Offset Frequency (Hz)

PLL enabled, fVCO = 9830.4 MHz, fREF = 491.52MSPS, PLL enabled, fVCO = 9830.4 MHz, fREF = 491.52MSPS,
measured at 2TXOUT measured at 2TXOUT
Figure 6-505. Phase Noise for 10-GHz VCO vs Figure 6-506. Phase Noise for 10-GHz VCO vs
Offset Frequency and Temperature at fOUT = 1910 Offset Frequency and fOUT at 25°C
MHz
-80 -80
fOUT=2610MHz fOUT=2610MHz
-90 fOUT=3510MHz -90 fOUT=3510MHz
fOUT=4910MHz fOUT=4910MHz
-100 -100
Phase Noise (dBc/Hz)

Phase Noise (dBc/Hz)

-110 -110

-120 -120

-130 -130

-140 -140

-150 -150

-160 -160
1E+3 1E+4 1E+5 1E+6 1E+7 1E+8 1E+3 1E+4 1E+5 1E+6 1E+7 1E+8
Offset Frequency (Hz) Offset Frequency (Hz)

PLL enabled, fVCO = 9830.4 MHz, fREF = 491.52MSPS, PLL enabled, fVCO = 9830.4 MHz, fREF = 491.52MSPS,
measured at 2TXOUT measured at 2TXOUT

Figure 6-507. Phase Noise for 10-GHz VCO vs Figure 6-508. Phase Noise for 10-GHz VCO vs
Offset Frequency and fOUT at –40°C Offset Frequency and fOUT at 110°C

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-40 -120
fREF = 122.88MHz fREF = 122.88MHz

Phase Noise at 600kHz Offset (dBc/Hz)

-42 fREF = 245.76MHz -121 fREF = 245.76MHz
fREF = 491.52MHz fREF = 368.64MHz
Integrated Phase Noise (dBc)
-44 -122
-46 -123
-48 -124
-50 -125
-52 -126
-54 -127
-56 -128
-58 -129
-60 -130
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
Temperature (qC) Temperature (qC)

PLL enabled, fVCO = 9830.4 MHz, 1-kHz to 100-MHz, single- PLL enabled, fVCO = 9830.4 MHz, measured at 2TXOUT
sided integration bandwidth, measured at 2TXOUT
Figure 6-510. Phase Noise for 10-GHz VCO at 600
Figure 6-509. Integrated Phase Noise for 10-GHz kHz vs Temperature and fREF at fOUT = 2.6 GHz
VCO vs Temperature and fREF at fOUT = 2.6 GHz
-125 -125
fREF = 122.88MHz
Phase Noise at 800kHz Offset (dBc/Hz)

Phase Noise at 1MHz Offset (dBc/Hz)

-126 -126 fREF = 245.76MHz
-127 -127 fREF = 491.52MHz

-128 -128
-129 -129
-130 -130
-131 -131
-132 -132
-133 fREF = 122.88MHz -133
-134 fREF = 245.76MHz -134
fREF = 491.52MHz
-135 -135
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
Temperature (qC) Temperature (qC)

PLL enabled, fVCO = 9830.4 MHz, measured at 2TXOUT PLL enabled, fVCO = 9830.4 MHz, measured at 2TXOUT

Figure 6-511. Phase Noise for 10-GHz VCO at 800 Figure 6-512. Phase Noise for 10-GHz VCO at 1
kHz vs Temperature and fREF at fOUT = 2.6 GHz MHz vs Temperature and fREF at fOUT = 2.6 GHz
-130 -140
fREF = 122.88MHz fREF = 122.88MHz
Phase Noise at 1.8MHz Offset (dBc/Hz)

Phase Noise at 5MHz Offset (dBc/Hz)

-131 fREF = 245.76MHz -141 fREF = 245.76MHz

-132 fREF = 491.52MHz -142 fREF = 491.52MHz

-133 -143
-134 -144
-135 -145
-136 -146
-137 -147
-138 -148
-139 -149
-140 -150
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
Temperature (qC) Temperature (qC)

PLL enabled, fVCO = 9830.4 MHz, measured at 2TXOUT PLL enabled, fVCO = 9830.4 MHz, measured at 2TXOUT

Figure 6-513. Phase Noise for 10-GHz VCO at 1.8 Figure 6-514. Phase Noise for 10-GHz VCO at 5
MHz vs Temperature and fREF at fOUT = 2.6 GHz MHz vs Temperature and fREF at fOUT = 2.6 GHz

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-150 -80
25qC
Phase Noise at 50MHz Offset (dBc/Hz)
-151 -90 -40qC
-152 110qC
-100

Phase Noise (dBc/Hz)

-153
-110
-154
-155 -120

-156 -130
-157
-140
-158 fREF = 122.88MHz
fREF = 245.76MHz -150
-159
fREF = 491.52MHz
-160 -160
-40 -20 0 20 40 60 80 100 1E+3 1E+4 1E+5 1E+6 1E+7 1E+8
Temperature (qC) Offset Frequency (Hz)

PLL enabled, fVCO = 9830.4 MHz, measured at 2TXOUT PLL enabled, fVCO = 8847.36 MHz, fREF = 491.52MSPS,
measured at 2TXOUT
Figure 6-515. Phase Noise for 10-GHz VCO at 50
MHz vs Temperature and fREF at fOUT = 2.6 GHz Figure 6-516. Phase Noise for 9-GHz VCO vs Offset
Frequency and Temperature at fOUT = 1910 MHz
-80 -80
fOUT=2610MHz fOUT=2610MHz
-90 fOUT=3510MHz -90 fOUT=3510MHz
fOUT=4910MHz fOUT=4910MHz
-100 -100
Phase Noise (dBc/Hz)

Phase Noise (dBc/Hz)

-110 -110

-120 -120

-130 -130

-140 -140

-150 -150

-160 -160
1E+3 1E+4 1E+5 1E+6 1E+7 1E+8 1E+3 1E+4 1E+5 1E+6 1E+7 1E+8
Offset Frequency (Hz) Offset Frequency (Hz)

PLL enabled, fVCO = 8847.36 MHz, fREF = 491.52MSPS, PLL enabled, fVCO = 8847.36 MHz, fREF = 491.52MSPS,
measured at 2TXOUT measured at 2TXOUT

Figure 6-517. Phase Noise for 9-GHz VCO vs Offset Figure 6-518. Phase Noise for 9-GHz VCO vs Offset
Frequency and fOUT at 25°C Frequency and fOUT at –40°C
-80 -60
fOUT=2610MHz 1kHz 1MHz
-90 fOUT=3510MHz -70 10kHz 10MHz
fOUT=4910MHz -80 100kHz 100MHz
-100
Phase Noise (dBc/Hz)

-90
Temperature (qC)

-110
-100
-120 -110

-130 -120
-130
-140
-140
-150
-150
-160 -160
1E+3 1E+4 1E+5 1E+6 1E+7 1E+8 -40 -20 0 20 40 60 80 100 120
Offset Frequency (Hz) Phase Noise (dBc) D303

PLL enabled, fVCO = 8847.36 MHz, fREF = 491.52MSPS, PLL enabled, fVCO = 8847.36 MHz, fREF = 491.52MSPS,
measured at 2TXOUT minimum LPF BW, measured at 2TXOUT
Figure 6-519. Phase Noise for 9-GHz VCO vs Offset Figure 6-520. Phase Noise for 9-GHz VCO vs
Frequency and fOUT at 110°C Temperature Over Offset Frequency at fOUT = 2.6
GHz

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-80
25qC
-90 -40qC
110qC
-100

Phase Noise (dBc/Hz)

-110

-120

-130

-140

-150

-160
1E+3 1E+4 1E+5 1E+6 1E+7 1E+8
Offset Frequency (Hz)

PLL enabled, fVCO = 7864.32 MHz, fREF = 491.52MSPS, measured at 2TXOUT

Figure 6-521. Phase Noise for 8-GHz VCO vs Offset Frequency and Temperature at fOUT = 1910 MHz

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7 Device and Documentation Support

7.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
7.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
7.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
7.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

7.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

8 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

AFE7950IABJ ACTIVE FCBGA ABJ 400 90 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 AFE7950I Samples

AFE7950IALK ACTIVE FCBGA ALK 400 90 Non-RoHS Call TI Level-3-220C-168 HR -40 to 85 AFE7950 Samples
& Green SNPB

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 12-Jun-2023

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Aug-2023

TRAY

L - Outer tray length without tabs KO -

Outer
tray
height

W-
Outer
tray
width
Text

P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device Package Package Pins SPQ Unit array Max L (mm) W K0 P1 CL CW
Name Type matrix temperature (mm) (µm) (mm) (mm) (mm)
(°C)
AFE7950IABJ ABJ FCBGA 400 90 6 x 16 150 315 135.9 7620 19.5 21 19.2
AFE7950IABJ ABJ FCBGA 400 90 6 x 16 150 315 135.9 7620 19.5 21 19.2
AFE7950IALK ALK FCBGA 400 90 6 x 16 150 315 135.9 7620 19.5 21 19.2

Pack Materials-Page 1
 PACKAGE OUTLINE
ABJ0400A SCALE 0.750
FCBGA - 2.65 mm max height
BALL GRID ARRAY

17.2
BALL A1 CORNER A
16.8

17.2
( 16)
16.8

2.65
2.29 (1.4)
0.2 C
C

SEATING PLANE
0.76 NOTE 4
BALL TYP
0.56
0.12 C
0.5
TYP
0.3
15.2 TYP

SYMM
0.8 TYP (0.9) TYP

Y
W
V
U
T
R
P
N 15.2
M SYMM
L TYP
K
J
H
G
0.55 F
400X E
0.45 D
0.15 C A B C
B
0.08 C NOTE 3 A
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20 0.8 TYP
4221311/D 03/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.
4. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.
5. The lids are electrically floating (e.g. not tied to GND).

www.ti.com
 EXAMPLE BOARD LAYOUT
ABJ0400A FCBGA - 2.65 mm max height
BALL GRID ARRAY

(0.8) TYP

A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

(0.8) TYP C
D
E
F
400X ( 0.4) G
H
J
K SYMM
L
M
N
P
R
T
U
V
W
Y

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:6X

( 0.4) 0.025 MAX

METAL 0.025 MIN METAL
UNDER
MASK

SOLDER MASK EXPOSED EXPOSED ( 0.4)

OPENING METAL METAL SOLDER MASK
OPENING
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE
4221311/D 03/2023
NOTES: (continued)

6. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).

www.ti.com
 EXAMPLE STENCIL DESIGN
ABJ0400A FCBGA - 2.65 mm max height
BALL GRID ARRAY

(0.8) TYP ( 0.4) TYP

A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

(0.8) C
TYP
D
E
F
G
H
J
K SYMM

L
M
N
P
R
T
U
V
W
Y

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL
SCALE:6X

4221311/D 03/2023

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
 PACKAGE OUTLINE
ALK0400A SCALE 0.750
FCBGA - 2.65 mm max height
BALL GRID ARRAY

17.2
BALL A1 CORNER A
16.8

17.2
( 16)
16.8

2.65
2.29 (1.4)
0.2 C
C

SEATING PLANE
0.76 NOTE 4
BALL TYP
0.56
0.12 C
0.5
TYP
0.3
15.2 TYP

SYMM
0.8 TYP (0.9) TYP

Y
W
V
U
T
R
P
N 15.2
M SYMM
L TYP
K
J
H
G
0.55 F
400X E
0.45 D
0.15 C A B C
B
0.08 C NOTE 3 A
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20 0.8 TYP
4225930/C 03/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.
4. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.
5. Pb-Free die bump and SnPb solder ball.
6. The lids are electrically floating (e.g. not tied to GND).

www.ti.com
 EXAMPLE BOARD LAYOUT
ALK0400A FCBGA - 2.65 mm max height
BALL GRID ARRAY

(0.8) TYP

A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

(0.8) TYP C
D
E
F
400X ( 0.4) G
H
J
K SYMM
L
M
N
P
R
T
U
V
W
Y

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:6X

( 0.4) 0.025 MAX

METAL 0.025 MIN METAL
UNDER
MASK

SOLDER MASK EXPOSED EXPOSED ( 0.4)

OPENING METAL METAL SOLDER MASK
OPENING
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE
4225930/C 03/2023
NOTES: (continued)

7. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).

www.ti.com
 EXAMPLE STENCIL DESIGN
ALK0400A FCBGA - 2.65 mm max height
BALL GRID ARRAY

(0.8) TYP ( 0.4) TYP

A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

(0.8) C
TYP
D
E
F
G
H
J
K SYMM

L
M
N
P
R
T
U
V
W
Y

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL
SCALE:6X

4225930/C 03/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
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