SOLOMON SYSTECH

SEMICONDUCTOR TECHNICAL DATA

SSD1906

Advanced Information

256K Embedded Display SRAM

LCD Graphic Controller
CMOS

This document contains information on a new product. Specifications and information herein are subject to change
without notice.

SSD1906 Rev 1.1 P 1/159 Aug 2005 Copyright  2005 Solomon Systech Limited

Downloaded from Arrow.com.

 TABLE OF CONTENTS

1 GENERAL DESCRIPTION...............................................................................................................................2

2 FEATURES..........................................................................................................................................................3
2.1 INTEGRATED DISPLAY BUFFER .......................................................................................................................3
2.2 CPU INTERFACE .............................................................................................................................................3
2.3 DISPLAY SUPPORT ..........................................................................................................................................3
2.4 DISPLAY MODES.............................................................................................................................................3
2.5 DISPLAY FEATURES ........................................................................................................................................3
2.6 CLOCK SOURCE ..............................................................................................................................................4
2.7 MISCELLANEOUS ............................................................................................................................................4
2.8 PACKAGE ........................................................................................................................................................4
3 ORDERING INFORMATION...........................................................................................................................4

4 BLOCK DIAGRAM............................................................................................................................................5
4.1 PIN ARRANGEMENT .................................................................................................................................6
4.1.1 100 pin TQFP ........................................................................................................................................6
4.1.2 100 pin TFBGA......................................................................................................................................8
5 PIN DESCRIPTION..........................................................................................................................................10
5.1 HOST INTERFACE ..........................................................................................................................................11
5.2 LCD INTERFACE ..........................................................................................................................................12
5.3 CLOCK INPUT ...............................................................................................................................................14
5.4 MISCELLANEOUS ..........................................................................................................................................14
5.5 POWER AND GROUND ...................................................................................................................................14
5.6 SUMMARY OF CONFIGURATION OPTIONS .....................................................................................................14
5.7 HOST BUS INTERFACE PIN MAPPING ............................................................................................................16
5.8 LCD INTERFACE PIN MAPPING ....................................................................................................................17
5.9 DATA BUS ORGANIZATION ...........................................................................................................................18
6 FUNCTIONAL BLOCK DESCRIPTIONS ....................................................................................................19
6.1 MCU INTERFACE .........................................................................................................................................19
6.2 CONTROL REGISTER .....................................................................................................................................19
6.3 DISPLAY OUTPUT .........................................................................................................................................19
6.4 DISPLAY BUFFER ..........................................................................................................................................19
6.5 PWM CLOCK AND CV PULSE CONTROL ......................................................................................................19
6.6 CLOCK GENERATOR .....................................................................................................................................19
7 REGISTERS ......................................................................................................................................................20
7.1 REGISTER MAPPING......................................................................................................................................20
7.2 REGISTER DESCRIPTIONS ..............................................................................................................................20
7.2.1 Read-Only Configuration Registers.....................................................................................................20
7.2.2 Clock Configuration Registers.............................................................................................................21
7.2.3 Look-Up Table Registers .....................................................................................................................22
7.2.4 Panel Configuration Registers.............................................................................................................26
7.2.5 Display Mode Registers .......................................................................................................................37
7.2.6 Main Window Registers .......................................................................................................................40
7.2.7 Floating Window Registers..................................................................................................................42
7.2.8 Miscellaneous Registers ......................................................................................................................47
7.2.9 General IO Pins Registers ...................................................................................................................49
7.2.10 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers ..52
7.2.11 Cursor Mode Registers ........................................................................................................................55

Solomon Systech Aug 2005 P 2/159 Rev 1.1 SSD1906

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 8 MAXIMUM RATINGS.....................................................................................................................................69

9 DC CHARACTERISTICS................................................................................................................................70

10 AC CHARACTERISTICS............................................................................................................................70
10.1 CLOCK TIMING .............................................................................................................................................71
10.1.1 Input Clocks .........................................................................................................................................71
10.1.2 Internal Clocks.....................................................................................................................................72
10.2 CPU INTERFACE TIMING ..............................................................................................................................73
10.2.1 Generic #1 Interface Timing................................................................................................................73
10.2.2 Generic #2 Interface Timing (e.g. ISA)................................................................................................75
10.2.3 Motorola MC68K #1 Interface Timing (e.g. MC68000)......................................................................77
10.2.4 Motorola DragonBall Interface Timing with DTACK# (e.g. MC68EZ328/MC68VZ328)...................79
10.2.5 Motorola DragonBall Interface Timing without DTACK# (e.g. MC68EZ328/MC68VZ328)..............81
10.2.6 Hitachi SH-3 Interface Timing (e.g. SH7709A) ...................................................................................83
10.2.7 Hitachi SH-4 Interface Timing (e.g. SH7751) .....................................................................................85
10.3 LCD POWER SEQUENCING ...........................................................................................................................87
10.3.1 Passive/TFT Power-On Sequence........................................................................................................87
10.3.2 Passive/TFT Power-Off Sequence .......................................................................................................88
10.3.3 Power Saving Status ............................................................................................................................89
10.4 DISPLAY INTERFACE.....................................................................................................................................90
10.4.1 Generic STN Panel Timing ..................................................................................................................91
10.4.2 Monochrome 4-Bit Panel Timing.........................................................................................................93
10.4.3 Monochrome 8-Bit Panel Timing.........................................................................................................96
10.4.4 Color 4-Bit Panel Timing ....................................................................................................................99
10.4.5 Color 8-Bit Panel Timing (Format stripe) .........................................................................................102
10.4.6 Generic TFT Panel Timing ................................................................................................................105
10.4.7 9/12/18-Bit TFT Panel Timing...........................................................................................................106
10.4.8 160x160 Sharp HR-TFT Panel Timing (e.g. LQ031B1DDxx) ...........................................................110
10.4.9 Generic HR-TFT Panel Timing .........................................................................................................114
11 CLOCKS ......................................................................................................................................................116
11.1 CLOCK DESCRIPTIONS ................................................................................................................................116
11.1.1 BCLK .................................................................................................................................................116
11.1.2 MCLK ................................................................................................................................................117
11.1.3 PCLK .................................................................................................................................................117
11.1.4 PWMCLK...........................................................................................................................................118
11.2 CLOCKS VERSUS FUNCTIONS ......................................................................................................................119
12 POWER SAVING MODE ..........................................................................................................................120

13 FRAME RATE CALCULATION..............................................................................................................120

14 DISPLAY DATA FORMATS.....................................................................................................................121

15 LOOK-UP TABLE ARCHITECTURE.....................................................................................................122

15.1 MONOCHROME MODES ..............................................................................................................................122
15.1.1 1 Bit-per-pixel Monochrome Mode....................................................................................................122
15.1.2 2 Bit-per-pixel Monochrome Mode....................................................................................................122
15.1.3 4 Bit-per-pixel Monochrome Mode....................................................................................................123
15.1.4 8 Bit-per-pixel Monochrome Mode....................................................................................................123
15.1.5 16 Bit-Per-Pixel Monochrome Mode.................................................................................................123
15.2 COLOR MODES ...........................................................................................................................................124
15.2.1 1 Bit-Per-Pixel Color.........................................................................................................................124

SSD1906 Rev 1.1 P 3/159 Aug 2005 Solomon Systech

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 15.2.2 2 Bit-Per-Pixel Color.........................................................................................................................125
15.2.3 4 Bit-Per-Pixel Color.........................................................................................................................126
15.2.4 8 Bit-per-pixel Color Mode................................................................................................................127
15.2.5 16 Bit-Per-Pixel Color Mode.............................................................................................................128
16 BIG-ENDIAN BUS INTERFACE..............................................................................................................128
16.1 BYTE SWAPPING BUS DATA .......................................................................................................................128
16.1.1 16 Bpp Color Depth...........................................................................................................................129
16.1.2 1/2/4/8 Bpp Color Depth....................................................................................................................129
17 VIRTUAL DISPLAY MODE .....................................................................................................................130

18 DISPLAY ROTATE MODE.......................................................................................................................131

18.1 90° DISPLAY ROTATE MODE ......................................................................................................................131
18.1.1 Register Programming.......................................................................................................................131
18.2 180° DISPLAY ROTATE MODE ....................................................................................................................132
18.2.1 Register Programming.......................................................................................................................132
18.3 270° DISPLAY ROTATE MODE ....................................................................................................................133
18.3.1 Register Programming.......................................................................................................................133
19 FLOATING WINDOW MODE .................................................................................................................134
19.1 WITH DISPLAY ROTATE MODE ENABLED...................................................................................................135
19.1.1 Display Rotate Mode 90°...................................................................................................................135
19.1.2 Display Rotate Mode 180°.................................................................................................................135
19.1.3 Display Rotate Mode 270°.................................................................................................................136
20 HARDWARE CURSOR MODE ................................................................................................................137
20.1 WITH DISPLAY ROTATE MODE ENABLED...................................................................................................138
20.1.1 Display Rotate Mode 90° ...................................................................................................................138
20.1.2 Display Rotate Mode 180° .................................................................................................................139
20.1.3 Display Rotate Mode 270° .................................................................................................................139
20.2 PIXEL FORMAT (NORMAL ORIENTATION MODE) .........................................................................................139
20.2.1 4/8/16 Bit-per-pixel............................................................................................................................140
20.3 PIXEL FORMAT (90˚ DISPLAY ROTATE MODE) ...........................................................................................140
20.3.1 4 Bit-per-pixel....................................................................................................................................140
20.3.2 8 Bit-per-pixel....................................................................................................................................142
20.3.3 16 Bit-per-pixel..................................................................................................................................142
20.4 PIXEL FORMAT (180˚ DISPLAY ROTATE MODE) .........................................................................................143
20.4.1 4 Bit-per-pixel....................................................................................................................................143
20.4.2 8 Bit-per-pixel....................................................................................................................................143
20.4.3 16 Bit-per-pixel..................................................................................................................................144
20.5 PIXEL FORMAT (270˚ DISPLAY ROTATE MODE) .........................................................................................144
20.5.1 4 Bit-per-pixel....................................................................................................................................144
20.5.2 8 Bit-per-pixel....................................................................................................................................145
20.5.3 16 Bit-per-pixel..................................................................................................................................145
21 APPLICATION EXAMPLES ....................................................................................................................147

22 APPENDIX...................................................................................................................................................153
22.1 PACKAGE MECHANICAL DRAWING FOR 100 PINS TQFP ............................................................................153
22.2 PACKAGE MECHANICAL DRAWING FOR 100 PINS TFBGA.........................................................................154
22.3 REGISTER TABLE ........................................................................................................................................156

Solomon Systech Aug 2005 P 4/159 Rev 1.1 SSD1906

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 Figures

Figure 4-1 : Block Diagram ........................................................................................................................... 5

Figure 4-2 : Pinout Diagram – 100 pin TQFP ............................................................................................... 6
Figure 4-3 : Pinout Diagram – 100 pin TFBGA ............................................................................................. 8
Figure 7-1 : GPIO Offset for 320x240 HR-TFT ........................................................................................... 36
Figure 7-2 : Display Data Byte/Word Swap ................................................................................................ 39
Figure 7-3 : PWM Clock/CV Pulse Block Diagram ..................................................................................... 52
Figure 10-1 : Clock Input Requirements ..................................................................................................... 71
Figure 10-2 : Generic #1 Interface Timing .................................................................................................. 73
Figure 10-3 : Generic #2 Interface Timing .................................................................................................. 75
Figure 10-4 : Motorola MC68K #1 Interface Timing.................................................................................... 77
Figure 10-5 : Motorola DragonBall Interface with DTACK# Timing ............................................................ 79
Figure 10-6 : Motorola DragonBall Interface without DTACK# Timing ....................................................... 81
Figure 10-7 : Hitachi SH-3 Interface Timing................................................................................................ 83
Figure 10-8 : Hitachi SH-4 Interface Timing................................................................................................ 85
Figure 10-9 : Passive/TFT Power-On Sequence Timing ............................................................................ 87
Figure 10-10 : Passive/TFT Power-Off Sequence Timing .......................................................................... 88
Figure 10-11 : Power Saving Status Timing ............................................................................................... 89
Figure 10-12 : Panel Timing Parameters ................................................................................................ 90
Figure 10-13 : Generic STN Panel Timing ............................................................................................. 91
Figure 10-14 : Monochrome 4-Bit Panel Timing .................................................................................... 93
Figure 10-15 : Monochrome 4-Bit Panel A.C. Timing ........................................................................... 94
Figure 10-16 : Monochrome 8-Bit Panel Timing .................................................................................... 96
Figure 10-17 : Monochrome 8-Bit Panel A.C. Timing ........................................................................... 97
Figure 10-18 : Color 4-Bit Panel Timing .................................................................................................. 99
Figure 10-19 : Color 4-Bit Panel A.C. Timing ....................................................................................... 100
Figure 10-20 : Color 8-Bit Panel Timing (Format stripe) .................................................................... 102
Figure 10-21 : Color 8-Bit Panel A.C. Timing (Format stripe)............................................................ 103
Figure 10-22 : Generic TFT Panel Timing ............................................................................................ 105
Figure 10-23 : 12-Bit TFT Panel Timing ................................................................................................ 106
Figure 10-24 : TFT A.C. Timing.............................................................................................................. 108
Figure 10-25 : 160x160 Sharp HR-TFT Panel Horizontal Timing ..................................................... 110
Figure 10-26 : 160x160 Sharp HR-TFT Panel Vertical Timing.......................................................... 112
Figure 10-27 : HR-TFT Panel Horizontal Timing ................................................................................. 114
Figure 10-28 : HR-TFT Panel Vertical Timing ...................................................................................... 115
Figure 11-1 : Clock Generator Block Diagram ..................................................................................... 116
Figure 14-1 : 1/2/4/8/16 Bit-Per-Pixel Display Data Memory Organization .............................................. 121
Figure 15-1 : 1 Bit-per-pixel Monochrome Mode Data Output Path ................................................. 122
Figure 15-2 : 2 Bit-per-pixel Monochrome Mode Data Output Path ................................................. 122
Figure 15-3 : 4 Bit-per-pixel Monochrome Mode Data Output Path ................................................. 123
Figure 15-4 : 8 Bit-per-pixel Monochrome Mode Data Output Path ................................................. 123
Figure 15-5 : 1 Bit-Per-Pixel Color Mode Data Output Path .............................................................. 124
Figure 15-6 : 2 Bit-Per-Pixel Color Mode Data Output Path .............................................................. 125
Figure 15-7 : 4 Bit-Per-Pixel Color Mode Data Output Path .............................................................. 126
Figure 15-8 : 8 Bit-per-pixel Color Mode Data Output Path............................................................... 127
Figure 16-1 : Byte-swapping for 16 Bpp ............................................................................................... 128
Figure 16-2 : Byte-swapping for 1/2/4/8 Bpp ....................................................................................... 129
Figure 17-1 : Main Window inside Virtual Image Area.............................................................................. 130
Figure 18-1 : Relationship Between The Screen Image and the Image Refreshed in 90° Display Rotate
Mode. ................................................................................................................................................. 131

SSD1906 Rev 1.1 P 5/159 Aug 2005 Solomon Systech

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 Figure 18-2 : Relationship Between The Screen Image and the Image Refreshed in 180° Display Rotate
Mode. ................................................................................................................................................. 132
Figure 18-3 : Relationship Between The Screen Image and the Image Refreshed in 270° Display Rotate
Mode. ................................................................................................................................................. 133
Figure 19-1 : Floating Window with Display Rotate Mode disabled ................................................. 134
Figure 19-2 : Floating Window with Display Rotate Mode 90° enabled ........................................... 135
Figure 19-3 : Floating Window with Display Rotate Mode 180° enabled ........................................ 135
Figure 19-4 : Floating Window with Display Rotate Mode 270° enabled ........................................ 136
Figure 20-1 : Display Precedence in Hardware Cursor ............................................................................ 137
Figure 20-2 : Cursors on the main window ............................................................................................... 138
Figure 20-3 : Cursors with Display Rotate Mode 90° enabled.................................................................. 138
Figure 20-4 : Cursors with Display Rotate Mode 180° enabled................................................................ 139
Figure 20-5 : Cursors with Display Rotate Mode 270° enabled................................................................ 139
Figure 21-1: Typical System Diagram (Generic #1 Bus) .......................................................................... 147
Figure 21-2 : Typical System Diagram (Generic #2 Bus) ......................................................................... 148
Figure 21-3 : Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000) .......................................... 149
Figure 21-4 : Typical System Diagram (Motorola MC68EZ328/MC68VZ328 “DragonBall” Bus) ............. 150
Figure 21-5 : Typical System Diagram (Hitachi SH-3 Bus)....................................................................... 151
Figure 21-6 : Typical System Diagram (Hitachi SH-4 Bus)....................................................................... 152

Solomon Systech Aug 2005 P 6/159 Rev 1.1 SSD1906

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 Tables

Table 3-1 : Ordering Information ................................................................................................................... 4

Table 4-1 : TQFP Pin Assignment Table ...................................................................................................... 7
Table 4-2 : TFBGA Pin Assignment Table.................................................................................................... 9
Table 5-1 : Host Interface Pin Descriptions ................................................................................................ 11
Table 5-2 : LCD Interface Pin Descriptions............................................................................................ 12
Table 5-3 : Clock Input Pin Descriptions..................................................................................................... 14
Table 5-4 : Miscellaneous Pin Descriptions ................................................................................................ 14
Table 5-5 : Power And Ground Pin Descriptions ........................................................................................ 14
Table 5-6 : Summary of Power-On/Reset Options ..................................................................................... 15
Table 5-7 : Host Bus Interface Pin Mapping ............................................................................................... 16
Table 5-8 : LCD Interface Pin Mapping....................................................................................................... 17
Table 5-9 : Data Bus Organization.............................................................................................................. 18
Table 5-10 : Pin State Summary................................................................................................................. 18
Table 7-1 : MCLK Divide Selection ............................................................................................................. 21
Table 7-2 : PCLK Divide Selection.............................................................................................................. 22
Table 7-3 : PCLK Source Selection ............................................................................................................ 22
Table 7-4 : Panel Data Width Selection ...................................................................................................... 26
Table 7-5 : Active Panel Resolution Selection ............................................................................................ 27
Table 7-6 : LCD Panel Type Selection........................................................................................................ 27
Table 7-7 : Color Invert Mode Options.................................................................................................... 38
Table 7-8 : LCD Bit-per-pixel Selection .................................................................................................. 38
Table 7-9 : Display Rotate Mode Select Options ........................................................................................ 40
Table 7-10 : 32-bit Address X Increments for Various Color Depths.......................................................... 44
Table 7-11 : 32-bit Address Y Increments for Various Color Depths.......................................................... 45
Table 7-12 : 32-bit Address X Increments for Various Color Depths.......................................................... 46
Table 7-13 : 32-bit Address Y Increments for Various Color Depths.......................................................... 47
Table 7-14 : PWM Clock Control................................................................................................................. 52
Table 7-15 : CV Pulse Control .................................................................................................................... 53
Table 7-16 : PWM Clock Divide Select Options.......................................................................................... 53
Table 7-17 : CV Pulse Divide Select Options ............................................................................................. 54
Table 7-18 : LPWMOUT Duty Cycle Select Options................................................................................... 55
Table 7-19 : X Increment Mode for Various Color Depths.......................................................................... 58
Table 7-20 : Y Increment Mode for Various Color Depths.......................................................................... 59
Table 8-1 : Absolute Maximum Ratings ...................................................................................................... 69
Table 8-2 : Recommended Operating Conditions ...................................................................................... 70
Table 9-1 : Electrical Characteristics for IOVDD = 3.3V typical.................................................................... 70
Table 10-1 : Clock Input Requirements for CLKI ........................................................................................ 71
Table 10-2 : Clock Input Requirements for AUXCLK.................................................................................. 72
Table 10-3 : Internal Clock Requirements .................................................................................................. 72
Table 10-4 : Generic #1 Interface Timing ................................................................................................... 74
Table 10-5 : Generic #2 Interface Timing ................................................................................................... 76
Table 10-6 : Motorola MC68K #1 Interface Timing ..................................................................................... 78
Table 10-7 : Motorola DragonBall Interface with DTACK# Timing ............................................................. 80
Table 10-8 : Motorola DragonBall Interface without DTACK# Timing ........................................................ 82
Table 10-9 : Hitachi SH-3 Interface Timing................................................................................................. 84
Table 10-10 : Hitachi SH-4 Interface Timing............................................................................................... 86
Table 10-11 : Passive/TFT Power-On Sequence Timing ........................................................................... 87
Table 10-12 : Passive/TFT Power-Off Sequence Timing ........................................................................... 88
Table 10-13 : Power Saving Status Timing................................................................................................. 89
Table 10-14 : Panel Timing Parameter Definition and Register Summary................................................. 90
Table 10-15 : Monochrome 4-Bit Panel A.C. Timing .................................................................................. 95
Table 10-16 : Monochrome 8-Bit Panel A.C. Timing .................................................................................. 98
Table 10-17 : Color 4-Bit Panel A.C. Timing............................................................................................. 101

SSD1906 Rev 1.1 P 7/159 Aug 2005 Solomon Systech

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 Table 10-18 : Color 8-Bit Panel A.C. Timing (Format stripe) .................................................................... 104
Table 10-19 : TFT A.C. Timing.................................................................................................................. 109
Table 10-20 : 160x160 Sharp HR-TFT Horizontal Timing ........................................................................ 111
Table 10-21 : 160x160 Sharp HR-TFT Panel Vertical Timing .................................................................. 113
Table 10-22 : 320x240 HR-TFT Panel Horizontal Timing......................................................................... 115
Table 10-23 : 320x240 HR-TFT Panel Vertical Timing............................................................................. 115
Table 11-1 : BCLK Clock Selection........................................................................................................... 116
Table 11-2 : MCLK Clock Selection .......................................................................................................... 117
Table 11-3 : PCLK Clock Selection........................................................................................................... 118
Table 11-4 : Relationship between MCLK and PCLK ............................................................................... 118
Table 11-5 : PWMCLK Clock Selection ................................................................................................ 118
Table 11-6 : SSD1906 Internal Clock Requirements ................................................................................ 119
Table 12-1 : Power Saving Mode Function Summary .............................................................................. 120
Table 20-1 : Indexing scheme for Hardware Cursor ................................................................................. 137
Table 22-1 : SSD1906 Register Table (1 of 3).......................................................................................... 156
Table 22-2 : SSD1906 Register Table (2 of 3).......................................................................................... 157
Table 22-3 : SSD1906 Register Table (3 of 3).......................................................................................... 158

Solomon Systech Aug 2005 P 8/159 Rev 1.1 SSD1906

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 1 GENERAL DESCRIPTION

The SSD1906 is a graphics controller with built-in 256Kbyte SRAM display buffer, supporting color and mono LCD.
The SSD1906 can support a wide range of active and passive panels and interface with various CPUs. The
advanced design, together with integrated memory and timing circuits produces a low cost, low power, single chip
solution for handheld devices or appliances, including Pocket/Palm-size PCs and mobile communication devices.

The SSD1906 supports most of the common resolutions for portable appliances and features hardware display
rotation, covering various form factor requirements. The controller also features Virtual Display, Floating Window
(variable size Overlay Window) and two Cursors to reduce software manipulation. The 32-bit internal data path
provides high bandwidth display memory for fast screen updates and the SSD1906 also provides the advantage of
a single power supply.

The SSD1906 features low-latency CPU access, supporting microprocessors without RDY#/WAIT# handshaking
signals. This impartiality to CPU type or operating system makes the controller an ideal display solution for a wide
variety of applications. The SSD1906 is available in a 100 pin TQFP & TFBGA package.

Solomon Systech Aug 2005 P 2/159 Rev 1.1 SSD1906

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 2 FEATURES

2.1 Integrated Display Buffer

• Embedded 256K byte SRAM display buffer.

2.2 CPU Interface

• Directly interfaces to:
Generic #1 bus interface with WAIT# signal
Generic #2 bus interface with WAIT# signal
Intel StrongARM/XScale
Motorola MX1 Dragonball
Motorola MC68K
Motorola DragonBall MC68EZ328/MC68VZ328
Hitachi SH-3
Hitachi SH-4
• 8-bit processor support with “glue logic”.
• “Fixed” and low-latency CPU access times.
• Registers are memory-mapped with dedicated M/R# input, which selects between memory
and register address space.
• The contiguous 256K byte display buffer is directly accessible through the 18-bit address bus.

2.3 Display Support

• 4/8-bit monochrome STN interface.
• 4/8-bit color STN interface.
• 9/12/18-bit Active Matrix TFT interface.
• Direct support for 18-bit Sharp HR-TFT interface (160x160, 320x240).

2.4 Display Modes

• 1/2/4/8/16 bit-per-pixel (bpp) color depths.
• Up to 64 gray shades using Frame Rate Control (FRC) and dithering on monochrome passive
LCD panels.
• Up to 256k colors on passive STN panels.
• Up to 256k colors on active matrix LCD panels.
• Resolution examples :
320x320 at a color depth of 16 bpp
160x160 at a color depth of 16 bpp
160x240 at a color depth of 16 bpp

2.5 Display Features

• Display Rotation Mode: 90°, 180°, 270° counter-clockwise hardware rotation of display image.
• Virtual Display Support: displays image larger than the panel size using panning and scrolling.
• Floating Window Mode: displays a variable size window overlaid on the background image.
• 2 Hardware Cursors (for 4/8/16 bpp): simultaneously displays two cursors overlaid on the
background image.
• Double Buffering/Multi-pages: provides smooth animation and instantaneous screen updates.

Solomon Systech Aug 2005 P 3/159 Rev 1.1 SSD1906

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 2.6 Clock Source
• Two clock inputs: CLKI and AUXCLK, but possible to use one clock input only.
• Bus clock (BCLK) is derived from the CLKI and can be internally divided by 2, 3, or 4.
• Memory clock (MCLK) is derived from the BCLK and can be internally divided by 2, 3, or 4.
• Pixel clock (PCLK) can be derived from CLKI, AUXCLK, BCLK, or MCLK and can be internally
divided by 2, 3, 4, or 8.

2.7 Miscellaneous
• Hardware/Software Color Invert
• Software Power Saving mode
• General Purpose Input / Output pins available
• Single Supply Operation : 3.0V – 3.6V

2.8 Package
• 100-pin TQFP package
• 100-pin TFBGA package

3 ORDERING INFORMATION
Table 3-1 : Ordering Information
Ordering Part Number Package Form
SSD1906QT2 100 TQFP (Tray)
SSD1906QT2R3 100 TQFP (Tape and reel)
SSD1906G14 100 TFBGA (Tray)
SSD1906G14R3 100 TFBGA (Tape and reel)

Solomon Systech Aug 2005 P 4/159 Rev 1.1 SSD1906

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 4

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CONTROL REGISTER & GPIO
MCU INTERFACE

Solomon Systech
WE0#, WE1#,
RD/WR#, RD#,
BS#,CS#; GPIO & GPIO[6:0]
CONTROL LOOK UP TABLE (LUT)
RESET#, M/R#
REGISTERS
BLOCK DIAGRAM

GPO
A[17:0]

D[15:0]

MCU
DISPLAY OUTPUT

DECODE

INTERFACE
READ/WRITE
LFRAME,
FRC/TFT CONTROLS & LLINE,
CF[7:0] DISPLAY DATA DISPLAY DATA FORMAT LSHIFT, LDEN,
PREFETCH UNIT CONVERTION
LDATA[17:0]

WAIT#

Aug 2005
DISPLAY BUFFER (256KB)

Figure 4-1 : Block Diagram

P 5/159
DISPLAY MEMORY
MEMORY R/W
CONTROL
WITH CONTROL

CLOCK INTERNAL
CLKI, AUXCLK CLOCKS
GENERATOR

Rev 1.1
PULSE WIDTH MODULATION CLOCK AND LPWMOUT,
CONTRAST VOLTAGE PULSE CONTROL LCVOUT

SSD1906
 4.1 PIN ARRANGEMENT

4.1.1 100 pin TQFP

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
LDATA17
LDATA16
LDATA15
LDATA14
LDATA13
LDATA12
LDATA11
LDATA10
LDATA9
LDATA8
LDATA7
IOVDD
VSS
LDATA6
LDATA5
LDATA4
LDATA3
LDATA2
LDATA1
LDATA0
LSHIFT
LLINE
LFRAME
COREVDD
76 50
77 IOVDD VSS
AUXCLK 49
78 IOVDD
CF7 48
79 LDEN
CF6 47
80 GPO 46
81 CF5 LCVOUT
CF4 45
82 GPIO0 44
83 CF3 GPIO1
CF2 43
84 GPIO2 42
85 CF1 GPIO3
CF0 41
86 GPIO4 40
87 A17 GPIO5
A16 SSD1906 39
88 GPIO6 38
89 A15 LPWMOUT
A14 37
90 IOVDD 36
91 A13 VSS
A12 35
92 D0 34
93 A11 D1
A10 33
94 D2 32
95 A9 D3
A8 31
96 D4 30
97 A7 D5
A6 29
98 D6 28
99 A5 D7
A4 27
D8
COREVDD

100 26
RD/WR#
RESET#

VSS IOVDD
WAIT#
WE0#
WE1#

IOVDD
M/R#

CLKI
RD#
CS#

BS#

D15
D14
D13
D12
D11
D10
VSS

VSS
D9
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Figure 4-2 : Pinout Diagram – 100 pin TQFP

Note
The CoreVDD is an internal regulator output pin and 0.1µF capacitor to VSS is required on each CoreVDD pin.

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 Table 4-1 : TQFP Pin Assignment Table
Pin # Signal Name Pin # Signal Name Pin # Signal Name Pin # Signal Name
1 COREVDD 26 IOVDD 51 COREVDD 76 IOVDD
2 A3 27 D8 52 LFRAME 77 AUXCLK
3 A2 28 D7 53 LLINE 78 CF7
4 A1 29 D6 54 LSHIFT 79 CF6
5 A0 30 D5 55 LDATA0 80 CF5
6 CS# 31 D4 56 LDATA1 81 CF4
7 M/R# 32 D3 57 LDATA2 82 CF3
8 BS# 33 D2 58 LDATA3 83 CF2
9 RD# 34 D1 59 LDATA4 84 CF1
10 WE0# 35 D0 60 LDATA5 85 CF0
11 WE1# 36 VSS 61 LDATA6 86 A17
12 RD/WR# 37 IOVDD 62 VSS 87 A16
13 RESET# 38 LPWMOUT 63 IOVDD 88 A15
14 VSS 39 GPIO6 64 LDATA7 89 A14
15 CLKI 40 GPIO5 65 LDATA8 90 A13
16 IOVDD 41 GPIO4 66 LDATA9 91 A12
17 WAIT# 42 GPIO3 67 LDATA10 92 A11
18 D15 43 GPIO2 68 LDATA11 93 A10
19 D14 44 GPIO1 69 LDATA12 94 A9
20 D13 45 GPIO0 70 LDATA13 95 A8
21 D12 46 LCVOUT 71 LDATA14 96 A7
22 D11 47 GPO 72 LDATA15 97 A6
23 D10 48 LDEN 73 LDATA16 98 A5
24 D9 49 IOVDD 74 LDATA17 99 A4
25 VSS 50 VSS 75 VSS 100 VSS

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 4.1.2 100 pin TFBGA

1 2 3 4 5 6 7 8 9 10
BOTTOM VIEW

Figure 4-3 : Pinout Diagram – 100 pin TFBGA

Note
The CoreVDD is an internal regulator output pin and 0.1µF capacitor to VSS is required on each CoreVDD pin.

Solomon Systech Aug 2005 P 8/159 Rev 1.1 SSD1906

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 Table 4-2 : TFBGA Pin Assignment Table
Signal Signal Signal Signal Signal
Pin # Pin # Pin # Pin # Pin #
Name Name Name Name Name
A1 VSS C1 IOVDD E1 CF3 G1 A12 J1 A5
A2 LDATA17 C2 CF7 E2 CF2 G2 A11 J2 A4
A3 LDATA13 C3 LDATA15 E3 CF1 G3 A10 J3 A2
A4 LDATA9 C4 LDATA11 E4 CF0 G4 A9 J4 A0
A5 LDATA6 C5 IOVDD E5 LDATA8 G5 WE0# J5 BS#
A6 LDATA2 C6 LDATA4 E6 GPIO5 G6 RD#/WR J6 VSS
A7 LSHIFT C7 LDATA1 E7 GPIO6 G7 WAIT# J7 D14
A8 LFRAME C8 GPO E8 LPWMOUT G8 D4 J8 D12
A9 COREVDD C9 LCVOUT E9 IOVDD G9 D5 J9 D9
A10 VSS C10 GPIO0 E10 VSS G10 D6 J10 IOVDD
B1 AUXCLK D1 CF6 F1 A17 H1 A8 K1 VSS
B2 LDATA16 D2 CF5 F2 A16 H2 A7 K2 COREVDD
B3 LDATA14 D3 CF4 F3 A15 H3 A6 K3 A3
B4 LDATA10 D4 LDATA12 F4 A14 H4 CS# K4 A1
B5 VSS D5 LDATA7 F5 A13 H5 RD# K5 M/R#
B6 LDATA3 D6 LDATA5 F6 WE1# H6 RESET# K6 CLKI
B7 LDATA0 D7 GPIO1 F7 D0 H7 IOVDD K7 D15
B8 LLINE D8 GPIO2 F8 D1 H8 D11 K8 D13
B9 IOVDD D9 GPIO3 F9 D2 H9 D7 K9 D10
B10 LDEN D10 GPIO4 F10 D3 H10 D8 K10 VSS

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 5 PIN DESCRIPTION

Key:
I = Input
O =Output
IO = Bi-directional (input/output)
P = Power pin
LIS = LVTTL Schmitt input
LB2 = LVTTL IO buffer (8mA/-8mA at 3.3V)
LB3 = LVTTL IO buffer (12mA/-12mA at 3.3V)
LO3 = LVTTL output buffer (12mA/-12mA at 3.3V)
LT2 = Tri-state output buffer (8mA/-8mA at 3.3V)
LT3 = Tri-state output buffer (12mA/-12mA at 3.3V)
Hi-Z = High impedance

Note : LVTTL is low voltage TTL (see Section 9 “DC CHARACTERISTICS”).

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 5.1 Host Interface
Table 5-1 : Host Interface Pin Descriptions
TQFP TFBGA RESET#
Pin Name Type Description
Pin # Pin # State
This input pin has multiple functions.
• For Generic #1, this pin is not used and should be
connected to VSS.
• For Generic #2, this is an input of the system address bit
0 (A0).
• For MC68K #1, this is an input of the lower data strobe
A0 I 5 J4 0
(LDS#).
• For DragonBall, this pin is not used and should be
connected to VSS.
• For SH-3/SH-4, this pin is not used and should be
connected to VSS.
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
F1-F5,
G1-G4,
2-4, 86-
A[17:1] I H1-H3, 0 System address bus bits 17-1.
99
J1-J3,
K3-K4
Input data from the system data bus.
F7-F10, • For Generic #1, these pins are connected to D[15:0].
G8-G10, • For Generic #2, these pins are connected to D[15:0].
18-24,
D[15:0] IO H8-H10, Hi-Z • For MC68K #1, these pins are connected to D[15:0].
27-35
J7-J9, • For DragonBall, these pins are connected to D[15:0].
K7-K9 • For SH-3/SH-4, these pins are connected to D[15:0].
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
This input pin has multiple functions.
• For Generic #1, this is an input of the write enable signal
for the lower data byte (WE0#).
• For Generic #2, this is an input of the write enable signal
(WE#).
WE0# I 10 G5 1 • For MC68K #1, this pin must be tied to IOVDD.
• For DragonBall, this is an input of the byte enable signal
for the D[7:0] data byte (LWE#).
• For SH-3/SH-4, this is input of the write enable signal for
data D[7:0].
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
This input pin has multiple functions.
• For Generic #1, this is an input of the write enable signal
for the upper data byte (WE1#).
• For Generic #2, this is an input of the byte enable signal
for the high data byte (BHE#).
• For MC68K #1, this is an input of the upper data strobe
WE1# I 11 F6 1
(UDS#).
• For DragonBall, this is an input of the byte enable signal
for the D[15:8] data byte (UWE#).
• For SH-3/SH-4, this is input of the write enable signal for
data D[15:8].
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
Chip select input.
CS# I 6 H4 1
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
This input pin is used to select the display buffer or internal
registers of the SSD1906. M/R# is set high to access the
M/R# I 7 K5 0
display buffer and low to access the registers.
See Table 5-7 : Host Bus Interface Pin Mapping for summary.

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 TQFP TFBGA RESET#
Pin Name Type Description
Pin # Pin # State
This input pin has multiple functions.
• For Generic #1, this pin must be tied to IOVDD.
• For Generic #2, this pin must be tied to IOVDD .
• For MC68K #1, this is an input of the address strobe
BS# I 8 J5 1
(AS#).
• For DragonBall, this pin must be tied to IOVDD .
• For SH-3/SH-4, this is input of the bus start signal (BS#).
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
This input pin has multiple functions.
• For Generic #1, this is an input of the read command for
the upper data byte (RD1#).
• For Generic #2, this pin must be tied to IOVDD .
• For MC68K #1, this is an input of the R/W# signal.
RD/WR# I 12 G6 1
• For DragonBall, this pin must be tied to IOVDD .
• For SH-3/SH-4, this is input of the RD/WR# signal. The
SSD1905 needs this signal for early decode of the bus
cycle.
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
This input pin has multiple functions.
• For Generic #1, this is an input of the read command for
the lower data byte (RD0#).
• For Generic #2, this is an input of the read command
(RD#).
RD# I 9 H5 1
• For MC68K #1, this pin must be tied to IOVDD.
• For DragonBall, this is an input of the output enable
(OE#).
• For SH-3/SH-4, this is input of the read signal (RD#).
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
During a data transfer, this output pin is driven active to force
the system to insert wait states. It is driven inactive to indicate
the completion of a data transfer. WAIT# is released to the
high impedance state after the data transfer is complete. Its
active polarity is configurable. A pull-up or pull-down resistor
should be used to resolve any data contention issues.
See Table 5-6 : Summary of Power-On/Reset Options.
• For Generic #1, this pin outputs the wait signal (WAIT#).
• For Generic #2, this pin outputs the wait signal (WAIT#).
WAIT# O 17 G7 Hi-Z
• For MC68K #1, this pin outputs the data transfer
acknowledge signal (DTACK#).
• For DragonBall, this pin outputs the data transfer
acknowledge signal (DTACK#).
• For SH-3 mode, this pin outputs the wait request signal
(WAIT#).
• For SH-4 mode, this pin outputs the device ready signal
(RDY#).
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
Active low input to set all internal registers to the default state
and to force all signals to their inactive states. It is
RESET# I 13 H6 0 recommended to place a 0.1µF capacitor to VSS.

Note : When reset state is released (RESET# = “H”),

normal operation can be started after 3 BCLK period.

5.2 LCD Interface

Table 5-2 : LCD Interface Pin Descriptions

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 TQFP TFBGA RESET#
Pin Name Type Cell Description
Pin # Pin # State
A2-A6,
B2-B4,
B6-B7,
55-61,
LDATA[17:0] O C3-C4, LO3 0 Panel Data bits 17-0.
64-74
C6-C7,
D4-D6,
E5
This output pin has multiple functions.
• Frame Pulse
LFRAME O 52 A8 LO3 0
• SPS for Sharp HR-TFT
See Table 5-8 : LCD Interface Pin Mapping for summary.
This output pin has multiple functions.
• Line Pulse
LLINE O 53 B8 LO3 0
• LP for Sharp HR-TFT
See Table 5-8 : LCD Interface Pin Mapping for summary.
This output pin has multiple functions.
• Shift Clock
LSHIFT O 54 A7 LO3 0
• CLK for Sharp HR-TFT
See Table 5-8 : LCD Interface Pin Mapping for summary.
This output pin has multiple functions.
• Display enable (LDEN) for TFT panels
LDEN O 48 B10 LO3 0 • LCD back-plane bias signal (MOD) for all other LCD
panels
See Table 5-8 : LCD Interface Pin Mapping for summary.
This pin has multiple functions.
• PS for Sharp HR-TFT
LIS/
GPIO0 IO 45 C10 0 • General purpose IO pin 0 (GPIO0)
LT3
• Hardware Color Invert
See Table 5-8 : LCD Interface Pin Mapping for summary.
This pin has multiple functions.
• CLS for Sharp HR-TFT
GPIO1 IO 44 D7 LB3 0
• General purpose IO pin 1 (GPIO1)
See Table 5-8 : LCD Interface Pin Mapping for summary.
This pin has multiple functions.
• REV for Sharp HR-TFT
GPIO2 IO 43 D8 LB3 0
• General purpose IO pin 2 (GPIO2)
See Table 5-8 : LCD Interface Pin Mapping for summary.
This pin has multiple functions.
• SPL for Sharp HR-TFT
GPIO3 IO 42 D9 LB3 0
• General purpose IO pin 3 (GPIO3)
See Table 5-8 : LCD Interface Pin Mapping for summary.
This pin has multiple functions.
GPIO4 IO 41 D10 LB3 0 • General purpose IO pin 4 (GPIO4)
See Table 5-8 : LCD Interface Pin Mapping for summary.
This pin has multiple functions.
GPIO5 IO 40 E6 LB3 0 • General purpose IO pin 5 (GPIO5)
See Table 5-8 : LCD Interface Pin Mapping for summary.
This pin has multiple functions.
GPIO6 IO 39 E7 LB3 0 • General purpose IO pin 6 (GPIO6)
See Table 5-8 : LCD Interface Pin Mapping for summary.
This output pin has multiple functions.
LPWMOUT O 38 E8 LB3 0 • PWM Clock output
• General purpose output
This output pin has multiple functions.
LCVOUT O 46 C9 LB3 0 • CV Pulse Output
• General purpose output

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 5.3 Clock Input
Table 5-3 : Clock Input Pin Descriptions
TQFP TFBGA RESET#
Pin Name Type Cell Description
Pin # Pin # State
Typically used as input clock source for bus clock and
CLKI I 15 K6 LIS —
memory clock
This pin may be used as input clock source for pixel
AUXCLK I 77 B1 LIS — clock. This input pin must be connected to VSS if not
used.

5.4 Miscellaneous
Table 5-4 : Miscellaneous Pin Descriptions
TQFP TFBGA RESET
Pin Name Type Cell Description
Pin # Pin # # State
These inputs are used to configure the SSD1906 – see
Table 5-6 : Summary of Power-On/Reset Options.
C2, D1-
CF[7:0] I 78-85 D3, E1- LIS —
Note: These pins are used for configuration of the
E4
SSD1906 and must be connected directly to IOVDD
or VSS .
General Purpose Output (potentially used for controlling
GPO O 47 C8 LO3 0
the LCD power).

5.5 Power and Ground

Table 5-5 : Power And Ground Pin Descriptions
TQFP TFBGA RESET
Pin Name Type Cell Description
Pin # Pin # # State
16, 26, B9, C1,
Power supply pins. It is recommended to place a
IOVDD P 37, 49, C5, E9, P —
0.1µF bypass capacitor close to each of these pins.
63, 76 H7, J10
COREVDD pins are internal voltage regulator output
pins, used by the internal circuitry only. They
COREVDD P 1, 51 A9, K2 P — cannot be used for driving external circuitry.
Place a 0.1µF bypass capacitor close to each of
these pins.
A1,
14, 25, A10,
36, 50, B5,
VSS P P — Ground pins
62, 75, E10,
100 J6, K1,
K10

5.6 Summary of Configuration Options

These pins are used for configuration of the SSD1906 and must be connected directly to IOVDD or VSS. The state of
CF[5:0] is latched on the rising edge of RESET#, or after the software reset function is activated (REG[A2h] bit 0).
Changing state at any other time has no effect.

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 Table 5-6 : Summary of Power-On/Reset Options

SSD1906 Power-On/Reset State

Configuration
Input 1 (Connected to IOVDD) 0 (Connected to VSS)
Select host bus interface as follows:
CF2 CF1 CF0 Host Bus
0 0 0 SH-3/SH-4
0 0 1 MC68K #1
0 1 0 Reserved
0 1 1 Generic#1
CF[2:0]
1 0 0 Generic#2
1 0 1 Reserved
1 1 0 DragonBall (MC68EZ328/MC68VZ328)
1 1 1 Reserved

Note: The host bus interface is 17-bit only.

Configure GPIO pins as inputs at Configure GPIO pins as outputs at power-on
CF3
power-on (for use by HR-TFT when selected)
CF4 Big Endian bus interface Little Endian bus interface
CF5 WAIT# is active high WAIT# is active low
CLKI to BCLK divide select:
CF7 CF6 CLKI to BCLK Divide Ratio
0 0 1:1
CF[7:6]
0 1 2:1
1 0 3:1
1 1 4:1

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 5.7 Host Bus Interface Pin Mapping
Table 5-7 : Host Bus Interface Pin Mapping
Motorola
SSD1906 Pin Motorola MC68EZ328/ Hitachi Hitachi
Generic #1 Generic #2
Name MC68K #1 MC68VZ328 SH-3 SH-4
DragonBall
Connected to Connected to Connected to Connected to
A0 A0 LDS#
VSS VSS VSS VSS
A[17:1] A[17:1] A[17:1] A[17:1] A[17:1] A[17:1] A[17:1]
D[15:0] D[15:0] D[15:0] D[15:0]1 D[15:0] D[15:0] D[15:0]
CS# External Decode CSX# CSn# CSn#
M/R# External Decode
CLKI BUSCLK BUSCLK CLK CLKO CKIO CKIO
Connected to
BS# Connected to IOVDD AS# BS# BS#
IOVDD
Connected to Connected to
RD/WR# RD1# R/W# RD/WR# RD/WR#
IOVDD IOVDD
Connected to
RD# RD0# RD# OE# RD# RD#
IOVDD
Connected to
WE0# WE0# WE# LWE# WE0# WE0#
IOVDD
WE1# WE1# BHE# UDS# UWE# WE1# WE1#
WAIT# WAIT# WAIT# DTACK# DTACK# WAIT#/ RDY#
RESET# RESET# RESET# RESET# RESET# RESET# RESET#

Note
1
If the target MC68K bus is 32-bit then these signals should be connected to D[31:16].

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 5.8 LCD Interface Pin Mapping

Table 5-8 : LCD Interface Pin Mapping

Monochrome
Pin Name Color Passive Panel Color TFT Panel
Passive Panel

4-bit 8-bit 4-bit 8-bit 9-bit 12-bit 18-bit 18-bit Sharp

(format 1
HR-TFT
stripe)
LFRAME LFRAME SPS
LLINE LLINE LP
LSHIFT LSHIFT CLK
LDEN MOD LDEN Drive 0
2
LDATA0 Drive 0 D0 Drive 0 D0(G3) R2 R3 R5 R5
2
LDATA1 Drive 0 D1 Drive 0 D1(R3) R1 R2 R4 R4
2
LDATA2 Drive 0 D2 Drive 0 D2(B2) R0 R1 R3 R3
LDATA3 Drive 0 D3 Drive 0 D3(G2)2 G2 G3 G5 G5
2 2
LDATA4 D0 D4 D0(R2) D4(R2) G1 G2 G4 G4
LDATA5 D1 D5 D1(B1)2 D5(B1)2 G0 G1 G3 G3
LDATA6 D2 D6 D2(G1)2 D6(G1)2 B2 B3 B5 B5
LDATA7 D3 D7 D3(R1)2 D7(R1)2 B1 B2 B4 B4
LDATA8 Drive 0 Drive 0 Drive 0 Drive 0 B0 B1 B3 B3
LDATA9 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 R0 R2 R2
LDATA10 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 R1 R1
LDATA11 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 R0 R0
LDATA12 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 G0 G2 G2
LDATA13 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 G1 G1
LDATA14 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 G0 G0
LDATA15 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 B0 B2 B2
LDATA16 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 B1 B1
LDATA17 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 B0 B0
GPIO0 GPIO0 GPIO0 GPIO0 GPIO0 GPIO0 GPIO0 GPIO0 PS
GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 CLS
GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 REV
GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 SPL
GPIO4
GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4
(output only)
GPIO5
GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5 GPIO5
(output only)
GPIO6
GPIO6 GPIO6 GPIO6 GPIO6 GPIO6 GPIO6 GPIO6 GPIO6
(output only)
GPO GPO (General Purpose Output)
LCVOUT LCVOUT
LPWMOUT LPWMOUT

Note
1
GPIO pins must be configured as outputs (CF3 = 0 during RESET# active) when the HR-TFT panels are
selected.
2
These pin mappings use common signal names for each panel type. However signal names may differ between
panel manufacturers. The values shown in brackets represent the color components as mapped to the
corresponding LDATAxx signals at the first valid edge of LSHIFT. For further LDATAxx to LCD interface
mapping see Section 10.4 “Display Interface”.

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 5.9 Data Bus Organization
There are two data bus architectures; little endian and big endian. Little endian means the bytes at lower
addresses have a lower significance. Big endian means the most significant byte has the lowest address.

Table 5-9 : Data Bus Organization

D[15:8] D[7:0]
Big endian 2N 2N + 1
Little endian 2N + 1 2N

N : Byte Address

Table 5-10 : Pin State Summary

MCU Mode (Endian) A0 RD/WR# RD# WE1# WE0# Operation
Generic#1 (Big) X 0 0 1 1 Word read
X 0 1 1 1 High byte read 2N
X 1 0 1 1 Low byte read 2N+1
X 1 1 0 0 Word write
X 1 1 0 1 High byte write 2N
X 1 1 1 0 Low byte write 2N+1
Generic#1 (Little) X 0 0 1 1 Word read
X 0 1 1 1 High byte read 2N+1
X 1 0 1 1 Low byte read 2N
X 1 1 0 0 Word write
X 1 1 0 1 High byte write 2N+1
X 1 1 1 0 Low byte write 2N
Generic#2 (Big) 0 X 0 0 1 Word read
0 X 0 1 1 High byte read 2N
1 X 0 0 1 Low byte read 2N+1
0 X 1 0 0 Word write
0 X 1 1 0 High byte write 2N
1 X 1 0 0 Low byte write 2N+1
Generic#2 (Little) 0 X 0 0 1 Word read
1 X 0 0 1 High byte read 2N+1
0 X 0 1 1 Low byte read 2N
0 X 1 0 0 Word write
1 X 1 0 0 High byte write 2N+1
0 X 1 1 0 Low byte write 2N
MC68K#1 (Big) 0 1 X 0 X Word read
1 1 X 0 X High byte read 2N
0 1 X 1 X Low byte read 2N+1
0 0 X 0 X Word write
1 0 X 0 X High byte write 2N
0 0 X 1 X Low byte write 2N+1
MC68K#1 (Little) 0 1 X 0 X Word read
0 1 X 1 X High byte read 2N+1
1 1 X 0 X Low byte read 2N
0 0 X 0 X Word write
0 0 X 1 X High byte write 2N+1
1 0 X 0 X Low byte write 2N

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 MCU Mode (Endian) A0 RD/WR# RD# WE1# WE0# Operation
MC68EZ328 / X X 0 X X Word read
MC68VZ328 (Big) X X 1 0 0 Word write
X X 1 0 1 High byte write 2N
X X 1 1 0 Low byte write 2N+1
MC68EZ328 / X X 0 X X Word read
MC68VZ328 (Little) X X 1 0 0 Word write
X X 1 0 1 High byte write 2N+1
X X 1 1 0 Low byte write 2N
SH-3/SH-4 (Big) X X 0 1 1 Word read
X X 1 0 0 Word write
X X 1 0 1 High byte write 2N
X X 1 1 0 Low byte write 2N+1
SH-3/SH-4 (Little) X X 0 1 1 Word read
X X 1 0 0 Word write
X X 1 0 1 High byte write 2N+1
X X 1 1 0 Low byte write 2N

6 FUNCTIONAL BLOCK DESCRIPTIONS

6.1 MCU Interface

Responds to bus request for various kinds of MCU and translates to internal interface signals.

6.2 Control Register

The control register stores register data to control the LCD panel. The register data’s register value is controlled
through the MCU Interface read/write. The read/write access of LUT is also controlled by the control register. The
detail of this register and register mapping is discussed in Section 7 “Registers”.

6.3 Display Output

Display output serializes the display data from the display buffer and reconstructs this according to the display
panel format. When the display mode is not 16 bpp, display data is converted to color data by the built-in 18 bit
LUT. For details about LUT, please refer to Section 15 “Look-Up Table Architecture”.

6.4 Display Buffer

Display buffer consists of 256KB SRAM, organized as a 32-bit wide internal data path for fast retrieval of display
datal.

6.5 PWM Clock and CV Pulse Control

Provides programmable waveform for Pulse Width Modulation (PWM) and Contrast Voltage (CV) generation.

6.6 Clock Generator

Clock Generator provides internal clocks. For detailed operation of clock generator see Section 11 “Clocks”.

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 7 Registers
This section details how and where to access the SSD1906 registers and also provides detailed information about
the layout and use of each register.

7.1 Register Mapping

The SSD1906 registers are memory-mapped. When the system decodes the input pins, as CS# = 0 and M/R# = 0,
the registers may be accessed. The register space is decoded by A[17:0].

7.2 Register Descriptions

Unless specified otherwise, all register bits are set to 0 during power-on or software reset (REG[A2h] bit 0 = 1). All
bits marked “0” should be programmed as zero. All bits marked “1” should be programmed as one.

Key :
RO : Read Only
WO : Write Only
RW : Read/Write
NA : Not Applicable
X : Don’t Care

7.2.1 Read-Only Configuration Registers

Display Buffer Size Register REG[01h]

Bit 7 6 5 4 3 2 1 0
Display Display Display Display Display Display Display Display
Buffer Buffer Buffer Buffer Buffer Buffer Buffer Buffer
Size Size Size Size Size Size Size Size
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RO RO RO RO RO RO RO RO
Reset 0 1 0 0 0 0 0 0
state

Bits 7-0 Display Buffer Size Bits [7:0]

This register indicates the size of the SRAM display buffer in 4K byte multiple. The
SSD1906 display buffer is 256K bytes and therefore this register returns a value of 40h
(64).
Value of this register = display buffer size ÷ 4K bytes
= 256K bytes ÷ 4K bytes
= 40h (64)

Configuration Readback Register REG[02h]

Bit 7 6 5 4 3 2 1 0
CF7 Status CF6 Status CF5 Status CF4 Status CF3 Status CF2 Status CF1 Status CF0 Status
Type RO RO RO RO RO RO RO RO
Reset X X X X X X X X
state

Bits 7-0 CF[7:0] Status

These status bits return the status of the configuration pins CF[7:0]. CF[5:0] and are
latched at the rising edge of RESET# or software reset (REG[A2h] bit 0 = 1).

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 Product / Revision Code Register REG[03h]
Bit 7 6 5 4 3 2 1 0
Product Product Product Product Product Product Revision Revision
Code Code Code Code Code Code Code Bit 1 Code Bit 0
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RO RO RO RO RO RO RO RO
Reset 0 1 1 1 1 0 X X
state

Bits 7-2 Product Code Bits [5:0]

These are read-only bits that indicate the product code. The product code of SSD1906
is 011110.
Bits 1-0 Revision Code Bits [1:0]
These are read-only bits that indicate the revision code.

7.2.2 Clock Configuration Registers

Memory Clock Configuration Register REG[04h]

Bit 7 6 5 4 3 2 1 0
0 0 MCLK MCLK 0 0 0 0
Divide Divide
Select Bit 1 Select Bit 0
Type NA NA RW RW NA NA NA NA
Reset 0 0 0 0 0 0 0 0
state

Bits 5-4 MCLK Divide Select Bits [1:0]

These bits determine the divide used to generate the Memory Clock (MCLK) from the
Bus Clock (BCLK).

Table 7-1 : MCLK Divide Selection

MCLK Divide Select Bits [1:0] BCLK to MCLK Frequency Ratio
00 1:1
01 2:1
10 3:1
11 4:1

Pixel Clock Configuration Register REG[05h]

Bit 7 6 5 4 3 2 1 0
0 PCLK PCLK PCLK 0 0 PCLK PCLK
Divide Divide Divide Source Source
Select Bit 2 Select Bit 1 Select Bit 0 Select Bit 1 Select Bit 0
Type NA RW RW RW NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

Bits 6-4 PCLK Divide Select Bits [2:0]

These bits determine the divided used to generate the Pixel Clock (PCLK) from the
Pixel Clock Source.

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 Table 7-2 : PCLK Divide Selection
PCLK Divide Select Bits [2:0] PCLK Source to PCLK Frequency Ratio
000 1:1
001 2:1
010 3:1
011 4:1
1XX 8:1
x = don’t care

Bits 1-0 PCLK Source Select Bits [1:0]

These bits determine the source of the Pixel Clock (PCLK).

Table 7-3 : PCLK Source Selection

PCLK Source Select Bits [1:0] PCLK Source
00 MCLK
01 BCLK
10 CLKI
11 AUXCLK

7.2.3 Look-Up Table Registers

Look-Up Table Blue Write Data Register REG[08h]

Bit 7 6 5 4 3 2 1 0
LUT Blue LUT Blue LUT Blue LUT Blue LUT Blue LUT Blue X X
Write Data Write Data Write Data Write Data Write Data Write Data
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0
state

Bits 7-2 LUT Blue Write Data Bits [5:0]

This register contains the data to be written to the blue component of the Look-Up
Table.

The data is stored in this register, until a write to the LUT Write Address register
(REG[0Bh]) moves the data into the Look-Up Table.
Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is
written.

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 Look-Up Table Green Write Data Register REG[09h]
Bit 7 6 5 4 3 2 1 0
LUT Green LUT Green LUT Green LUT Green LUT Green LUT Green X X
Write Data Write Data Write Data Write Data Write Data Write Data
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0
state

Bits 7-2 LUT Green Write Data Bits [5:0]

This register contains the data to be written to the green component of the Look-Up
Table.
The data is stored in this register, until a write to the LUT Write Address register
(REG[0Bh]) moves the data into the Look-Up Table.

Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is
written.

Look-Up Table Red Write Data Register REG[0Ah]

Bit 7 6 5 4 3 2 1 0
LUT Red LUT Red LUT Red LUT Red LUT Red LUT Red X X
Write Data Write Data Write Data Write Data Write Data Write Data
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0
state

Bits 7-2 LUT Red Write Data Bits [5:0]

This register contains the data to be written to the red component of the Look-Up
Table.

The data is stored in this register, until a write to the LUT Write Address register
(REG[0Bh]) moves the data into the Look-Up Table.

Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is
written.

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 Look-Up Table Write Address Register REG[0Bh]
Bit 7 6 5 4 3 2 1 0
LUT Write LUT Write LUT Write LUT Write LUT Write LUT Write LUT Write LUT Write
Address Bit Address Bit Address Bit Address Bit Address Bit Address Bit Address Bit Address Bit
7 6 5 4 3 2 1 0
Type WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0
state

Bits 7-0 LUT Write Address Bits [7:0]

This register is a pointer to the Look-Up Table (LUT), is used to write LUT data stored
in REG[08h], REG[09h], and REG[0Ah]. Note: The data is updated to the LUT only
upon completion of a write to this register. This is a write-only register and returns
00h if read.

Note
The SSD1906 has three 256-entry, 6-bit-wide LUT’s, one each for red, green and blue
(see Section 15 “Look-Up Table Architecture”).

Look-Up Table Blue Read Data Register REG[0Ch]

Bit 7 6 5 4 3 2 1 0
LUT Blue LUT Blue LUT Blue LUT Blue LUT Blue LUT Blue 0 0
Read Data Read Data Read Data Read Data Read Data Read Data
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0
state

Bits 7-2 LUT Blue Read Data Bits [5:0]

This register contains the data from the blue component of the Look-Up Table. The
LUT entry read is controlled by the LUT Read Address Register (REG[0Fh]).Note: This
register is updated only when the LUT Read Address Register (REG[0Fh]) is
written.

Look-Up Table Green Read Data Register REG[0Dh]

Bit 7 6 5 4 3 2 1 0
LUT Green LUT Green LUT Green LUT Green LUT Green LUT Green 0 0
Read Data Read Data Read Data Read Data Read Data Read Data
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0
state

Bits 7-2 LUT Green Read Data Bits [5:0]

This register contains the data from the green component of the Look-Up Table. The
LUT entry read is controlled by the LUT Read Address Register (REG[0Fh]).

Note: This register is updated only when the LUT Read Address Register
(REG[0Fh]) is written.

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 Look-Up Table Red Read Data Register REG[0Eh]
Bit 7 6 5 4 3 2 1 0
LUT Red LUT Red LUT Red LUT Red LUT Red LUT Red 0 0
Read Data Read Data Read Data Read Data Read Data Read Data
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RO RO RO RO RO RO RO RO
Reset 0 0 0 0 0 0 0 0
state

Bits 7-2 LUT Red Read Data Bits [5:0]

This register contains the data from the red component of the Look-Up Table. The LUT
entry read is controlled by the LUT Read Address Register (REG[0Fh]). Note: This
register is updated only when the LUT Read Address Register (REG[0Fh]) is
written.

Look-Up Table Read Address Register REG[0Fh]

Bit 7 6 5 4 3 2 1 0
LUT Read LUT Read LUT Read LUT Read LUT Read LUT Read LUT Read LUT Read
Address Bit Address Bit Address Bit Address Bit Address Bit Address Bit Address Bit Address Bit
7 6 5 4 3 2 1 0
Type WO WO WO WO WO WO WO WO
Reset 0 0 0 0 0 0 0 0
state

Bits 7-0 LUT Read Address Bits [7:0]

This register is a pointer to the Look-Up Table (LUT) which is used to read LUT data
and store it in REG[0Ch], REG[0Dh], REG[0Eh]. The data is read from the LUT only
when a write to this register is completed. This is a write-only register and returns
00h if read.

Note: The SSD1906 has three 256-entry, 6-bit-wide LUT’s, one each for red, green
and blue (see Section 15 “Look-Up Table Architecture”).

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 7.2.4 Panel Configuration Registers

Panel Type Register REG[10h]

Bit 7 6 5 4 3 2 1 0
Color STN Color/Mono Panel Data Panel Data Active Panel Type Panel Type Panel Type
Panel Panel Width Bit 1 Width Bit 0 Panel Bit 2 Bit 1 Bit 0
Select Select Resolution
Select
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bit 7 Color STN Panel Select

When this bit = 0, non color STN LCD panel is selected.
When this bit = 1, color STN LCD panel is selected.
Bit 6 Color/Mono Panel Select
When this bit = 0, monochrome LCD panel is selected.
When this bit = 1, color LCD panel is selected.
Bits 5-4 Panel Data Width Bits [1:0]
These bits are determined by the data width of the LCD panel. Refer to Table 7-4 :
Panel Data Width Selection for the selection.

Table 7-4 : Panel Data Width Selection

Panel Data Width Bits [1:0] Passive Panel Data Width Active Panel Data Width
00 4-bit 9-bit
01 8-bit 12-bit
10 Reserved 18-bit
11 Reserved Reserved

Bit 3 Active Panel Resolution Select

This bit determines one of two panel resolutions when HR-TFT is selected, but hasno
effect unless HR-TFT is selected (REG[10h] bits 2:0 = 010).

Note
This bit sets some internal non-configurable timing values for the selected panel.
However, all panel configuration registers (REG[12h] – REG[40h]) still require
programming with the appropriate values for the selected panel.

For panel AC timing, see Section 10.4 “Display Interface”.

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 Table 7-5 : Active Panel Resolution Selection
Active Panel Resolution Select Bit HR-TFT Resolution
0 160x160
1 320x240

Bits 2-0 Panel Type Bits[2:0]

These bits select the panel type.

Table 7-6 : LCD Panel Type Selection

Panel Type Bits [2:0] Panel Type
000 STN
001 TFT
010 HR-TFT
011 , 100, 101, 110, 111 Reserved

MOD Rate Register REG[11h]

Bit 7 6 5 4 3 2 1 0
0 0 MOD Rate MOD Rate MOD Rate MOD Rate MOD Rate MOD Rate
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type NA NA RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bits 5-0 MOD Rate Bits [5:0]

When these bits are all 0, the MOD output signal (LDEN) toggles every LFRAME.
For any non-zero value n, the MOD output signal (LDEN) toggles every n LLINE.
These bits are for passive LCD panels only.

Horizontal Total Register REG[12h]

Bit 7 6 5 4 3 2 1 0
0 Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal
Total Bit 6 Total Bit 5 Total Bit 4 Total Bit 3 Total Bit 2 Total Bit 1 Total Bit 0
Type NA RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bits 6-0 Horizontal Total Bits [6:0]

These bits specify the LCD panel Horizontal,total period, in 8 pixel resolution. The
Horizontal Total is the sum of the Horizontal Display period plus the Horizontal Non-
Display period. The maximum Horizontal Total is 1024 pixels. See Figures 10-12.
“Panel Timing Parameters”.
Horizontal Total in number of pixels = (Bits [6:0] + 1) x 8.

Note:This register must be programmed so that:

HDPS + HDP < HT

For panel AC timing and timing parameter definitions, see Section 10.4 “Display
Interface”.

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 Horizontal Display Period Register REG[14h]
Bit 7 6 5 4 3 2 1 0
0 Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal
Display Display Display Display Display Display Display
Period Bit 6 Period Bit 5 Period Bit 4 Period Bit 3 Period Bit 2 Period Bit 1 Period Bit 0
Type NA RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bits 6-0 Horizontal Display Period Bits [6:0]

These bits specify the LCD panel Horizontal Display period, in 8 pixel resolution. The
Horizontal Display period should be less than the Horizontal Total, to allow for a
sufficient Horizontal Non-Display period.
Horizontal Display Period, in number of pixels = (Bits [6:0] + 1) x 8

Note:Maximum value of REG[14h] ≤ 0x3F when Display Rotate Mode (90°° or 270°°)
is selected.

For panel AC timing and timing parameter definitions, see Section 10.4 “Display
Interface”.

Horizontal Display Period Start Position Register 0 REG[16h]

Bit 7 6 5 4 3 2 1 0
Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal
Display Display Display Display Display Display Display Display
Period Start Period Start Period Start Period Start Period Start Period Start Period Start Period Start
Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit
7 6 5 4 3 2 1 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Horizontal Display Period Start Position Register 1 REG[17h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Horizontal Horizontal
Display Display
Period Start Period Start
Position Bit Position Bit
9 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[17h] bits1-0, Horizontal Display Period Start Position Bits [9:0]

REG[16h] bits 7-0 These bits specify the Horizontal Display Period Start Position in 1 pixel resolution.

For panel AC timing and timing parameter definitions, see Section 10.4 “Display
Interface”.

Vertical Total Register 0 REG[18h]

Bit 7 6 5 4 3 2 1 0
Vertical Vertical Vertical Vertical Vertical Vertical Vertical Vertical
Total Bit 7 Total Bit 6 Total Bit 5 Total Bit 4 Total Bit 3 Total Bit 2 Total Bit 1 Total Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Vertical Total Register 1 REG[19h]

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 Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Vertical Vertical
Total Bit 9 Total Bit 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[19h] bits 1-0, Vertical Total Bits [9:0]

REG[18h] bits 7-0 These bits specify the LCD panel Vertical Total period, in 1 line resolution. The Vertical
Total is the sum of the Vertical Display Period and the Vertical Non-Display Period.
The maximum Vertical Total is 1024 lines. See Figures 10-12. “Panel Timing
Parameters”. Vertical Total in number of lines = Bits [9:0]+ 1

Note: This register must be programmed so that

VDPS + VDP < VT

For panel AC timing and timing parameter definitions see Section 10.4 “Display
Interface”.

Vertical Display Period Register 0 REG[1Ch]

Bit 7 6 5 4 3 2 1 0
Vertical Vertical Vertical Vertical Vertical Vertical Vertical Vertical
Display Display Display Display Display Display Display Display
Period Bit 7 Period Bit 6 Period Bit 5 Period Bit 4 Period Bit 3 Period Bit 2 Period Bit 1 Period Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Vertical Display Period Register 1 REG[1Dh]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Vertical Vertical
Display Display
Period Bit 9 Period Bit 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[1Dh] bits 1-0, Vertical Display Period Bits [9:0]

REG[1Ch] bits 7-0 These bits specify the LCD panel Vertical Display period, in 1 line resolution. The
Vertical Display period should be less than the Vertical Total, allowing sufficient
Vertical Non-Display period.

Vertical Display Period, in number of lines = Bits [9:0] + 1

For panel AC timing and timing parameter definitions see Section 10.4 “Display
Interface”.

Solomon Systech Aug 2005 P 29/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 Vertical Display Period Start Position Register 0 REG[1Eh]
Bit 7 6 5 4 3 2 1 0
Vertical Vertical Vertical Vertical Vertical Vertical Vertical Vertical
Display Display Display Display Display Display Display Display
Period Start Period Start Period Start Period Start Period Start Period Start Period Start Period Start
Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit
7 6 5 4 3 2 1 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Vertical Display Period Start Position Register 1 REG[1Fh]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Vertical Vertical
Display Display
Start Start
Position Position
Period Bit 9 Period Bit 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[1Fh] bits 1-0, Vertical Display Period Start Position Bits [9:0]
REG[1Eh] bits 7-0 These bits specify the Vertical Display Period Start Position in 1 line resolution.

For panel AC timing and timing parameter definitions see Section 10.4 “Display
Interface”.

LLINE Pulse Width Register REG[20h]

Bit 7 6 5 4 3 2 1 0
LLINE LLINE LLINE LLINE LLINE LLINE LLINE LLINE
Pulse Pulse Width Pulse Width Pulse Width Pulse Width Pulse Width Pulse Width Pulse Width
Polarity Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bit 7 LLINE Pulse Polarity

This bit determines the polarity of the horizontal sync signal. The horizontal sync signal
is typically named as LLINE or LP, depending on the panel type.
When this bit = 0, the horizontal sync signal is active low.
When this bit = 1, the horizontal sync signal is active high.
Bits 6-0 LLINE Pulse Width Bits [6:0]
These bits specify the width of the panel horizontal sync signal, in number of PCLK.
The horizontal sync signal is typically named as LLINE or LP, depending on the panel
type.

LLINE Pulse Width in PCLK = Bits [6:0] + 1

For panel AC timing and timing parameter definitions see Section 10.4 “Display
Interface”.

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 LLINE Pulse Start Position Register 0 REG[22h]
Bit 7 6 5 4 3 2 1 0
LLINE LLINE LLINE LLINE LLINE LLINE LLINE LLINE
Pulse Start Pulse Start Pulse Start Pulse Start Pulse Start Pulse Start Pulse Start Pulse Start
Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit
7 6 5 4 3 2 1 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

LLINE Pulse Start Position Register 1 REG[23h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 LLINE LLINE
Pulse Start Pulse Start
Position Bit Position Bit
9 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[23h] bits 1-0, LLINE Pulse Start Position Bits [9:0]

REG[22h] bits 7-0 These bits specify the start position of the horizontal sync signal, in number of PCLK.

LLINE Pulses Start Position in PCLK = Bits [9:0] + 1

For panel AC timing and timing parameter definitions see Section10.4 “Display Interface”.

LFRAME Pulse Width Register REG[24h]

Bit 7 6 5 4 3 2 1 0
LFRAME 0 0 0 0 LFRAME LFRAME LFRAME
Pulse Pulse Width Pulse Width Pulse Width
Polarity Bit 2 Bit 1 Bit 0
Type RW NA NA NA NA RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bit 7 LFRAME Pulse Polarity

This bit selects the polarity of the vertical sync signal. The vertical sync signal is
typically named ;LFRAME or SPS, depending on the panel type.
When this bit = 0, the vertical sync signal is active at low.
When this bit = 1, the vertical sync signal is active at high.
Bits 2-0 LFRAME Pulse Width Bits [2:0]
These bits specify the width of the panel vertical sync signal, in 1 line resolution. The
vertical sync signal is typically named; LFRAME or SPS, depending on the panel type.
LFRAME Pulse Width in number of pixels = (Bits [2:0] + 1) x Horizontal Total + offset

For panel AC timing and timing parameter definitions see Section 10.4 “Display Interface”.

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 LFRAME Pulse Start Position Register 0 REG[26h]
Bit 7 6 5 4 3 2 1 0
LFRAME LFRAME LFRAME LFRAME LFRAME LFRAME LFRAME LFRAME
Pulse Start Pulse Start Pulse Start Pulse Start Pulse Start Pulse Start Pulse Start Pulse Start
Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit
7 6 5 4 3 2 1 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

LFRAME Pulse Start Position register 1 REG[27h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 LFRAME LFRAME
Pulse Start Pulse Start
Position Bit Position Bit
9 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[27h] bits 1-0 LFRAME Pulse Start Position Bits [9:0]

REG[26h] bits 7-0 These bits specify the start position of the vertical sync signal, in 1 line resolution.

LFRAME Pulse Start Position in number of pixels = (Bits [9:0]) x Horizontal Total +
offset

For panel AC timing and timing parameter definitions see Section 10.4 “Display Interface”.

LFRAME Pulse Start Offset Register 0 REG[30h]

Bit 7 6 5 4 3 2 1 0
LFRAME LFRAME LFRAME LFRAME LFRAME LFRAME LFRAME LFRAME
Start Offset Start Offset Start Offset Start Offset Start Offset Start Offset Start Offset Start Offset
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

LFRAME Pulse Start Offset Register 1 REG[31h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 LFRAME LFRAME
Start Offset Start Offset
Bit 9 Bit 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[31h] bits 1-0 LFRAME Pulse Start Offset [9:0]

REG[30h] bits 7-0 These bits specify the start offset of the vertical sync signal within a line, in 1 pixel
resolution.

For panel AC timing and timing parameter definitions see Section 10.4 “Display Interface”.

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 LFRAME Pulse Stop Offset Register 0 REG[34h]
Bit 7 6 5 4 3 2 1 0
LFRAME LFRAME LFRAME LFRAME LFRAME LFRAME LFRAME LFRAME
Stop Offset Stop Offset Stop Offset Stop Offset Stop Offset Stop Offset Stop Offset Stop Offset
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

LFRAME Pulse Stop Offset Register 1 REG[35h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 LFRAME LFRAME
Stop Offset Stop Offset
Bit 9 Bit 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[35h] bits 1-0 LFRAME Pulse Stop Offset [9:0]

REG[34h] bits 7-0 These bits specify the stop offset of the vertical sync signal in a line, in 1 pixel
resolution.

For panel AC timing and timing parameter definitions see Section 10.4 “Display Interface”.

HR-TFT Special Output Register REG[38h]

Bit 7 6 5 4 3 2 1 0
Reserved GPIO1 GPIO LSHIFT LSHIFT GPIO0 / PS CLS Double
Control Preset Polarity Mask GPIO1 Alternate
Enable swap Swap
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bit 7 Reserved bit

This bit should be programmed by 0.
Bit 6 GPIO1 Control
When this bit = 1, GPIO1 should be programmed with the appropriate values;
REG[3Ah] and [3Bh].
When this bit = 0, GPIO1 can toggle once per line.
Bit 5 GPIO Preset Enable
When this bit = 1, GPIO0 should be programmed with the appropriate values
;REG[3Ch], [3Eh] GPIO1 can be controlled by REG[38h] bit 6 and GPIO2 should be
programmed with REG[40h].
When this bit = 0, GPIO0, GPIO1 and GPIO2 signals are preset to defined values.
Bit 4 LSHIFT Polarity Swap
When this bit = 1, LSHIFT signal is falling trigger.
When this bit = 0, LSHIFT signal is rising trigger.
Bit 3 LSHIFT Mask
When this bit = 1, LSHIFT signal is enabled in non display period.
When this bit = 0, LSHIFT signal is masked in non display period.
Bit 2 GPIO0 / GPIO1 Swap
When this bit = 1, GPIO0/GPIO1 signals are swapped.
When this bit = 0, GPIO0/GPIO1 signals are not swapped.
Bit 1 PS Alternate
When this bit = 1, PS signal changes alternatively.

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 When this bit = 0, PS signal remains the same.
Bit 0 CLS Double
When this bit = 1, number of CLS pulses remain the same.
When this bit = 0, number of CLS pulses doubles.

Note
Bits 6-5 are effective for 320x240 HR-TFT panels only (REG[10h] bits 3-0 = 1010).

Bits 4-2 are effective for HR-TFT panels only (REG[10h] bits 2-0 = 010).

Bits 1-0 are effective for 160x160 HR-TFT panels only (REG[10h] bits 3-0 = 0010).

For panel AC timing and timing parameter definitions see Section 10.4.8 “160x160 Sharp
HR-TFT Panel Timing (e.g. LQ031B1DDxx)” and 10.4.9 “Generic HR-TFT Panel Timing”.

GPIO1 Pulse Start Register REG[3Ah]

Bit 7 6 5 4 3 2 1 0
GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1
Start Bit 7 Start Bit 6 Start Bit 5 Start Bit 4 Start Bit 3 Start Bit 2 Start Bit 1 Start Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bits 7-0 GPIO1 Pulse Start [7:0]

These bits specify the start offset of the GPIO1 signal within a line, in 1 pixel resolution.
See Figure 7-1 : GPIO Offset for 320x240 HR-TFT.

Note
This register must be programmed so that:.
GPIO1 Pulse Stop Value, REG[3Bh] ≥ GPIO1 Pulse Start Value, REG[3Ah]
GPIO1 Pulse Width = (STOP – START + 1) Ts
This register is effective for 320x240 HR-TFT panels and GPIO Preset enabled only
(REG[10h] bits 3-0 = 1010 and REG[38h] bit 6-5 = 11).

For panel AC timing and timing parameter definitions see Section 10.4.9 “Generic HR-TFT
Panel Timing.

GPIO1 Pulse Stop Register REG[3Bh]

Bit 7 6 5 4 3 2 1 0
GPIO1 Stop GPIO1 Stop GPIO1 Stop GPIO1 Stop GPIO1 Stop GPIO1 Stop GPIO1 Stop GPIO1 Stop
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bits 7-0 GPIO1 Pulse Stop [7:0]

These bits specify the stop offset of the GPIO1 signal within a line, in 1 pixel resolution.
See Figure 7-1 : GPIO Offset for 320x240 HR-TFT.

Note
This register must be programmed such so that:.
GPIO1 Pulse Stop Value, REG[3Bh] ≥ GPIO1 Pulse Start Value, REG[3Ah]
GPIO1 Pulse Width = (STOP – START + 1) Ts
This register is effective for 320x240 HR-TFT panels and GPIO Preset enabled only
(REG[10h] bits 3-0 = 1010 and REG[38h] bit 6-5 = 11).

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 For panel AC timing and timing parameter definitions see Section 10.4.9 “Generic HR-TFT
Panel Timing.

GPIO0 Pulse Start Register REG[3Ch]

Bit 7 6 5 4 3 2 1 0
GPIO0 GPIO0 GPIO0 GPIO0 GPIO0 GPIO0 GPIO0 GPIO0
Start Bit 7 Start Bit 6 Start Bit 5 Start Bit 4 Start Bit 3 Start Bit 2 Start Bit 1 Start Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bits 7-0 GPIO0 Pulse Start [7:0]

These bits specify the start offset of the GPIO0 signal within a line, in 1 pixel resolution.
See Figure 7-1 : GPIO Offset for 320x240 HR-TFT.

Note
This register must be programmed so that:.
GPIO0 Pulse Stop Value, REG[3Eh] ≥ GPIO0 Pulse Start Value, REG[3Ch]
GPIO0 Pulse Width = (STOP – START + 1) Ts
This register is effective for 320x240 HR-TFT panels and GPIO Preset enabled only
(REG[10h] bits 3-0 = 1010 and REG[38h] bit 5 = 1).

For panel AC timing and timing parameter definitions see Section 10.4.9 “Generic HR-TFT
Panel Timing”.

GPIO0 Pulse Stop Register REG[3Eh]

Bit 7 6 5 4 3 2 1 0
GPIO0 Stop GPIO0 Stop GPIO0 Stop GPIO0 Stop GPIO0 Stop GPIO0 Stop GPIO0 Stop GPIO0 Stop
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bits 7-0 GPIO0 Pulse Stop [7:0]

These bits specify the stop offset of the GPIO0 signal within a line, in 1 pixel resolution.
See Figure 7-1 : GPIO Offset for 320x240 HR-TFT.

Note
This register must be programmed so that:.
GPIO0 Pulse Stop Value, REG[3Eh] ≥ GPIO0 Pulse Start Value, REG[3Ch]
GPIO0 Pulse Width = (STOP – START + 1) Ts
This register is effective for 320x240 HR-TFT panels and GPIO Preset enabled only
(REG[10h] bits 3-0 = 1010 and REG[38h] bit 5 = 1).

For panel AC timing and timing parameter definitions see Section 10.4.9 “Generic HR-TFT
Panel Timing”.

GPIO2 Pulse Delay Register REG[40h]

Bit 7 6 5 4 3 2 1 0
GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2
Delay Bit 7 Delay Bit 6 Delay Bit 5 Delay Bit 4 Delay Bit 3 Delay Bit 2 Delay Bit 1 Delay Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

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 Bits 7-0 GPIO2 Pulse Delay [7:0]
These bits specify the pulse delay of the GPIO2 signal within a line, in 1 pixel
resolution. See Figure 7-1 : GPIO Offset for 320x240 HR-TFT.

Note
This register is effective for 320x240 HR-TFT panels and GPIO Preset enabled only
(REG[10h] bits 3-0 = 1010 and REG[38h] bit 5 = 1).

For panel AC timing and timing parameter definitions see Section 10.4.9 “Generic HR-TFT
Panel Timing”.

LLINE
(LP)

START1
GPIO1
(CLS)
STOP1
START0
GPIO0
(PS)

STOP0
DELAY
GPIO2
(REV)

* For REG[22] = 0,
START1 = 0 Ts if REG[3Ah] = 00; STOP1 = n+1 Ts if REG[3Bh] = n
START0 = 0 Ts if REG[3Ch] = 00; STOP0 = n+1 Ts if REG[3Eh] = n
DELAY = 0 Ts if REG[40h] = 00

Figure 7-1 : GPIO Offset for 320x240 HR-TFT

STN Color Depth Control Register REG[45h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 STN Color
Depth
Control
Type NA NA NA NA NA NA NA RW
Reset 0 0 0 0 0 0 0 0
state

Bit 0 STN Color Depth control

This bit controls the maximum number of colors available for STN panels.

When this bit = 0, it allows maximum 32k color depth.

When this bit = 1, it allows maximum 256k color depth.

Refer Table 7-8 : LCD Bit-per-pixel Selection for the color depth relationship.

Note
This register is effective for STN panel only (REG[10h] bits 2:0 = 000).
This register can be reset by the RESET signal pin only.

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 Dithering / FRC Control Register REG[50h]
Bit 7 6 5 4 3 2 1 0
Dynamic 0 0 0 Reserved Reserved 0 0
Dithering
Enable
Type RW NA NA NA RW RW NA NA
Reset 0 0 0 0 0 0 0 0
state

Bit 7 Dynamic Dithering Enable

This bit enables the dynamic dithering, the dithering mask changing after each 16
frames.

When this bit = 0, dynamic dithering is disabled.

When this bit = 1, dynamic dithering is enabled.

Note
This register is effective for both STN panel and dithering enabled (REG[10h] bits 2:0 =
000 and REG[70h] bit 6 = 0).
Bits 3-2 Reserved bit
These bits should be programmed by 0.

7.2.5 Display Mode Registers

Display Mode Register REG[70h]

Bit 7 6 5 4 3 2 1 0
Display Dithering Hardware Software 0 Bit-per-pixel Bit-per-pixel Bit-per-pixel
Blank Disable Color Invert Color Invert Select Bit 2 Select Bit 1 Select Bit 0
Enable
Type RW RW RW RW NA RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bit 7 Display Blank

When this bit = 0, the LCD display output is enabled.
When this bit = 1, the LCD display output is blank and all LCD data outputs are forced
to zero (i.e., the screen is blank).
Bit 6 Dithering Disable
SSD1906 uses a combination of FRC and 4 pixel square formation dithering to achieve
more colors per pixel.
When this bit = 0, dithering is enabled on the passive LCD panel,allowing maximum 64
intensity levels for each color component (RGB).
When this bit = 1, dithering is disabled on the passive LCD panel, allowing maximum
16 intensity levels for each color component (RGB).

Note
This bit does not refer to the number of simultaneously displayed colors, but rather the
maximum available colors (refer Table 7-8 : LCD Bit-per-pixel Selection for the
maximum number of displayed colors).
Bit 5 Hardware Color Invert Enable
This bit allows the Color Invert feature to be controlled using the General Purpose IO

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 pin GPIO0. This bit has no effect if REG[70h] bit 7 = 1. This option is not available if
configured for a HR-TFT as GPIO0 is used as an LCD control signal.

When this bit = 0, GPIO0 has no effect on the display color.

When this bit = 1, display color may be inverted via GPIO0.

Note
Display color is inverted after the Look-Up Table.
The SSD1906 requires some configurations before the hardware color invert feature is
enabled.
• CF3 must be set to 1 during RESET# activation
• GPIO Pin Input Enable (REG[A9h] bit 7) must be set to 1
• GPIO0 Pin IO Configuration (REG[A8h] bit 0) must be set to 0
If Hardware Color Invert is not available (i.e. HR-TFT panel is used), the color invert
function can be controlled by software using REG[70h] bit 4. See Table 7-7 : Color
Invert Mode Options summarizes the color invert options available.
Bit 4 Software Color Invert
When this bit = 0, display color is normal.
When this bit = 1, display color is inverted.
See Table 7-7 : Color Invert Mode Options. This bit has no effect if REG[70h] bit 7 = 1
or REG[70h] bit 5 = 1.

Note
Display color is inverted after the Look-Up Table.

Table 7-7 : Color Invert Mode Options

Hardware Color Invert Enable Software Color Invert GPIO0 Display Color
0 0 X Normal
0 1 X Invert
1 X 0 Normal
1 X 1 Invert
x = don’t care

Bits 2-0 Bit-per-pixel Select Bits [2:0]

These bits select the bpp color depth for the displayed data for both the main window
and the floating window (if active).
Note
1, 2, 4 and 8 bpp modes use the 18-bit LUT, allowing maximum 256K colors. 16 bpp
mode bypasses the LUT, allowing 64K colors.

Table 7-8 : LCD Bit-per-pixel Selection

Maximum Number of Colors/Shades
Max. No. Of
Passive Panel
Bit-per-pixel Color Depth Simultaneously
(Dithering On)
Select Bits [2:0] (bpp) TFT Panel Displayed
REG[45h] REG[45h] Colors/Shades
bit 0 = 0 bit 0 = 1
000 1 bpp 32K/32 256K/64 256K/64 2/2
001 2 bpp 32K/32 256K/64 256K/64 4/4
010 4 bpp 32K/32 256K/64 256K/64 16/16
011 8 bpp 32K/32 256K/64 256K/64 256/64
100 16 bpp 32K/32 64K/64 64K/64 64K/64
101, 110, 111 Reserved n/a n/a n/a n/a

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 Special Effects Register REG[71h]
Bit 7 6 5 4 3 2 1 0
Display Display 0 Floating 0 0 Display Display
Data Data Window Rotate Rotate
Word Swap Byte Swap Enable Mode Mode
Select Select
Bit 1 Bit 0
Type RW RW NA RW NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

Bit 7 Display Data Word Swap

The display pipe fetches 32-bit of data from the display buffer. This bit enables the
lower 16-bit word and the upper 16-bit word to be swapped before sending them to the
LCD display. If the Display Data Byte Swap bit is also enabled then the byte order of
the fetched 32-bit data is reversed.
Bit 6 Display Data Byte Swap
The display pipe fetches 32-bit of data from the display buffer. This bit enables
swapping of byte 0, byte 1, byte 2 and byte 3, before sending them to the LCD. If the
Display Data Word Swap bit is also set then the byte order of the fetched 32-bit data is
reversed.

Note
For further information on byte swapping for Big Endian mode, see Section 16 “Big-Endian
Bus Interface”.

byte 0

32-bit display data byte 1

from display buffer To LUT
Data
byte 2 Serialization

byte 3

Byte Swap Word Swap

Figure 7-2 : Display Data Byte/Word Swap

Bit 4 Floating Window Enable

This bit enables the floating window, within the main window, used for the Floating
Window feature. The location of the floating window within the main window is
determined by the Floating Window Position X registers (REG[84h], REG[85h],
REG[8Ch], REG[8Dh]) and Floating Window Position Y registers (REG[88h],
REG[89h], REG[90h], REG[91h]). The floating window has its own Display Start
Address register (REG[7Ch, REG[7Dh], REG[7Eh]) and Memory Address Offset
register (REG[80h], REG[81h]). The floating window shares the same color depth and
display orientation as the main window.

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 When this bit = 1, Floating Window is enabled.
When this bit = 0, Floating Window is disabled.
Bits 1-0 Display Rotate Mode Select Bits [1:0]
These bits select different display orientations:

Table 7-9 : Display Rotate Mode Select Options

Display Rotate Mode Select Bits [1:0] Display Orientation
00 0° (Normal)
01 90°
10 180°
11 270°

7.2.6 Main Window Registers

Main Window Display Start Address Register 0 REG[74h]

Bit 7 6 5 4 3 2 1 0
Main Main Main Main Main Main Main Main
window window window window window window window window
Display Display Display Display Display Display Display Display
Start Start Start Start Start Start Start Start
Address Address Address Address Address Address Address Address
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Main Window Display Start Address Register 1 REG[75h]

Bit 7 6 5 4 3 2 1 0
Main Main Main Main Main Main Main Main
window window window window window window window window
Display Display Display Display Display Display Display Display
Start Start Start Start Start Start Start Start
Address Address Address Address Address Address Address Address
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Main Window Display Start Address Register 2 REG[76h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 Main
window
Display
Start
Address
Bit 16
Type NA NA NA NA NA NA NA RW
Reset 0 0 0 0 0 0 0 0
state

REG[76h] bit 0, Main Window Display Start Address Bits [16:0]

REG[75h] bits 7-0, These bits form the 17-bit address for the starting double-word of the LCD image in the
REG[74h] bits 7-0 display buffer for the main window.

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 Note that this is a double-word (32-bit) address. An entry of 00000h into these
registers represents the first double-word of display memory, an entry of 00001h
represents the second double-word of the display memory and so forth.

Calculate the Display Start Address as follows :

Main Window Display Start Address Bits 16:0
= Image address ÷ 4 (valid only for Display Rotate Mode 0°)

Note
For information on setting this register for other Display Rotate Mode see Section 18
“Display Rotate Mode”.

Main Window Line Address Offset Register 0 REG[78h]

Bit 7 6 5 4 3 2 1 0
Main Main Main Main Main Main Main Main
window window window window window window window window
Line Line Line Line Line Line Line Line
Address Address Address Address Address Address Address Address
Offset Bit 7 Offset Bit 6 Offset Bit 5 Offset Bit 4 Offset Bit 3 Offset Bit 2 Offset Bit 1 Offset Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Main Window Line Address Offset Register 1 REG[79h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Main Main
window window
Line Line
Address Address
Offset Bit 9 Offset Bit 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[79h] bits 1-0, Main Window Line Address Offset Bits [9:0]
REG[78h] bits 7-0 This register specifies the offset, in double words, from the beginning of one display
line to the beginning of the next display line, in the main window. Note that this is a
32-bit address increment.

Calculate the Line Address Offset as follows :

Main Window Line Address Offset bits 9-0
= Display Width in pixels ÷ (32 ÷ bpp)

Note
A virtual display can be created by programming this register with a value greater than
the formula requires. When a virtual display is created the image width is larger than
the display width and the displayed image becomes a window into the larger, virtual
image.

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 7.2.7 Floating Window Registers

Floating Window Display Start Address Register 0 REG[7Ch]

Bit 7 6 5 4 3 2 1 0
Floating Floating Floating Floating Floating Floating Floating Floating
Window Window Window Window Window Window Window Window
Display Display Display Display Display Display Display Display
Start Start Start Start Start Start Start Start
Address Address Address Address Address Address Address Address
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Floating Window Display Start Address Register 1 REG[7Dh]

Bit 7 6 5 4 3 2 1 0
Floating Floating Floating Floating Floating Floating Floating Floating
Window Window Window Window Window Window Window Window
Display Display Display Display Display Display Display Display
Start Start Start Start Start Start Start Start
Address Address Address Address Address Address Address Address
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Floating Window Display Start Address Register 2 REG[7Eh]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 Floating
Window
Display
Start
Address
Bit 16
Type NA NA NA NA NA NA NA RW
Reset 0 0 0 0 0 0 0 0
state

REG[7Eh] bit 0, Floating Window Display Start Address Bits [16:0]

REG[7Dh] bits 7-0, These bits form the 17-bit address for the starting double-word of the floating window.
REG[7Ch] bits 7-0
Note that this is a double-word (32-bit) address. An entry of 00000h into these
registers represents the first double-word of display memory, an entry of 00001h
represents the second double-word of the display memory and so forth.

Note
These bits will not be effective until the Floating Window Enable bit is set to 1
(REG[71h] bit 4=1).

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 Floating Window Line Address Offset Register 0 REG[80h]
Bit 7 6 5 4 3 2 1 0
Floating Floating Floating Floating Floating Floating Floating Floating
Window Window Window Window Window Window Window Window
Line Line Line Line Line Line Line Line
Address Address Address Address Address Address Address Address
Offset Bit 7 Offset Bit 6 Offset Bit 5 Offset Bit 4 Offset Bit 3 Offset Bit 2 Offset Bit 1 Offset Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Floating Window Line Address Offset Register 1 REG[81h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Floating Floating
Window Window
Line Line
Address Address
Offset Bit 9 Offset Bit 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[81h] bits 1-0, Floating Window Line Address Offset Bits [9:0]
REG[80h] bits 7-0 These bits are the LCD displays 10-bit address offset from the starting double-word of
line “n” to the starting double-word of line “n + 1” for the floating window. Note that this
is a 32-bit address increment.

Note
These bits will not be effective until the Floating Window Enable bit is set to 1
(REG[71h] bit 4=1).

Floating Window Start Position X Register 0 REG[84h]

Bit 7 6 5 4 3 2 1 0
Floating Floating Floating Floating Floating Floating Floating Floating
Window Window Window Window Window Window Window Window
Start X Start X Start X Start X Start X Start X Start X Start X
Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit
7 6 5 4 3 2 1 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

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 Floating Window Start Position X Register 1 REG[85h]
Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Floating Floating
Window Window
Start X Start X
Position Bit Position Bit
9 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[85h] bits 1-0, Floating Window Start Position X Bits [9:0]

REG[84h] bits 7-0 These bits determine the start position X of the floating window, in relation to the origin
of the panel. Due to the SSD1906 Display Rotate feature, the start position X may not
be a horizontal position value (only true in 0° and 180° rotation). For further information
on defining the value of the Start Position X register see Section 19 “Floating Window
Mode”.

The value of this register is also increased differently, based on the display orientation.
For 0° and 180° Display Rotate Mode, the start position X is incremented by x pixels
where x is relative to the current color depth. Refer to Table 7-10 : 32-bit Address X
Increments for Various Color Depths. For 90° and 270° Display Rotate Mode, the start
position X is incremented by 1 line.

Depending on the color depth, some of the higher bits in this register are unused, as
the maximum horizontal display width is 1024 pixels.

Note
These bits will not be effective until the Floating Window Enable bit is set to 1
(REG[71h] bit 4=1).

Table 7-10 : 32-bit Address X Increments for Various Color Depths

Color Depth (bpp) Pixel Increment (x)
1 32
2 16
4 8
8 4
16 2

Floating Window Start Position Y Register 0 REG[88h]

Bit 7 6 5 4 3 2 1 0
Floating Floating Floating Floating Floating Floating Floating Floating
Window Window Window Window Window Window Window Window
Start Y Start Y Start Y Start Y Start Y Start Y Start Y Start Y
Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit
7 6 5 4 3 2 1 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

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 Floating Window Start Position Y Register 1 REG[89h]
Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Floating Floating
Window Window
Start Y Start Y
Position Bit Position Bit
9 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[89h] bits 1-0, Floating Window Start Position Y Bits [9:0]

REG[88h] bits 7-0 These bits determine the start position Y of the floating window in relation to the origin
of the panel. Due to the SSD1906 Display Rotate feature, the start position Y may not
be a vertical position value (only true in 0° and 180° Floating Window). For further
information on defining the value of the Start Position Y register see Section 19
“Floating Window Mode”.

The register is also incremented according to the display orientation. For 0° and 180°
Display Rotate Mode, the start position Y is incremented by 1 line. For 90° and 270°
Display Rotate Mode, the start position Y is incremented by y pixels where y is relative
to the current color depth. Refer to Table 7-11 : 32-bit Address Y Increments for
Various Color Depths.

Depending on the color depth, some of the higher bits in this register are unused, as
the maximum vertical display height is 1024 pixels.

Note
These bits will not effective until the Floating Window Enable bit is set to 1 (REG[71h]
bit 4=1).

Table 7-11 : 32-bit Address Y Increments for Various Color Depths

Color Depth (bpp) Pixel Increment (y)
1 32
2 16
4 8
8 4
16 2

Floating Window End Position X Register 0 REG[8Ch]

Bit 7 6 5 4 3 2 1 0
Floating Floating Floating Floating Floating Floating Floating Floating
Window Window Window Window Window Window Window Window
End X End X End X End X End X End X End X End X
Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit
7 6 5 4 3 2 1 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

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 Floating Window End Position X Register 1 REG[8Dh]
Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Floating Floating
Window Window
End X End X
Position Bit Position Bit
9 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[8Dh] bits 1-0, Floating Window End Position X Bits [9:0]

REG[8Ch] bits 7-0 These bits determine the end position X of the floating window in relation to the origin
of the panel. Due to the SSD1906 Display Rotate feature, the end position X may not
be a horizontal position value (only true in 0° and 180° rotation). For further information
on defining the value of the End Position X register see 19 “Floating Window Mode”.

The value of this register is also increased according to the display orientation. For 0°
and 180° Display Rotate Mode, the end position X is incremented by x pixels where x
is relative to the current color depth. Refer to Table 7-12 : 32-bit Address X Increments
for Various Color Depths. For 90° and 270° Display Rotate Mode, the end position X is
incremented by 1 line.

Depending on the color depth, some of the higher bits in this register are unused, as
the maximum horizontal display width is 1024 pixels.

Note
These bits will not be effective until the Floating Window Enable bit is set to 1
(REG[71h] bit 4=1).

Table 7-12 : 32-bit Address X Increments for Various Color Depths

Color Depth (bpp) Pixel Increment (x)
1 32
2 16
4 8
8 4
16 2

Floating Window End Position Y Register 0 REG[90h]

Bit 7 6 5 4 3 2 1 0
Floating Floating Floating Floating Floating Floating Floating Floating
Window Window Window Window Window Window Window Window
End Y End Y End Y End Y End Y End Y End Y End Y
Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit Position Bit
7 6 5 4 3 2 1 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

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 Floating Window End Position Y Register 1 REG[91h]
Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Floating Floating
Window Window
End Y End Y
Position Bit Position Bit
9 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[91h] bits 1-0, Floating Window End Position Y Bits [9:0]

REG[90h] bits 7-0 Due to the SSD1906 Display Rotate feature, the end position Y may not be a vertical
position value (only true in 0° and 180° Display Rotate Mode). For further information
on defining the value of the End Position Y register see Section 19 “Floating Window
Mode”.

The value of this register is also increased according to the display orientation. For 0°
and 180° Display Rotate Mode, the end position Y is incremented by 1 line. For 90°
and 270° Display Rotate Mode, the end position Y is incremented by y pixels where y
is relative to the current color depth. Refer to Table 7-13 : 32-bit Address Y Increments
for Various Color Depths.

Depending on the color depth, some of the higher bits in this register are unused, as
the maximum vertical display height is 1024 pixels.
Note
These bits will not be effective until the Floating Window Enable bit is set to 1
(REG[71h] bit 4=1).

Table 7-13 : 32-bit Address Y Increments for Various Color Depths

Color Depth (bpp) Pixel Increment (y)
1 32
2 16
4 8
8 4
16 2

7.2.8 Miscellaneous Registers

Power Saving Configuration Register REG[A0h]

Bit 7 6 5 4 3 2 1 0
Vertical 0 0 0 Memory 0 0 Power
Non- Controller Saving
Display Power Mode
Period Saving Enable
Status Status
Type RO NA NA NA RO NA NA RW
Reset 1 0 0 0 0 0 0 1
state

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 Bit 7 Vertical Non-Display Period Status
When this bit = 0, the LCD panel is in Vertical Display Period.
When this bit = 1, the LCD panel is in Vertical Non-Display Period.
Bit 3 Memory Controller Power Saving Status
This bit indicates the Power Saving status of the memory controller.
When this bit = 0, the memory controller is powered up.
When this bit = 1, the memory controller is powered down.
Bit 0 Power Saving Mode Enable
When this bit = 1, Power Saving mode is enabled.
When this bit = 0, Power Saving mode is disabled.

Software Reset Register REG[A2h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 Software
Reset
Type NA NA NA NA NA NA NA WO
Reset 0 0 0 0 0 0 0 0
state

Bit 0 Software Reset

When a one is written to this bit, the SSD1906 registers are reset. This bit has no
effect on the contents of the display buffer.

Scratch Pad Register 0 REG[A4h]

Bit 7 6 5 4 3 2 1 0
Scratch Scratch Scratch Scratch Scratch Scratch Scratch Scratch
Pad Pad Pad Pad Pad Pad Pad Pad
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Scratch Pad Register 1 REG[A5h]

Bit 7 6 5 4 3 2 1 0
Scratch Scratch Scratch Scratch Scratch Scratch Scratch Scratch
Pad Pad Pad Pad Pad Pad Pad Pad
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[A5h] bits 7-0, Scratch Pad Bits [15:0]

REG[A4h] bits 7-0 This register contains general purpose read/write bits. These bits have no effect on
hardware configuration.

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 Command Initialization Register REG[134h]
Bit 7 6 5 4 3 2 1 0
Command Command Command Command Command Command Command Command
Initial bit 7 Initial bit 6 Initial bit 5 Initial bit 4 Initial bit 3 Initial bit 2 Initial bit 1 Initial bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bits 7-0 Command Initialization Bits [7:0]

This is a startup register to initial the SSD1906 which should be programmed with 0x00
before register initialization.

7.2.9 General IO Pins Registers

General Purpose I/O Pins Configuration Register 0 REG[A8h]

Bit 7 6 5 4 3 2 1 0
0 GPIO6 I/O GPIO5 I/O GPIO4 I/O GPIO3 I/O GPIO2 I/O GPIO1 I/O GPIO0 I/O
Configuration Configuration Configuration Configuration Configuration Configuration Configuration
Type NA RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bit 6 GPIO6 I/O Configuration

When this bit = 0, GPIO6 is configured as an input pin.
When this bit = 1, GPIO6 is configured as an output pin.
Bit 5 GPIO5 I/O Configuration
When this bit = 0, GPIO5 is configured as an input pin.
When this bit = 1, GPIO5 is configured as an output pin.
Bit 4 GPIO4 I/O Configuration
When this bit = 0, GPIO4 is configured as an input pin.
When this bit = 1, GPIO4 is configured as an output pin.
Bit 3 GPIO3 I/O Configuration
When this bit = 0, GPIO3 is configured as an input pin.
When this bit = 1, GPIO3 is configured as an output pin.
Bit 2 GPIO2 I/O Configuration
When this bit = 0, GPIO2 is configured as an input pin.
When this bit = 1, GPIO2 is configured as an output pin.
Bit 1 GPIO1 I/O Configuration
When this bit = 0, GPIO1 is configured as an input pin.
When this bit = 1, GPIO1 is configured as an output pin.
Bit 0 GPIO0 I/O Configuration
When this bit = 0, GPIO0 is configured as an input pin.
When this bit = 1, GPIO0 is configured as an output pin.

Note
If CF3 = 0 during RESET# is active, then all GPIO pins are configured as outputs only and
this register has no effect. This case allows the GPIO pins to be used by the HR-TFT
panel interfaces. For a summary of GPIO usage for HR-TFT, see Table 5-8 : LCD
Interface Pin Mapping.

The input functions of the GPIO pins are not enabled until REG[A9h] bit 7 is set to 1.

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 General Purpose IO Pins Configuration Register 1 REG[A9h]
Bit 7 6 5 4 3 2 1 0
GPIO Pin 0 0 0 0 0 0 0
Input
Enable
Type RW NA NA NA NA NA NA NA
Reset 0 0 0 0 0 0 0 0
state

Bit 7 GPIO Pin Input Enable

This bit is used to enable the input function of the GPIO pins. It must be changed to a 1
after power-on reset to enable the input function of the GPIO pins.

General Purpose IO Pins Status/Control Register 0 REG[ACh]

Bit 7 6 5 4 3 2 1 0
0 GPIO6 Pin GPIO5 Pin GPIO4 Pin GPIO3 Pin GPIO2 Pin GPIO1 Pin GPIO0 Pin
IO Status IO Status IO Status IO Status IO Status IO Status IO Status
Type NA RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Note
For information on GPIO pin mapping when HR-TFT panels are selected, see Table 5-2 : LCD Interface Pin
Descriptions.

Bit 6 GPIO6 Pin IO Status

When GPIO6 is configured as an output, writing a 1 to this bit drives GPIO6 high and
writing a 0 to this bit drives GPIO6 low.
When GPIO6 is configured as an input, a read from this bit returns the status of
GPIO6.
Bit 5 GPIO5 Pin IO Status
When GPIO5 is configured as an output, writing a 1 to this bit drives GPIO5 high and
writing a 0 to this bit drives GPIO5 low.
When GPIO5 is configured as an input, a read from this bit returns the status of
GPIO5.
Bit 4 GPIO4 Pin IO Status
When GPIO4 is configured as an output, writing a 1 to this bit drives GPIO4 high and
writing a 0 to this bit drives GPIO4 low.
When GPIO4 is configured as an input, a read from this bit returns the status of
GPIO4.
Bit 3 GPIO3 Pin IO Status
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO3 is
configured as an output, writing a 1 to this bit drives GPIO3 high and writing a 0 to this
bit drives GPIO3 low.
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO3 is
configured as an input, a read from this bit returns the status of GPIO3.
When a HR-TFT panel is enabled (REG[10h] bits 2:0 = 010), the HR-TFT signal SPL
signal is enabled whatever the value of this bit.

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 Bit 2 GPIO2 Pin IO Status
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO2 is
configured as an output, writing a 1 to this bit drives GPIO2 high and writing a 0 to this
bit drives GPIO2 low.
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO2 is
configured as an input, a read from this bit returns the status of GPIO2.
When a HR-TFT panel is enabled (REG[10h] bits 2:0 = 010), the HR-TFT signal REV
signal is enabled whatever the value of this bit.
Bit 1 GPIO1 Pin IO Status
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO1 is
configured as an output, writing a 1 to this bit drives GPIO1 high and writing a 0 to this
bit drives GPIO1 low.
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO1 is
configured as an input, a read from this bit returns the status of GPIO1.
When a HR-TFT panel is enabled (REG[10h] bits 2:0 = 010), the HR-TFT signal CLS
signal is enabled whatever the value of this bit.
Bit 0 GPIO0 Pin IO Status
When a HR-TFT panel is not selected (REG[10h] bits 2:0 is not 010) and GPIO0 is
configured as an output, writing a 1 to this bit drives GPIO0 high and writing a 0 to this
bit drives GPIO0 low.
When a HR-TFT is not selected (REG[10h] bits 2:0 is not 010) and GPIO0 is
configured as an input, a read from this bit returns the status of GPIO0.
When a HR-TFT panel is enabled (REG[10h] bits 2:0 = 010), the HR-TFT signal PS
signal is enabled whatever the value of this bit.

General Purpose IO Pins Status/Control Register 1 REG[ADh]

Bit 7 6 5 4 3 2 1 0
GPO 0 0 0 0 0 0 0
Control
Type RW NA NA NA NA NA NA NA
Reset 0 0 0 0 0 0 0 0
state

Bit 7 GPO Control

This bit controls the General Purpose Output pin.
Writing a 0 to this bit drives GPO to low.
Writing a 1 to this bit drives GPO to high.

Note
Many implementations use the GPO pin to control the LCD bias power (see Section
10.3, “LCD Power Sequencing”).

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 7.2.10 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration
Registers
PWM Clock Enable
PWM Clock Divided PWM Duty Cycle
Clock Modulation
PWMCLK Divider
LPWMOUT
Clock Source/ 2m Duty = n / 256
Frequency =
m = PWM Clock Divide Select value n = PWM Clock Duty Cycle Clock Source / (2m X 256)
PW M Clock Force High
CV Pulse Force High
Divided CV Pulse Burst
CV Pulse Clock Generation
Divider LCVOUT
Clock Source/ 2x y-pulse burst
Frequency =
x = CV Pulse Divide Select value y = Burst Length value Clock Source / (2x X 2)

CV Pulse Enable

Figure 7-3 : PWM Clock/CV Pulse Block Diagram

Note
For further information on PWMCLK, see Section 11.1.4 “PWMCLK”.

PWM Clock / CV Pulse Control Register REG[B0h]

Bit 7 6 5 4 3 2 1 0
PWM Clock 0 0 PWM Clock CV Pulse CV Pulse CV Pulse CV Pulse
Force High Enable Force High Burst Burst Start Enable
Status
Type RW NA NA RW RW RO RW RW
Reset 0 0 0 0 0 0 0 0
state

Bit 7 and Bit 4 PWM Clock Force High (bit 7) and PWM Clock Enable (bit 4)
These bits control the LPWMOUT pin and PWM Clock circuitry as Table 7-14 : PWM
Clock Control.
When LPWMOUT is forced low or forced high it can be used as a general purpose
output.

Note
The PWM Clock circuitry is disabled when Power Saving Mode is enabled.

Table 7-14 : PWM Clock Control

Bit 7 Bit 4 Result
0 1 PWM Clock circuitry enabled
(controlled by REG[B1h] and REG[B3h])
0 0 LPWMOUT forced low
1 X LPWMOUT forced high
x = don’t care

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 Bit 3 and Bit 0 CV Pulse Force High (bit 3) and CV Pulse Enable (bit 0)
These bits control the LCVOUT pin and CV Pulse circuitry as Table 7-15 : CV Pulse
Control.
When LCVOUT is forced low or forced high it can be used as a general purpose
output.

Note
Bit 3 must be set to 0 and bit 0 must be set to 1 before initiating a new burst using the
CV Pulse Burst Start bit.
The CV Pulse circuitry is disabled when Power Saving Mode is enabled.

Table 7-15 : CV Pulse Control

Bit 3 Bit 0 Result
0 1 CV Pulse circuitry enabled (controlled by REG[B1h] and REG[B2h])
0 0 LCVOUT forced low
1 x LCVOUT forced high
x = don’t care

Bit 2 CV Pulse Burst Status

A “1” indicates a CV pulse burst is occurring. A “0” indicates no CV pulse burst is
occurring. Software should wait for this bit to clear before starting another burst.
Bit 1 CV Pulse Burst Start
A “1” in this bit initiates a single LCVOUT pulse burst. The number of clock pulses
generated is programmable from 1 to 256. The frequency of the pulses is the divided
CV Pulse source divided by 2, with 50/50 duty cycle. This bit should be cleared to 0 by
software before initiating a new burst.
Note
This bit has effect only if the CV Pulse Enable bit is 1.

PWM Clock / CV Pulse Configuration Register REG[B1h]

Bit 7 6 5 4 3 2 1 0
PWM Clock PWM Clock PWM Clock PWM Clock CV Pulse CV Pulse CV Pulse PWMCLK
Divide Divide Divide Divide Divide Divide Divide Source
Select Select Select Select Select Select Select Select
Bit 3 Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bits 7-4 PWM Clock Divide Select Bits [3:0]

The value of these bits represents the power of 2 by which the selected PWM clock
source is divided.

Note
This divided clock is further divided by 256 before it is output at LPWMOUT.
Table 7-16 : PWM Clock Divide Select Options
PWM Clock Divide Select Bits [3:0] PWM Clock Divide Amount
0h 1
1h 2
2h 4
3h 8
... ...
Ch 4096

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 Dh-Fh 1

Bits 3-1 CV Pulse Divide Select Bits [2:0]

The value of these bits represents the power of 2 by which the selected CV Pulse
source is divided.

Note
This divided clock is further divided by 2 before it is output at the LCVOUT.

Table 7-17 : CV Pulse Divide Select Options

CV Pulse Divide Select Bits [2:0] CV Pulse Divide Amount
0h 1
1h 2
2h 4
3h 8
... ...
7h 128

Bit 0 PWMCLK Source Select

When this bit = 0, the clock source for PWMCLK is CLKI.
When this bit = 1, the clock source for PWMCLK is AUXCLK.

Note
For further information on the PWMCLK source select, see Section 11 “Clocks”.

CV Pulse Burst Length Register REG[B2h]

Bit 7 6 5 4 3 2 1 0
CV Pulse CV Pulse CV Pulse CV Pulse CV Pulse CV Pulse CV Pulse CV Pulse
Burst Burst Burst Burst Burst Burst Burst Burst
Length Length Length Length Length Length Length Length
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bits 7-0 CV Pulse Burst Length Bits [7:0]

The value of this register determines the number of pulses generated in a single CV
Pulse burst:
Number of pulses in a burst = Bits [7:0] + 1

LPWMOUT Duty Cycle Register REG[B3h]

Bit 7 6 5 4 3 2 1 0
LPWMOUT LPWMOUT LPWMOUT LPWMOUT LPWMOUT LPWMOUT LPWMOUT LPWMOUT
Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle Duty Cycle
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Bits 7-0 LPWMOUT Duty Cycle Bits [7:0]

This register determines the duty cycle of the LPWMOUT output.

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 Table 7-18 : LPWMOUT Duty Cycle Select Options
LPWMOUT Duty Cycle [7:0] LPWMOUT Duty Cycle
00h Always Low
01h High for 1 out of 256 clock periods
02h High for 2 out of 256 clock periods
… …
FFh High for 255 out of 256 clock periods.

7.2.11 Cursor Mode Registers

Cursor Feature Register REG[C0h]

Bit 7 6 5 4 3 2 1 0
Cursor1 Cursor2 0 0 0 0 0 0
Enable Enable
Type RW RW NA NA NA NA NA NA
Reset 0 0 0 0 0 0 0 0
state

Bit 7 Cursor1 Enable

When this bit = 0 Cursor1 is disabled.
When this bit = 1 Cursor1 is enabled.
Bit 6 Cursor2 Enable
When this bit = 0, Cursor2 is disabled.
When this bit = 1, Cursor2 is enabled.

Note
This register is effective for 4/8/16 bpp (REG[70h] Bits 2:0 = 010/011/100)

For Hardware Cursors operation, see Section 20 “Hardware Cursor Mode”.

Cursor1 Blink Total Register 0 REG[C4h]

Bit 7 6 5 4 3 2 1 0
Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1
Blink Total Blink Total Blink Total Blink Total Blink Total Blink Total Blink Total Blink Total
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor1 Blink Total Register 1 REG[C5h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Cursor1 Cursor1
Blink Total Blink Total
Bit 9 Bit 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[C5h] bits 1-0, Cursor1 Blink Total Bits [9:0]

REG[C4h] bits 7-0 This is the total blinking period per frame for cursor1. This register must be set to a
non-zero value in order to make the cursor visible.

Note

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 These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
Cursor1 Blink On Register 0 REG[C8h]
Bit 7 6 5 4 3 2 1 0
Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1
Blink On Bit Blink On Bit Blink On Bit Blink On Bit Blink On Bit Blink On Bit Blink On Bit Blink On Bit
7 6 5 4 3 2 1 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor1 Blink On Register 1 REG[C9h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Cursor1 Cursor1
Blink On Bit Blink On Bit
9 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[C9h] bits 1-0, Cursor1 Blink On Bits [9:0]

REG[C8h] bits 7-0 This is the blink on frame period for Cursor1. This register must be set to a non-zero
value in order to make the cursor1 visible. Also, cursor1 will start to blink if the
following conditions are fulfilled :

Cursor1 Blink Total Bits [9:0] > Cursor1 Blink On Bits [9:0] > 0

Note
To enable cursor1 without blinking, user must program cursor1 blink on register with a
non-zero value, and this value must be greater than or equal to Cursor1 Blink Total
Register.
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).

Cursor1 Memory Start Register 0 REG[CCh]

Bit 7 6 5 4 3 2 1 0
Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1
Memory Memory Memory Memory Memory Memory Memory Memory
Start Bit 7 Start Bit 6 Start Bit 5 Start Bit 4 Start Bit 3 Start Bit 2 Start Bit 1 Start Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor1 Memory Start Register 1 REG[CDh]

Bit 7 6 5 4 3 2 1 0
Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1
Memory Memory Memory Memory Memory Memory Memory Memory
Start Bit 15 Start Bit 14 Start Bit 13 Start Bit 12 Start Bit 11 Start Bit 10 Start Bit 9 Start Bit 8
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor1 Memory Start Register 2 REG[CEh]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 Cursor1
Memory
Start Bit 16
Type NA NA NA NA NA NA NA RW
Reset 0 0 0 0 0 0 0 0

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 Bit 7 6 5 4 3 2 1 0
state

REG[CEh] bit 0, Cursor1 Memory Start Bits [16:0]

REG[CDh] bits 7-0, These bits form the 17-bit address for the starting double-word of the LCD image in the
REG[CCh] bits 7-0 display buffer for the Cursor1 image.

Note that this is a double-word (32-bit) address. An entry of 00000h into these
registers represents the first double-word of display memory, an entry of 00001h
represents the second double-word of the display memory, and so on.
Calculate the Cursor1 Start Address as follows :
Cursor1 Memory Start Bits 16:0
= Cursor Image address ÷ 4 (valid only for Display Rotate Mode 0°)

Note
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).

Cursor1 Position X Register 0 REG[D0h]

Bit 7 6 5 4 3 2 1 0
Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1
Position X Position X Position X Position X Position X Position X Position X Position X
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor1 Position X Register 1 REG[D1h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Cursor1 Cursor1
Position X Position X
Bit 9 Bit 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[D1h] bits 1-0, Cursor1 Position X Bits [9:0]

REG[D0h] bits 7-0 This is starting position X of Cursor1 image. The definition of this register is same as
Floating Window Start Position X Register.

Note
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).

Cursor1 Position Y Register 0 REG[D4h]

Bit 7 6 5 4 3 2 1 0
Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1
Position Y Position Y Position Y Position Y Position Y Position Y Position Y Position Y
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor1 Position Y Register 1 REG[D5h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Cursor1 Cursor1
Position Y Position Y
Bit 9 Bit 8

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 Bit 7 6 5 4 3 2 1 0
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[D5h] bits 1-0, Cursor1 Position Y Bits [9:0]

REG[D4h] bits 7-0 This is starting position Y of Cursor1 image. The definition of this register is same as
Floating Window Y Start Position Register.

Note
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).

Cursor1 Horizontal Size Register 0 REG[D8h]

Bit 7 6 5 4 3 2 1 0
Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1
Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal
Size Bit 7 Size Bit 6 Size Bit 5 Size Bit 4 Size Bit 3 Size Bit 2 Size Bit 1 Size Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor1 Horizontal Size Register 1 REG[D9h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Cursor1 Cursor1
Horizontal Horizontal
Size Bit 9 Size Bit 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[D9h] bits 1-0, Cursor1 Horizontal Size Bits [9:0]

REG[D8h] bits 7-0 These bits specify the horizontal size of Cursor1.

Note
The definition of this register various under different panel orientation and color depth
settings.
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).

Table 7-19 : X Increment Mode for Various Color Depths

Orientation Color Depths (bpp) Increment (x)
4
16 pixels increment
0û 8
e.g. 0000h = 16 pixels; 0001h = 32 pixels
16
4 2 lines increment
90û 8 4 lines increment
16 8 lines increment
4
180û 8 16 pixels increment
16
4 2 lines increment
270û 8 4 lines increment
16 8 lines increment

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 Cursor1 Vertical Size Register 0 REG[DCh]
Bit 7 6 5 4 3 2 1 0
Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1
Vertical Vertical Vertical Vertical Vertical Vertical Vertical Vertical
Size Bit 7 Size Bit 6 Size Bit 5 Size Bit 4 Size Bit 3 Size Bit 2 Size Bit 1 Size Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor1 Vertical Size Register 1 REG[DDh]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Cursor1 Cursor1
Vertical Vertical
Size Bit 9 Size Bit 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[DDh] bits 1-0, Cursor1 Vertical Size Bits [9:0]

REG[DCh] bits 7-0 These bits specify the vertical size of Cursor1.

Note
The definition of this register various under different panel orientation and color depth
settings.
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
Table 7-20 : Y Increment Mode for Various Color Depths
Orientation Color Depths (bpp) Increment (y)
4
1 line increment
0û 8 e.g. 0000h = 1 line; 0001h = 2 lines
16
4 8 pixels increment
90û 8 4 pixels increment
16 2 pixels increment
4
180û 8 1 line increment
16
4 8 pixels increment
270û 8 4 pixels increment
16 2 pixels increment

Cursor1 Color Index1 Register 0 REG[E0h]

Bit 7 6 5 4 3 2 1 0
Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1
Color Color Color Color Color Color Color Color
Index1 Bit 7 Index1 Bit 6 Index1 Bit 5 Index1 Bit 4 Index1 Bit 3 Index1 Bit 2 Index1 Bit 1 Index1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

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 Cursor1 Color Index1 Register 1 REG[E1h]
Bit 7 6 5 4 3 2 1 0
Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1
Color Color Color Color Color Color Color Color
Index1 Bit Index1 Bit Index1 Bit Index1 Bit Index1 Bit Index1 Bit Index1 Bit Index1 Bit
15 14 13 12 11 10 9 8
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[E1h] bits 7-0, Cursor1 Color Index1 Bits [15:0]

REG[E0h] bits 7-0 Each cursor pixel is represented by 2 bits. This register stores the color index for pixel
value 01 of Cursor1, refer to Table 20-1.

Note
These bits will not be effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit
7=1).

For Hardware Cursors operation see Section 20 “Hardware Cursor Mode”.

Cursor1 Color Index2 Register 0 REG[E4h]

Bit 7 6 5 4 3 2 1 0
Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1
Color Color Color Color Color Color Color Color
Index2 Bit 7 Index2 Bit 6 Index2 Bit 5 Index2 Bit 4 Index2 Bit 3 Index2 Bit 2 Index2 Bit 1 Index2 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor1 Color Index2 Register 1 REG[E5h]

Bit 7 6 5 4 3 2 1 0
Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1
Color Color Color Color Color Color Color Color
Index2 Bit Index2 Bit Index2 Bit Index2 Bit Index2 Bit Index2 Bit Index2 Bit Index2 Bit
15 14 13 12 11 10 9 8
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[E5h] bits 7-0, Cursor1 Color Index2 Bits [15:0]

REG[E4h] bits 7-0 Each cursor pixel is represented by 2 bits. This register stores the color index for pixel
value 10 of Cursor1, refer to Table 20-1.

Note
These bits will not be effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit
7=1).

For Hardware Cursors operation see Section 20 “Hardware Cursor Mode”.

Cursor1 Color Index3 Register 0 REG[E8h]

Bit 7 6 5 4 3 2 1 0
Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1
Color Color Color Color Color Color Color Color
Index3 Bit 7 Index3 Bit 6 Index3 Bit 5 Index3 Bit 4 Index3 Bit 3 Index3 Bit 2 Index3 Bit 1 Index3 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

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 Cursor1 Color Index3 Register 1 REG[E9h]
Bit 7 6 5 4 3 2 1 0
Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1 Cursor1
Color Color Color Color Color Color Color Color
Index3 Bit Index3 Bit Index3 Bit Index3 Bit Index3 Bit Index3 Bit Index3 Bit Index3 Bit
15 14 13 12 11 10 9 8
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[E9h] bits 7-0, Cursor1 Color Index3 Bits [15:0]

REG[E8h] bits 7-0 Each cursor pixel is represented by 2 bits. This register stores the color index for pixel
value 11 of Cursor1, refer to Table 20-1.

Note
These bits will not be effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit
7=1).

For Hardware Cursors operation see Section 20 “Hardware Cursor Mode”.

Cursor2 Blink Total Register 0 REG[ECh]

Bit 7 6 5 4 3 2 1 0
Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2
Blink Total Blink Total Blink Total Blink Total Blink Total Blink Total Blink Total Blink Total
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor2 Blink Total Register 1 REG[EDh]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Cursor2 Cursor2
Blink Total Blink Total
Bit 9 Bit 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[EDh] bits 1-0, Cursor2 Blink Total Bits [9:0]

REG[ECh] bits 7-0 This is the total blinking period per frame for Cursor2. This register must be set to a
non-zero value in order to make the cursor visible.

Note
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).

Cursor2 Blink On Register 0 REG[F0h]

Bit 7 6 5 4 3 2 1 0
Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2
Blink On Bit Blink On Bit Blink On Bit Blink On Bit Blink On Bit Blink On Bit Blink On Bit Blink On Bit
7 6 5 4 3 2 1 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

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 Cursor2 Blink On Register 1 REG[F1h]
Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Cursor2 Cursor2
Blink On Bit Blink On Bit
9 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[F1h] bits 1-0, Cursor2 Blink On Bits [9:0]

REG[F0h] bits 7-0 This is the blink on frame period for Cursor2. This register must be set to a non-zero
value in order to make the Cursor2 visible. Cursor2 will start to blink if:

Cursor2 Blink Total Bits [9:0] > Cursor2 Blink On Bits [9:0] > 0

Note
To enable Cursor2 without blinking the user must program Cursor2 Blink On Register
with a non-zero value and this value must be greater than or equal to Cursor2 Blink
Total Register.
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).

Cursor2 Memory Start Register 0 REG[F4h]

Bit 7 6 5 4 3 2 1 0
Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2
Memory Memory Memory Memory Memory Memory Memory Memory
Start Bit 7 Start Bit 6 Start Bit 5 Start Bit 4 Start Bit 3 Start Bit 2 Start Bit 1 Start Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor2 Memory Start Register 1 REG[F5h]

Bit 7 6 5 4 3 2 1 0
Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2
Memory Memory Memory Memory Memory Memory Memory Memory
Start Bit 15 Start Bit 14 Start Bit 13 Start Bit 12 Start Bit 11 Start Bit 10 Start Bit 9 Start Bit 8
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor2 Memory Start Register 2 REG[F6h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 Cursor2
Memory
Start Bit 16
Type NA NA NA NA NA NA NA RW
Reset 0 0 0 0 0 0 0 0
state

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 REG[F6h] bit 0, Cursor2 Memory Start Bits [16:0]
REG[F5h] bits 7-0, These bits form the 17-bit address for the starting double-word of the LCD image in the
REG[F4h] bits 7-0 display buffer for the Cursor2 image.

Note that this is a double-word (32-bit) address. An entry of 00000h into these
registers represents the first double-word of display memory, an entry of 00001h
represents the second double-word of the display memory and so forth.
Calculate the Cursor2 Start Address as follows:
Cursor2 Memory Start Bits 16:0
= Cursor Image address ÷ 4 (valid only for Display Rotate Mode 0°)

Note
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).

Cursor2 Position X Register 0 REG[F8h]

Bit 7 6 5 4 3 2 1 0
Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2
Position X Position X Position X Position X Position X Position X Position X Position X
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor2 Position X Register 1 REG[F9h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Cursor2 Cursor2
Position X Position X
Bit 9 Bit 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[F9h] bits 1-0, Cursor2 Position X Bits [9:0]

REG[F8h] bits 7-0 This is starting position X of Cursor2 image. The definition of this register is the same
as the Floating Window Start Position X Register.

Note
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).

Cursor2 Position Y Register 0 REG[FCh]

Bit 7 6 5 4 3 2 1 0
Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2
Position Y Position Y Position Y Position Y Position Y Position Y Position Y Position Y
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor2 Position Y Register 1 REG[FDh]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Cursor2 Cursor2
Position Y Position Y
Bit 9 Bit 8
Type NA NA NA NA NA NA RW RW

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 Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
state

REG[FDh] bits 1-0, Cursor2 Position Y Bits [9:0]

REG[FCh] bits 7-0 This is the starting position Y of Cursor2 image. The definition of this register is the
same as the Floating Window Y Start Position Register.

Note
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).

Cursor2 Horizontal Size Register 0 REG[100h]

Bit 7 6 5 4 3 2 1 0
Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2
Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal
Size Bit 7 Size Bit 6 Size Bit 5 Size Bit 4 Size Bit 3 Size Bit 2 Size Bit 1 Size Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor2 Horizontal Size Register 1 REG[101h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Cursor2 Cursor2
Horizontal Horizontal
Size Bit 9 Size Bit 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[101h] bits 1-0, Cursor2 Horizontal Size Bits [9:0]

REG[100h] bits 7-0 These bits specify the horizontal size of Cursor2.

Note
The definition of this register varies under different panel orientation and color depth
settings, refer to Table 7-19 : X Increment Mode for Various Color Depths.
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).

Cursor2 Vertical Size Register 0 REG[104h]

Bit 7 6 5 4 3 2 1 0
Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2
Vertical Vertical Vertical Vertical Vertical Vertical Vertical Vertical
Size Bit 7 Size Bit 6 Size Bit 5 Size Bit 4 Size Bit 3 Size Bit 2 Size Bit 1 Size Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor2 Vertical Size Register 1 REG[105h]

Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 Cursor2 Cursor2
Vertical Vertical
Size Bit 9 Size Bit 8
Type NA NA NA NA NA NA RW RW
Reset 0 0 0 0 0 0 0 0
state

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 Solomon Systech Aug 2005 P 66/159 Rev 1.1 SSD1906

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 REG[105h] bits 1-0, Cursor2 Vertical Size Bits [9:0]
REG[104h] bits 7-0 These bits specify the vertical size of Cursor2.

Note
The definition of this register varies under different panel orientation and color depth
settings, refer to Table 7-20 : Y Increment Mode for Various Color Depths.
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).

Cursor2 Color Index1 Register 0 REG[108h]

Bit 7 6 5 4 3 2 1 0
Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2
Color Color Color Color Color Color Color Color
Index1 Bit 7 Index1 Bit 6 Index1 Bit 5 Index1 Bit 4 Index1 Bit 3 Index1 Bit 2 Index1 Bit 1 Index1 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor2 Color Index1 Register 1 REG[109h]

Bit 7 6 5 4 3 2 1 0
Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2
Color Color Color Color Color Color Color Color
Index1 Bit Index1 Bit Index1 Bit Index1 Bit Index1 Bit Index1 Bit Index1 Bit 9 Index1 Bit 8
15 14 13 12 11 10
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[109h] bits 7-0 Cursor2 Color Index1 Bits [15:0]

REG[108h] bits 7-0 Each cursor pixel is represented by 2 bits. This register stores the color index for pixel
value 01 of Cursor2, refer to Table 20-1.

Note
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).

For Hardware Cursor operation see Section 20 “Hardware Cursor Mode”.

Cursor2 Color Index2 Register 0 REG[10Ch]

Bit 7 6 5 4 3 2 1 0
Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2
Color Color Color Color Color Color Color Color
Index2 Bit 7 Index2 Bit 6 Index2 Bit 5 Index2 Bit 4 Index2 Bit 3 Index2 Bit 2 Index2 Bit 1 Index2 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor2 Color Index2 Register 1 REG[10Dh]

Bit 7 6 5 4 3 2 1 0
Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2
Color Color Color Color Color Color Color Color
Index2 Bit Index2 Bit Index2 Bit Index2 Bit Index2 Bit Index2 Bit Index2 Bit 9 Index2 Bit 8
15 14 13 12 11 10
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0

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 Bit 7 6 5 4 3 2 1 0
state

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 REG[10Dh] bits 7-0 Cursor2 Color Index2 Bits [15:0]
REG[10Ch] bits 7-0 Each cursor pixel is represented by 2 bits. This register stores the color index for pixel
value 10 of Cursor2, refer to Table 20-1.

Note
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).

For Hardware Cursor operation see Section 20 “Hardware Cursor Mode”.

Cursor2 Color Index3 Register 0 REG[110h]

Bit 7 6 5 4 3 2 1 0
Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2
Color Color Color Color Color Color Color Color
Index3 Bit 7 Index3 Bit 6 Index3 Bit 5 Index3 Bit 4 Index3 Bit 3 Index3 Bit 2 Index3 Bit 1 Index3 Bit 0
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

Cursor2 Color Index3 Register 1 REG[111h]

Bit 7 6 5 4 3 2 1 0
Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2 Cursor2
Color Color Color Color Color Color Color Color
Index3 Bit Index3 Bit Index3 Bit Index3 Bit Index3 Bit Index3 Bit Index3 Bit 9 Index3 Bit 8
15 14 13 12 11 10
Type RW RW RW RW RW RW RW RW
Reset 0 0 0 0 0 0 0 0
state

REG[111h] bits 7-0 Cursor2 Color Index3 Bits [15:0]

REG[110h] bits 7-0 Each cursor pixel is represented by 2 bits. This register stores the color index for pixel
value 11 of Cursor2, refer to Table 20-1.

Note
These bits will not be effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit
6=1).

For Hardware Cursor operation, see Section 20 “Hardware Cursor Mode”.

8 MAXIMUM RATINGS
Table 8-1 : Absolute Maximum Ratings
Symbol Parameter Rating Units
IOVDD Supply Voltage VSS - 0.3 to 4.0 V
VIN Input Voltage VSS - 0.3 to 5.0 V
VOUT Output Voltage VSS - 0.3 to IOVDD + 0.5 V
TSTG Storage Temperature -65 to 150 °C
TSOL Solder Temperature/Time 260 for 10 sec. max at lead °C

Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be
restricted to the limits in the Electrical Characteristics tables or Pin Description section.

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 This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields;
however, it is advised that normal precautions are taken to avoid exposure to the high impedance circuit of any voltage
higher than the maximum rated voltages . For correct operation it is recommended that VIN and VOUT be constrained to
the range VSS ≤ (VIN or VOUT) ≤ IOVDD. Reliability of operation is enhanced if unused input is connected to an
appropriate logic voltage level (e.g., either VSS or IOVDD). This device is not radiation protected.

Table 8-2 : Recommended Operating Conditions

Symbol Parameter Condition Min Typ Max Units
IOVDD Supply Voltage VSS = 0V 3.0 3.3 3.6 V
VIN Input Voltage VSS IOVDD V
TOPR Operating Temperature -30 25 85 °C

9 DC CHARACTERISTICS

Table 9-1 : Electrical Characteristics for IOVDD = 3.3V typical

Symbol Parameter Condition Min Typ Max Units
IDDS Quiescent Current Quiescent Conditions 120 µA
IIZ Input Leakage Current -1 1 µA
IOZ Output Leakage Current -1 1 µA
VOH High Level Output Voltage IOVDD = min IOVDD -0.4 V
IOH = -8mA (Type 2)
-12mA (Type 3)
VOL Low Level Output Voltage IOVDD = min 0.4 V
IOL = 8mA (Type2)
12mA (Type 3)
VIH High Level Input Voltage LVTTL Level, IOVDD = max IOVDD -0.8 V
VIL Low Level Input Voltage LVTTL Level, IOVDD = min 0.8 V
VT+ High Level Input Voltage LVTTL Schmitt 1.1 V

VT- Low Level Input Voltage LVTTL Schmitt 0.94 V

VH1 Hysteresis Voltage LVTTL Schmitt 0.15 V
CI Input Pin Capacitance 10 pF
CO Output Pin Capacitance 10 pF
CIO Bi-Directional Pin 10 pF
Capacitance

10 AC CHARACTERISTICS
Conditions: IOVDD = 3.3V ± 10%
TA = -30°C to 85°C
Trise and Tfall for all inputs must be < 5 ns (10% ~ 90%)
CL = 50pF (Bus/CPU Interface)
CL = 0pF (LCD Panel Interface)

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 10.1 Clock Timing

10.1.1 Input Clocks

Clock Input Waveform

tPWH tPWL

90%
VIH
VIL
10%

tf
tr

TOSC

Figure 10-1 : Clock Input Requirements

Table 10-1 : Clock Input Requirements for CLKI

Symbol Parameter Min Max Units
fOSC Input Clock Frequency (CLKI) 66 MHz
TOSC Input Clock period (CLKI) 1/fOSC ns
tPWH Input Clock Pulse Width High (CLKI) 5 ns
tPWL Input Clock Pulse Width Low (CLKI) 5 ns
tf Input Clock Fall Time (10% - 90%) 5 ns
tr Input Clock Rise Time (10% - 90%) 5 ns

Note
Maximum internal requirements for clocks, derived from CLKI, must be considered when determining the
frequency of CLKI. See Section 10.1.2 “Internal Clocks” for internal clock requirements.

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 Table 10-2 : Clock Input Requirements for AUXCLK
Symbol Parameter Min Max Units
fOSC Input Clock Frequency (AUXCLK) 66 MHz
TOSC Input Clock period (AUXCLK) 1/fOSC ns
tPWH Input Clock Pulse Width High 5 ns
(AUXCLK)
t PWL Input Clock Pulse Width Low 5 ns
(AUXCLK)
tf Input Clock Fall Time (10% - 90%) 5 ns
tr Input Clock Rise Time (10% - 90%) 5 ns

Note :
Maximum internal requirements for clocks, derived from AUXCLK, must be considered when determining the
frequency of AUXCLK. See Section 10.1.2 “Internal Clocks” for internal clock requirements.

10.1.2 Internal Clocks

Table 10-3 : Internal Clock Requirements

Symbol Parameter Min Max Units
fBCLK Bus Clock frequency 66 MHz
fMCLK Memory Clock frequency 55 MHz
fPCLK Pixel Clock frequency 55 MHz
fPWMCLK PWM Clock frequency 66 MHz

Note :
For further information on internal clocks refer to Section 11 “Clocks”.

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 10.2 CPU Interface Timing
The following section is the CPU interface AC Timing based on IOVDD = 3.3V.

10.2.1 Generic #1 Interface Timing

TCLK t1 t2

CLK

t3 t4

A[17:1],
M/R#,

t5 t6

CS#
t7
t8
RD0#, RD1#
WE0#, WE1#
t10
t9

WAIT#

t11 t12

D[15:0]
(write)

t13 t14 t15

D[15:0]
(read) VALID

Figure 10-2 : Generic #1 Interface Timing

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 Table 10-4 : Generic #1 Interface Timing
Symbol Parameter Min Max Units
fCLK Bus Clock frequency 66 MHz
TCLK Bus Clock period 1/fCLK ns
t1 Clock pulse width high 6 ns
t2 Clock pulse width low 6 ns
t3 A[17:1], M/R# setup to first CLK rising edge where CS# = 0 and 1 ns
either RD0#, RD1# = 0 or WE0#, WE1# = 0
t4 A[17:1], M/R# hold from either RD0#, RD1# or WE0#, WE1# 0 ns
rising edge
t5 CS# setup to CLK rising edge 1 ns
t6 CS# hold from either RD0#, RD1# or WE0#, WE1# rising edge 1 ns
t7a RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK 13 TCLK
t7b RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK ÷2 18 TCLK
t7c RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK ÷3 23 TCLK
t7d RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK ÷4 28 TCLK
t8 RD0#, RD1#, WE0#, WE1# setup to CLK rising edge 1 ns
t9 Falling edge of either RD0#, RD1# or WE0#, WE1# to WAIT# 3 15 ns
driven low
t10 Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT# 3 13 ns
high impedance
t11 D[15:0] setup to third CLK rising edge where CS# = 0 and 0 ns
WE0#,WE1#=0 (write cycle)(see note 1)
t12 D[15:0] hold from WAIT# rising edge (write cycle) 0 ns
t13 RD0#, RD1# falling edge to D[15:0] driven (read cycle) 3 14 ns
t14 WAIT# rising edge to D[15:0] valid (read cycle) 2 ns
t15 RD0#, RD1# rising edge to D[15:0] high impedance (read cycle) 3 11 ns

1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.

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 10.2.2 Generic #2 Interface Timing (e.g. ISA)

TBUSCLK t1 t2

BUSCLK

t3 t4

SA[17:0],
M/R#, SBHE#

t5 t6

CS#
t7
t8
MEMR#
MEMW#
t10
t9

IOCHRDY

t11 t12

SD[15:0]
(write)

t13 t14 t15

SD[15:0]
(read) VALID

Figure 10-3 : Generic #2 Interface Timing

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 Table 10-5 : Generic #2 Interface Timing
Symbol Parameter Min Max Units
fBUSCLK Bus Clock frequency 66 MHz
TBUSCLK Bus Clock period 1/fBUSCLK ns
t1 Clock pulse width high 6 ns
t2 Clock pulse width low 6 ns
t3 SA[17:0], M/R#, SBHE# setup to first BUSCLK rising edge 1 ns
where CS# = 0 and either MEMR# = 0 or MEMW# = 0
t4 SA[17:0], M/R#, SBHE# hold from either MEMR# or MEMW# 0 ns
rising edge
t5 CS# setup to BUSCLK rising edge 1 ns
t6 CS# hold from either MEMR# or MEMW# rising edge 0 ns
t7a MEMR# or MEMW# asserted for MCLK = BCLK 13 TBUSCLK
t7b MEMR# or MEMW# asserted for MCLK = BCLK ÷2 18 TBUSCLK
t7c MEMR# or MEMW# asserted for MCLK = BCLK ÷3 23 TBUSCLK

t7d MEMR# or MEMW# asserted for MCLK = BCLK ÷4 28 TBUSCLK

t8 MEMR# or MEMW# setup to BUSCLK rising edge 1 ns

t9 Falling edge of either MEMR# or MEMW# to IOCHRDY driven 3 15 ns
low
t10 Rising edge of either MEMR# or MEMW# to IOCHRDY high 3 13 ns
impedance
t11 SD[15:0] setup to third BUSCLK rising edge where CS# = 0 and 0 ns
MEMW#=0 (write cycle)(see note1)
t12 SD[15:0] hold from IOCHRDY rising edge (write cycle) 0 ns
t13 MEMR# falling edge to SD[15:0] driven (read cycle) 3 13 ns
t14 IOCHRDY rising edge to SD[15:0] valid (read cycle) 2 ns
t15 Rising edge of MEMR# to SD[15:0] high impedance (read 3 12 ns
cycle)

1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.

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 10.2.3 Motorola MC68K #1 Interface Timing (e.g. MC68000)
TCLK t1 t2

CLK

t3 t4

A[17:1],
M/R#

t5 t6

CS#
t7
t8 t9
AS#

t11
t10 t12
UDS#,
LDS#

t13 t14

R/W#

t15 t16

DTACK#

t17 t18

D[15:0]
(write)

t19 t20 t21

D[15:0]
VALID
(read)

Figure 10-4 : Motorola MC68K #1 Interface Timing

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 Table 10-6 : Motorola MC68K #1 Interface Timing
Symbol Parameter Min Max Units
fCLK Bus Clock frequency 66 MHz
TCLK Bus Clock period 1/fCLK ns
t1 Clock pulse width high 6 ns
t2 Clock pulse width low 6 ns
t3 A[17:1], M/R# setup to first CLK rising edge where CS# = 0, 1 ns
AS#=0,UDS#=0,and LDS#=0
t4 A[17:1], M/R# hold from AS# rising edge 0 ns
t5 CS# setup to CLK rising edge while AS#, UDS#/LDS# = 0 1 ns
t6 CS# hold from AS# rising edge 0 ns
t7a AS# asserted for MCLK = BCLK 13 TCLK
t7b AS# asserted for MCLK = BCLK ÷2 18 TCLK
t7c AS# asserted for MCLK = BCLK ÷3 23 TCLK
t7d AS# asserted for MCLK = BCLK ÷4 28 TCLK
t8 AS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# =0 1 ns
t9 AS# setup to CLK rising edge 2 TCLK
t10 UDS#/LDS# setup to CLK rising edge while CS#, AS#, 1 ns
UDS#/LDS# = 0
t11 UDS#/LDS# high setup to CLK rising edge 2 ns
t12 First CLK rising edge where AS#=1 to DTACK# high 3 14 ns
impedance
t13 R/W# setup to CLK rising edge before all CS#, AS#, UDS# 1 ns
and/or LDS# = 0
t14 R/W# hold from AS# rising edge 0 ns
t15 AS# = 0 and CS# = 0 to DTACK# driven high 3 13 ns
t16 AS# rising edge to DTACK# rising edge 4 16 ns
t17 D[15:0] valid to third CLK rising edge where CS# = 0, AS# = 0 0 ns
and either UDS# = 0 or LDS# = 0 (write cycle) (see note 1)
t18 D[15:0] hold from DTACK# falling edge (write cycle) 0 ns
t19 UDS# = 0 and/or LDS# = 0 to D[15:0] driven (read cycle) 3 13 ns
t20 DTACK# falling edge to D[15:0] valid (read cycle) 2 ns
t21 UDS#, LDS# rising edge to D[15:0] high impedance (read 3 13 ns
cycle)

1. t17 is the delay from when data is placed on the bus until the data is latched into the write buffer.

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 10.2.4 Motorola DragonBall Interface Timing with DTACK# (e.g. MC68EZ328/MC68VZ328)
TCLKO t1 t2

CLKO

t3 t4

A[17:1]

t5
t6 t7
CSX#

UWE#/LWE# t8 t9

(write)

t10 t11
OE#
(read)

t12 t13
Hi-Z Hi-Z
D[15:0]
(write)
t14 t15

Hi-Z Hi-Z
D[15:0]
VALID
(read)
t16 t19
t17 t18

DTACK#

Figure 10-5 : Motorola DragonBall Interface with DTACK# Timing

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 Table 10-7 : Motorola DragonBall Interface with DTACK# Timing
Symbol Parameter MC68EZ328 MC68VZ328 Units
Min Max Min Max
fCLKO Bus Clock frequency 16 33 MHz
TCLKO Bus Clock period 1/fCLKO 1/fCLKO ns
t1 Clock pulse width high 28.1 13.5 ns
t2 Clock pulse width low 28.1 13.5 ns
t3 A[17:1] setup 1st CLKO when CSX# = 0 and 0 0 ns
either UWE#/LWE# or OE# =0
t4 A[17:1] hold from CSX# rising edge 0 0 ns
t5a CSX# asserted for MCLK = BCLK 13 13 TCLKO
t5b CSX# asserted for MCLK = BCLK ÷2 18 18 TCLKO
t5c CSX# asserted for MCLK = BCLK ÷3 23 23 TCLKO
t5d CSX# asserted for MCLK = BCLK ÷4 28 28 TCLKO
t6 CSX# setup to CLKO rising edge 0 0 ns
t7 CSX# rising edge to CLKO rising edge 0 0 ns
t8 UWE#/LWE# falling edge to CLKO rising 0 0 ns
edge
t9 UWE#/LWE# rising edge to CSX# rising 0 0 ns
edge
t10 OE# falling edge to CLKO rising edge 1 1 ns
t11 OE# hold from CSX# rising edge 0 0 ns
t12 D[15:0] setup to 3rd CLKO when CSX#, 0 0 ns
UWE#/LWE# asserted (write cycle) (see
note 1)
t13 D[15:0] in hold from CSX# rising 0 0 ns
edge(write cycle)
t14 Falling edge of OE# to D[15:0] driven 3 15 3 15 ns
(read cycle)
t15 CLKO rising edge to D[15:0] output Hi-Z 2 12 2 12 ns
(read cycle)
t16 CSX# falling edge to DTACK# driven 3 13 3 13 ns
high
t17 DTACK# falling edge to D[15:0]valid 2 2 ns
(read cycle)
t18 CSX# high to DTACK# high 3 16 3 16 ns
t19 CLKO rising edge to DTACK# Hi-Z 1 6 1 6 ns
1
t12 is the delay from when data is placed on the bus until the data is latched into the write buffer.

Solomon Systech Aug 2005 P 80/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 10.2.5 Motorola DragonBall Interface Timing without DTACK# (e.g. MC68EZ328/MC68VZ328)

TCLKO t1 t2

CLKO
t3 t4

A[17:1]

t5
t6 t7

CSX#

t8 t9
UWE#/LWE#
(write)

t10 t11
OE#
(read)

t12 t13
Hi-Z Hi-Z
D[15:0]
(write)
t15 t16
t14
Hi-Z Hi-Z
D[15:0]
VALID
(read)

Figure 10-6 : Motorola DragonBall Interface without DTACK# Timing

Solomon Systech Aug 2005 P 81/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 Table 10-8 : Motorola DragonBall Interface without DTACK# Timing
Symbol Parameter MC68EZ328 MC68VZ328 Units
Min Max Min Max
fCLKO Bus Clock frequency 16 33 MHz
TCLKO Bus Clock period 1/fCLKO 1/fCLKO ns
t1 Clock pulse width high 28.1 13.6 ns
t2 Clock pulse width low 28.1 13.6 ns
t3 A[17:1] setup 1st CLKO when CSX# = 0 and 0 0 ns
either UWE#/LWE# or OE# =0
t4 A[16:1] hold from CSX# rising edge 0 0 ns
t5a CSX# asserted for MCLK = BCLK 13 13 TCLKO
t5b CSX# asserted for MCLK = BCLK ÷2 18 18 TCLKO
t5c CSX# asserted for MCLK = BCLK ÷3 23 23 TCLKO
t5d CSX# asserted for MCLK = BCLK ÷4 28 28 TCLKO
t6 CSX# setup to CLKO rising edge 0 0 ns
t7 CSX# rising edge to CLKO rising edge 0 0 ns
t8 UWE#/LWE# falling edge to CLKO rising 0 0 ns
edge
t9 UWE#/LWE# rising edge to CSX# rising 0 0 ns
edge
t10 OE# falling edge to CLKO rising edge 1 1 ns
t11 OE# hold from CSX# rising edge 0 0 ns
t12 D[15:0] setup to 3rd CLKO when CSX#, 0 0 ns
UWE#/LWE# asserted (write cycle) (see
note 1)
t13 D[15:0] hold from CSX# rising edge(write 0 0 ns
cycle)
t14 Falling edge of OE# to D[15:0] driven 3 15 3 15 ns
(read cycle)
t15a 1st CLKO rising edge after OE# and 13 13 TCLKO
CSX# asserted low to D[15:0] valid for
MCLK = BCLK (read cycle)
t15b 1st CLKO rising edge after OE# and 18 18 TCLKO
CSX# asserted low to D[15:0] valid for
MCLK = BCLK ÷2 (read cycle)
t15c 1st CLKO rising edge after OE# and 23 23 TCLKO
CSX# asserted low to D[15:0] valid for
MCLK = BCLK ÷3 (read cycle)
t15d 1st CLKO rising edge after OE# and 28 28 TCLKO
CSX# asserted low to D[15:0] valid for
MCLK = BCLK ÷4 (read cycle)
t16 CLKO rising edge to D[15:0] output Hi-Z 2 12 2 12 ns
(read cycle)

Note
1 t12 is the delay from when data is placed on the bus until the data is latched into the write buffer.

Solomon Systech Aug 2005 P 82/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 10.2.6 Hitachi SH-3 Interface Timing (e.g. SH7709A)

TCKIO t1 t2

CKIO

t3 t4

A[17:1], M/R#,
RD/WR#
t5 t6

BS#
t8
t7

CSn#
t9 t11
t10

WEn#, RD#

t12 t13

Hi-Z Hi-Z
WAIT#

t14 t15

D[15:0] Hi-Z Hi-Z

(write)
t16 t17
D[15:0]
Hi-Z Hi-Z
(read) VALID

Figure 10-7 : Hitachi SH-3 Interface Timing

Solomon Systech Aug 2005 P 83/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 Table 10-9 : Hitachi SH-3 Interface Timing
Symbol Parameter Min Max Units
fCKIO Bus Clock frequency 66 MHz
TCKIO Bus Clock period 1/fCKIO ns
t1 Bus Clock pulse width low 9 ns
t2 Bus Clock pulse width high 9 ns
t3 A[17:1], M/R#, RD/WR# setup to CKIO 1 ns
t4 CSn# high setup to CKIO 1 ns
t5 BS# setup 1 ns
t6 BS# hold 2 ns
t7 CSn# setup 1 ns
t8 A[17:1], M/R#, RD/WR# hold from CS# 0 ns
t9a RD# or WEn# asserted for MCLK = BCLK (max. 13 TCKIO
MCLK=50MHz)
t9b RD# or WEn# asserted for MCLK = BCLK ÷2 18 TCKIO
t9c RD# or WEn# asserted for MCLK = BCLK ÷3 23 TCKIO
t9d RD# or WEn# asserted for MCLK = BCLK ÷4 28 TCKIO
t10 Falling edge RD# to D[15:0] driven (read cycle) 3 12 ns
t11 Rising edge CSn# to WAIT# high impedance 2 10 ns
t12 Falling edge CSn# to WAIT# driven low 3 TCKIO + 2 3 TCKIO + ns
12
t13 CLIO to WAIT# delay 4 18 ns
t14 D[15:0] setup to 2nd CKIO after BS# (write cycle) (see note 1) 0 ns
t15 D[15:0] hold (write cycle) 0 ns
t16 WAIT# rising edge to D[15:0] valid (read cycle) 2 ns
t17 Rising edge RD# to D[15:0] high impedance (read cycle) 3 12 ns

1. t14 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Note:Minimum three software WAIT states are required.

Solomon Systech Aug 2005 P 84/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 10.2.7 Hitachi SH-4 Interface Timing (e.g. SH7751)

TCKIO t1 t2

CKIO

t3 t8

A[17:1], M/R#,
RD/WR#
t5 t6

BS#
t4
t7

CSn#
t9 t13
t10

WEn#, RD#

t12 t14
t11

Hi-Z Hi-Z
RDY#

t15 t16

D[15:0] Hi-Z Hi-Z

(write)
t17 t18
D[15:0]
Hi-Z Hi-Z
(read) VALID

Figure 10-8 : Hitachi SH-4 Interface Timing

Solomon Systech Aug 2005 P 85/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 Table 10-10 : Hitachi SH-4 Interface Timing
Symbol Parameter Min Max Units
fCKIO Clock frequency 66 MHz
TCKIO Clock period 1/fCKIO ns
t1 Clock pulse width low 6.8 ns
t2 Clock pulse width high 6.8 ns
t3 A[17:1], M/R#, RD/WR# setup to CKIO 1 ns
t4 A[17:1], M/R#, RD/WR# hold from CSn# 0 ns
t5 BS# setup 1 ns
t6 BS# hold 2 ns
t7 CSn# setup 1 ns
t8 CSn# high setup to CKIO 2 ns
t9a RD# or WEn# asserted for MCLK = BCLK (max. 13 TCKIO
MCLK=50MHz)
t9b RD# or WEn# asserted for MCLK = BCLK ÷2 18 TCKIO
t9c RD# or WEn# asserted for MCLK = BCLK ÷3 23 TCKIO
t9d RD# or WEn# asserted for MCLK = BCLK ÷4 28 TCKIO
t10 Falling edge RD# to D[15:0] driven (read cycle) 3 12 ns
t11 Falling edge CSn# to RDY# driven high 3 TCKIO + 3 3 TCKIO + ns
12
t12 CKIO to RDY# low 4 18 ns
t13 CSn# high to RDY# high 4 14 ns
t14 Falling edge CKIO to RDY# high impedance 4 14 ns
t15 D[15:0] setup to 2 nd CKIO after BS# (write cycle) (see note 1) 0 ns
t16 D[15:0] hold (write cycle) 0 ns
t17 RDY# falling edge to D[15:0] valid (read cycle) 2 ns
t18 Rising edge RD# to D[15:0] high impedance (read cycle) 3 12 ns

1. t15 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Note:Minimum three software WAIT states are required.

Solomon Systech Aug 2005 P 86/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 10.3 LCD Power Sequencing

10.3.1 Passive/TFT Power-On Sequence

GPO*

t1
Power Saving
Mode Enable**
(REG[A0h] bit 0)
t2

LCD Signals***

*It is recommended to use the general purpose output pin GPO to control the LCD bias power.
**The LCD power-on sequence is activated by programming the Power Saving Mode Enable bit (REG[A0h] bit 0) to 0.
***LCD Signal include: LDATA[17:0], LSHIFT, LLINE, LFRAME, and LDEN.

Figure 10-9 : Passive/TFT Power-On Sequence Timing

Table 10-11 : Passive/TFT Power-On Sequence Timing

Symbol Parameter Min Max Units
t1 LCD signals active to LCD bias active Note 1 Note 1
t2 Power Saving Mode disabled to LCD signals 0 20 ns
active

1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the
panel connected.

Note:For HR-TFT Power-On/Off sequence information see referenced document of Sharp HR-TFT Panels.

Solomon Systech Aug 2005 P 87/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 10.3.2 Passive/TFT Power-Off Sequence

t1

GPO*

Power Saving
Mode Enable**
(REG[A0h] bit 0)
t2

LCD Signals***

*It is recommended to use the general purpose output pin GPO to control the LCD bias power.
**The LCD power-off sequence is activated by programming the Power Saving Mode Enable bit (REG[A0h] bit 0) to 1.
***LCD Signal include: LDATA[17:0], LSHIFT, LLINE, LFRAME, and LDEN.

Figure 10-10 : Passive/TFT Power-Off Sequence Timing

Table 10-12 : Passive/TFT Power-Off Sequence Timing

Symbol Parameter Min Max Units
t1 LCD bias deactivated active to LCD signals Note 1 Note 1
inactive
t2 Power Saving Mode disabled to LCD signals 0 20 ns
low

1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel
connected.

Solomon Systech Aug 2005 P 88/159 Rev 1.1 SSD1906

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 10.3.3 Power Saving Status

t1
Power Saving
Mode Enable*
(REG[A0h] bit 0)
t2
Memory Controller
Power Saving Status**

* Power Saving Mode is controlled by the Power Saving Mode Enable bit (REG[A0h] bit 0).
** Memory Controller Power Saving Status is controlled by the Memory Controller Power Saving Status bit (REG[A0h] bit3).

Figure 10-11 : Power Saving Status Timing

Table 10-13 : Power Saving Status Timing

Symbol Parameter Min Max Units
t1 Power Saving Mode disabled to Memory Note 1 Note 1 ns
Controller Power Saving Status low
t2 Power Saving Mode enabled to Memory 0 20 MCLK
Controller Power Saving Status high (note 1)

1. For further information on the internal clock MCLK see Section11.1.2, “MCLK”.

Solomon Systech Aug 2005 P 89/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 10.4 Display Interface
Figure 10-12 : Panel Timing Parameters shows the timing parameters required to drive a flat panel display.
Timing details for each supported panel types are provided in the remainder of this section.

HT

HDPS

HPS
HPW

VDPS

HDP

VT VPS VDP

VPW

Figure 10-12 : Panel Timing Parameters

Table 10-14 : Panel Timing Parameter Definition and Register Summary

Symbol Description Derived From Units

HT Horizontal Total ((REG[12h] bits 6-0) + 1) x 8
2 2
HDP Horizontal Display Period ((REG[14h] bits 6-0) + 1) x 8
1
3 3 5 Ts
HDPS Horizontal Display Period Start Position ((REG[17h]bits1-0,REG[16h]bits7-0)+ Offset )
HPS LLINE Pulse Start Position (REG[23h] bits 1-0, REG[22h] bits 7-0) + 1
HPW LLINE Pulse Width (REG[20h] bits 6-0) + 1
VT Vertical Total ((REG[19h] bits 1-0, REG[18h] bits 7-0) + 1) x HT
4 4
VDP Vertical Display Period ((REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1) x HT
VDPS Vertical Display Period Start Position (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0) x HT
VPS LFRAME Pulse Start Position (REG[27h] bits 1-0, REG[26h] bits 7-0) x HT + Ts
1
(REG[31h] bits 1-0, REG[30h] bits 7-0)
VPW LFRAME Pulse Width ((REG[24h] bits 2-0) + 1) x HT + (REG[35h] bits 1-
0, REG[34h] bits 7-0) – (REG[31h] bits 1-0,
REG[30h] bits 7-0)

The following conditions must be fulfilled for all panel timings:

Solomon Systech Aug 2005 P 90/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 HDPS + HDP < HT
VDPS + VDP < VT
1
Ts = pixel clock period
2
The HDP must be a minimum of 32 pixels and can be increased by multiples of 8.
3
The HDPS parameter contains an offset that depends on the panel type. This offset is the constant in the
equation to describes parameter t14 min in the AC Timing tables for the various panel types.
4
The VDP must be a minimum of 2 lines.
5
Offset for STN and CSTN panel = 22, offset for TFT panel = 5.

10.4.1 Generic STN Panel Timing

VT (= 1 Frame)

VPS VPW

LFRAME

VDPS VDP

LLINE

MOD (LDEN)

LDATA[17:0]

HT (= 1 Line)

HPS HPW

LLINE

LSHIFT

1PCLK

MOD (LDEN)

HDPS HDP

LDATA[17:0]

Figure 10-13 : Generic STN Panel Timing

Solomon Systech Aug 2005 P 91/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 VT = Vertical Total
= [(REG[19h]bits1-0,REG[18h]bits7-0)+ 1] lines
VPS = LFRAME Pulse Start Position
= [(REG[27h] bits 1-0, REG[26h] bits 7-0)] x HT + (REG[31h] bits 1-0, REG[30h] bits 7-0) pixels
VPW = LFRAME Pulse Width
= [(REG[24h] bits 2-0) + 1] x HT + (REG[35h] bits 1-0, REG[34h] bits 7-0) – (REG[31h] bits 1-0, REG[30h]
bits 7-0) pixels
VDPS = Vertical Display Period Start Position
= [(REG[1Fh]bits1-0,REG[1Eh]bits7-0)] lines
VDP = Vertical Display Period
= [(REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1] lines
* The VDP must be a minimum of 2 lines
HT = Horizontal Total
= [((REG[12h] bits 6-0) + 1) x 8] pixels
HPS = LLINE Pulse Start Position
= [(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1] pixels
HPW = LLINE Pulse Width
= [(REG[20h] bits 6-0) + 1] pixels
HDPS = Horizontal Display Period Start Position
= [(REG[17h]bits1-0,REG[16h]bits7-0)+ 22] pixels
HDP = Horizontal Display Period
= [((REG[14h] bits 6-0) + 1) x 8] pixels
∗ The HDP must be a minimum of 32 pixels and can be increased by multiples of 8.

*Panel Type Bits (REG[10h] bits 2-0) = 000b (STN)

*LFRAME Pulse Polarity Bit (REG[24h] bit 7) = 1 (active high)
*LLINE Polarity Bit (REG[20h] bit 7) = 1 (active high).

Solomon Systech Aug 2005 P 92/159 Rev 1.1 SSD1906

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 10.4.2 Monochrome 4-Bit Panel Timing

VDP VNDP

LFRAME

LLINE

LDEN (MOD)

LDATA[7:4] LINE1 LINE2 LINE3 LINE239 LINE240 LINE1 LINE2

LLINE

LDEN (MOD)
HDP HNDP

LSHIFT

LDATA7 1-1 1-5 1-317

LDATA6 1-2 1-6 1-318

1-3 1-7
LDATA5 1-319

LDATA4 1-4 1-8 1-320

*Diagram drawn with 2 LLINE vertical blank period

Example timing for a 320x240 panel

Figure 10-14 : Monochrome 4-Bit Panel Timing

VDP = Vertical Display Period

= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 Lines
VNDP = Vertical Non-Display Period
= VT -VDP
= (REG[19h] bits 1:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines
HDP = Horizontal Display Period
= ((REG[14h] bits 6:0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6:0) + 1) x 8Ts) - (((REG[14h] bits 6:0) + 1) x 8Ts)

Solomon Systech Aug 2005 P 93/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 t1 t2
Sync Timing

LFRAME

t4 t3
LLINE

t5

LDEN (MOD)

Data Timing

LLINE

t6 t8 t9
t7 t14 t11 t10

LSHIFT

t12 t13

LDATA[7:4]
1 2

Figure 10-15 : Monochrome 4-Bit Panel A.C. Timing

Solomon Systech Aug 2005 P 94/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 Table 10-15 : Monochrome 4-Bit Panel A.C. Timing
Symbol Parameter Min Typ Max Units
t1 LFRAME setup to LLINE falling edge note 2 Ts (note 1)
t2 LFRAME hold from LLINE falling edge note 3 Ts
t3 LLINE period note 4 Ts
t4 LLINE pulse width note 5 Ts
t5 MOD transition to LLINE falling edge note 6 Ts
t6 LSHIFT falling edge to LLINE rising edge note 7 Ts
t7 LSHIFT falling edge to LLINE falling edge t 6 + t4 Ts
t8 LLINE falling edge to LSHIFT falling edge t14 + 2 Ts
t9 LSHIFT period 4 Ts
t10 LSHIFT pulse width low 2 Ts
t11 LSHIFT pulse width high 2 Ts
t12 LDATA[7:4] setup to LSHIFT falling edge 2 Ts
t13 LDATA[7:4] hold from LSHIFT falling edge 2 Ts
t14 LLINE falling edge to LSHIFT rising edge note 8 Ts

1. Ts = pixel clock period

2. t1 min = (HPS+ HPW) – (REG[31h] bits 1-0, REG[30h] bits 7-0)
3. t2 min = VPW - t1 min
4. t3 min = HT
5. t4 min = HPW
6. t5 min = HT - HPS
7. t6 min = HPS - (HDP + HDPS - 2) if negative add t3 min
8. t14 min = HDPS - (HPS + t4 min) if negative add t3 min

Solomon Systech Aug 2005 P 95/159 Rev 1.1 SSD1906

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 10.4.3 Monochrome 8-Bit Panel Timing

VDP VNDP

LFRAME

LLINE

LDEN (MOD)

LDATA[7:0] LINE1 LINE2 LINE3 LINE479 LINE480 LINE1 LINE2

LLINE

LDEN (MOD)
HDP HNDP

LSHIFT

LDATA7 1-1 1-9 1-633

LDATA6 1-2 1-10 1-634

1-3 1-11
LDATA5 1-635

LDATA4 1-4 1-12 1-636

LDATA3 1-5 1-13 1-637

LDATA2 1-6 1-14 1-638

LDATA1 1-7 1-15 1-639

LDATA0 1-8 1-16 1-640

*Diagram drawn with 2 LLINE vertical blank period

Example timing for a 640x480 panel

Figure 10-16 : Monochrome 8-Bit Panel Timing

VDP = Vertical Display Period
= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 Lines
VNDP = Vertical Non-Display Period
= VT-VDP
= (REG[19h] bits 1:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines
HDP = Horizontal Display Period
= ((REG[14h] bits 6:0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6:0) + 1) x 8Ts) - (((REG[14h] bits 6:0) + 1) x 8Ts)

Solomon Systech Aug 2005 P 96/159 Rev 1.1 SSD1906

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 t1 t2
Sync Timing

LFRAME

t4 t3
LLINE

t5

LDEN (MOD)

Data Timing

LLINE

t6 t8 t9
t7 t14 t11 t10

LSHIFT

t12 t13

LDATA[7:0]
1 2

Figure 10-17 : Monochrome 8-Bit Panel A.C. Timing

Solomon Systech Aug 2005 P 97/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 Table 10-16 : Monochrome 8-Bit Panel A.C. Timing
Symbol Parameter Min Typ Max Units
t1 LFRAME setup to LLINE falling edge note 2 Ts (note 1)
t2 LFRAME hold from LLINE falling edge note 3 Ts
t3 LLINE period note 4 Ts
t4 LLINE pulse width note 5 Ts
t5 MOD transition to LLINE falling edge note 6 Ts
t6 LSHIFT falling edge to LLINE rising edge note 7 Ts
t7 LSHIFT falling edge to LLINE falling edge t 6 + t4 Ts
t8 LLINE falling edge to LSHIFT falling edge t14 + 4 Ts
t9 LSHIFT period 8 Ts
t10 LSHIFT pulse width low 4 Ts
t11 LSHIFT pulse width high 4 Ts
t12 LDATA[7:0] setup to LSHIFT falling edge 4 Ts
t13 LDATA[7:0] hold from LSHIFT falling edge 4 Ts
t14 LLINE falling edge to LSHIFT rising edge note 8 Ts

1. Ts = pixel clock period

2. t1 min = (HPS+ HPW) – (REG[31h] bits 1-0, REG[30h] bits 7-0)
3. t2 min = VPW - t1 min
4. t3 min = HT
5. t4 min = HPW
6. t5 min = HT - HPS
7. t6 min = HPS - (HDP + HDPS - 4) if negative add t3 min
8. t14 min = HDPS - (HPS + t4 min) if negative add t3 min

Solomon Systech Aug 2005 P 98/159 Rev 1.1 SSD1906

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 10.4.4 Color 4-Bit Panel Timing
VDP VNDP

LFRAME

LLINE

LDEN (MOD)

LDATA[7:4] LINE1 LINE2 LINE3 LINE239 LINE240 LINE1 LINE2

LLINE

LDEN (MOD)
HDP HNDP

LSHIFT

LDATA7 1-R1 1-G2 1-B3 1-B319

LDATA6 1-G1 1-B2 1-R4 1-R320

LDATA5 1-B1 1-R3 1-G4 1-G320

LDATA4 1-R2 1-G3 1-B4 1-B320

*Diagram drawn with 2 LLINE vertical blank period

Example timing for a 320x240 panel

Figure 10-18 : Color 4-Bit Panel Timing

VDP = Vertical Display Period

= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 Lines
VNDP = Vertical Non-Display Period
= VT-VDP
= (REG[19h] bits 1:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines
HDP = Horizontal Display Period
= ((REG[14h] bits 6:0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period
= HT - HDP
(((REG[12h] bits 6:0) + 1) x 8Ts) - (((REG[14h] bits 6:0) + 1) x 8Ts)

Solomon Systech Aug 2005 P 99/159 Rev 1.1 SSD1906

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 t1 t2
Sync Timing

LFRAME

t4 t3
LLINE

t5

LDEN (MOD)

Data Timing

LLINE

t6 t8 t9
t7 t14 t11 t10

LSHIFT

t12 t13

LDATA[7:4]
1 2

Figure 10-19 : Color 4-Bit Panel A.C. Timing

Solomon Systech Aug 2005 P 100/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 Table 10-17 : Color 4-Bit Panel A.C. Timing
Symbol Parameter Min Typ Max Units
t1 LFRAME setup to LLINE falling edge note 2 Ts (note 1)
t2 LFRAME hold from LLINE falling edge note 3 Ts
t3 LLINE period note 4 Ts
t4 LLINE pulse width note 5 Ts
t5 MOD transition to LLINE falling edge note 6 Ts
t6 LSHIFT falling edge to LLINE rising edge note 7 Ts
t7 LSHIFT falling edge to LLINE falling edge t 6 + t4 Ts
t8 LLINE falling edge to LSHIFT falling edge t14 + 0.5 Ts
t9 LSHIFT period 2 Ts
t10 LSHIFT pulse width low 1 Ts
t11 LSHIFT pulse width high 1 Ts
t12 LDATA[7:4] setup to LSHIFT falling edge 1 Ts
t13 LDATA[7:4] hold from LSHIFT falling edge 1 Ts
t14 LLINE falling edge to LSHIFT rising edge note 8 Ts

1. Ts = pixel clock period

2. t1 min = (HPS+ HPW) – (REG[31h] bits 1-0, REG[30h] bits 7-0)
3. t2 min = VPW - t1 min
4. t3 min = HT
5. t4 min = HPW
6. t5 min = HT - HPS
7. t6 min = HPS - (HDP + HDPS - 3) if negative add t3 min
8. t14 min = HDPS - (HPS + t4 min) + 1 if negative add t3 min

Solomon Systech Aug 2005 P 101/159 Rev 1.1 SSD1906

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 10.4.5 Color 8-Bit Panel Timing (Format stripe)

VDP VNDP

LFRAME

LLINE

LDEN (MOD)

LDATA[7:0] LINE1 LINE2 LINE3 LINE479 LINE480 LINE1 LINE2

LLINE

LDEN (MOD)
HDP HNDP

LSHIFT

LDATA7 1-R1 1-B3 1-G6 1-G638

LDATA6 1-G1 1-R4 1-B6 1-B638

LDATA5 1-B1 1-G4 1-R7 1-R639

LDATA4 1-R2 1-B4 1-G7 1-G639

LDATA3 1-G2 1-R5 1-B7 1-B639

LDATA2 1-B2 1-G5 1-R8 1-R640

LDATA1 1-R3 1-B5 1-G8 1-G640

LDATA0 1-G3 1-R6 1-B8 1-B640

*Diagram drawn with 2 LLINE vertical blank period

Example timing for a 640X480 panel

Figure 10-20 : Color 8-Bit Panel Timing (Format stripe)

Solomon Systech Aug 2005 P 102/159 Rev 1.1 SSD1906

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 VDP = Vertical Display Period
= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 Lines
VNDP = Vertical Non-Display Period
= VT-VDP
= (REG[19h] bits 1:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines
HDP = Horizontal Display Period
= ((REG[14h] bits 6:0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6:0) + 1) x 8Ts) - (((REG[14h] bits 6:0) + 1) x 8Ts)

t1 t2
Sync Timing

LFRAME

t4 t3
LLINE

t5

LDEN (MOD)

Data Timing

LLINE

t6 t8 t9
t7 t14 t11 t10

LSHIFT

t12 t13

LDATA[7:0]
1 2

Figure 10-21 : Color 8-Bit Panel A.C. Timing (Format stripe)

Solomon Systech Aug 2005 P 103/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 Table 10-18 : Color 8-Bit Panel A.C. Timing (Format stripe)
Symbol Parameter Min Typ Max Units
t1 LFRAME setup to LLINE falling edge note 2 Ts (note 1)
t2 LFRAME hold from LLINE falling edge note 3 Ts
t3 LLINE period note 4 Ts
t4 LLINE pulse width note 5 Ts
t5 MOD transition to LLINE falling edge note 6 Ts
t6 LSHIFT falling edge to LLINE rising edge note 7 Ts
t7 LSHIFT falling edge to LLINE falling edge t 6 + t4 Ts
t8 LLINE falling edge to LSHIFT falling edge t14 + 2 Ts
t9 LSHIFT period 2 Ts
t10 LSHIFT pulse width low 1 Ts
t11 LSHIFT pulse width high 1 Ts
t12 LDATA[7:0] setup to LSHIFT falling edge 1 Ts
t13 LDATA[7:0] hold to LSHIFT falling edge 1 Ts
t14 LLINE falling edge to LSHIFT rising edge note 8 Ts

1. Ts = pixel clock period

2. t1 min = (HPS+ HPW) – (REG[31h] bits 1-0, REG[30h] bits 7-0)
3. t2 min = VPW - t1 min
4. t3 min = HT
5. t4 min = HPW
6. t5 min = t3 min -HPS
7. t6 min = HPS - (HDP + HDPS - 1) if negative add t3 min
8. t14 min = HDPS - (HPS + t4 min) if negative add t3 min

Solomon Systech Aug 2005 P 104/159 Rev 1.1 SSD1906

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 10.4.6 Generic TFT Panel Timing
VT (= 1 Frame)

VPS VPW

LFRAME

VDPS VDP

LLINE

LDEN

LDATA[17:0]

HT (= 1 Line)

HPS HPW

LLINE

LSHIFT

LDEN

HDPS HDP

LDATA[17:0]

Figure 10-22 : Generic TFT Panel Timing

VT = Vertical Total
= [(REG[19h] bits 1-0, REG[18h] bits 7-0) + 1] lines
VPS = LFRAME Pulse Start Position
= [(REG[27h] bits 1-0, REG[26h] bits 7-0)] x HT + (REG[31h] bits 1-0, REG[30h] bits 7-0) pixels
VPW = LFRAME Pulse Width
= [(REG[24h]bits2-0)+ 1] x HT + (REG[35h] bits 1-0, REG[34h] bits 7-0) – (REG[31h] bits 1-0, REG[30h]
bits 7-0) pixels

Solomon Systech Aug 2005 P 105/159 Rev 1.1 SSD1906

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 VDPS = Vertical Display Period Start Position
= [(REG[1Fh]bits1-0,REG[1Eh]bits7-0)] lines
VDP = Vertical Display Period
= [(REG[1Dh]bits1-0,REG[1Ch]bits7-0)+ 1] lines
* The VDP must be a minimum of 2 lines
HT = Horizontal Total
= [((REG[12h] bits 6-0) + 1) x 8] pixels
HPS = LLINE Pulse Start Position
= [(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1] pixels
HPW = LLINE Pulse Width
= [(REG[20h] bits 6-0)+ 1] pixels
HDPS = Horizontal Display Period Start Position
= [(REG[17h] bits 1-0, REG[16h] bits 7-0) + 5] pixels
HDP = Horizontal Display Period
= [((REG[14h] bits 6-0) + 1) x 8] pixels
∗ The HDP must be a minimum of 32 pixels and can be increased by multiples of 8.

*Panel Type Bits (REG[10h] bits 2-0) = 001 (TFT)

*LLINE Pulse Polarity Bit (REG[24h] bit 7) = 0 (active low)
*LFRAME Polarity Bit (REG[20h] bit 7) = 0 (active low)

10.4.7 9/12/18-Bit TFT Panel Timing

VNDP2 VDP VNDP1

LFRAME

LLINE

LDATA[11:0] LINE480 LINE1 LINE480

LDEN

LLINE
HNDP1 HDP HNDP2

LSHIFT

LDEN

LDATA[11:0] 1-1 1-2 1-640

Note: LDEN is used to indicated the first pixel

Example Timing for 12-bit 640x480 panel

Figure 10-23 : 12-Bit TFT Panel Timing

Solomon Systech Aug 2005 P 106/159 Rev 1.1 SSD1906

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 VDP = Vertical Display Period
= VDP Lines
VNDP = Vertical Non-Display Period
= VNDP1 + VNDP2
= VT – VDP Lines
VNDP1 = Vertical Non-Display Period 1
= VNDP - VNDP2 Lines
VNDP2 = Vertical Non-Display Period 2
= VDPS - VPS Lines if negative add VT
HDP = Horizontal Display Period
= HDP Ts
HNDP = Horizontal Non-Display Period
= HNDP1 + HNDP2
= HT - HDP Ts
HNDP1 = Horizontal Non-Display Period 1
= HDPS - HPS Ts if negative add HT
HNDP2 = Horizontal Non-Display Period 2
= HPS – (HDP + HDPS) Ts if negative add HT

Solomon Systech Aug 2005 P 107/159 Rev 1.1 SSD1906

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 t1
t2

LFRAME
t3

LLINE

t4

LLINE
t5 t8
t6 t7

LDEN

t9 t12
tt10 t11 t13 t14
10

LSHIFT

t15 t16

1 2 639 640
LDATA[11:0]

Figure 10-24 : TFT A.C. Timing

Solomon Systech Aug 2005 P 108/159 Rev 1.1 SSD1906

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 Table 10-19 : TFT A.C. Timing
Symbol Parameter Min Typ Max Units
t1 LFRAME cycle time VT Lines
t2 LFRAME pulse width low VPW Lines
t3 LFRAME falling edge to LLINE falling edge phase HPS Ts(note1)
difference
t4 LLINE cycle time HT Ts
t5 LLINE pulse width low HPW Ts
t6 LLINE falling edge to LDEN active note 2 250 Ts
t7 LDEN pulse width HDP Ts
t8 LDEN falling edge to LLINE falling edge note 3 Ts
t9 LSHIFT period 1 Ts
t10 LSHIFT pulse width high 0.5 Ts
t11 LSHIFT pulse width low 0.5 Ts
t12 LLINE setup to LSHIFT falling edge 0.5 Ts
t13 LDEN to LSHIFT falling edge setup time 0.5 Ts
t14 LDEN hold from LSHIFT falling edge 0.5 Ts
t15 Data setup to LSHIFT falling edge 0.5 Ts
t16 Data hold from LSHIFT falling edge 0.5 Ts

1. Ts = pixel clock period

2. t6min = HDPS - HPS if negative add HT
3. t8min = HPS - (HDP + HDPS ) if negative add HT

Solomon Systech Aug 2005 P 109/159 Rev 1.1 SSD1906

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 10.4.8 160x160 Sharp HR-TFT Panel Timing (e.g. LQ031B1DDxx)
LFRAME
(SPS)
t1

LLINE
(LP)

t2
t3
LLINE
(LP)

t4

LSHIFT (CLK)
REG[38h] bit 4 = 0

LSHIFT (CLK)
REG[38h] bit 4 = 1
t5 t6

LDATA[17:0] D1 D2 D3 D159 D160

t7 t8
t9 t10

GPIO3
(SPL)

t11

GPIO1
(CLS)
t12

GPIO0
(PS)
t13

GPIO2
(REV)

Figure 10-25 : 160x160 Sharp HR-TFT Panel Horizontal Timing

Solomon Systech Aug 2005 P 110/159 Rev 1.1 SSD1906

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 Table 10-20 : 160x160 Sharp HR-TFT Horizontal Timing
Symbol Parameter Min Typ Max Units
t1 LLINE start position 13 Ts (note 1)
t2 Horizontal total period 180 Ts
t3 LLINE width 2 Ts
t4 LSHIFT period 1 Ts
t5 Data setup to LSHIFT rising edge 0.5 Ts
t6 Data hold from LSHIFT rising edge 0.5 Ts
t7 Horizontal display start position 5 Ts
t8 Horizontal display period 160 Ts
t9 LLINE rising edge to GPIO3 rising edge 4 Ts
t10 GPIO3 pulse width 1 Ts
t11 GPIO1(GPIO0) pulse width 136 Ts
t12 GPIO1 rising edge (GPIO0 falling edge) to LLINE rise edge 4 Ts
t13 GPIO2 toggle edge to LLINE rise edge 10 Ts

1. Ts = pixel clock period

2. t1typ = (REG[22h] bits 7-0) + 1
3. t2typ = ((REG[12h] bits 6-0) + 1) x 8
4. t3typ = (REG[20h] bits 6-0) + 1
5. t7typ = ((REG[16h] bits 7-0) + 1) - ((REG[22h] bits 7-0) + 1)
6. t8typ = ((REG[14h] bits 6-0) + 1) x 8

Solomon Systech Aug 2005 P 111/159 Rev 1.1 SSD1906

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 t1
t2 t3

LDATA[17:0] LINE1 LINE2 LINE160

t4
LFRAME
(SPS)

t5 t6
GPIO1(CLS)
REG[38h]
bit 0 = 0
GPIO1(CLS)
REG[38h]
bit 0 = 1

GPIO0(PS)
REG[38h]
bit 1 = 0
t7 t8
GPIO0(PS)
REG[38h]
bit 1 = 1

t9
LLINE
(LP)

LSHIFT
(CLK)
t10 t11 t12
GPIO1(CLS)
REG[38h]
bit 0 = 0 t13
t14
GPIO0(PS)
REG[38h]
bit 1 = 1

Figure 10-26 : 160x160 Sharp HR-TFT Panel Vertical Timing

Solomon Systech Aug 2005 P 112/159 Rev 1.1 SSD1906

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 Table 10-21 : 160x160 Sharp HR-TFT Panel Vertical Timing
Symbol Parameter Min Typ Max Units
t1 Vertical total period 203 Lines
t2 Vertical display start position 40 Lines
t3 Vertical display period 160 Lines
t4 FPRAME sync pulse width 2 Lines
1
t5 LFRAME falling edge to GPIO1 alternate timing start 5 Lines
1
t6 GPIO1 alternate timing period 4 Lines
2
t7 LFRAME falling edge to GPIO0 alternate timing start 40 Lines
2
t8 GPIO0 alternate timing period 162 Lines
t9 GPIO1 first pulse rising edge to LLINE rising edge 4 Ts (note 1)
1
t10 GPIO1 first pulse width 48 Ts
1
t11 GPIO1 first pulse falling edge to second pulse rising edge 40 Ts
1
t12 GPIO1 second pulse width 48 Ts
2
t13 GPIO0 falling edge to LLINE rising edge 4 Ts
2
t14 GPIO0 low pulse width 24 Ts

1. Ts = pixel clock period

1
Timing for CLS signal change bit enabled (REG[38h] bit 0 = 0) only
2
Timing for PS signal change bit enabled (REG[38h] bit 1 = 1) only

Solomon Systech Aug 2005 P 113/159 Rev 1.1 SSD1906

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 10.4.9 Generic HR-TFT Panel Timing
LFRAME
(SPS)
t1

LLINE
(LP)

t2
t3
LLINE
(LP)

t4

LSHIFT (CLK)
REG[38h] bit 4 = 0

LSHIFT (CLK)
REG[38h] bit 4 = 1
t5 t6

LDATA[17:0] D1 D2 D3 D319 D320

t7 t8
t9 t10

GPIO3
(SPL)

t11

GPIO1
(CLS)
t12

GPIO0
(PS)
t13

GPIO2
(REV)

Example timing for a 320x240 panel

Figure 10-27 : HR-TFT Panel Horizontal Timing

Solomon Systech Aug 2005 P 114/159 Rev 1.1 SSD1906

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 Table 10-22 : 320x240 HR-TFT Panel Horizontal Timing
Symbol Parameter Min Typ Max Units
t1 LLINE start position 14 Ts (note 1)
t2 Horizontal total period 400 440 Ts
t3 LLINE width 1 Ts
t4 LSHIFT period 1 Ts
t5 Data setup to LSHIFT rising edge 0.5 Ts
t6 Data hold from LSHIFT rising edge 0.5 Ts
t7 Horizontal display start position 60 Ts
t8 Horizontal display period 320 Ts
t9 LLINE rising edge to GPIO3 rising edge 59 Ts
t10 GPIO3 pulse width 1 Ts
t11 GPIO1(GPIO0) pulse width 353 Ts
t12 GPIO1 rising edge (GPIO0 falling edge) to LLINE rise edge 5 Ts
t13 GPIO2 toggle edge to LLINE rise edge 11 Ts

1. Ts = pixel clock period

2. t1typ = (REG[22h] bits 7-0) + 1
3. t2typ = ((REG[12h] bits 6-0) + 1) x 8
4. t3typ = (REG[20h] bits 6-0) + 1
5. t7typ = ((REG[16h] bits 7-0) + 1) - ((REG[22h] bits 7-0) + 1)
6. t8typ = ((REG[14h] bits 6-0) + 1) x 8
t1

t2 t3

LDATA[17:0] LINE1 LINE2 LINE240

t4
LFRAME
(SPS)

Example timing for 320x240 panel

Figure 10-28 : HR-TFT Panel Vertical Timing

Table 10-23 : 320x240 HR-TFT Panel Vertical Timing

Symbol Parameter Min Typ Max Units
t1 Vertical total period 245 330 Lines
t2 Vertical display start position 4 Lines
t3 Vertical display period 240 Lines
t4 Vertical sync pulse width 2 Lines

Solomon Systech Aug 2005 P 115/159 Rev 1.1 SSD1906

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 11 Clocks
The following is a block diagram of the SSD1906’s internal clocks.

CLK MUX
CLKI-GEN CLKI
BCLK
CLKI MCLK
MCLK
PCLK1

PWMCLK1 PCLK

STOP CONTROL

STOP CONTROL
PWMCLK

PWMCLK2
AUXCLK
PCLK2

AUXCLK-GEN

Figure 11-1 : Clock Generator Block Diagram

11.1 Clock Descriptions

11.1.1 BCLK
BCLK is an internal clock derived from CLKI. BCLK can be a divided version (÷ 1, ÷ 2, ÷ 3, ÷ 4) of CLKI. CLKI is
typically derived from the host CPU bus clock.

The source clock options for BCLK can be selected from the following table.
Table 11-1 : BCLK Clock Selection
Source Clock Options BCLK Selection
CLKI CF[7:6] = 00
CLKI ÷ 2 CF[7:6] = 01
CLKI ÷ 3 CF[7:6] = 10
CLKI ÷ 4 CF[7:6] = 11

Solomon Systech Aug 2005 P 116/159 Rev 1.1 SSD1906

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 Note
For synchronous bus interfaces the BCLK should be set the same as the CPU bus clock (not a divided version of
CLKI) e.g. SH-3, SH-4.

11.1.2 MCLK
The MCLK provides the internal clock required to access the embedded SRAM. The SSD1906 has an efficient
power saving control for clocks ,as they are off when not in use.

Further, reducing the MCLK frequency relative to the BCLK frequency increases the CPU cycle latency and
therefore reduces screen update performance. For a balance between power saving and performance the MCLK
should be configured so it has a high enough frequency setting to provide sufficient screen refresh with acceptable
CPU cycle latency.

The source clock options for MCLK can be selected from the following table.
Table 11-2 : MCLK Clock Selection
Source Clock Options MCLK Selection (REG[04h])
BCLK 00h
BCLK ÷ 2 10h
BCLK ÷ 3 20h
BCLK ÷ 4 30h

11.1.3 PCLK
The PCLK is the internal clock used to control the LCD panel. The PCLK should be chosen to match the optimum
frame rate of the LCD panel. See Section 13 ”Frame Rate Calculation” for details on the relationship between the
PCLK and frame rate.

Some flexibility is possible in selected the PCLK. Firstly, LCD panels typically have a range of permissible frame
rates. Secondly, it may be possible to choose a higher PCLK frequency and tailor the horizontal and vertical non-
display periods. This will lower the frame-rate to its optimal value.

The source clock options for PCLK can be selected from the following Table 11-3 : PCLK Clock Selection.

Solomon Systech Aug 2005 P 117/159 Rev 1.1 SSD1906

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 Table 11-3 : PCLK Clock Selection
Source Clock Options PCLK Selection (REG[05h])
MCLK 00h
MCLK ÷ 2 10h
MCLK ÷ 3 20h
MCLK ÷ 4 30h
MCLK ÷ 8 40h
BCLK 01h
BCLK ÷ 2 11h
BCLK ÷ 3 21h
BCLK ÷ 4 31h
BCLK ÷ 8 41h
CLKI 02h
CLKI ÷ 2 12h
CLKI ÷ 3 22h
CLKI ÷ 4 32h
CLKI ÷ 8 42h
AUXCLK 03h
AUXCLK ÷ 2 13h
AUXCLK ÷ 3 23h
AUXCLK ÷ 4 33h
AUXCLK ÷ 8 43h

A relationship exists between the frequency of MCLK and PCLK which must be maintained, as detailed in the
following Table 11-4 : Relationship between MCLK and PCLK.
Table 11-4 : Relationship between MCLK and PCLK
Color Depth (bpp) MCLK to PCLK Relationship
16 fMCLK ≥ fPCLK x 2
8 fMCLK ≥ fPCLK
4 fMCLK ≥ fPCLK ÷ 2
2 fMCLK ≥ fPCLK ÷ 4
1 fMCLK ≥ fPCLK ÷ 8

11.1.4 PWMCLK
The PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel.
The source clock options for PWMCLK can be selected from the following table.

For further information on controlling the PWMCLK see Section 0 “

Note: The SSD1906 provides Pulse Width Modulation output on the pin LPWMOUT, which can be used
to control the LCD panels, supporting PWM control of the back-light inverter.

Table 11-5 : PWMCLK Clock Selection

Source Clock Options PWMCLK Selection REG[B1h] bit 0
CLKI 0
AUXCLK 1

Solomon Systech Aug 2005 P 118/159 Rev 1.1 SSD1906

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 11.2 Clocks versus Functions
The following Table 11-6 : SSD1906 Internal Clock Requirements, lists the internal clocks required for the following
SSD1906 functions.
Table 11-6 : SSD1906 Internal Clock Requirements
Function Bus Clock Memory Clock Pixel Clock PWM Clock
(BCLK) (MCLK) (PCLK) (PWMCLK)
Register Read/Write Required Not Required Not Required Not Required
Memory Read/Write Required Required Not Required Not Required
Look-Up Table Register Required Not Required Not Required Not Required
Read/Write
Software Power Saving Required Not Required Not Required Not Required
LCD Output Required Required Required Not Required
PWM/CV Output Required Required Required Required

Solomon Systech Aug 2005 P 119/159 Rev 1.1 SSD1906

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 12 Power Saving Mode
The Power Saving Mode is incorporated into the SSD1906 to accommodate the need for reduced power
consumption in the hand-held device market. This mode is enabled via the Power Saving Mode Enable bit
(REG[A0h] bit 0).

Power Saving Mode powers down the panel and stops display refresh accesses to the display buffer.

Table 12-1 : Power Saving Mode Function Summary

Software Power Saving Normal
IO Access Possible? Yes Yes
Memory Access Possible? No1 Yes
Look-Up Table Registers Access Possible? Yes Yes
Sequence Controller Running? No Yes
Display Active? No Yes
LCD Interface Outputs Forced Low Active
PWMCLK Stopped Active
2
GPIO3:0 Pins configured for HR-TFT Forced Low Active
2 3
GPIO Pins configured as GPIO’s Access Possible ? Yes Yes

Note :
1
When Power Saving mode is enabled the controlled memory is powered down. The status of the controlled
memory is indicated by the Memory Controller Power Saving Status bit (REG[A0h] bit 3). For Power Saving Status
AC timing see Section 10.3.3 “Power Saving Status”.
2
GPIO Pins are configured using the configurations pin CF3 which is latched on the rising edge of RESET#. For
information on CF3 see Table 5-6 : Summary of Power-On/Reset Options.
3
GPIO’s can be accessed, and if configured as outputs, can also be changed.

After reset, the SSD1906 stays in Power Saving Mode. Software must initialize the chip (i.e. program all the
registers) and then clear the Power Saving Mode Enable bit.

13 Frame Rate Calculation

The following formula is used to calculate the display frame rate.
f PCLK
FrameRate =
( HT ) x(VT )

Where:
fPCLK = PCLK frequency (Hz)
HT = Horizontal Total
= ((REG[12h] bits 6-0) + 1) x 8 Ts
VT = Vertical Total
= ((REG[19h] bits 1-0, REG[18h] bits 7-0) + 1) Lines

Solomon Systech Aug 2005 P 120/159 Rev 1.1 SSD1906

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 14 Display Data Formats
The following diagram show the display mode data formats.

1 bpp: bit 7 bit 0 P0 P1 P2 P3 P4 P5 P6 P7

Byte 0 A0 A1 A2 A3 A4 A5 A6 A7
Byte 1 A8 A9 A10 A11 A12 A13 A 14 A15
LUT Pn = RGB value from LUT
Byte 2 A16 A17 A18 A19 A20 A21 A 22 A23 Index (An)
Host Address

Display Buffer Panel Display

2 bpp: bit 7 bit 0 P0 P1 P2 P3 P4 P5 P6 P7

Byte 0 A0 B0 A1 B1 A2 B2 A3 B3
Byte 1 A4 B4 A5 B5 A6 B6 A7 B7
LUT Pn = RGB value from LUT
Byte 2 A8 B8 A9 B9 A10 B10 A 11 B11 Index (An, Bn)

Host Address
Display Buffer Panel Display

4 bpp: bit 7 bit 0 P0 P1 P2 P3 P4 P5 P6 P7

Byte 0 A0 B0 C0 D0 A1 B1 C1 D1
Byte 1 A2 B2 C2 D2 A3 B3 C3 D3
LUT Pn = RGB value from LUT
Byte 2 A4 B4 C4 D4 A5 B5 C5 D5 Index (An, Bn, Cn, D n)

Host Address
Display Buffer Panel Display

8 bpp: bit 7 bit 0 P0 P1 P2 P3 P4 P5 P6 P7

Byte 0 A0 B0 C0 D0 E0 F0 G0 H0
Byte 1 A1 B1 C1 D1 E1 F1 G1 H1
LUT Pn = RGB value from LUT Index
Byte 2 A2 B2 C2 D2 E2 F2 G2 H2 (An, Bn, Cn, Dn, En, Fn, Gn, H n)

Host Address
Display Buffer Panel Display

16 bpp: bit 7 bit 0 P0 P1 P2 P3 P4 P5 P6 P7

Byte 0 G02 G01 G00 B04 B03 B02 B 01 B00

Bypasses LUT
Byte 1 R04 R03 R02 R01 R00 G05 G04 G03
Pn = (Rn4-0, Gn5-0, Bn4-0)
Byte 2 G12 G11 G10 B14 B13 B12 B 11 B10
Byte 3 R14 R13 R12 R11 R10 G15 G14 G13
Panel Display
Host Address Display Buffer

Figure 14-1 : 1/2/4/8/16 Bit-Per-Pixel Display Data Memory Organization

Note
1. For 16 bpp format Rn, Gn and Bn represent the red, green, and blue color components.

Solomon Systech Aug 2005 P 121/159 Rev 1.1 SSD1906

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 15 Look-Up Table Architecture
The following figures show the display data output path only.

Note
When Color Invert is enabled the display color is inverted after the Look-Up Table.

15.1 Monochrome Modes

The green Look-Up Table (LUT) is used for all monochrome modes.

15.1.1 1 Bit-per-pixel Monochrome Mode

Green Look-Up Table 256x6

6-bit Gray Data

1 bit-per-pixel data 00
from Display Buffer 01

Figure 15-1 : 1 Bit-per-pixel Monochrome Mode Data Output Path

15.1.2 2 Bit-per-pixel Monochrome Mode

Green Look-Up Table 256x6

2 bit-per-pixel data 00 6-bit Gray Data

01
from Display Buffer 02
03

Figure 15-2 : 2 Bit-per-pixel Monochrome Mode Data Output Path

Solomon Systech Aug 2005 P 122/159 Rev 1.1 SSD1906

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 15.1.3 4 Bit-per-pixel Monochrome Mode

Green Look-Up Table 256x6

00
01
02
03
04
05
06 6-bit Gray Data
4 bit-per-pixel data 07
from Display Buffer 08
09
0A
0B
0C
0D
0E
0F

Figure 15-3 : 4 Bit-per-pixel Monochrome Mode Data Output Path

15.1.4 8 Bit-per-pixel Monochrome Mode

Green Look-Up Table 256x6

00
01
02
03
04
05
06
07
8 bit-per-pixel data 6-bit Gray Data
from Display Buffer
F8
F9
FA
FB
FC
FD
FE
FF

Figure 15-4 : 8 Bit-per-pixel Monochrome Mode Data Output Path

15.1.5 16 Bit-Per-Pixel Monochrome Mode

The LUT is bypassed and the green data is directly mapped for this color depth– See
Figure 14-1 : 1/2/4/8/16 Bit-Per-Pixel Display Data Memory Organization.

Solomon Systech Aug 2005 P 123/159 Rev 1.1 SSD1906

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 15.2 Color Modes

15.2.1 1 Bit-Per-Pixel Color

Red Look-Up Table 256x6

00 6-bit Red Data

01

Green Look-Up Table 256x6

1 bit-per-pixel data 00
6-bit Green Data
from Display Buffer 01

Blue Look-Up Table 256x6

00 6-bit Blue Data

01

Figure 15-5 : 1 Bit-Per-Pixel Color Mode Data Output Path

Solomon Systech Aug 2005 P 124/159 Rev 1.1 SSD1906

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 15.2.2 2 Bit-Per-Pixel Color

Red Look-Up Table 256x6

00
01 6-bit Red Data
02
03

Green Look-Up Table 256x6

00
01 6-bit Green Data
2 bit-per-pixel data 02
from Display Buffer 03

Blue Look-Up Table 256x6

00 6-bit Blue Data

01
02
03

Figure 15-6 : 2 Bit-Per-Pixel Color Mode Data Output Path

Solomon Systech Aug 2005 P 125/159 Rev 1.1 SSD1906

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 15.2.3 4 Bit-Per-Pixel Color

Red Look-Up Table 256x6

00
01
02
03
04
05
06
07 6-bit Red Data
08
09
0A
0B
0C
0D
0E
0F

Green Look-Up Table 256x6

00
01
02
03
04
05
06
4 bit-per-pixel data 07 6-bit Green Data
from Display Buffer 08
09
0A
0B
0C
0D
0E
0F

Blue Look-Up Table 256x6

00
01
02
03
04
05
06
07 6-bit Blue Data
08
09
0A
0B
0C
0D
0E
0F

Figure 15-7 : 4 Bit-Per-Pixel Color Mode Data Output Path

Solomon Systech Aug 2005 P 126/159 Rev 1.1 SSD1906

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 15.2.4 8 Bit-per-pixel Color Mode
Red Look-Up Table 256x6
00
01
02
03
04
05
06
07

6-bit Red Data

F8
F9
FA
FB
FC
FD
FE
FF

Green Look-Up Table 256x6

00
01
02
03
04
05
06
07
8 bit-per-pixel data 6-bit Green Data
from Display Buffer
F8
F9
FA
FB
FC
FD
FE
FF

Blue Look-Up Table 256x6

00
01
02
03
04
05
06
07
6-bit Blue Data

F8
F9
FA
FB
FC
FD
FE
FF

Figure 15-8 : 8 Bit-per-pixel Color Mode Data Output Path

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 15.2.5 16 Bit-Per-Pixel Color Mode
The LUT is bypassed at 16 bpp and the color data is directly mapped for this color depth. The color pixel is
arranged as 5-6-5 RGB format. See Figure 14-1 : 1/2/4/8/16 Bit-Per-Pixel Display Data Memory Organization.

16 Big-Endian Bus Interface

16.1 Byte Swapping Bus Data

The display buffer and register architecture of the SSD1906 is inherently little-endian. If configured as big-
endian (CF4 = 1 at reset), bus accesses are automatically handled by byte swapping all the read/write
data to/from the internal display buffer and registers.

Bus data byte swapping translates all byte accesses correctly to the SSD1906 register and display buffer
locations. To maintain the correct translation for 16-bit word access, even address bytes must be mapped
to the MSB of the 16-bit word, and odd address bytes to the LSB of the 16-bit word. For example:

D[15:8] Display
Buffer
D[7:0] Address

15 0 15 0
0 aa bb CPU Data bb aa 0
Byte Swap
2 cc 2
dd dd cc
System
Memory Display
Address MSB LSB Data
Byte Swap
aabb ccdd

System
Memory Display
(Big-Endian) Buffer
(Little-Endian)

* MSB is assumed to be associated with even address.

* LSB is assumed to be associated with odd address.

Byte write 11h to register address 1Eh -> REG[1Eh] <= 11h
Byte write 22h to register address 1Fh -> REG[1Fh] <= 22h
Word write 1122h to register address 1Eh-> REG[1Eh] <= 11h
REG[1Fh] <= 22h
Figure 16-1 : Byte-swapping for 16 Bpp

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 16.1.1 16 Bpp Color Depth
For 16 bpp color depth, the Display Data Byte Swap bit (REG[71h] bit 6) must be set to 1

For 16 bpp color depth, the MSB of the 16-bit pixel data is stored at the even system memory address
location and the LSB of the 16-bit pixel data is stored at the odd system memory address location. Bus
data byte swapping (automatic when the SSD1906 is configured for Big-Endian) causes the 16-bit pixel
data to be stored and byte-swapped in the SSD1906 display buffer. During display refresh this stored data
must be byte-swapped again before it is sent to the display.

16.1.2 1/2/4/8 Bpp Color Depth

For 1/2/4/8 bpp color depth, byte swapping must be performed on the bus data, but not the display data.

For 1/2/4/8 bpp color depth, the Display Data Byte Swap bit (REG[71h] bit 6) must be set to 0.

D[15:8] Display
Buffer
D[7:0] Address

15 0 15 0
0 11 CPU Data
22 22 11 0
Byte Swap

System
Memory
Address
11 22

System
Memory Display
(Big-Endian) Buffer
(Little-Endian)

* High byte lane (D[15:8]) data (e.g. 11) is associated with even address.
* Low byte lane (D[7:0]) data (e.g. 22) is associated with odd address.

Figure 16-2 : Byte-swapping for 1/2/4/8 Bpp

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 17 Virtual Display Mode
Virtual display is where the image to be viewed is larger than the physical display. This difference can be in the
horizontal, vertical, or both, dimensions. To view the image the display is used as a window into the display
buffer. At any given time only a portion of the image is visible. Panning and scrolling are used to view the full
image. Panning describes the horizontal (side to side) motion of the display area. Scrolling describes the
vertical (up and down) motion of the display area.
The Main Window Display Start Address register specifies the starting address of main window image in the
display buffer. The Main Window Line Address Offset register determines the number of horizontal pixels in
the virtual image. See Figure 17-1 : Main Window inside Virtual Image Area .

240 x 160 Panning

Main Window

Scrolling
320 x 240
Virtual Image Area

Figure 17-1 : Main Window inside Virtual Image Area

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 18 Display Rotate Mode
Most computer displays are refreshed in landscape orientation – from left to right and top to bottom. Computer
images are stored in the same manner. Display Rotate Mode is designed to rotate the displayed image on a
LCD by 90°, 180°, or 270° in an counter-clockwise direction. The rotation is done in hardware and is
transparent to the user for all display buffer reads and writes. By processing the rotation in hardware, Display
Rotate Mode offers a performance advantage over software rotation of the displayed image.

The image is not actually rotated in the display buffer since there is no address translation during CPU
read/write. The image is rotated during display refresh.

18.1 90° Display Rotate Mode

The following figure shows how the programmer sees a 320x480 rotated image and how the image is being
displayed. The application image is written to the SSD1906 as: A–B–C–D. The display is refreshed by the
SSD1906 as: B-D-A-C.

physical memory
start address

A B

Display

D
B
480

Rotate

Window
Display
Rotate
Window display start address

320
(panel origin)

C
A

C D 480
320

image seen by programmer image refreshed by SSD1906

= image in display buffer

Figure 18-1 : Relationship Between The Screen Image and the Image Refreshed in 90° Display Rotate
Mode.

18.1.1 Register Programming

Enable 90° Display Rotate Mode
Set Display Rotate Mode Select bits to 01 (REG[71h] bits 1:0 = 01).

Display Start Address

The display refresh circuitry starts at pixel “B”, therefore the Main Window Display Start Address
registers (REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel “B”.
To calculate the value of the address of pixel “B” use the following formula (assuming 8bpp color
depth).
Main Window Display Start Address bits 16-0
= ((Image address + (panel height x bpp ÷ 8)) ÷ 4) –1
= ((0 + (320 pixels x 8 bpp ÷ 8)) ÷ 4) – 1

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 = 79 (4Fh)

Line Address Offset

The Main Window Line Address Offset register (REG[78h], REG[79h]) is based on the display
width and programmed using the following formula.
Main Window Line Address Offset bits 9-0
= Display width in pixels ÷ (32 ÷ bpp)
= 320 pixels ÷ (32 ÷ 8 bpp)
= 80 (50h)

18.2 180° Display Rotate Mode

The following figure shows how the programmer sees a 480x320 landscape image and how the image is
being displayed. The application image is written to the SSD1906 as: A–B–C–D. The display is refreshed
by the SSD1906 as: D-C-B-A.

physical memory display start address

start address (panel origin)

A B
D C
Window
Display
Rotate
Rotate
320

320
Window
Display

C D
B A

480 480

image seen by programmer image refreshed by SSD1906

= image in display buffer

Figure 18-2 : Relationship Between The Screen Image and the Image Refreshed in 180° Display Rotate
Mode.

18.2.1 Register Programming

Enable 180° Display Rotate Mode
Set Display Rotate Mode Select bits to 10 (REG[71h] bits 1:0 = 10).

Display Start Address

The display refresh circuitry starts at pixel “D”, therefore the Main Window Display Start Address
registers (REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel “D”.
To calculate the value of the address of pixel “D” use the following formula (assumes 8bpp color
depth).
Main Window Display Start Address bits 16-0
= ((Image address + (image width x (panel height – 1) + panel width) x bpp ÷ 8) ÷ 4) –1
= ((0 + (480 pixels x 319 pixels + 480 pixels) x 8 bpp ÷ 8) ÷ 4) – 1
= 38399 (95FFh)

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 Line Address Offset
The Main Window Line Address Offset register (REG[78h], REG[79h]) is based on the display
width and programmed using the following formula.
Main Window Line Address Offset bits 9-0
= Display width in pixels ÷ (32 ÷ bpp)
= 480 pixels ÷ (32 ÷ 8 bpp)
= 120 (78h)

18.3 270° Display Rotate Mode

The following figure shows how the programmer sees a 320x480 rotated image and how the image is
being displayed. The application image is written to the SSD1906 as: A–B–C–D. The display is refreshed
by the SSD1906 as: C-A-D-B.

physical memory
start address

A B

Display
C

A
480

Rotate

Window

Display
Rotate
Window display start address

320
(panel origin)
D

B
C D 480
320

image seen by programmer image refreshed by SSD1906

= image in display buffer

Figure 18-3 : Relationship Between The Screen Image and the Image Refreshed in 270° Display Rotate
Mode.

18.3.1 Register Programming

Enable 270° Display Rotate Mode
Set Display Rotate Mode Select bits to 11 (REG[71h] bits 1:0 = 11).

Display Start Address

The display refresh circuitry starts at pixel “C”, therefore the Main Window Display Start Address
registers (REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel “C”.
To calculate the value of the address of pixel “C” use the following formula (assuming 8bpp color
depth).
Main Window Display Start Address bits 16-0
= (Image address + ((panel width – 1) x image width x bpp ÷ 8) ÷ 4)
= (0 + ((480 pixels – 1) x 320 pixels x 8 bpp ÷ 8) ÷ 4)

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 = 38320 (95B0h)

Line Address Offset

The Main Window Line Address Offset register (REG[78h], REG[79h]) is based on the display
width and programmed using the following formula.
Main Window Line Address Offset bits 9-0
= Display width in pixels ÷ (32 ÷ bpp)
= 320 pixels ÷ (32 ÷ 8 bpp)
= 80 (50h)

19 Floating Window Mode

This mode enables a floating window within the main display window. The floating window can be
positioned anywhere within the virtual display and is controlled through the Floating Window control
registers (REG[7Ch] throughREG[91h]). The floating window retains the same color depth and display
orientation as the main window.

The following diagram shows an example of a floating window within a main window and the registers
used to position it.

Normal Orientation Mode Floating Window Start Y Position

(REG[89h],REG[88h])
panel’s origin
Floating Window End Y Position
(REG[91h],REG[90h])
Main Window

Floating Window

Floating Window End X Position

Floating Window Start X Position
(REG[8Dh],REG[8Ch])
(REG[85h],REG[84h])

Figure 19-1 : Floating Window with Display Rotate Mode disabled

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 19.1 With Display Rotate Mode Enabled

19.1.1 Display Rotate Mode 90°

90°° Display Rotate Mode panel’s origin

Floating Window End X Position Floating Window Start X Position

(REG[8Dh],REG[8Ch]) (REG[85h],REG[84h])

Floating window
Floating Window Start Y Position
(REG[89h],REG[88h])

Main Window Floating Window End Y Position

(REG[91h],REG[90h])

Figure 19-2 : Floating Window with Display Rotate Mode 90° enabled

19.1.2 Display Rotate Mode 180°

180°° Display Rotate Mode Floating Window Start X Position
Floating Window End X Position (REG[85h],REG[84h])
(REG[8Dh],REG[8Ch])

Floating Window

Main Window

Floating Window End Y Position

(REG[91h],REG[90h]) Floating Window Start Y Position panel’s origin
(REG[89h],REG[88h])

Figure 19-3 : Floating Window with Display Rotate Mode 180° enabled

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 19.1.3 Display Rotate Mode 270°

270°° Display Rotate Mode

Floating Window End Y Position

(REG[91h],REG[90h])
Main Window

Floating Window Start Y Position

(REG[89h],REG[88h])
Floating Window

Floating Window Start X Position

(REG[85h],REG[84h]) Floating Window End X Position
(REG[8Dh],REG[8Ch])
panel’s origin

Figure 19-4 : Floating Window with Display Rotate Mode 270° enabled

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 20 Hardware Cursor Mode
This mode enables two cursors on the main display window. The cursors can be positioned anywhere within the
display and are controlled through Cursor Mode registers (REG[C0h] through REG[111h]). Cursor support is
available only at 4/8/16-bpp display modes.

Each cursor pixel is 2-bit and the indexing scheme is as follows:

Table 20-1 : Indexing scheme for Hardware Cursor
Value Color of Cursor 1 / Cursor 2
00 Transparent
01 Content of color index 1 register (REG[E1h], REG[E0h] / REG[109h], REG[108h])
10 Content of color index 2 register (REG[E5h], REG[E4h] / REG[10Dh], REG[10Ch])
11 Content of color index 3 register (REG[E9h], REG[E8h] / REG[111h], REG[110h])

Three 16-bit color index registers (REG[E0h] through REG[E9h] and REG[108h] through REG[111h]) have been
implemented for each cursor. Only the lower portion of the color index register is used in 4/8-bpp display modes.
The LUT is bypassed and the color data is directly mapped for 16-bpp display mode.

4 Bit-per-pixel
15 12 11 8 7 4 3 0
Don’t Care 4-bit Color Index

8 Bit-per-pixel
15 12 11 8 7 4 3 0
Don’t Care 8-bit Color Index

16 Bit-per-pixel (the index registers represents the 16-bit color component)

15 13 12 8 7 3 2 0
Green Component Blue Component Red Component Green Component
Bits 2-0 Bits 4-0 Bits 4-0 Bits 5-3

The display precedence is Cursor1 > Cursor2 > Floating window > Main Window.

Cursor 1

Cursor 2

Floating Window

Main Window

Figure 20-1 : Display Precedence in Hardware Cursor

Note :
The minimum size varies for different color depths and display orientations.

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 The cursors retains the same color depth and display orientation as the main window. The following diagram
shows an example of two cursors within a main window and the registers used to position it.

Cursor1 Position Y
(REG[D5h],REG[D4h]) Cursor2 Position Y
(REG[FDh],REG[FCh])
panel’s origin

Main-Window

Cursor1
Cursor1 Position X
(REG[D1h],REG[D0h])

Cursor2

Cursor2 Position X
(REG[F9h],REG[F8h])

Figure 20-2 : Cursors on the main window

20.1 With Display Rotate Mode Enabled

20.1.1 Display Rotate Mode 90°°

Cursor1 Position X
Cursor2 Position X (REG[D1h],REG[D0h])
(REG[F9h],REG[F8h])

panel’s origin

Cursor1
Cursor1 Position Y
(REG[D5h],REG[D4h])
Cursor2

Main-Window
Cursor2 Position Y
(REG[FDh],REG[FCh])

Figure 20-3 : Cursors with Display Rotate Mode 90° enabled

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 20.1.2 Display Rotate Mode 180°°

Cursor2 Position X Cursor1 Position X

(REG[F9h],REG[F8h]) (REG[D1h],REG[D0h])

Main-Window

Cursor1

Cursor2
Cursor1 Position Y
(REG[D5h],REG[D4h])

Cursor2 Position Y panel’s origin

(REG[FDh],REG[FCh])

Figure 20-4 : Cursors with Display Rotate Mode 180° enabled

20.1.3 Display Rotate Mode 270°°

Cursor1 Position Y
(REG[D5h],REG[D4h])

Main-Window
Cursor2 Position Y
(REG[FDh],REG[FCh]) Cursor1

Cursor2
Cursor1 Position X
(REG[D1h],REG[D0h])

panel’s origin Cursor2 Position X

(REG[F9h],REG[F8h])

Figure 20-5 : Cursors with Display Rotate Mode 270° enabled

20.2 Pixel format (Normal orientation mode)

Assuming the pixel data stores start at address n, where n must be divisible by 4 (i.e. aligned to 32-bit
boundary). In this example, a 16x16 cursor is displayed which each cursor index is defined by x and y
coordinate, C(y,x).

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 20.2.1 4/8/16 Bit-per-pixel
7 6 5 4 3 2 1 0
Addr. n C(0,0) C(0,1) C(0,2) C(0,3)
Addr. n+1 C(0,4) C(0,5) C(0,6) C(0,7)
Addr. n+2 C(0,8) C(0,9) C(0,10) C(0,11)
Addr. n+3 C(0,12) C(0,13) C(0,14) C(0,15)
Addr. n+4 C(1,0) C(1,1) C(1,2) C(1,3)
.
.
.
Addr. n + 60 C(15,0) C(15,1) C(15,2) C(15,3)
Addr. n + 61 C(15,4) C(15,5) C(15,6) C(15,7)
Addr. n + 62 C(15,8) C(15,9) C(15,10) C(15,11)
Addr. n + 63 C(15,12) C(15,13) C(15,14) C(15,15)

20.3 Pixel format (90˚ Display Rotate Mode)

Assuming the pixel data stores start at address n, where n must be divisible by 4 (i.e. aligned to 32-bit
boundary). In this example, a 16x16 cursor is displayed which each cursor index is defined x and y coordinate,
C(y,x).

20.3.1 4 Bit-per-pixel
7 6 5 4 3 2 1 0
Addr. n C(0,8) C(0,9) C(0,10) C(0,11)
Addr. n+1 C(0,12) C(0,13) C(0,14) C(0,15)
Addr. n+2 C(1,8) C(1,9) C(1,10) C(1,11)
Addr. n+3 C(1,12) C(1,13) C(1,14) C(1,15)

.
.
.
Addr. n + 28 C(14,8) C(14,9) C(14,10) C(14,11)
Addr. n + 29 C(14,12) C(14,13) C(14,14) C(14,15)
Addr. n + 30 C(15,8) C(15,9) C(15,10) C(15,11)
Addr. n + 31 C(15,12) C(15,13) C(15,14) C(15,15)
Addr. n + 32 C(0,0) C(0,1) C(0,2) C(0,3)
Addr. n + 33 C(0,4) C(0,5) C(0,6) C(0,7)
Addr. n + 34 C(1,0) C(1,1) C(1,2) C(1,3)
Addr. n + 35 C(1,4) C(1,5) C(1,6) C(1,7)

.
.
.
Addr. n + 60 C(14,0) C(14,1) C(14,2) C(14,3)
Addr. n + 61 C(14,4) C(14,5) C(14,6) C(14,7)
Addr. n + 62 C(15,0) C(15,1) C(15,2) C(15,3)
Addr. n + 63 C(15,4) C(15,5) C(15,6) C(15,7)

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 20.3.2 8 Bit-per-pixel
7 6 5 4 3 2 1 0
Addr. n C(0,12) C(0,13) C(0,14) C(0,15)
Addr. n+1 C(1,12) C(1,13) C(1,14) C(1,15)
Addr. n+2 C(2,12) C(2,13) C(2,14) C(2,15)
Addr. n+3 C(3,12) C(3,13) C(3,14) C(3,15)

.
.
.
Addr. n + 12 C(12,12) C(12,13) C(12,14) C(12,15)
Addr. n + 13 C(13,12) C(13,13) C(13,14) C(13,15)
Addr. n + 14 C(14,12) C(14,13) C(14,14) C(14,15)
Addr. n + 15 C(15,12) C(15,13) C(15,14) C(15,15)
Addr. n + 16 C(0,8) C(0,9) C(0,10) C(0,11)
Addr. n + 17 C(1,8) C(1,9) C(1,10) C(1,11)
Addr. n + 18 C(2,8) C(2,9) C(2,10) C(2,11)
Addr. n + 19 C(3,8) C(3,9) C(3,10) C(3,11)

.
.
.
Addr. n + 60 C(12,0) C(12,1) C(12,2) C(12,3)
Addr. n + 61 C(13,0) C(13,1) C(13,2) C(13,3)
Addr. n + 62 C(14,0) C(14,1) C(14,2) C(14,3)
Addr. n + 63 C(15,0) C(15,1) C(15,2) C(15,3)

20.3.3 16 Bit-per-pixel
7 6 5 4 3 2 1 0
Addr. n C(0,14) C(0,15) C(1,14) C(1,15)
Addr. n+1 C(2,14) C(2,15) C(3,14) C(3,15)
Addr. n+2 C(4,14) C(4,15) C(5,14) C(5,15)
Addr. n+3 C(6,14) C(6,15) C(7,14) C(7,15)
Addr. n+4 C(8,14) C(8,15) C(9,14) C(9,15)
Addr. n+5 C(10,14) C(10,15) C(11,14) C(11,15)
Addr. n+6 C(12,14) C(12,15) C(12,14) C(12,15)
Addr. n+7 C(14,14) C(14,15) C(15,14) C(15,15)
Addr. n+8 C(0,12) C(0,13) C(1,12) C(1,13)
Addr. n+9 C(2,12) C(2,13) C(3,12) C(3,13)
Addr. n + 10 C(4,12) C(4,13) C(5,12) C(5,13)
Addr. n + 11 C(6,12) C(6,13) C(7,12) C(7,13)

.
.
.
Addr. n + 60 C(8,0) C(8,1) C(9,0) C(9,1)
Addr. n + 61 C(10,0) C(10,1) C(11,0) C(11,1)
Addr. n + 62 C(12,0) C(12,1) C(12,0) C(12,1)
Addr. n + 63 C(14,0) C(14,1) C(15,0) C(15,1)

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 20.4 Pixel format (180˚ Display Rotate Mode)

Assuming the pixel data stores start at address n, where n must be divisible by 4 (i.e. aligned to 32-bit
boundary). In this example, a 16x16 cursor is displayed which each cursor index is defined by x and y
coordinate, C(y,x).

20.4.1 4 Bit-per-pixel
7 6 5 4 3 2 1 0
Addr. n C(15,8) C(15,9) C(15,10) C(15,11)
Addr. n+1 C(15,12) C(15,13) C(15,14) C(15,15)
Addr. n+2 C(15,0) C(15,1) C(15,2) C(15,3)
Addr. n+3 C(15,4) C(15,5) C(15,6) C(15,7)
Addr. n+4 C(14,8) C(14,9) C(14,10) C(14,11)

.
.
.
Addr. n + 60 C(0,8) C(0,9) C(0,10) C(0,11)
Addr. n + 61 C(0,12) C(0,13) C(0,14) C(0,15)
Addr. n + 62 C(0,0) C(0,1) C(0,2) C(0,3)
Addr. n + 63 C(0,4) C(0,5) C(0,6) C(0,7)

20.4.2 8 Bit-per-pixel
7 6 5 4 3 2 1 0
Addr. n C(15,12) C(15,13) C(15,14) C(15,15)
Addr. n+1 C(15,8) C(15,9) C(15,10) C(15,11)
Addr. n+2 C(15,4) C(15,5) C(15,6) C(15,7)
Addr. n+3 C(15,0) C(15,1) C(15,2) C(15,3)
Addr. n+4 C(14,12) C(14,13) C(14,14) C(14,15)

.
.
.
Addr. n + 60 C(0,12) C(0,13) C(0,14) C(0,15)
Addr. n + 61 C(0,8) C(0,9) C(0,10) C(0,11)
Addr. n + 62 C(0,4) C(0,5) C(0,6) C(0,7)
Addr. n + 63 C(0,0) C(0,1) C(0,2) C(0,3)

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 20.4.3 16 Bit-per-pixel
7 6 5 4 3 2 1 0
Addr. n C(15,14) C(15,15) C(15,12) C(15,13)
Addr. n+1 C(15,10) C(15,11) C(15,8) C(15,9)
Addr. n+2 C(15,6) C(15,7) C(15,4) C(15,5)
Addr. n+3 C(15,2) C(15,3) C(15,0) C(15,1)
Addr. n+4 C(14,14) C(14,15) C(14,12) C(14,13)

.
.
.
Addr. n + 60 C(0,14) C(0,15) C(0,12) C(0,13)
Addr. n + 61 C(0,10) C(0,11) C(0,8) C(0,9)
Addr. n + 62 C(0,6) C(0,7) C(0,4) C(0,5)
Addr. n + 63 C(0,2) C(0,3) C(0,0) C(0,1)

20.5 Pixel format (270˚ Display Rotate Mode)

Assuming the pixel data stores start at address n, where n must be divisible by 4 (i.e. aligned to 32-bit
boundary). In this example, a 16x16 cursor is displayed which each cursor index is defined by x and y
coordinate, C(y,x).

20.5.1 4 Bit-per-pixel
7 6 5 4 3 2 1 0
Addr. n C(15,0) C(15,1) C(15,2) C(15,3)
Addr. n+1 C(15,4) C(15,5) C(15,6) C(15,7)
Addr. n+2 C(14,0) C(14,1) C(14,2) C(14,3)
Addr. n+3 C(14,4) C(14,5) C(14,6) C(14,7)
.
.
.
Addr. n + 28 C(1,0) C(1,1) C(1,2) C(1,3)
Addr. n + 29 C(1,4) C(1,5) C(1,6) C(1,7)
Addr. n + 30 C(0,0) C(0,1) C(0,2) C(0,3)
Addr. n + 31 C(0,4) C(0,5) C(0,6) C(0,7)
Addr. n + 32 C(15,8) C(15,9) C(15,10) C(15,11)
Addr. n + 33 C(15,12) C(15,13) C(15,14) C(15,15)
Addr. n + 34 C(14,8) C(14,9) C(14,10) C(14,11)
Addr. n + 35 C(14,12) C(14,13) C(14,14) C(14,15)

.
.
.
Addr. n + 60 C(1,8) C(1,9) C(1,10) C(1,11)
Addr. n + 61 C(1,12) C(1,13) C(1,14) C(1,15)
Addr. n + 62 C(0,8) C(0,9) C(0,10) C(0,11)

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 Addr. n + 63 C(0,12) C(0,13) C(0,14) C(0,15)

20.5.2 8 Bit-per-pixel
7 6 5 4 3 2 1 0
Addr. n C(15,0) C(15,1) C(15,2) C(15,3)
Addr. n+1 C(14,0) C(14,1) C(14,2) C(14,3)
Addr. n+2 C(13,0) C(13,1) C(13,2) C(13,3)
Addr. n+3 C(12,0) C(12,1) C(12,2) C(12,3)

.
.
.
Addr. n + 12 C(3,0) C(3,1) C(3,2) C(3,3)
Addr. n + 13 C(2,0) C(2,1) C(2,2) C(2,3)
Addr. n + 14 C(1,0) C(1,1) C(1,2) C(1,3)
Addr. n + 15 C(0,0) C(0,1) C(0,2) C(0,3)
Addr. n + 16 C(15,4) C(15,5) C(15,6) C(15,7)
Addr. n + 17 C(14,4) C(14,5) C(14,6) C(14,7)
Addr. n + 18 C(13,4) C(13,5) C(13,6) C(13,7)
Addr. n + 19 C(12,4) C(12,5) C(12,6) C(12,7)

.
.
.
Addr. n + 60 C(3,12) C(3,13) C(3,14) C(3,15)
Addr. n + 61 C(2,12) C(2,13) C(2,14) C(2,15)
Addr. n + 62 C(1,12) C(1,13) C(1,14) C(1,15)
Addr. n + 63 C(0,12) C(0,13) C(0,14) C(0,15)

20.5.3 16 Bit-per-pixel
7 6 5 4 3 2 1 0
Addr. n C(15,0) C(15,1) C(14,0) C(14,1)
Addr. n+1 C(13,0) C(13,1) C(12,0) C(12,1)
Addr. n+2 C(11,0) C(11,1) C(10,0) C(10,1)
Addr. n+3 C(9,0) C(9,1) C(8,0) C(8,1)
Addr. n+4 C(7,0) C(7,1) C(6,0) C(6,1)
Addr. n+5 C(5,0) C(5,1) C(4,0) C(4,1)
Addr. n+6 C(3,0) C(3,1) C(2,0) C(2,1)
Addr. n+7 C(1,0) C(1,1) C(0,0) C(0,1)
Addr. n+8 C(15,2) C(15,3) C(14,2) C(14,3)
Addr. n+9 C(13,2) C(13,3) C(12,2) C(12,3)
Addr. n + 10 C(11,2) C(11,3) C(10,2) C(10,3)
Addr. n + 11 C(9,2) C(9,3) C(8,2) C(8,3)
.
.
.
Addr. n + 60 C(7,14) C(7,15) C(6,14) C(6,15)
Addr. n + 61 C(5,14) C(5,15) C(4,14) C(4,15)

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 Addr. n + 62 C(3,14) C(3,15) C(2,14) C(2,15)
Addr. n + 63 C(1,14) C(1,15) C(0,14) C(0,15)

Solomon Systech Aug 2005 P 146/159 Rev 1.1 SSD1906

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 21 APPLICATION EXAMPLES

IOVDD Oscillator

10kΩ
Generic #1
BUS
COREVDD

AUXCLK
BS#
0.1µF
0.1µF

A[27:18] Decoder M/R# 3.3V

CSn# CS# IOVDD 0.1µF 8-Bit

CSTN
A[17:1] A[17:1] LCD
D[15:0] D[15:0] LDATA[7:0] D[7:0] Display
SSD1906 LFRAME LFRAME
WE0# WE0#
WE1# WE1#

Bias Power
RD0# RD0# LLINE LLINE
RD1# RD/WR# LSHIFT LSHIFT
WAIT# WAIT# LDEN MOD

BUSCLK CLKI
RESET# GPO
CF0

RESET#
CF1

CF2
CF0

0.1µF A0
4.7kΩ IOVDD

4.7kΩ
10kΩ
10kΩ

Figure 21-1: Typical System Diagram (Generic #1 Bus)

Solomon Systech Aug 2005 P 147/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 Oscillator
IOVDD

Generic #2 10kΩ 10kΩ

BUS

AUXCLK
BS# COREVDD 0.1µF
RD/WR# 0.1µF

A[27:18] Decoder M/R# 3.3V

CSn# CS# IOVDD 0.1µF 9-Bit

TFT
A[17:0] A[17:0] Display
D[15:0] D[15:0] LDATA[8:0] D[8:0]
SSD1906 LFRAME LFRAME
WE# WE0#
BHE# WE1#

Bias Power
RD# RD# LLINE LLINE
LSHIFT LSHIFT
WAIT# WAIT# LDEN LDEN

BUSCLK CLKI
RESET# RESET# GPO

CF0
CF1

CF2
CF0

0.1µF

IOVDD
4.7kΩ
4.7kΩ 10kΩ

Figure 21-2 : Typical System Diagram (Generic #2 Bus)

Solomon Systech Aug 2005 P 148/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 Oscillator
IOVDD

MC68K #1 10kΩ 10kΩ

BUS

AUXCLK
RD# COREVDD
0.1µF
WE0#
A[23:18], Decoder M/R# 3.3V
FC0, FC1
IOVDD
Decoder 0.1µF
CS# 18-Bit
LDATA[17:0] D[17:0] HR-TFT
A[17:1] A[17:1] LFRAME SPS Display
D[15:0] D[15:0] LLINE LP
LDS# A0 SSD1906 LSHIFT CLK
UDS# WE1#
AS# BS# GPIO0 PS

Bias Power
R/W# RD/WR# GPIO1 CLS
DTACK# WAIT# GPIO2 REV
GPIO3 SPL

CLK CLKI
RESET# RESET# GPO

CF0
CF1

CF2
CF0
0.1µF

IOVDD

4.7kΩ
10kΩ
4.7kΩ

Figure 21-3 : Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000)

Solomon Systech Aug 2005 P 149/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 Oscillator
IOVDD

MC68EZ328/
10kΩ 10kΩ
MC68VZ328

AUXCLK
DragonBall BS# COREVDD 0.1µF
0.1µF
BUS RD/WR#
3.3V
IOVDD
A[25:18] Decoder M/R# 0.1µF
12-bit
CSX# CS# LDATA[11:0] D[11:0] TFT
LSHIFT LSHIFT Display
A[17:1] A[17:1]
D[15:0] D[15:0] SSD1906
LFRAME LFRAME
LWE# WE0# LLINE LLINE

Bias Power
UWE# WE1# LDEN LDEN
OE# RD #
DTACK# WAIT#
CLKO CLKI
RESET# RESET#
A0 GPO

CF0
CF1

CF2
CF0
0.1µF

4.7kΩ IOVDD
4.7kΩ

10kΩ
10kΩ

Figure 21-4 : Typical System Diagram (Motorola MC68EZ328/MC68VZ328 “DragonBall” Bus)

Solomon Systech Aug 2005 P 150/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 Oscillator

SH-3
BUS

AUXCLK
COREVDD

A[25:18] Decoder M/R# 3.3V

IOVDD
CSn# CS#
12-Bit
A[17:1] A[17:1] TFT
D[15:0] D[15:0] Display
WE0# WE0#
WE1# WE1# SSD1906
BS# BS# LDATA[11:0] D[11:0]
RD/WR# RD/WR# LFRAME LFRAME

Bias Power
RD# RD# LLINE LLINE
LSHIFT LSHIFT
WAIT# WAIT# LDEN LDEN

CKIO CLKI
RESET# GPO

CF0
RESET#
CF1

CF2
CF0

A0

4.7kΩ
4.7kΩ 4.7kΩ
4.7kΩ

Figure 21-5 : Typical System Diagram (Hitachi SH-3 Bus)

Solomon Systech Aug 2005 P 151/159 Rev 1.1 SSD1906

Downloaded from Arrow.com.

 Oscillator

SH-4
BUS

AUXCLK
COREVDD

A[25:18] Decoder M/R# 3.3V

IOVDD
CSn# CS#
18-Bit
A[17:1] A[17:1] TFT
D[15:0] D[15:0] Display
WE0# WE0#
WE1# WE1# SSD1906
BS# BS# LDATA[17:0] D[17:0]
RD/WR# RD/WR# LFRAME LFRAME

Bias Power
RD# RD# LLINE LLINE
LSHIFT LSHIFT
RDY# WAIT# LDEN LDEN

CKIO CLKI
RESET# RESET# GPO

CF0
CF1

CF2
A0 CF0

4.7kΩ
4.7kΩ 4.7kΩ
4.7kΩ

Figure 21-6 : Typical System Diagram (Hitachi SH-4 Bus)

Solomon Systech Aug 2005 P 152/159 Rev 1.1 SSD1906

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 22 APPENDIX

22.1 Package Mechanical Drawing for 100 pins TQFP

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 22.2 Package Mechanical Drawing for 100 pins TFBGA

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 Solomon Systech Aug 2005 P 155/159 Rev 1.1 SSD1906

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 22.3 Register Table
Table 22-1 : SSD1906 Register Table (1 of 3)
Register Pg
Read-Only Configuration Registers
REG[01h] Display Buffer Size Register 20
REG[02h] Configuration Readback Register 20
REG[03h] Product / Revision Code Register 21
Clock Configuration Registers
REG[04h] Memory Clock Configuration Register 21
REG[05h] Pixel Clock Configuration Register 21
Look-Up Table Registers
REG[08h] Look-Up Table Blue Write Data Register 22
REG[09h] Look-Up Table Green Write Data Register 23
REG[0Ah] Look-Up Table Red Write Data Register 23
REG[0Bh] Look-Up Table Write Address Register 24
REG[0Ch] Look-Up Table Blue Read Data Register 24
REG[0Dh] Look-Up Table Green Read Data Register 24
REG[0Eh] Look-Up Table Red Read Data Register 25
REG[0Fh] Look-Up Table Read Address Register 25
Panel Configuration Registers
REG[10h] Panel Type Register 26
REG[11h] MOD Rate Register 27
REG[12h] Horizontal Total Register 27
REG[14h] Horizontal Display Period Register 28
REG[16h] Horizontal Display Period Start Position Register 0 28
REG[17h] Horizontal Display Period Start Position Register 1 28
REG[18h] Vertical Total Register 0 28
REG[19h] Vertical Total Register 1 28
REG[1Ch] Vertical Display Period Register 0 29
REG[1Dh] Vertical Display Period Register 1 29
REG[1Eh] Vertical Display Period Start Position Register 0 30
REG[1Fh] Vertical Display Period Start Position Register 1 30
REG[20h] LLINE Pulse Width Register 30
REG[22h] LLINE Pulse Start Position Register 0 31
REG[23h] LLINE Pulse Start Position Register 1 31
REG[24h] LFRAME Pulse Width Register 31
REG[26h] LFRAME Pulse Start Position Register 0 32
REG[27h] LFRAME Pulse Start Position Register 1 32
REG[30h] LFRAME Pulse Start Offset Register 0 32
REG[31h] LFRAME Pulse Start Offset Register 1 32
REG[34h] LFRAME Pulse Stop Offset Register 0 33
REG[35h] LFRAME Pulse Stop Offset Register 1 33
REG[38h] HR-TFT Special Output Register 33
REG[3Ah] GPIO1 Pulse Start Register 34
REG[3Bh] GPIO1 Pulse Stop Register 34
REG[3Ch] GPIO0 Pulse Start Register 35
REG[3Eh] GPIO0 Pulse Stop Register 35
REG[40h] GPIO2 Pulse Delay Register 35
REG[45h] STN Color Depth Control Register 36
REG[50h] Dynamic Dithering Control Register 37
Display Mode Registers
REG[70h] Display Mode Register 37
REG[71h] Special Effects Register 39
Main Window Registers
REG[74h] Main Window Display Start Address Register 0 40
REG[75h] Main Window Display Start Address Register 1 40
REG[76h] Main Window Display Start Address Register 2 40
REG[78h] Main Window Line Address Offset Register 0 41
REG[79h] Main Window Line Address Offset Register 1 41

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 Table 22-2 : SSD1906 Register Table (2 of 3)
Register Pg
Floating Window Registers
REG[7Ch] Floating Window Display Start Address Register 0 42
REG[7Dh] Floating Window Display Start Address Register 1 42
REG[7Eh] Floating Window Display Start Address Register 2 42
REG[80h] Floating Window Line Address Offset Register 0 43
REG[81h] Floating Window Line Address Offset Register 1 43
REG[84h] Floating Window Start Position X Register 0 43
REG[85h] Floating Window Start Position X Register 1 44
REG[88h] Floating Window Start Position Y Register 0 44
REG[89h] Floating Window Start Position Y Register 1 45
REG[8Ch] Floating Window End Position X Register 0 45
REG[8Dh] Floating Window End Position X Register 1 46
REG[90h] Floating Window End Position Y Register 0 46
REG[91h] Floating Window End Position Y Register 1 47
Miscellaneous Registers
REG[A0h] Power Saving Configuration Register 47
REG[A2h] Software Reset Register 48
REG[A4h] Scratch Pad Register 0 48
REG[A5h] Scratch Pad Register 1 48
REG[134h] Command Initialization Register 49
General Purpose IO Pins Registers
REG[A8h] General Purpose IO Pins Configuration Register 0 49
REG[A9h] General Purpose IO Pins Configuration Register 1 50
REG[ACh] General Purpose IO Pins Status/Control Register 0 50
REG[ADh] General Purpose IO Pins Status/Control Register 1 51
PWM Clock and CV Pulse Configuration Registers
REG[B0h] PWM Clock / CV Pulse Control Register 52
REG[B1h] PWM Clock / CV Pulse Configuration Register 53
REG[B2h] CV Pulse Burst Length Register 54
REG[B3h] LPWMOUT Duty Cycle Register 54

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 Table 22-3 : SSD1906 Register Table (3 of 3)
Register Pg
Cursor Mode Registers
REG[C0h] Cursor Feature Register 55
REG[C4h] Cursor1 Blink Total Register 0 55
REG[C5h] Cursor1 Blink Total Register 1 55
REG[C8h] Cursor1 Blink On Register 0 56
REG[C9h] Cursor1 Blink On Register 1 56
REG[CCh] Cursor1 Memory Start Register 0 56
REG[CDh] Cursor1 Memory Start Register 1 56
REG[CEh] Cursor1 Memory Start Register 2 56
REG[D0h] Cursor1 Position X Register 0 57
REG[D1h] Cursor1 Position X Register 1 57
REG[D4h] Cursor1 Position Y Register 0 57
REG[D5h] Cursor1 Position Y Register 1 57
REG[D8h] Cursor1 Horizontal size Register 0 58
REG[D9h] Cursor1 Horizontal size Register 1 58
REG[DCh] Cursor1 Vertical size Register 0 59
REG[DDh] Cursor1 Vertical size Register 1 59
REG[E0h] Cursor1 Color Index1 Register 0 59
REG[E1h] Cursor1 Color Index1 Register 1 60
REG[E4h] Cursor1 Color Index2 Register 0 60
REG[E5h] Cursor1 Color Index2 Register 1 60
REG[E8h] Cursor1 Color Index3 Register 0 60
REG[E9h] Cursor1 Color Index3 Register 1 62
REG[ECh] Cursor2 Blink Total Register 0 62
REG[EDh] Cursor2 Blink Total Register 1 62
REG[F0h] Cursor2 Blink On Register 0 62
REG[F1h] Cursor2 Blink On Register 1 63
REG[F4h] Cursor2 Memory Start Register 0 63
REG[F5h] Cursor2 Memory Start Register 1 63
REG[F6h] Cursor2 Memory Start Register 2 63
REG[F8h] Cursor2 Position X Register 0 64
REG[F9h] Cursor2 Position X Register 1 64
REG[FCh] Cursor2 Position Y Register 0 64
REG[FDh] Cursor2 Position Y Register 1 64
REG[100h] Cursor2 Horizontal size Register 0 65
REG[101h] Cursor2 Horizontal size Register 1 65
REG[104h] Cursor2 Vertical size Register 0 65
REG[105h] Cursor2 Vertical size Register 1 65
REG[108h] Cursor2 Color Index1 Register 0 67
REG[109h] Cursor2 Color Index1 Register 1 67
REG[10Ch] Cursor2 Color Index2 Register 0 67
REG[10Dh] Cursor2 Color Index2 Register 1 67
REG[110h] Cursor2 Color Index3 Register 0 69
REG[111h] Cursor2 Color Index3 Register 1 69

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Downloaded from Arrow.com.

 Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any, and all, liability, including without limitation consequential or incidental
damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each
customer application by the customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others.
Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or
manufacture of the part.

With collaboration of https://www.displayfuture.com

Solomon Systech Aug 2005 P 159/159 Rev 1.1 SSD1906

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