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OPA551, OPA552
SBOS100B – JULY 1999 – REVISED JANUARY 2016

OPA55x High-Voltage, High-Current Operational Amplifiers

1 Features 3 Description
•
1 Wide Supply Range: ±4 V to ±30 V The OPA551x devices are low-cost operational
amplifiers with high-voltage (60-V) and high-current
• High Output Current: 200 mA Continuous (200-mA) capability.
• Low Noise: 14 nV/√Hz
The OPA551 is unity-gain stable and features high
• Fully Protected: slew rate (15 V/µs) and wide bandwidth (3 MHz). The
– Thermal Shutdown OPA552 is optimized for gains of 5 or greater, and
– Output Current-Limited offers higher speed with a slew rate of 24 V/µs and a
bandwidth of 12 MHz. Both devices are suitable for
• Thermal Shutdown Indicator
telephony, audio, servo, and test applications.
• Wide Output Swing: 2 V from Rail
These laser-trimmed, monolithic integrated circuits
• Fast Slew Rate: provide excellent low-level accuracy along with high
– OPA551: 15 V/µs output swing. High performance is maintained as the
– OPA552: 24 V/µs amplifier swings to its specified limits.
• Wide Bandwidth: The OPA55x devices are internally protected against
– OPA551: 3 MHz overtemperature conditions and current overloads.
The thermal shutdown indicator flag provides a
– OPA552: 12 MHz current output to alert the user when thermal
• Packages: PDIP-8, SOIC-8, or DDPAK/TO-263-7 shutdown has occurred.
The OPA55x devices are available in PDIP-8 and
2 Applications SOIC-8 packages, as well as a DDPAK-7/TO-263
• Telephony surface-mount plastic power package. They are
• Test Equipment specified for operation over the extended industrial
temperature range, –40°C to +125°C.
• Audio Amplifiers
• Transducer Excitation Device Information(1)
• Servo Drivers PART NUMBER PACKAGE BODY SIZE (NOM)
PDIP (8) 9.81 mm × 6.35 mm
OPA55x SOIC (8) 4.9 mm × 3.91 mm
DDPAK/TO-263 (7) 10.1 mm × 8.99 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Simplified Functional Diagram

V+

V±IN ±

OPA551 VO

V+IN +

Flag
V±

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA551, OPA552
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Table of Contents
1 Features .................................................................. 1 8.1 Application Information............................................ 13
2 Applications ........................................................... 1 8.2 Typical Application ................................................. 13
3 Description ............................................................. 1 9 Power Supply Recommendations...................... 17
4 Revision History..................................................... 2 9.1 Power Supplies ....................................................... 17
5 Pin Configuration and Functions ......................... 3 10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
6 Specifications......................................................... 4
10.2 Layout Example .................................................... 18
6.1 Absolute Maximum Ratings ...................................... 4
10.3 Power Dissipation ................................................. 18
6.2 ESD Ratings ............................................................ 4
10.4 Safe Operating Area ............................................. 19
6.3 Recommended Operating Conditions....................... 4
10.5 Heat Sinking ......................................................... 20
6.4 Thermal Information .................................................. 4
6.5 Electrical Characteristics: VS = ±30 V....................... 5 11 Device and Documentation Support ................. 21
6.6 Typical Characteristics .............................................. 7 11.1 Device Support...................................................... 21
11.2 Documentation Support ....................................... 21
7 Detailed Description ............................................ 11
11.3 Community Resources.......................................... 21
7.1 Overview ................................................................. 11
11.4 Trademarks ........................................................... 21
7.2 Functional Block Diagram ....................................... 11
11.5 Electrostatic Discharge Caution ............................ 21
7.3 Feature Description................................................. 11
11.6 Glossary ................................................................ 21
7.4 Device Functional Modes........................................ 12
8 Application and Implementation ........................ 13 12 Mechanical, Packaging, and Orderable
Information ........................................................... 22

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (October 2003) to Revision B Page

• Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
• Changed package references throughout document: SO-8 to SOIC-8 and DDPAK-7 to DDPAK-7/TO-263 ....................... 1
• Deleted lead temperature specifications from Absolute Maximum Ratings table ................................................................. 4
• Deleted charged-device model (CDM) specification from ESD Ratings table ...................................................................... 4

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5 Pin Configuration and Functions

OPA551, OPA552 P Package

8-Pin PDIP OPA551, OPA552 D Package
Top View 8-Pin SOIC
Top View

NC 1 8 Flag
V– 1 8 Flag
–In 2 7 V+
–In 2 7 V+
+In 3 6 Out
+In 3 6 Out
V– 4 5 NC
V– 4 5 V–

OPA551, OPA552 KTW Package

7-Pin DDPAK/TO-263 Surface-Mount
Top View

1 2 3 4 5 6 7

+In NC V+ Flag
–In V– Out
NOTE: Tab is connected to V– supply.

Pin Functions
PIN
DDPAK/ I/O DESCRIPTION
NAME SOIC PDIP
TO-263
Flag 8 8 7 O Thermal shutdown indicator
+IN 3 3 1 I Noninverting input
–IN 2 2 2 I Inverting input
NC — 1, 5 3 — No internal connection (can be left floating)
Out 6 6 6 O Output
Tab — — Tab — Connect to V– supply
V+ 7 7 5 — Positive (highest) power supply
V– 1, 4, 5 4 4 — Negative (lowest) power supply

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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply, VS = (V+) to (V–) 60 V
Input voltage range, VIN (V–) – 0.5 (V+) + 0.5 V
Output See SOA Curve (Safe Operating Area)
Operating temperature, TA –55 125 °C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±3000 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VS Supply voltage 8 (±4) 60 (±30) V
Specified temperature –40 125 °C

6.4 Thermal Information

OPA551, OPA552
D P KTW
THERMAL METRIC (1) UNIT
(SOIC) (PDIP) (DDPAK/TO-263)
8 PINS 8 PINS 7 PINS
RθJA Junction-to-ambient thermal resistance 96.7 44.1 22.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 38.7 31.8 34.7 °C/W
RθJB Junction-to-board thermal resistance 38.2 21.4 7.7 °C/W
ψJT Junction-to-top characterization parameter 3.7 9.1 3.3 °C/W
ψJB Junction-to-board characterization parameter 37.5 21.2 7.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — 0.6 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics: VS = ±30 V

At TJ = 25°C (1), RL = 3 kΩ connected to ground, and VOUT = 0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VCM = 0 V, IO = 0 mA ±1 ±3
VOS Input offset voltage mV
TJ = –40°C to 125°C ±5
dVOS /dT Input offset voltage vs temperature TJ = –40°C to 125°C ±7 µV/°C
PSRR Input offset voltage vs power supply VS = ±4 V to ±30 V, VCM = 0 V 10 30 µV/V
INPUT BIAS CURRENT
IB Input bias current ±20 ±100 pA
IOS Input offset current ±3 ±100 pA
NOISE
en Input voltage noise density f = 1 kHz 14 nV/√Hz
in Current noise density f = 1 kHz 3.5 fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) + 2.5 (V+) – 2.5 V
CMRR Common-mode rejection ratio –27.5 V < VCM < +27.5 V 92 102 dB
INPUT IMPEDANCE
Differential 1013 || 2 Ω || pF
Common-mode 1013 || 6 Ω || pF
OPEN-LOOP GAIN
RL = 3 kΩ, –28 V < VO < +28 V 110 126
RL = 3 kΩ, –28 V < VO < +28 V,
AOL Open-loop voltage gain 100 dB
TJ = –40°C to 125°C
RL = 300 Ω, –27 V < VO < +27 V 120
OPA551 FREQUENCY RESPONSE
GBW Gain-bandwidth product 3 MHz
SR Slew rate G=1 ±15 V/µs
0.1% G = 1, CL = 100 pF, 10-V Step 1.3
Settling time µs
0.01% G = 1, CL = 100 pF, 10-V Step 2
f = 1 kHz, VO = 15 VRMS, RL = 3 kΩ,
0.0005%
G=3
THD+N Total harmonic distortion + noise
f = 1 kHz, VO = 15 VRMS, RL = 300 kΩ,
0.0005%
G=3
Overload recovery time VIN × Gain = VS 1 µs
OPA552 FREQUENCY RESPONSE
GBW Gain-bandwidth product 12 MHz
SR Slew rate G=5 ±24 V/µs
0.1% G = 5, CL = 100 pF, 10-V Step 2.2
Settling time µs
0.01% G = 5, CL = 100 pF, 10-V Step 3
f = 1 kHz, VO = 15 VRMS, RL = 3 kΩ,
0.0005%
G=5
THD+N Total harmonic distortion + noise
f = 1 kHz, VO = 15 VRMS, RL = 300 kΩ,
0.0005%
G=5
Overload recovery time VIN × Gain = VS 1 µs

(1) All tests are high-speed tested at 25°C ambient temperature. Effective junction temperature is 25°C unless otherwise noted.

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Electrical Characteristics: VS = ±30 V (continued)

At TJ = 25°C(1), RL = 3 kΩ connected to ground, and VOUT = 0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
IO = 200 mA (V–) + 3 (V+) – 3
IO = 200 mA
(V–) + 3.5 (V+) – 3.5
TJ = –40°C to 125°C
VOUT Voltage output V
IO = 10 mA (V–) + 2 (V+) – 2
IO = 10 mA
(V–) + 2.5 (V+) – 2.7
TJ = –40°C to 125°C
Package dependent — see Power
IO Maximum continuous current output: DC ±200 mA
Dissipation section
ISC Short-circuit current ±380 mA
CLOAD Capacitive load drive Stable operation See Figure 19
SHUTDOWN FLAG
Normal operation, sourcing 0.05 1
µA
Thermal shutdown status output Thermal shutdown, sourcing 80 120 160
Voltage compliance range V– (V+) –1.5 V
Shutdown 160
Junction temperature °C
Reset from shutdown 140
POWER SUPPLY
VS Specified voltage ±30 V
Operating voltage range ±4 ±30 V
IO = 0 mA ±7 ±8.5
IQ Quiescent current mA
TJ = –40°C to 125°C ±10
TEMPERATURE RANGE
Specified range –40 125
TJ °C
Operating range –55 125

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6.6 Typical Characteristics

At TJ = 25°C, VS = ±30 V and RL = 3 kΩ, unless otherwise noted.

140 0 140 0
OPA551 OPA552
120 –20 120 –20
Gain Gain
100 –40 100 –40

80 –60 80 –60
Phase
Gain (dB)

Gain (dB)
Phase (°)

Phase (°)
60 –80 60 Phase –80

40 –100 40 –100

20 –120 20 –120

0 –140 0 –140

–20 –160 –20 –160

–40 –180 –40 –180

1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

Figure 1. Open-Loop Gain and Phase vs Frequency Figure 2. Open-Loop Gain and Phase vs Frequency
(OPA551) (OPA552)
120 120

100 100
–PSRR
80 80
CMRR (dB)

PSRR (dB)

60 60
+PSRR
40 40

20 20

0 0
1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

Figure 3. Common-Mode Rejection Ratio vs Frequency Figure 4. Power-Supply Rejection Ratio vs Frequency
10k 0.1
VO = 15Vrms
RL = 3kΩ, 300Ω
G = 3 (OPA551)
Voltage Noise (nV/√Hz)
Current Noise (fA/√Hz)

1k G = 5 (OPA552)
0.01
THD+N (%)

in
100

0.001
10 en

1 0.0001
10 100 1k 10k 100k 1M 1 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

Figure 5. Input Voltage and Current Noise Spectral Density Figure 6. Total Harmonic Distortion + Noise vs Frequency
vs Frequency

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Typical Characteristics (continued)

At TJ = 25°C, VS = ±30 V and RL = 3 kΩ, unless otherwise noted.
±30 (V+)

(V+)–1 +85°C
Maximum Output Voltage (V)

±25
+25°C

Output Voltage Swing (V)

(V+)–2
±20
OPA552 –55°C
(V+)–3
±15
(V–)+3
OPA551 –55°C +25°C
±10
(V–)+2

±5 Without Slew-Induced (V–)+1

Distortion +85°C
0 (V–)
1 10 100 1k 10k 100k 1M 10M 0 50 100 150 200 250 300 350 400
Frequency (Hz) Output Current (mA)

Figure 7. Maximum Output Voltage Swing vs Frequency Figure 8. Output Voltage Swing vs Output Current
130 100k
125
AOL
120 10k
115
Current (pA)

110
Gain (dB)

1k
PSRR
105 +IB
100 CMRR 100
95
–IB
90 10
85
–IOS
80 1
–75 –25 25 75 125 –75 –50 –25 0 25 50 75 100 125
Ambient Temperature (°C) Ambient Temperature ( °C)

Figure 9. Open-Loop Gain, Power-Supply Rejection Ratio, Figure 10. Input Bias Current and Input Offset Current
and Common-Mode Rejection Ratio vs Temperature vs Temperature
9 450 100
8 430
Gain Bandwidth Product (MHz)

7 IQ 410

6 390
–ISC
ISC (mA)
IQ (mA)

5 370 OPA552
+ISC 10
4 350

3 330
OPA551
2 310

1 290

0 270 1
–75 –50 –25 0 25 50 75 100 125 150 –80 –60 –40 –20 0 20 40 60 80 100 120 140
Temperature (° C) Temperature ( °C)

Figure 11. Quiescent Current and Short-Circuit Current Figure 12. Gain Bandwidth Product vs Temperature
vs Temperature

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Typical Characteristics (continued)

At TJ = 25°C, VS = ±30 V and RL = 3 kΩ, unless otherwise noted.
35 30

30 25
+IB
25 20
Slew Rate (V/µs)

OPA552 –IB

Current (pA)
20 15
OPA551
15 10

10 5

5 0 IOS

0 –5
–60 –40 –20 0 20 40 60 80 100 120 140 –30 –20 –10 0 10 20 30
Junction Temperature (° C) Common-Mode Voltage (V)

Figure 13. Slew Rate vs Temperature Figure 14. Input Bias Current and Input Offset Current
vs Common-Mode Voltage
7.6 405 18
Typical production
distribution of
15
Short-Circuit Current (mA)

packaged units.
Quiescent Current (mA)

–ISC
Percent of Amplifiers (%)
7.2 395
IQ 12

6.8 385
9

6
6.4 +ISC 375

3
6.0 365
0 5 10 15 20 25 30 35 0
Supply Voltage (V)
< –3.0

< –2.4

< –1.8

< –1.2

< –0.6

< 0.0

< 0.6

< 1.2

< 1.8

< 2.4

< 3.0
Offset Voltage (mV)
Figure 15. Quiescent Current and Short-Circuit Current Figure 16. Offset Voltage Production Distribution
vs Supply Voltage
18 100
Typical production
16 distribution of OPA551
14 packaged units. 0.01%
Percent of Amplifiers (%)

Settling Time (µs)

12 OPA551
10 0.1%

8 10

6 OPA552
0.01%
4
OPA552
2 0.1%

0
1
< 0.0

< 1.5

< 3.0

< 4.50

< 6.0

< 7.5

< 9.0

< 10.5

< 12.0

< 13.5

< 15.0

1 10 100
Gain (V/V)
Offset Drift µV/°C

Figure 17. Offset Voltage Drift Production Distribution Figure 18. Settling Time vs Closed-Loop Gain

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Typical Characteristics (continued)

At TJ = 25°C, VS = ±30 V and RL = 3 kΩ, unless otherwise noted.
60
OPA551, G = 1 OPA551
OPA552
50 G = –4

OPA551
40 G = –1
Overshoot (%)

OPA552

5V/div
30 G = –6

20

OPA551
10 G = –2
OPA552, G = –8
0
0.01 0.1 1 10 Time (1µs/div)
Load Capacitance (nF) G = 1, CL = 100 pF

Figure 19. Small-Signal Overshoot Figure 20. Large-Signal Step Response

vs Load Capacitance OPA551

OPA552 OPA551

25mV/div
5V/div

Time (1µs/div) Time (1µs/div)

G = 1, CL = 100 pF G = 1, CL = 100 pF

Figure 21. Large-Signal Step Response Figure 22. Small-Signal Step Response
OPA552 OPA551

OPA552 OPA551
100mV/div

5V/div

Time (1µs/div) Time (1µs/div)

G = 1, CL = 100 pF G = 1, CL = 1000 pF

Figure 23. Small-Signal Step Response Figure 24. Small-Signal Step Response
OPA552 OPA551

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7 Detailed Description

7.1 Overview
The OPA55x devices are low-cost, laser-trimmed, operational amplifiers that feature outstanding low-level
accuracy coupled with high output swing. High device performance is maintained as these amplifiers swing to the
specified device limits in a wide range of applications. The OPA551 is unity-gain stable while the OPA552 is
optimized for gains of 5 or greater.

7.2 Functional Block Diagram

V+

V-IN

Differential Voltage High Current

VO
Amplifier Amplifier Output Stage

Thermal
V+IN Shutdown and
Flag Output

V-

Flag

7.3 Feature Description

7.3.1 Thermal Shutdown
Internal thermal shutdown circuitry shuts down the output when the die temperature reaches approximately
160°C and resets when the die has cooled to 140°C. The flag pin can be monitored to determine if shutdown has
occurred. During normal operation, the current source from the flag pin is less than 50 nA. During shutdown, the
flag pin sources 120 µA (typical).

7.3.2 Current Limit

The OPA55x devices are designed with internal current-limiting circuitry that limits the output current to
approximately 380 mA. The current limit varies with increasing junction temperature as shown in (Figure 11).
This feature, in combination with the thermal protection circuitry, provides protection from many types of overload
conditions, including short-circuit to ground.

7.3.3 Input Protection

The OPA55x features internal clamp diodes to protect the inputs when voltages beyond the supply rails are
encountered. However, input current must be limited to 5 mA. In some cases, an external series resistor may be
required. Many input signals are inherently current-limited; therefore, a limiting resistor may not be required.
Consider that a large series resistor, in conjunction with the input capacitance, can affect stability.

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Feature Description (continued)

7.3.4 Thermal Protection
The OPA55x has thermal shutdown circuitry that protects the amplifier from damage caused by overload
conditions. The thermal protection circuitry disables the output when the junction temperature reaches
approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C,
the output circuitry is automatically re-enabled.
The thermal shutdown function is not intended to replace proper heat sinking. Activation of the thermal shutdown
circuitry is an indication of excessive power dissipation or an inadequate heat sink. Continuously running the
amplifier into thermal shutdown can degrade reliability.
The thermal shutdown indicator (flag) pin can be monitored to determine if shutdown is occurring. During normal
operation, the current output from the flag pin is typically 50 nA. During shutdown, the current output from the
flag pin increases to 120 μA (typical). This current output allows for easy interfacing to external logic. Refer to
Figure 25 and Figure 26 for two examples that implement this function.

OPA551 VOUT

Flag
80 µA to +5V
160 µA

HCT
27kΩ

Logic
Ground
HCT logic has relatively well-controlled logic level. A properly chosen resistor value can ensure proper logic high level
throughout the full range of flag output current.

Figure 25. Interfacing With HCT Logic

OPA551 VOUT

VLOGIC

HP5082-2835

CMOS
47kΩ

Logic
Ground
Interface to virtually any CMOS logic gate by choosing resistor value that provides a guaranteed logic high voltage
with the minimum (80 µA) flag current. A diode clamp to the logic supply voltage assures that the CMOS is not
damaged by overdrive.

Figure 26. Interfacing With CMOS Logic

7.4 Device Functional Modes

The OPA551 and OPA552 have a single functional mode. The device is operational when the power supply is
above 8 V and the junction temperature is below 160°C.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

Figure 27 shows the OPA551 connected as a basic noninverting amplifier. The OPA551 can be used in virtually
any operational amplifier configuration. The OPA552 is designed for use in configurations with gains of 5 or
greater. Power-supply terminals must be bypassed with 0.1-µF capacitors, or greater, near the power-supply
pins. Be sure that the capacitors are appropriately rated for the power-supply voltage used. The OPA55x can
supply output currents up to 200 mA with excellent performance.

8.2 Typical Application

V+
10µF
R2
G = 1+
+ R1
0.1µF

R1 R2

OPA551 VO

VIN ZL
Flag

(optional)

0.1µF

10µF
+

V–
Figure 27. Basic Circuit Connections

8.2.1 Design Requirements

• Operate from power supplies between ±15 V to ±30 V
• Drive passive and reactive loads up to 1 A
• Drive large capacitive loads
• Operate up to 125°C

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Typical Application (continued)

8.2.2 Detailed Design Procedure

8.2.2.1 Capacitive Loads

The dynamic characteristics of the OPA55x have been optimized for commonly-encountered gains, loads, and
operating conditions. The combination of low closed-loop gain and capacitive load decreases the phase margin
and may lead to gain peaking or oscillations. Figure 28 shows a circuit that preserves phase margin with a 10-nF
capacitive load. Figure 33 shows the small-signal step response for the circuit in Figure 28. Consult SBOA015 for
more information.
+30V

OPA551

RG RF 10nF
4kΩ 4kΩ
VI
CS CF
1.8nF 220pF

–30V

Figure 28. Driving Large Capacitive Loads

8.2.2.2 Increasing Output Current

In those applications where the 200 mA of output current is not sufficient to drive the desired load, output current
can increase by connecting two or more OPA551s or OPA552s in parallel, as shown in Figure 29. Amplifier A1 is
the master amplifier and may be configured in virtually an operational amplifier circuit. Amplifier A2, the slave, is
configured as a unity-gain buffer. Alternatively, external output transistors can be used to boost output current.
The circuit in Figure 30 is capable of supplying output currents up to 1 A. Alternatively, consider the OPA547,
OPA548, and OPA549 series power operational amplifiers for high output current drive, along with programmable
current limit and output disable capability.
R1 R2

“MASTER” RS(1)
10Ω
OPA551
VIN

RS(1)
10Ω
OPA551

“SLAVE” RL

NOTE: (1) RS resistors minimize the circulating

current that can flow between the two devices
due to VOS errors.

Figure 29. Parallel Amplifiers Increase Output Current Capability

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Typical Application (continued)

R1 R2

+30V

TIP29C
CF
R4
0.2Ω
R3(1)
100Ω
OPA551 VO
VIN
R4
0.2Ω
LOAD
TIP30C

–30V
NOTE: (1) R3 provides current limit and allows the amplifier to
drive the load when the output is between 0.7V and –0.7V.

Figure 30. External Output Transistors Boost Output Current Up to 1 A

8.2.2.3 Using the OPA552 in Low Gains

The OPA552 family is intended for applications with signal gains of 5 or greater, but it is possible to take
advantage of the high slew rate in lower gains using an external compensation technique in an inverting
configuration. This technique maintains low-noise characteristics of the OPA552 architecture at low frequencies.
Depending on the application, a small increase in high-frequency noise may result. This technique shapes the
loop gain for good stability while giving an easily-controlled, second-order, lowpass frequency response.
Considering only the noise gain (noninverting signal gain) for the circuit of Figure 31, the low-frequency noise
gain (NG1) is set by the resistor ratios, while the high-frequency noise gain (NG2) is set by the capacitor ratios.
The capacitor values set both the transition frequencies and the high-frequency noise gain. If this noise gain,
determined by NG2 = 1 + CS / CF, is set to a value greater than the recommended minimum stable gain for the
operational amplifier and the noise gain pole, set by 1 / RFCF, is placed correctly, a very well-controlled, second-
order, lowpass frequency response is the result.
To choose the values for both CS and CF, two parameters and only three equations must be solved. First, the
target for the high-frequency noise gain (NG2) must be greater than the minimum stable gain for the OPA552. In
the circuit shown in Figure 31, a target NG2 of 10 is used. Second, the signal gain of –1 shown in Figure 31 sets
the low frequency noise gain to NG1 = 1 + RF / RG (= 2 in this example). Using these two gains, knowing the gain
bandwidth product (GBP) for the OPA552 (12 MHz), and targeting a maximally flat, second-order, lowpass
Butterworth frequency response (Q = 0.707), the key frequency in the compensation can be found.
For the values shown in Figure 31, the f–3dB is approximately 956 kHz. This frequency is less than that predicted
by simply dividing the GBP by NG1. The compensation network controls the bandwidth to a lower value while
providing the full slew rate at the output and an exceptional distortion performance as a result of increased loop
gain at frequencies below NG1 × Z0. The capacitor values shown in Figure 31 are calculated for NG1 = 2 and
NG2 = 10 with no adjustment for parasitics.
Optimize the actual circuit values by checking the small-signal step response with actual load conditions.
Figure 32 shows the small-signal step response of this OPA552, G = –1 circuit with a 500-pF load. It is well-
behaved with no tendency to oscillate. If CS and CF are removed, the circuit becomes unstable.
SPACER

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Typical Application (continued)

+30V
OPA552

OPA552 VOUT

20mV/div
RG RF
1kΩ 1kΩ
VIN
CS CF
1.88nF 208pF

–30V
Time (1µs/div)

NG1 = 1 + RF/RG = 2
NG2 = 1 + CS/CF = 10

Figure 31. Compensation of the OPA552 for G = 1 Figure 32. Small-Signal Step Response for
Figure 31

8.2.2.4 Offset Voltage Error Calculation

The offset voltage (VOS) of the OPA51 and OPA552 is specified with a ±30-V power supply and the common-
mode voltage centered between the supplies (VS / 2 = 0 V). Additional specifications for power-supply rejection
and common-mode rejection are provided to allow the user to easily calculate worst-case excepted offset under
the conditions of a given application.
Power-supply rejection ratio (PSRR) is specified in µV/V. For the OPA55x, worst-case PSRR is 30 µV/V, which
means for each volt of change in total power-supply voltage, the offset may shift by up to 30 µV/V. Common-
mode rejection ratio (CMRR) is specified in dB, which can be converted to µV/V using Equation 1:
CMRR in (V/V) = 10[(CMRR in dB)/–20] (1)
For the OPA55x, the worst-case CMRR at ±30-mV supply over the full common-mode range is 96 dB, or
approximately 15.8 µV/V. This result means that for every volt of change in common-mode, the offset may shift
up to 15.8 µV. These numbers can be used to calculate excursions from the specified offset voltage under
different applications conditions. For example, a common application might configure the amplifier with a –48-V
single supply with –6-V common-mode. This configuration represents a 12-V variation in power supply: ±30 V or
60 V in the offset specification versus 48 V in the application. In addition, this configuration has an 18-V variation
in common-mode voltage: VS / 2 = –24 V is the specification for these power supplies, but the common-mode
voltage is –6 V in the application.
Calculation of the worst-case expected offset for this example is calculated by Equation 2 and Equation 3.
Worst-case VOS = maximum specified VOS + (power-supply variation × PSRR) + (common-mode variation × CMRR) (2)
VOSwc = 5 mV + (12 V × 30 µV/V) + (18 V × 15.8 µV/V) = ±5.64 mV (3)

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Typical Application (continued)

8.2.3 Application Curve
Figure 33 shows the small-signal step response for the circuit in Figure 28. Consult AB-028 for more information.

OPA551

20mV/div

Time (2.5µs/div)

Figure 33. Small-Signal Step Response for Driving Large Capacitive Loads

9 Power Supply Recommendations

9.1 Power Supplies

The OPA55x may be operated from power supplies of ±4 V to ±30 V, or a total of 60 V with excellent
performance. Most behavior remains unchanged throughout the full operating voltage range. Parameters that
vary significantly with operating voltage are shown in the Typical Characteristics.
For applications that do not require symmetrical output voltage swing, power-supply voltages do not need to be
equal. The OPA55x can operate with as little as 8 V between the supplies or with up to 60 V between the
supplies. For example, the positive supply could be set to 50 V with the negative supply at –10 V, or vice-versa.
The SOIC-8 package outline shows three negative supply (V–) pins. These pins are internally connected for
improved thermal performance.

NOTE
Pin 4 must be used as the primary current carrier for the negative supply. It is
recommended that pins 1 and 5 are not directly connected to V–. Instead, connect pins 1
and 5 to a thermal mass. DO NOT lay out the printed-circuit-board (PCB) to use pins 1
and 5 as feedthroughs to the negative supply. Such a configuration results in a
performance reduction.

The tab of the DDPAK/TO-263 package is electrically connected to the negative supply (V–). However, this
connection must not be used to carry current. For best thermal performance, solder the tab directly to the PCB
copper area (see the Heat Sinking section).

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10 Layout

10.1 Layout Guidelines

The circuit board must have as much ground plane area as possible. Power supply and output traces must be
sized to handle the required current. Keep input and output terminals separated as much as possible.

10.2 Layout Example

PDIP-8 and
SOIC-8 DDPAK-7
Flag
Gain Resistor Gain Resistor V- V+
0.01 µF
GND Grey area is bypass
ground layer 0.1 µF
- bypasses
VIN V+ Output
VIN VOUT Flag
+ R1 R2
Bypass VIN
Capacitor
V-

Figure 34. Layout Example (OPA551)

10.3 Power Dissipation

Internal power dissipation of these operational amplifiers can be quite large. Many of the specifications for the
OPA55x are for a specified junction temperature. If the device is not subjected to internal self-heating, the
junction temperature is the same as the ambient. However, in practical applications, the device self-heats and
the junction temperature becomes significantly higher than ambient. After junction temperature has been
established, performance parameters that vary with junction temperature can be determined from the
performance curves. The following calculation can be performed to establish junction temperature as a function
of ambient temperature and the conditions of the application.
Consider the OPA551 in a circuit configuration where the load is 600 Ω and the output voltage is 15 V. The
supplies are at ±30 V and the ambient temperature (TA) is 40°C. The θJA for the 8-pin PDIP package is 100°C/W.
First, the internal heating of the operational amplifier is in Equation 4:
PD(internal) = IQ × VS = 7.2 mA × 60 V = 432 mW (4)
The output current (IO) can be calculated in Equation 5:
IO = VOUT/RL = 15 V/600 Ω = 25 mA (5)
The power being dissipated (PD) in the output transistor of the amplifier can be calculated in Equation 6 and
Equation 7:
PD(output stage) = IO× (VS –– VO) = 25 mA × (30 – 15) = 375 mW (6)
PD(total) = PD(internal) + PD(output stage) = 432 mW + 375 mW = 807 mW (7)
The resulting junction temperature can be calculated in Equation 8 and Equation 9:
TJ = TA + PD θJA (8)
TJ = 40°C + 807 mW × 100°C/W = 120.7°C
where
• TJ = junction temperature (°C)
• TA = ambient temperature (°C)
• θJA = junction-to-air thermal resistance (°C/W) (9)
For the DDPAK/TO-263 package, the θJA is 65°C/W with no heat sinking, resulting in a junction temperature of
92.5°C.

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Power Dissipation (continued)

To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature
until the thermal protection is activated. Use worst-case load and signal conditions. For good reliability, the
thermal protection must trigger more than 35°C above the maximum expected ambient condition of a given
application. This limit ensures a maximum junction temperature of 125°C at the maximum expected ambient
condition.
If the OPA551 or OPA552 is to be used in an application requiring more than 0.5-W continuous power
dissipation, TI recommends that the DDPAK/TO-263 package option be used. The DDPAK/TO-263 has superior
thermal dissipation characteristics and is more easily adapted to a heatsink.
Operation from a single power supply (or unbalanced power supplies) can produce even larger power dissipation
because a larger voltage can be impressed across the conducting output transistor. Consult SBOA022 for further
information on how to calculate or measure power dissipation.
Power dissipation can be minimized by using the lowest possible supply voltage. For example, with a 200-mA
load, the output swings to within 3.5 V of the power-supply rails. Set the power supplies to no more than 3.5 V
above the maximum output voltage swing required by the application to minimize the power dissipation.

10.4 Safe Operating Area

The Safe Operating Area (SOA) curves Figure 35, Figure 36, and Figure 37 show the permissible range of
voltage and current. These curves shown represent devices soldered to a circuit board with no heatsink. The
safe output current decreases as the voltage across the output transistor (VS – VO) increases. For further insight
on SOA, consult AB-039.
Output short circuits are a very demanding case for SOA. A short-circuit to ground forces the full power-supply
voltage (V+ or V–) across the conducting transistor and produces a typical output current of 380 mA. With ±30-V
power supplies, this configuration creates an internal dissipation of 11.4 W. This dissipation far exceeds the
maximum rating and is not recommended. If operation in this region is unavoidable, use the DDPAK/TO-263
package with a heatsink.
1000 1000

25°C 25°C
100 100

125°C 125°C
IO (mA)

IO (mA)

10 10
85°C 85°C

1 1

0.1 0.1
1 10 100 1 10 100
| VS | – | VO | (V) | VS | – | VO | (V)

Figure 35. PDIP-8 Safe Operating Area Figure 36. SOIC-8 Safe Operating Area

1000
25°C 25°C
1" Copper
100

125°C
IO (mA)

10 125°C
1" Copper 85°C

0.1
1 10 100
| VS | – | VO | (V)

Figure 37. DDPAK-7/TO-263 Safe Operating Area

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10.5 Heat Sinking

Power dissipated in the OPA551 or OPA552 causes the junction temperature to rise. For reliable operation, limit
the junction temperature to 125°C. Many applications require a heatsink to assure that the maximum operating
junction temperature is not exceeded. The heatsink required depends on the power dissipated and on ambient
conditions.
For heatsinking purposes, the tab of the DDPAK/TO-263 is typically soldered directly to the PCB copper area.
Increasing the copper area improves heat dissipation. Figure 38 shows typical thermal resistance from junction-
to-ambient as a function of copper area.
Depending on conditions, additional heatsinking may be required. Aavid Thermal Products Inc. manufactures
surface-mountable heatsinks designed specifically for use with DDPAK/TO-263 packages. Further information is
available on the Aavid web site, www.aavid.com.
To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature
until the thermal protection is activated. Use worst-case load and signal conditions. For good reliability, the
thermal protection must trigger more than 25°C above the maximum expected ambient condition of your
application. This level produces a junction temperature of 125°C at the maximum expected ambient condition.
50
Thermal Resistance, θJA (°C/W)

OPA551, OPA552
40 Surface-Mount Package
1oz. copper

30

20

10

0
0 1 2 3 4 5
Copper Area (inches 2)

Figure 38. Thermal Resistance vs Circuit Board Copper Area

Circuit Board Copper Area

Figure 39. OPA551, OPA552 Surface-Mount Package Circuit Board Copper Area

20 Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated

Product Folder Links: OPA551 OPA552

 OPA551, OPA552
www.ti.com SBOS100B – JULY 1999 – REVISED JANUARY 2016

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support

11.2.1 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.

Table 1. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
OPA551 Click here Click here Click here Click here Click here
OPA552 Click here Click here Click here Click here Click here

11.2.2 Related Documentation

For related documentation, please see the following:
• Heat Sinking — TO-3 Thermal Mode (SBOA021)
• Application bulletin AB-028: Feedback Plots Define Op Amp AC Performance (SBOA015)
• Application bulletin AB-039: Power Amplifier Stress and Power Handling Limitations (SBOA022)

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

Copyright © 1999–2016, Texas Instruments Incorporated Submit Documentation Feedback 21

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OPA551, OPA552
SBOS100B – JULY 1999 – REVISED JANUARY 2016 www.ti.com

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

(1) For improved thermal performance, increase footprint area.

(2) Mean dimensions in inches. Refer to the mechanical drawings or www.ti.com for tolerances and detailed package
drawings.

Figure 40. TO-220 and DDPAK Solder Footprints

22 Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated

Product Folder Links: OPA551 OPA552

 PACKAGE OPTION ADDENDUM

www.ti.com 29-Jun-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA551FA/500 ACTIVE DDPAK/ KTW 7 500 RoHS & Green Call TI | SN Level-2-260C-1 YEAR -40 to 125 OPA551FA Samples
TO-263
OPA551FA/500G3 ACTIVE DDPAK/ KTW 7 500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 OPA551FA Samples
TO-263
OPA551FAKTWT ACTIVE DDPAK/ KTW 7 250 RoHS & Green Call TI | SN Level-2-260C-1 YEAR -40 to 125 OPA551FA Samples
TO-263
OPA551FAKTWTG3 ACTIVE DDPAK/ KTW 7 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 OPA551FA Samples
TO-263
OPA551PA ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 OPA551PA Samples

OPA551PAG4 LIFEBUY PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 OPA551PA
OPA551UA ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 OPA Samples
551UA
OPA551UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 OPA Samples
551UA
OPA551UAE4 LIFEBUY SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 OPA
551UA
OPA552FA/500 ACTIVE DDPAK/ KTW 7 500 RoHS & Green Call TI | SN Level-2-260C-1 YEAR -40 to 125 OPA552FA Samples
TO-263
OPA552FAKTWT ACTIVE DDPAK/ KTW 7 250 RoHS & Green Call TI | SN Level-2-260C-1 YEAR OPA552FA Samples
TO-263
OPA552FAKTWTG3 LIFEBUY DDPAK/ KTW 7 250 RoHS & Green SN Level-2-260C-1 YEAR OPA552FA
TO-263
OPA552UA ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR OPA Samples
552UA
OPA552UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR OPA Samples
552UA

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 29-Jun-2023

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Dec-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA551UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA552UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Dec-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA551UA/2K5 SOIC D 8 2500 356.0 356.0 35.0
OPA552UA/2K5 SOIC D 8 2500 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 2-Dec-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
OPA551PA P PDIP 8 50 506 13.97 11230 4.32
OPA551PAG4 P PDIP 8 50 506 13.97 11230 4.32
OPA551UA D SOIC 8 75 506.6 8 3940 4.32
OPA551UAE4 D SOIC 8 75 506.6 8 3940 4.32
OPA552UA D SOIC 8 75 506.6 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 MECHANICAL DATA

MPSF015 – AUGUST 2001

KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT

0.410 (10,41) 0.304 (7,72)

–A–
0.385 (9,78) 0.006 0.296 (7,52)
–B–
0.303 (7,70) 0.300 (7,62)
0.0625 (1,587) H 0.297 (7,54) 0.055 (1,40) 0.252 (6,40)
0.064 (1,63)
0.0585 (1,485) 0.045 (1,14)
0.056 (1,42)

0.370 (9,40) 0.187 (4,75)

0.330 (8,38) 0.179 (4,55)
H A
0.605 (15,37)
0.595 (15,11)
0.012 (0,305)
C 0.000 (0,00)
0.104 (2,64)
0.019 (0,48) 0.096 (2,44) H
0.017 (0,43)

0.050 (1,27) 0.026 (0,66)

C
0.034 (0,86) 0.014 (0,36)
0°~3°
C F 0.022 (0,57)
0.010 (0,25) M B AM C M

0.183 (4,65)
0.170 (4,32)

4201284/A 08/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Lead width and height dimensions apply to the
plated lead.
D. Leads are not allowed above the Datum B.
E. Stand–off height is measured from lead tip
with reference to Datum B.
F. Lead width dimension does not include dambar
protrusion. Allowable dambar protrusion shall not
cause the lead width to exceed the maximum
dimension by more than 0.003”.
G. Cross–hatch indicates exposed metal surface.
H. Falls within JEDEC MO–169 with the exception
of the dimensions indicated.

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