1.
Define the terms setup time, hold time and clock to output time of a flip flop and what are
the constraints imposed by these parameters on the circuit operations.
2. Develop verilog module for 7 segment decoder. Include an additional input „blank‟ that
overrides the BCD input and causes all segments not to be lit.
3. Explain functional verification and formal verification for a verilog module
4. What are the effects of capacitive loading and propagation delay on signal transitions
between logic levels?
5. Develop verilog module for 4:1 MUX.
6. Explain general view of digital system with data path & control section.
7. Explain with illustration, a simple design methodology followed in IC industries.
8. Explain the following constraints imposed in real world circuits:
(i) Noise margin (ii) Propagation delay (iii) Static Levels
(iv) Static and dynamic power consumption.
9. Develop a verilog module of a debouncer for a push button switvh that uses a debounce
interval of 10ns. Assume the system clock frequency is 50 MHz.
10. Design and develop a circuit and verilog module for modulo 10 counters.
11. What is the distinction between a Moore and Mealy finite state machine?
12. What are the two sources of power consumption in digital components? Explain.
13. Design an encoder for the burglar alarm that has sensors for each of the 8 zones as a
priority encoder with zone 1 having highest priority down to zone 8 having lowest
priority.
14. Develop a datapath to perform complex multiplication of two complex number whose
real and imaginary parts are represented as signed fixed point numbers with 4-pre binary
points and 12 post binary points. Real and imaginary parts of the product are represented
with 8 pre-binary points and 24 post-binary points. Area is the main constraint. Also,
write the verilog model of the complex multiplier datapath.
15. Write a logic circuit and Verilog model for a Vat Buzzer circuit in a factory. The factory
has two vats, only one of which is used at a time . The liquid in the vat in use needs to be
at the right temperature , between 25 ̊C and 30 ̊C. Each vat has two temperature sensors
indicating whether the temperature is above 25 ̊C and above 30 ̊C, respectively. The vats
also have low level sensors. The supervisor needs to be woken up by a buzzer when the
temperature is too high or too low or the vat level is too low. He has a switch to select
which vat is in use.
16. Write a Verilog model for an encoder for use in a domestic burglar alarm that has sensors
for each of eight zones. Each sensor signal is 1 when an intrusion is detected in that zone,
and 0 otherwise. The encoder has three bits of output, encoding the zone as follows: Zone
1: 000, Zone 2: 001, Zone 3: 010, Zone 4: 011, Zone 5: 100, Zone 6: 101, Zone 7: 110 &
Zone 8: 111.
17. Explain the concept of verification of combinational circuits with suitable example.
18. Explain the constraints of clocked synchronous timing methodology with suitable
diagrams.
19. Write a Verilog model of complex multiplier Control Section FSM.
20. Describe the embedded system design methodology.
21. Describe the concept of Logic Levels and Noise Margin in Digital Circuits.
