Si4720/21-B20

B R O A D C A S T FM R A DI O T R A N S C E I V E R F O R P O R TA B L E A P P L I C A T I O N S

Features
 Full FM RX and TX in 3 x 3 QFN  Adjustable seek parameters
 Worldwide FM RX band support  Adjustable mono/stereo blend
 Compliant with worldwide FM TX  Adjustable soft mute
regulations
 Advanced modulation control
 Excellent real-world performance
 Supports integrated TX/RX  Audio dynamic range control
antenna  Audio silence detector
Ordering Information:
 Programmable transmit output  Programmable reference clock
voltage See page 42.
input
 Frequency synthesizer with  2-wire and 3-wire control
integrated VCO interface Pin Assignments
 Integrated LDO regulator  2.7 to 5.5 V supply voltage
Si4720/21
 Minimal BOM (15 mm2)  3 x 3 x 0.55 mm 20-pin Pb-free
(Top View)
 Digital audio output QFN package
(Si4721 only)  RDS/RDBS encoder/decoder
 Digital audio input (Si4721 only)

GPO3/DCLK
GPO2/INT

LIN/DFS
Applications

GPO1
NC
 Cellular handsets/hands-free  Wireless speakers/microphone 20 19 18 17
NC 1 16
 MP3 players  Satellite digital audio radios
FMI 2 15 RIN/DOUT
 Portable media players  Personal computers/notebooks
RFGND 3 GND 14 LOUT/DFS
Description TXO 4 PAD 13 ROUT/DIN
RST 5 12 GND
The Si4720/21 integrates the complete tuner and transmit functions for
6 7 8 9 10 11 VDD
FM broadcast reception and standards-compliant, unlicensed FM
SEN

SCLK

RCLK

VIO
SDIO

broadcast stereo transmission. Users must comply with local radio

frequency (RF) transmission regulations.
Functional Block Diagram Patents pending
Notes:
Si4720/21 1. To ensure proper operation and FM
Tx/Rx Ant transceiver performance, follow the
TXO LIN/DFS
guidelines in “AN383: 3 mm x 3 mm
L1
120 nH
QFN Universal Layout Guide.”
RIN/DOUT
Silicon Laboratories will evaluate
Rx Ant* ADC DAC ROUT/DIN schematics and layouts for qualified
FMI
LNA customers.
MUX

PGA DSP
RFGND
ADC DAC
2. Place the Si4720/21 as close as
LOUT/DFS
AGC
possible to the antenna jack, and
2.7–5.5 V VDD
keep the FMI trace as short as
CONTROL
C1 GND LDO AFC GPO
INTERFACE
possible.
22 uF
GPO3/DCLK
GPO2/INT
RCLK

GPO1

SEN
SCLK
SDIO
RST
VIO

*Note: Dedicated Rx antenna is optional

Rev. 1.0 2/08 Copyright © 2008 by Silicon Laboratories Si4720/21-B20

.
Si4720/21-B20

2 Rev. 1.0
 Si4720/21-B20

TABLE O F C ONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1. Test Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2. Test Circuit Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1. Analog Audio Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2. Typical Application Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3. Digital Audio Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4. Typical Application Schematic Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4. Universal AM/FM RX/FM TX Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.1. Universal AM/FM RX/FM TX Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2. Application Schematics and Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.4. Integrated Antenna Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.5. Receiver Digital Audio Interface (Si4721 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.6. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.7. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.8. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.9. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.10. RDS/RBDS Processor (Si4721 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.11. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.12. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.13. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.14. FM Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.15. Receive Power Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.16. Transmitter Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.17. Line Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.18. Audio Dynamic Range Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.19. Audio Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.20. Pre-emphasis and De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.21. RDS/RBDS Processor (Si4721 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.22. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.23. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.24. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.25. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.26. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.27. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7. Pin Descriptions: Si4720/21-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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Si4720/21-B20
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.1. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2. Si4720/21 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.3. Si4721 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10. Package Outline: Si4720/21-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11. PCB Land Pattern: Si4720/21-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
12. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

4 Rev. 1.0
 Si4720/21-B20
1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit
Supply Voltage VDD 2.7 — 5.5 V
Interface Supply Voltage VIO 1.5 — 3.6 V
Power Supply Power-Up Rise Time VDDRISE 10 — — µs
Interface Power Supply Power-Up Rise Time VIORISE 10 — — µs
Ambient Temperature TA –20 25 85 C
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless
otherwise stated.

Table 2. Absolute Maximum Ratings1,2

Parameter Symbol Value Unit
Supply Voltage VDD –0.5 to 5.8 V
Interface Supply Voltage VIO –0.5 to 3.9 V
Input Current3 IIN 10 mA
3
Input Voltage VIN –0.3 to (VIO + 0.3) V
Operating Temperature TOP –40 to 95 C
Storage Temperature TSTG –55 to 150 C
RF Input Level4 0.4 VPK
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended
operating conditions for extended periods may affect device reliability.
2. The Si4720/21 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2/INT, and GPO3.
4. At RF input pin FMI.

Rev. 1.0 5
Si4720/21-B20

Table 3. DC Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
FM Receiver
RX Supply Current IRX — 19.2 22 mA
1
RX Supply Current IRX Low SNR level — 19.8 23 mA
RX Interface Supply Current IIORX — 320 600 µA
2
RX RDS Supply Current IFM Analog Output Mode — 19.9 23 mA
RX Supply Current2 IFMD Digital Output Mode — 18.0 20.5 mA
FM Transmitter
TX Supply Current ITX — 18.8 22.8 mA
TX Interface Supply Current IIOTX — 320 600 µA
FM Transmitter from Digital Audio Input
TX Supply Current IDTX DCLK = 3.072 MHz — 18.3 — mA
TX Interface Supply Current IDIO DCLK = 3.072 MHz — 320 — µA
FM Transmitter in Receive Power Scan Mode
RX Supply Current IRX — 16.8 — mA
RX Interface Supply Current IIORPS — 400 — µA
Supplies and Interface
VDD Powerdown Current IDDPD Powerdown mode — 10 20 µA
VIO Powerdown Current IIOPD SCLK, RCLK inactive — 3 10 µA
Powerdown mode
High Level Input Voltage3 VIH 0.7 x VIO — VIO + 0.3 V
3
Low Level Input Voltage VIL –0.3 — 0.3 x VIO V
High Level Input Current3 IIH VIN = VIO = 3.6 V –10 — 10 µA
Low Level Input Current3 IIL VIN = 0 V, VIO = 3.6 V –10 — 10 µA
High Level Output Voltage4 VOH IOUT = 500 µA 0.8 x VIO — — V
Low Level Output Voltage4 VOL IOUT = –500 µA — — 0.2 x VIO V
Notes:
1. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
2. Guaranteed by characterization.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2/INT, and GPO3.
4. For output pins SDIO, GPO1, GPO2/INT, and GPO3.

6 Rev. 1.0
 Si4720/21-B20

Table 4. Reset Timing Characteristics1,2,3

(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Min Typ Max Unit

RST Pulse Width and GPO1, GPO2/INT Setup to RST tSRST 100 — — µs

GPO1, GPO2/INT Hold from RST tHRST 30 — — ns

Important Notes:
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the 1st start condition.
3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs, to provide time for on-chip 1 M devices (active while RST is low) to pull GPO1 high and
GPO2 low.

tSRST tHRST

70%
RST
30%

70%
GPO1
30%

GPO2/ 70%

INT 30%

Figure 1. Reset Timing Parameters for Busmode Select

Rev. 1.0 7
Si4720/21-B20

Table 5. 2-Wire Control Interface Characteristics1,2,3

(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

SCLK Frequency fSCL 0 — 400 kHz
SCLK Low Time tLOW 1.3 — — µs
SCLK High Time tHIGH 0.6 — — µs
SCLK Input to SDIO Setup tSU:STA 0.6 — — µs
(START)
SCLK Input to SDIO Hold (START) tHD:STA 0.6 — — µs
SDIO Input to SCLK Setup tSU:DAT 100 — — ns
SDIO Input to SCLK Hold4,5 tHD:DAT 0 — 900 ns
SCLK input to SDIO Setup (STOP) tSU:STO 0.6 — — µs
STOP to START Time tBUF 1.3 — — µs
SDIO Output Fall Time tf:OUT — 250 ns
Cb
20 + 0.1 ------------
1 pF

SDIO Input, SCLK Rise/Fall Time tf:IN — 300 ns

Cb
tr:IN 20 + 0.1 ------------
1 pF

SCLK, SDIO Capacitive Loading Cb — — 50 pF

Input Filter Pulse Suppression tSP — — 50 ns
Notes:
1. When VIO = 0 V, SCLK and SDIO are low-impedance. 2-wire control interface is I2C compatible.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si4720/21 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum
tHD:DAT specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated as long as all other timing parameters are met.

8 Rev. 1.0
 Si4720/21-B20

tSU:STA tHD:STA tLOW tHIGH tr:IN tf:IN tSP tSU:STO tBUF

70%
SCLK
30%

70%
SDIO
30%

START tHD:DAT tSU:DAT tf:IN,

tr:IN STOP START
tf:OUT

Figure 2. 2-Wire Control Interface Read and Write Timing Parameters

SCLK

A6-A0,
SDIO D7-D0 D7-D0
R/W

START ADDRESS + R/W ACK DATA ACK DATA ACK STOP

Figure 3. 2-Wire Control Interface Read and Write Timing Diagram

Rev. 1.0 9
Si4720/21-B20

Table 6. 3-Wire Control Interface Characteristics

(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

SCLK Frequency fCLK 0 — 2.5 MHz
SCLK High Time tHIGH 25 — — ns
SCLK Low Time tLOW 25 — — ns
SDIO Input, SEN to SCLKSetup tS 20 — — ns
SDIO Input to SCLKHold tHSDIO 10 — — ns
SEN Input to SCLKHold tHSEN 10 — — ns
SCLKto SDIO Output Valid tCDV Read 2 — 25 ns
SCLKto SDIO Output High Z tCDZ Read 2 — 25 ns
SCLK, SEN, SDIO, Rise/Fall time tR, tF — — 10 ns
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.

70%
SCLK
30%

tR tF
tS tHSDIO tHIGH tLOW tHSEN
70%
SEN tS
30%

70% A6-A5,
SDIO A7 R/W, A0 D15 D14-D1 D0
30% A4-A1

Address In Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters

70%
SCLK
30%

tS t HSDIO tCDV tHSEN

t CDZ
70%
SEN tS
30%

70% A6-A5,
SDIO A7 R/W, A0 D15 D14-D1 D0
30% A4-A1

Address In ½ Cycle Bus Data Out

Turnaround
Figure 5. 3-Wire Control Interface Read Timing Parameters

10 Rev. 1.0
 Si4720/21-B20

Table 7. SPI Control Interface Characteristics

(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

SCLK Frequency fCLK 0 — 2.5 MHz
SCLK High Time tHIGH 25 — — ns
SCLK Low Time tLOW 25 — — ns
SDIO Input, SEN to SCLKSetup tS 15 — — ns
SDIO Input to SCLKHold tHSDIO 10 — — ns
SEN Input to SCLKHold tHSEN 5 — — ns
SCLKto SDIO Output Valid tCDV Read 2 — 25 ns
SCLKto SDIO Output High Z tCDZ Read 2 — 25 ns
SCLK, SEN, SDIO, Rise/Fall time tR, tF — — 10 ns
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.

70%
SCLK
30%

tR tF
tHIGH tLOW tHSDIO
tHSEN
70%
SEN tS
tS
30%

70%
SDIO C7 C6–C1 C0 D7 D6–D1 D0
30%

Control Byte In 8 Data Bytes In

Figure 6. SPI Control Interface Write Timing Parameters

70%
SCLK
30%

tCDV
tS
tHSDIO t HSEN
70%
SEN tS
30%
tCDZ

SDIO 70%
C7 C6–C1 C0 D7 D6–D1 D0
30%

Control Byte In Bus 16 Data Bytes Out

Turnaround (SDIO or GPO1)
Figure 7. SPI Control Interface Read Timing Parameters

Rev. 1.0 11
Si4720/21-B20

Table 8. Digital Audio Interface Characteristics (Receive)

(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

DCLK Cycle Time tDCT 26 — 1000 ns
DCLK pulse width high tDCH 10 — — ns
DCLK pulse width low tDCL 10 — — ns
DFS set-up time to DCLK rising edge tSU:DFS 5 — — ns
DFS hold time from DCLK rising edge tHD:DFS 5 — — ns
DOUT propagation delay from DCLK falling edge tPD:DOUT 0 — 12 ns

tDCH tDCL

DCLK

tDCT

DFS
tHD:DFS tSU:DFS

DOUT
tPD:OUT

Figure 8. Digital Audio Interface Timing Parameters, I2S Mode

12 Rev. 1.0
 Si4720/21-B20

Table 9. FM Receiver Characteristics1,2

(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Input Frequency fRF 76 — 108 MHz
Sensitivity with Headphone Net- (S+N)/N = 26 dB — 2.2 3.5 µV EMF
work3,4,5
Sensitivity with 50  Network3,4,5,6 (S+N)/N = 26 dB — 1.1 — µV EMF
RDS Sensitivity6 f = 2 kHz, — 15 — µV EMF
RDS BLER < 5%
TXO Receiver Mode Sensitivity6 — 3.5 — µV EMF
6,7
LNA Input Resistance 3 4 5 k
LNA Input Capacitance6,7 4 5 6 pF
Input IP36,8 100 105 — dBµV EMF
3,4,6,7 m = 0.3 40 50 — dB
AM Suppression
Adjacent Channel Selectivity ±200 kHz 35 50 — dB
Alternate Channel Selectivity ±400 kHz 60 70 — dB
Spurious Response Rejection6 In-band 35 — — dB
3,4,7 72 80 90 mVRMS
Audio Output Voltage
Audio Output L/R Imbalance3,7,9 — — 1 dB
Audio Frequency Response Low6 –3 dB — — 30 Hz
Audio Frequency Response High6 –3 dB 15 — — kHz
7,9 25 — — dB
Audio Stereo Separation
3,4,5,7,10 55 63 — dB
Audio Mono S/N
Audio Stereo S/N4,5,7,10,11 — 58 — dB
Audio THD3,7,9 — 0.1 0.5 %
De-emphasis Time Constant6 FM_DEEMPHASIS = 2 70 75 80 µs
FM_DEEMPHASIS = 1 45 50 54 µs
Audio Output Load Resistance6,10 RL Single-ended 10 — — k
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests. Tested at
RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and
Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Guaranteed by characterization.
7. VEMF = 1 mV.
8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. Refer to "7. Pin Descriptions: Si4720/21-GM" on page 41.
9. f = 75 kHz.
10. At LOUT and ROUT pins.
11. Analog audio output mode.
12. At temperature 25 °C.

Rev. 1.0 13
Si4720/21-B20
Table 9. FM Receiver Characteristics1,2 (Continued)
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Audio Output Load Capacitance6,10 CL Single-ended — — 50 pF
Seek/Tune Time6 RCLK tolerance — — 80 ms/channel
= 100 ppm
Powerup Time6 From powerdown — — 110 ms
12
RSSI Offset Input levels of 8 and –3 — 3 dB
60 dBµV at RF Input
Notes:
1. Additional testing information is available in Application Note AN388. Volume = maximum for all tests. Tested at
RF = 98.1 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Antenna Selection and
Universal Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Guaranteed by characterization.
7. VEMF = 1 mV.
8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. Refer to "7. Pin Descriptions: Si4720/21-GM" on page 41.
9. f = 75 kHz.
10. At LOUT and ROUT pins.
11. Analog audio output mode.
12. At temperature 25 °C.

14 Rev. 1.0
 Si4720/21-B20

Table 10. FM Transmitter Characteristics1

Test conditions: VRF = 118 dBµV, stereo, f = 68.25 kHz, fpilot = 6.75 kHz, REFCLK = 32.768 kHz, 75 µs pre-emphasis,
unless otherwise specified.
Production test conditions: VDD = 3.3 V, VIO = 3.3 V, TA = 25 °C, FRF = 98 MHz.
Characterization test conditions: VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
Parameters are tested in production unless otherwise specified.

Parameter Symbol Test Condition Min Typ Max Unit

Transmit Frequency Range2 fRF 76 — 108 MHz
Transmit Frequency Accuracy and –3.5 — 3.5 kHz
Stability2,3
Transmit Voltage Accuracy2 VRF = 103–117 dBµV –2.5 — 2.5 dB
Transmit Voltage Accuracy VRF = 102, 118 dBµV –2.5 — 2.5 dB
Transmit Voltage Temperature Coef- –0.075 — –0.025 dB/°C
ficient2
Transmit Channel Edge Power > ±100 kHz, — — –20 dBc
pre-emphasis off
Transmit Adjacent Channel Power > ±200 kHz, — –30 –26 dBc
pre-emphasis off
Transmit Alternate Channel Power > ±400 kHz, — –30 –26 dBc
pre-emphasis off
Transmit Emissions In-band (76–108 MHz) — — –30 dBc
2
Output Capacitance Max CTUNE — 53 — pF
Output Capacitance Min2 CTUNE — 5 — pF
Pre-emphasis Time Constant2 TX_PREMPHASIS = 75 µs 70 75 80 µs
TX_PREMPHASIS = 50 µs 45 50 54 µs
Audio SNR Mono2 f = 22.5 kHz, Mono, 58 63 — dB
limiter off
Audio SNR Stereo f = 22.5 kHz, 53 58 — dB
fpilot = 6.75 kHz, Stereo,
limiter off
Audio THD Mono f = 75 kHz, Mono, — 0.1 0.5 %
limiter off
Notes:
1. FM transmitter performance specifications are subject to adherence to Silicon Laboratories guidelines in “AN383:
Universal Antenna Selection and Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers. Tested with test schematic (L = 120 nH, Q > 30) shown in Figure 10 on page 19.
2. Guaranteed by characterization.
3. No measurable fRF/VDD at VDD of 500 mVpk-pk at 100 Hz to 10 kHz.

Rev. 1.0 15
Si4720/21-B20
Table 10. FM Transmitter Characteristics1 (Continued)
Test conditions: VRF = 118 dBµV, stereo, f = 68.25 kHz, fpilot = 6.75 kHz, REFCLK = 32.768 kHz, 75 µs pre-emphasis,
unless otherwise specified.
Production test conditions: VDD = 3.3 V, VIO = 3.3 V, TA = 25 °C, FRF = 98 MHz.
Characterization test conditions: VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
Parameters are tested in production unless otherwise specified.

Parameter Symbol Test Condition Min Typ Max Unit

Audio THD Stereo2 f = 22.5 kHz, — 0.1 0.5 %
fpilot = 6.75 kHz, Stereo,
limiter off
Audio Stereo Separation2 left channel only 30 35 — dB
Sub Carrier Rejection Ratio SCR 40 50 — dB
Powerup Settling Time2 — — 110 ms
Input Signal Level2 VAI — — 0.636 VPK
Frequency Flatness2 Mono, ±1.5 dB, 30 — 15 k Hz
f = 75 kHz, 0, 50, 75 µs
pre-emphasis, limiter off
High Pass Corner Frequency2 Mono, –3 dB, f = 75 kHz, 5 — 30 Hz
0, 50, 75 µs pre-emphasis,
limiter off
Low Pass Corner Frequency2 Mono, –3 dB, f = 75 kHz, 15 k — 16 k Hz
0, 50, 75 µs pre-emphasis,
limiter off
Audio Imbalance Mono –1 — 1 dB
Pilot Modulation Rate Accuracy 2
f = 68.25 kHz, –10 — 10 %
fpilot = 6.75 kHz, Stereo
Audio Modulation Rate Accuracy2 f = 68.25 kHz, –10 — 10 %
fpilot = 6.75 kHz, Stereo
Input Resistance2 LIATTEN[1:0] = 11 50 60 — k
2
Input Capacitance — 10 — pF
Received Noise Level Accuracy 60 dBµV input, TA = 25 ºC — 54 — dBuV
(Si4720/21 Only)2
Notes:
1. FM transmitter performance specifications are subject to adherence to Silicon Laboratories guidelines in “AN383:
Universal Antenna Selection and Layout Guidelines.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers. Tested with test schematic (L = 120 nH, Q > 30) shown in Figure 10 on page 19.
2. Guaranteed by characterization.
3. No measurable fRF/VDD at VDD of 500 mVpk-pk at 100 Hz to 10 kHz.

16 Rev. 1.0
 Si4720/21-B20

Table 11. Digital Audio Interface Characteristics (Transmit)

(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

DCLK pulse width high tDCH 10 — — ns
DCLK pulse width low tDCL 10 — — ns
DFS set-up time to DCLK rising edge tSU:DFS 5 — — ns
DFS hold time from DCLK rising edge tHD:DFS 5 — — ns
DIN set-up time from DCLK rising edge tSU:DIN 5 — — ns
DIN hold time from DCLK rising edge tHD:DIN 5 — — ns
tR
DCLK, DFS, DIN, Rise/Fall time — — 10 ns
tF
DCLK Tx Frequency1,2 1.0 — 40.0 MHz
Notes:
1. Guaranteed by characterization.
2. The DCLK frequency may be set below the minimum specification if DIGITAL_INPUT_SAMPLE_RATE is first set to 0
(disable).

DCLK
tR tF

tHD:DFS tSU:DFS
DFS

tSU:DIN tHD:DIN
DIN

Figure 9. Digital Audio Interface Timing Parameters, I2S Mode

Rev. 1.0 17
Si4720/21-B20

Table 12. FM Receive Power Scan Characteristics1

(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz)

Parameter Symbol Test Condition Min Typ Max Unit

Tune and Signal Strength Measurement — — 80 ms
Time per Channel2
Notes:
1. Settling time for ac coupling capacitors on the audio input pins after Receive to Transmit transition can take a few
hundred milliseconds. The actual settling time depends on the values of the ac-coupling capacitors. Using digital audio
input mode avoids this settling time.
2. Guaranteed by characterization.

Table 13. Reference Clock and Crystal Characteristics

(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Reference Clock
1
RCLK Supported Frequencies 31.130 32.768 40,000 kHz
RCLK Frequency Tolerance2 –50 — 50 ppm
REFCLK_PRESCALE 1 — 4095

REFCLK 31.130 32.768 34.406 kHz

Crystal Oscillator
Crystal Oscillator Frequency — 32.768 — kHz
Crystal Frequency Tolerance2 –100 — 100 ppm
Board Capacitance — — 3.5 pF
Notes:
1. The Si4720/21 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK
frequencies between 31.130 kHz and 40 MHz that are not supported. See “AN332: Si4704/05/06/1x/2x/3x/4x FM
Transmitter/AM/FM/SW/LW/WB Receiver Programming Guide” for more details.
2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing.

18 Rev. 1.0
 Si4720/21-B20
2. Test Circuit
2.1. Test Circuit Schematic

VIO C2
0.47 µF

20
19
18
17
16
LIN

GPO1
NC

GPO2/INT
GPO3
LIN
RIN
C3
1 15 0.47 µF
NC RIN
2 14
FMI FMI LOUT LOUT
3 U1 13
RFGND ROUT ROUT
TX Antenna 4 Si4720/21 12
TXO GND
5 11
2 pF
C4 RST VDD
L1 VBATTERY
VTXOUT 120 nH C1
2.7 to 5.5 V
50 

RCLK
22 nF
SCLK
SDIO
R1 SEN

VIO
6
7
8
9
10
RST
SEN
SCLK
SDIO X1
RCLK
RCLK
VIO
C5 C6
1.5 to 3.6 V
Notes:
1. Si4720/21 is shown configured in I2C compatible bus mode.
2. GPO2/INT can be configured for interrupts with the powerup command.
3. To ensure proper operation and FM transmitter performance, follow the guidelines in
“AN383: 3 mm x 3 mm QFN Universal Layout Guide.”
Silicon Laboratories will evaluate schematics and layouts for qualified customers.
4. LIN, RIN line inputs must be ac-coupled.
Figure 10. Test Circuit Schematic
2.2. Test Circuit Bill of Materials

Table 14. Si4720/21 Test Circuit Bill of Materials

Component(s) Value/Description Supplier(s)
C1 Supply bypass capacitor, 22 nF, 20%, Z5U/X7R Murata
C2, C3 AC Coupling Capacitor, 0.47 µF Murata
C4 2 pF, ±.05 pF, 06035JZR0AB AVX
C5, C6 Crystal load capacitors, 22 pF, ±5%, COG Venkel
(Optional: for crystal oscillator option)
L1 120 nH inductor, Qmin = 30 Murata
R1 49.9 , 5% Murata
X1 32.768 kHz crystal (Optional: for crystal oscillator option) Epson
U1 Si4720/21 FM Radio Transceiver Silicon Laboratories

Rev. 1.0 19
Si4720/21-B20
3. Typical Application Schematic
3.1. Analog Audio Inputs/Outputs

VIO C2
0.47 µF

20
19
18
17
16
LIN

GPO3
NC
GPO1

LIN
GPO2/INT
RIN
C3
1 15 0.47 µF
NC RIN
RX Antenna 2 14
FMI LOUT LOUT
3 U1 13
RFGND ROUT ROUT
TX/RX Antenna 4 Si4720/21 12
TXO GND
5 11
RST VDD
L1 VBATTERY
120 nH C1
2.7 to 5.5 V

RCLK
SCLK 22 nF
SDIO
SEN

VIO
6
7
8
9
RST 10
SEN
SCLK
SDIO X1
RCLK
RCLK
VIO
1.5 to 3.6 V C4 C5

Notes:
1. Si4720/21 is shown configured in I2C compatible bus mode.
2. GPO2/INT can be configured for interrupts with the powerup command.
3. To ensure proper operation and FM transmitter performance, follow the guidelines in
“AN383: 3 mm x 3 mm QFN Universal Layout Guide.”
Silicon Laboratories will evaluate schematics and layouts for qualified customers.
4. LIN, RIN line inputs must be ac-coupled.
5. Dedicated RX antenna at FMI input optional.
Figure 11. Analog Audio Inputs/Outputs (LIN, RIN, LOUT, ROUT)
3.2. Typical Application Bill of Materials

Table 15. Si4720/21 Typical Application Bill of Materials

Component(s) Value/Description Supplier(s)
C1 Supply bypass capacitor, 22 nF, 20%, Z5U/X7R Murata
C2, C3 AC Coupling Capacitor, 0.47 µF Murata
C4, C5 Crystal load capacitors, 22 pF, ±5%, COG Venkel
(Optional: for crystal oscillator option)
L1 120 nH inductor, Qmin = 30 Murata
X1 32.768 kHz crystal (Optional: for crystal oscillator option) Epson
U1 Si4720/21 FM Radio Transceiver Silicon Laboratories

20 Rev. 1.0
 Si4720/21-B20
3.3. Digital Audio Inputs/Outputs

VIO R1
DCLK
DFS

20
19
18
17
16
DOUT

NC
GPO1

GPO3/DCLK
DFS
GPO2/INT
DFS
R2
DIN
1 15
NC DOUT R3
RX Antenna 2 14
FMI DFS
3 U1 13
RFGND DIN
TX/RX Antenna 4 Si4720/21 12
TXO GND
5 11
RST VDD
L1 VBATTERY
120 nH C1
2.7 to 5.5 V

RCLK
22 nF
SCLK
SDIO
SEN

VIO
6
7
8
9
10
RST
SEN
SCLK
SDIO
RCLK
VIO
1.5 to 3.6 V

Notes:
1. Si4720/21 is shown configured in I2C compatible bus mode.
2. GPO2/INT can be configured for interrupts with the powerup command.
3. To ensure proper operation and FM transmitter performance, follow the
guidelines in “AN383: Si47xx 3 mm x 3 mm QFN Universal Layout Guide.”
Silicon Laboratories will evaluate schematics and layouts for qualified customers.
4. Dedicated RX antenna at FMI input optional.
Figure 12. Digital Audio Inputs (DIN, DFS, DCLK)
3.4. Typical Application Schematic Bill of Materials

Table 16. Si4720/21 Bill of Materials

Component(s) Value/Description Supplier(s)
C1 Supply bypass capacitor, 22 nF, 20%, Z5U/X7R Murata
C2, C3 AC Coupling Capacitor, 0.47 µF Murata
L1 120 nH inductor, Qmin = 30 Murata
R1, R2 2 k Resistor Any
R3 600  Resistor Any
U1 Si4720/21 FM Radio Transceiver Silicon Laboratories

Rev. 1.0 21
Si4720/21-B20
4. Universal AM/FM RX/FM TX Application Schematic
Figure 13 shows an application schematic that supports the Si47xx family of 3 mm x 3 mm QFN products,
including the Si4702/3/4/5 FM receivers, Si471x FM transmitters, Si472x FM transceivers, and Si473x AM/FM
receivers.

FB1
2.5 k @ 100 MHz
R2 Right
Audio
U2
T5 Left Headphone Amplifier
Audio
FB2
S1 2.5 k @ 100 MHz
Si4702/03: Populate R12, R13, R21, C14, and C15
Si4704/05/1x/2x/3x Analog: Populate C7, C8, C14
J1 HP Jack and C15 as shown
Si4704/05/1x/2x/3x Digital: Populate R16, R17,
R18, R19, and R20 as shown

R16
2 k System Component VBATTERY
2.7 to 5.5 V
GPIO3
C4
LHEADPHONE GPIO2 R13 C7/R17
270 nH 1 nF 0
GPIO1 0.39 uF/ 2 k
LIN
System Component FM Embedded RX/TX Antenna

20
19
18
17
16
RIN
NC
GPO1

GPO3/DCLK
LIN/DFS
GPO2/IRQ
R12
0 C8/R18
R14 L1 0.39 uF/ 600 
D3 0 10 nH C14/R19
D4 C17/R21
3.3pF/0 
1 15 0.39 uF/ 0 
LSHORT NC GND/RIN/DOUT
120 nH 2 14
FMI LOUT/DFS
3 RFGND U1 13
ROUT/DIN
System Component 4 TXO/AMI Si47xx 12
GND C15/R20
5 RST V 11
System Component AM Ferrite Antenna DD VBATTERY 0.39 uF/ 0 
System Components
2.7 to 5.5 V
C1
22 nF
RCLK
SCLK
SDIO

LFERRITE C16
SEN

VIO

D5
180– 470 nF
600 uH
6
7
8
9
10

RST
SEN
SCLK
SDIO
RCLK
VIO

Figure 13. Universal AM/FM RX/FM TX Application Schematic

Following the schematic and layout recommendations detailed in “AN383: Universal Antenna Selection and Layout
Guidelines” will result in optimal performance with the minimal application schematic shown in Figure 13. “Universal
AM/FM RX/FM TX Application Schematic”. System components are those that are likely to be present for any tuner
or transmitter design.

22 Rev. 1.0
 Si4720/21-B20
4.1. Universal AM/FM RX/FM TX Bill of Materials
The bill of materials for the expanded application schematic shown in Figure 13 is provided in Table 17. Refer to
the individual device layout guides and antenna interface guides for a discussion of the purpose of each
component.

Table 17. Universal AM/FM/RX/FM TX Bill of Materials

Designator Description Note
C1 Supply bypass capacitor, 22 nF, 10%, Z5U/X7R, 0402
U1 Silicon Laboratories Si47xx, 3 mm x 3 mm, 20 pin, QFN
R12, R13, R19, 0  jumper, 0402 R12, R13, and R21 for
R20, R21 Si4702/03 Only
C16 AM antenna ac coupling capacitor, 470 nF, 20%, Z5U/X7R AM Ferrite Antenna
LFERRITE AM Ferrite loop stick, 180–600 µH AM Ferrite Antenna
FB1,FB2 Ferrite bead, 2.5 k @ 100 MHZ, 0603, Murata BLM18BD252SN1D Headphone Antenna
LHEADPHONE Headphone antenna matching inductor, 270 nH, 0603, Q>15, Murata Headphone Antenna
LQW18ANR27J00D
LSHORT Embedded antenna matching inductor, 120 nH, 0603, Q>30, Murata Embedded Antenna
LQW18ANR12J00D
R14 Embedded antenna jumper, 2.2 , 0402 Optional
C2 Supply bypass capacitor, 22 nF, 10%, Z5U/X7R, 0402 Optional
C3 Supply bypass capacitor, 100 nF, 10%, Z5U/X7R, 0402 Optional
C5, C6 Headphone amp output shunt capacitor, 100 pF, 10%, Z5U/X7R, 0402 Optional
R7-R11 Current limiting resistor, 20 –2 k, 0402 Optional
C12, C13 Crystal load capacitor, 22 pF, 5%, COG Optional
X1 Crystal, Epson FC-135 Optional
C7, C8 Si47xx input ac coupling capacitor, 0.39 µF, X7R/X5R, 0402 System Component
D1-D5 ESD Diode, SOT23-3, California Micro Devices CM1214-01ST System Component
C11 Supply bypass capacitor, 100 nF, 10%, Z5U/X7R, 0402 Headphone Amplifier
C4 Headphone antenna ac coupling capacitor, 1 nF, 10%, Z5U/X7R, 0402 Headphone Antenna
C9, C10 Headphone amp output ac coupling capacitor, 125 uF, X7R, 0805 Headphone Amplifier
C14, C15 Headphone amp input ac coupling capacitor, 0.39 µF, X7R/X5R, 0402 Headphone Amplifier
R1,R2,R3,R4 Headphone amp feedback/gain resistor, 20 k, 0402 Headphone Amplifier
R5, R6 Headphone amp bleed resistor, 100 k, 0402 Headphone Amplifier
U2 Headphone amplifier, National Semiconductor, LM4910MA Headphone Amplifier
R16, R17 Current limiting resistor, 2 k0402 System Component
R18 Current limiting resistor, 600 , 0402 System Component
L1 VCO filter inductor, 10 nH, 0603, Q30, Murata, LQW18ANR01J00D Optional
C17 VCO filter capacitor, 3.3 pF, 0402, COG, Venkel, Optional
C0402COG2503R3JN

Rev. 1.0 23
Si4720/21-B20
5. Functional Description
5.1. Overview

Si4720
Tx/Rx Ant
TXO LIN

L1
120 nH
RIN

Rx Ant* ADC DAC ROUT

FMI
LNA

MUX
PGA DSP
RFGND
ADC DAC LOUT
AGC

2.7–5.5 V VDD
CONTROL
GND LDO AFC GPO
C1 INTERFACE
22 uF

GPO2/INT
RCLK

GPO1

SEN
SCLK
SDIO

VIO
RST
GPO3
*Note: Dedicated Rx antenna is optional

Figure 14. Functional Block Diagram

The Si4720/21 is the first single-chip FM radio bypass capacitor, and a PCB space of approximately
transceiver. The proven and patented digital 15 mm2. The Si4720/21 is layout compatible with
architecture of the Si4720/21 combines the functionality Silicon Laboratories' Si470x FM radio receivers, Si473x
of the Si470x FM radio receiver with the Si471x FM AM/FM radio receivers, and the Si471x FM radio
transmitter, offering full FM receive and transmit transmitter solutions, allowing a single PCB layout to
capabilities in a single, ultra-small 3x3x0.55 mm QFN accommodate a variety of music features. High yield
package. The device leverages Silicon Laboratories’ manufacturability, unmatched performance, easy
highly successful and proven FM technology and offers design-in, and software programmability are key
unmatched integration and performance. FM receiver advantages of the Si4720.
and transmit functionality may be added to any portable The Si4720/21’s integrated receive power scan function
device by using this single chip. As with the Si470x and shares the same antenna as the transmitter allowing for
Si471x products, the Si4720/21 offers industry leading a compact printed circuit board design. The device
size, performance, low power consumption, and ease of operates in half duplex mode, meaning the transmitter
use. and receiver do not operate at the same time.
The Si4720/21 is the first FM radio transceiver The Si4720/21 performs FM modulation in the digital
integrated circuit to support a small loop antenna, which domain to achieve high fidelity, optimal performance
can be integrated into the enclosure or PCB of a versus power consumption, and flexibility of design. The
portable device. This feature enables applications that onboard DSP provides modulation adjustment and
also include Bluetooth functionality to perform FM radio audio dynamic range control for optimum sound quality.
reception without cables. For portable navigation
The Si4721 supports the European Radio Data System
devices, the Si4720’s antenna architecture permits
(RDS) and the US Radio Broadcast Data System
integration of the traffic messaging antenna into the
(RBDS) including all the symbol encoding, block
enclosure of the portable device, and eliminates the
synchronization, and error correction functions. Using
need for external antenna cables.
this feature, the Si4721 enables data such as artist
The Si4720's digital integration reduces the required name and song title to be transmitted to an RDS/RBDS
external components of traditional offerings, resulting in receiver.
a solution requiring only an external inductor and

24 Rev. 1.0
 Si4720/21-B20
The transmit output (TXO) connects directly to the The Si4720/21 reference clock is programmable,
transmit antenna with only one external inductor to supporting many RCLK inputs as shown in Table 10.
provide harmonic filtering. The output is programmable The S4720/21 are part of a family of broadcast audio
over a 10 dB voltage range in 1 dB steps. The TXO solutions offered in standard, 3 x 3 mm 20-pin QFN
output pin can also be configured for loop antenna packages. All solutions are layout compatible, allowing
support. Users are responsible for complying with local a single PCB to accommodate various feature offerings.
regulations on RF transmission (FCC, ETSI, ARIB,
The Si4720/21 includes line inputs to the on-chip
etc.).
analog-to-digital converters (ADC), a programmable
The digital audio interface operates in slave mode and reference clock input, and a configurable digital audio
supports a variety of MSB-first audio data formats interface. The chip supports I2C-compliant 2-wire, 8-bit
including I2S and left-justified modes. The interface has SPI, and a 3-wire control interface.
three pins: digital data input (DIN), digital frame
synchronization input (DFS), and a digital bit 5.2. Application Schematics and Operating
synchronization input clock (DCLK). The Si4720/21 Modes
supports a number of industry-standard sampling rates The application schematic for the Si4720/21 is shown in
including 32, 40, 44.1, and 48 kHz. The digital audio Section "3. Typical Application Schematic" on page 20.
interface enables low-power operation by eliminating The Si4720/21 supports selectable analog, digital, or
the need for redundant DACs and ADCs on the audio concurrent analog and digital audio output modes. In
baseband processor. the analog output mode, pin 13 is ROUT, pin 14 is
The Si4720/21 includes a low-noise stereo line input LOUT, and pin 17 is GPO3. In the digital output mode,
(LIN/RIN) with programmable attenuation. To ensure pin 15 is DOUT, pin 16 is DFS, and pin 17 is DCLK.
optimal audio performance, the Si4720/21 has a Concurrent analog and digital audio output mode
transmit line input property that allows the user to requires pins 13, 14, 15, 16, and 17. In addition to
specify the peak amplitude of the analog input required output mode, there is a clocking mode to clock the
to reach maximum deviation level. The deviation levels Si4720/21 from a reference clock or crystal oscillator.
of the audio, pilot, and RDS/RBDS signals can be The user sets the operating modes with commands as
independently programmed to customize FM transmitter described in Section "6. Commands and Properties" on
designs. The Si4720/21 has a programmable low audio page 36.
level and high audio level indicators that allows the user
to selectively enable and disable the carrier based on 5.3. FM Receiver
the presence of audio content. In addition, the device The Si4720/21 FM receiver is based on the proven
provides an overmodulation indicator to allow the user Si4700/01/02/03 FM radio receiver. The part leverages
to dynamically set the maximum deviation level. The Silicon Laboratories' proven and patented Si4700/01 FM
Si4720/21 has a programmable audio dynamic range broadcast radio receiver digital architecture, delivering
control that can be used to reduce the dynamic range of superior RF performance and interference rejection. The
the audio input signal and increase the volume at the proven digital techniques provide excellent sensitivity in
receiver. These features can dramatically improve the weak signal environments while providing superb
end user’s listening experience. selectivity and inter-modulation immunity in strong signal
The Si4720/21 is reset by applying a logic low on the environments.
RST pin. This causes all register values to be reset to The FM receiver supports the worldwide FM broadcast
their default values. The digital input/output interface band (76 to 108 MHz) with channel spacings of 50–
supply (VIO) provides voltage to the RST, SEN, SDIO, 200 kHz. The Low-IF architecture utilizes a single
RCLK, DIN, DFS, and DCLK pins and can be connected converter stage and digitizes the signal using a high-
to the audio baseband processor's supply voltage to resolution analog-to-digital converter. The resulting
save power and remove the need for voltage level digital signals are further processed through an on-chip
translators. RCLK is not required for register operation. DSP for digital channel selection, FM demodulation, and
ultimately stereo audio output. The audio output can be
directed either to an external headphone amplifier via
analog in/out or to other system ICs through digital audio
interface (I2S).

Rev. 1.0 25
Si4720/21-B20
5.4. Integrated Antenna Support 5.5. Receiver Digital Audio Interface
The Si4720/21 is the first FM receiver to support the fast (Si4721 Only)
growing trend to integrate the FM receiver antenna into The digital audio interface operates in slave mode and
the device enclosure. The chip is designed with this supports three different audio data formats:
function in mind from the outset, with multiple
international patents pending, thus it is superior to many  I2S
other options in price, board space, and performance.  Left-Justified

The Si4720/21 supports an internal RX antenna  DSP Mode

allowing for "wire free" listening to FM over Bluetooth. 5.5.1. Audio Data Formats
The user can receive FM over the integrated RX In I2S mode, by default the MSB is captured on the
antenna and stream it via Bluetooth to a Bluetooth- second rising edge of DCLK following each DFS
enabled headset. transition. The remaining bits of the word are sent in
Testing indicates that using Silicon Laboratories' order, down to the LSB. The left channel is transferred
patented techniques provides FM performance over an first when the DFS is low, and the right channel is
integrated antenna that can be very similar in many key transferred when the DFS is high.
metrics to performance using standard FM receive In Left-Justified mode, by default the MSB is captured
antennas (e.g., wired headset). Refer to “AN383: on the first rising edge of DCLK following each DFS
Antenna Selection and Universal Layout Guidelines” for transition. The remaining bits of the word are sent in
additional details on the implementation of support for order, down to the LSB. The left channel is transferred
an integrated antenna. first when the DFS is high, and the right channel is
Figure 15 shows a conceptual block diagram of the transferred when the DFS is low.
Si4720/21 architecture used to support the short In DSP mode, the DFS becomes a pulse with a width of
antenna. The headphone/dedicated FM receive 1DCLK period. The left channel is transferred first,
antenna is therefore optional. Host software can detect followed right away by the right channel. There are two
the presence of a headphone antenna and switch options in transferring the digital audio data in DSP
between the integrated antenna if desired. mode: the MSB of the left channel can be transferred on
the first rising edge of DCLK following the DFS pulse or
on the second rising edge.
Headphone
Ant* In all audio formats, depending on the word size, DCLK
FMI
frequency, and sample rates, there may be unused
LNA DCLK cycles after the LSB of each word before the next
RFGND DFS transition and MSB of the next word. In addition, if
preferred, the user can configure the MSB to be
AGC
Short/ captured on the falling edge of DCLK via properties.
Embedded The number of audio bits can be configured for 8, 16,
Ant LPI
20, or 24 bits.
L1 5.5.2. Audio Sample Rates
120 nH
The device supports a number of industry-standard
sampling rates including 32, 40, 44.1, and 48 kHz. The
digital audio interface enables low-power operation by
*Note: Dedicated RX antenna is optional. eliminating the need for redundant DACs on the audio
baseband processor.
Figure 15. Conceptual Block Diagram of the
Si4720/21 Short Antenna Support

26 Rev. 1.0
 Si4720/21-B20

(OFALL = 1) INVERTED
DCLK

(OFALL = 0) DCLK

DFS LEFT CHANNEL RIGHT CHANNEL

I2S
(OMODE = 0000)
1 DCLK 1 DCLK

DOUT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

MSB LSB MSB LSB

Figure 16. I2S Digital Audio Format

(OFALL = 1) INVERTED
DCLK

(OFALL = 0) DCLK

DFS LEFT CHANNEL RIGHT CHANNEL

Left-Justified
(OMODE = 0110)
DOUT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

MSB LSB MSB LSB

Figure 17. Left-Justified Digital Audio Format

(OFALL = 0) DCLK

DFS

LEFT CHANNEL RIGHT CHANNEL

(OMODE = 1100) DOUT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

(MSB at 1st rising edge)
MSB LSB MSB LSB
1 DCLK LEFT CHANNEL RIGHT CHANNEL
DOUT
1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n
(OMODE = 1000) (MSB at 2nd rising edge)
MSB LSB MSB LSB

Figure 18. DSP Digital Audio Format

5.6. Stereo Audio Processing 5.6.1. Stereo Decoder
The output of the FM demodulator is a stereo The Si4720/21's integrated stereo decoder
multiplexed (MPX) signal. The MPX standard was automatically decodes the MPX signal using DSP
developed in 1961, and is used worldwide. Today's techniques. The 0 to 15 kHz (L+R) signal is the mono
MPX signal format consists of left + right (L+R) audio, output of the FM tuner. Stereo is generated from the
left – right (L–R) audio, a 19 kHz pilot tone, and (L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is
RDS/RBDS data as shown in Figure 19 below. used as a reference to recover the (L–R) signal. Output
left and right channels are obtained by adding and
subtracting the (L+R) and (L–R) signals respectively.
Modulation Level

The Si4721 uses frequency information from the 19 kHz

stereo pilot to recover the 57 kHz RDS/RBDS signal.
Mono Audio
Left + Right
5.6.2. Stereo-Mono Blending
Stereo
Stereo Audio RDS/
Pilot
Left - Right
Adaptive noise suppression is employed to gradually
RBDS
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
0 15 19 23 38 53 57 reception conditions. Stereo/mono status can be
Frequency (kHz) monitored with the FM_RSQ_STATUS command. Mono
Figure 19. MPX Signal Spectrum operation can be forced with the
FM_BLEND_MONO_THRESHOLD property.

Rev. 1.0 27
Si4720/21-B20
5.7. De-Emphasis during reception. The tuning frequency can be directly
programmed using the FM_TUNE_FREQ and
Pre-emphasis and de-emphasis is a technique used by
command. The Si4720/21 supports channel spacing of
FM broadcasters to improve the signal-to-noise ratio of
50, 100, or 200 kHz in FM receiver mode.
FM receivers by reducing the effects of high-frequency
interference and noise. When the FM signal is 5.12. Seek
transmitted, a pre-emphasis filter is applied to Seek tuning will search up or down for a valid channel.
accentuate the high audio frequencies. The Si4720/21 Valid channels are found when the receive signal
incorporates a de-emphasis filter which attenuates high strength indicator (RSSI) and the signal-to-noise ratio
frequencies to restore a flat frequency response. Two (SNR) values exceed the set threshold. Using the SNR
time constants are used in various regions. The de- qualifier rather than solely relying on the more
emphasis time constant is programmable to 50 or 75 µs traditional RSSI qualifier can reduce false stops and
and is set by the FM_DEEMPHASIS property. increase the number of valid stations detected. Seek is
5.8. Stereo DAC initiated using the FM_SEEK_START command. The
RSSI and SNR threshold settings are adjustable using
High-fidelity stereo digital-to-analog converters (DACs) properties (see Table 15).
drive analog audio signals onto the LOUT and ROUT
Two seek options are available. The device will either
pins. The audio output may be muted. Volume is
wrap or stop at the band limits. If the seek operation is
adjusted digitally with the RX_VOLUME property.
unable to find a channel, the device will indicate failure
5.9. Soft Mute and return to the channel selected before the seek
operation began.
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal 5.13. Reference Clock
conditions. The softmute attenuation level is adjustable The Si4720/21 reference clock is programmable,
using the FM_SOFT_MUTE_MAX_ATTENUATION supporting RCLK frequencies in Table 13. Refer to
property. Table 3, “DC Characteristics,” on page 6 for switching
voltage levels and Table 9, “FM Receiver
5.10. RDS/RBDS Processor (Si4721 Only) Characteristics,” on page 13 for frequency tolerance
The Si4721 implements an RDS/RBDS* processor for information.
symbol decoding, block synchronization, error An onboard crystal oscillator is available to generate the
detection, and error correction. 32.768 kHz reference when an external crystal and load
The Si4721 device is user configurable and provides an capacitors are provided. Refer to "3. Typical Application
optional interrupt when RDS is synchronized, loses Schematic" on page 20. This mode is enabled using the
synchronization, and/or the user configurable RDS POWER_UP command. Refer to Table 21 "Si472x
FIFO threshold has been met. Property Summary".
The Si4721 reports RDS decoder synchronization The Si4720/21 performance may be affected by data
status and detailed bit errors in the information word for activity on the SDIO bus when using the integrated
each RDS block with the FM_RDS_STATUS command. internal oscillator. SDIO activity results from polling the
The range of reportable block errors is 0, 1–2, 3–5, or tuner for status or communicating with other devices
6+. More than six errors indicates that the that share the SDIO bus. If there is SDIO bus activity
corresponding block information word contains six or while the Si4720/21 is performing the seek/tune
more non-correctable errors or that the block checkword function, the crystal oscillator may experience jitter,
contains errors. which may result in mistunes, false stops, and/or lower
*Note: RDS/RBDS is referred to only as RDS throughout the SNR.
remainder of this document.
For best seek/tune results, Silicon Laboratories
5.11. Tuning recommends that all SDIO data traffic be suspended
during Si4720/21 seek and tune operations. This is
The frequency synthesizer uses Silicon Laboratories’
achieved by keeping the bus quiet for all other devices
proven technology, including a completely integrated
on the bus, and delaying tuner polling until the tune or
VCO. The frequency synthesizer generates the
seek operation is complete. The seek/tune complete
quadrature local oscillator signal used to downconvert
(STC) interrupt should be used instead of polling to
the RF input to a low intermediate frequency. The VCO
determine when a seek/tune operation is complete.
frequency is locked to the reference clock and adjusted
with an automatic frequency control (AFC) servo loop

28 Rev. 1.0
 Si4720/21-B20
5.14. FM Transmitter frequency deviation of 75 kHz corresponds to 100
percent modulation). Frequency deviation is related to
The transmitter (TX) integrates a stereo audio ADC to
the amplitude of the MPX signal by a gain constant,
convert analog audio signals to high fidelity digital
KVCO, as given by the following equation:
signals. Alternatively, digital audio signals can be
applied to the Si4720/21 directly to reduce power f = K VCO A m
consumption by eliminating the need to convert audio
baseband signals to analog and back again to digital. where f is the frequency deviation; KVCO is the
Digital signal processing is used to perform the stereo voltage-to-frequency gain constant, and Am is the
MPX encoding and FM modulation to a low digital IF. amplitude of the MPX message signal. For a fixed
Transmit baseband filters suppress out-of-channel KVCO, the amplitude of all the subchannel signals within
noise and images from the digital low-IF signal. A the MPX message signal must be scaled to give the
quadrature single-sideband mixer up-converts the appropriate total frequency deviation.
digital IF signal to RF, and internal RF filters suppress
noise and harmonics to support the harmonic emission MPX Encoder
requirements of cellular phones, GPS, WLAN, and other RDS(t) C2
wireless standards. 57 kHz
m(t)
The TXO output has over 10 dB of output level control, L(t) C0

programmable in approximately 1 dB steps. This large Frequency

output range enables a variety of antennas to be used Tripler
C1
for transmit, such as a monopole stub antenna or a loop Frequency
38 kHz 19 kHz
antenna. The 1 dB step size provides fine adjustment of Doubler

the output voltage. R(t) C0

The TXO output requires only one external 120 nH

inductor. The inductor is used to resonate the antenna Figure 20. MPX Encoder
and is automatically calibrated within the integrated Figure 20 shows a conceptual block diagram of an MPX
circuit to provide the optimum output level and encoder used to generate the MPX signal. L(t) and R(t)
frequency response for supported transmit frequencies. denote the time domain waveforms from the left and
Users are responsible for adjusting their system’s right audio channels, and RDS(t) denotes the time
radiated power levels to comply with local regulations domain waveform of the RDS/RBDS signal.
on RF transmission (FCC, ETSI, ARIB, etc.).
The MPX message signal can be expressed as follows:
5.15. Receive Power Scan m(t) = C0[L(t) + R(t)] + C1 cos(219 kHz)
The Si4720/21 is the industry’s first FM transmitter with + C0[L(t) – R(t)] cos(238 kHz)
integrated receive functionality to measure received
signal strength. This has been designed to specifically + C2RDS(t) cos(257 kHz)
handle various antenna lengths including integrated
where C0, C1, and C2 are gains used to scale the
PCB antennas, wire antennas, and loop antennas,
amplitudes of the audio signals (L(t) ± R(t)), the 19 kHz
allowing it to share the same antenna as the transmitter.
pilot tone, and the RDS subcarrier respectively, to
The receive function reuses the on-chip varactor from
generate the appropriate modulation level. To achieve
the transmitter to optimize the receive signal power
the modulation levels of Figure 20 with
applied to the front-end amplifier. Auto-calibration of the
KVCO = 75 kHz/V, C0 would be set to 0.45; C1 would be
varactor occurs with each tune command for consistent
set to 0.1, and C2 would be set to 0.0267 giving a peak
performance across the FM band.
audio frequency deviation of 0.9 x 75 kHz = 67.5 kHz, a
5.15.1. Stereo Encoder peak pilot frequency deviation of
Figure 19 shows an example modulation level 0.1 x 75 kHz = 7.5 kHz, and a peak RDS frequency
breakdown for the various components of a typical MPX deviation of 0.0267 x 75 kHz = 2.0025 kHz for a total
signal. peak frequency deviation of 77.0025 kHz.
The total modulation level for the MPX signal shown in In the Si4720/21, the peak audio, pilot, and RDS
Figure 19, assuming no correlation, is equal to the frequency deviations can be programmed directly with
arithmetic sum of each of the subchannel levels the Transmit Audio, Pilot, and RDS Deviation
resulting in 102.67 percent modulation or a peak commands with an accuracy of 10 Hz. For the example
frequency deviation of 77.0025 kHz (an instantaneous in Figure 20, the Transmit Audio Deviation is

Rev. 1.0 29
Si4720/21-B20
programmed with the value 6750, the Transmit Pilot In Left-Justified mode, the MSB is captured on the first
Deviation with 750, and the Transmit RDS Deviation rising edge of DCLK following each DFS transition. The
with 200, generating peak audio frequency deviations of remaining bits of the word are sent in order, down to the
67.5 kHz, peak pilot deviations of 7.5 kHz, and peak LSB. The Left Channel is transferred first when the DFS
RDS deviations of 2.0 kHz for a total peak frequency is high, and the Right Channel is transferred when the
deviation of 77 kHz. The total peak transmit frequency DFS is low.
deviation of the Si4720/21 can range from 0 to 100 kHz In DSP mode, the DFS becomes a pulse with a width of
and is equal to the arithmetic sum of the Transmit 1 DCLK period. The Left Channel is transferred first,
Audio, Pilot, and RDS deviations. Users must comply followed right away by the Right Channel. There are two
with local regulations on radio frequency transmissions. options in transferring the digital audio data in DSP
Each of the individual deviations (transmit audio, pilot, mode: the MSB of the left channel can be transferred on
and RDS) can be independently programmed; however, the first rising edge of DCLK following the DFS pulse or
the total peak frequency deviation cannot exceed on the second rising edge.
100 kHz. In all audio formats, depending on the word size, DCLK
The Si4720/21 provides an overmodulation indicator to frequency and sample rates, there may be unused
allow the user to dynamically set the maximum DCLK cycles after the LSB of each word before the next
deviation level. If the instantaneous frequency exceeds DFS transition and MSB of the next word.
the deviation level specified by the The number of audio bits can be configured for 8, 16,
TX_AUDIO_DEVIATION property, the SQINT interrupt 20, or 24 bits.
bit (and optional interrupt) will be set.
5.16.2. Audio Sample Rates
5.16. Transmitter Digital Audio Interface The device supports a number of industry-standard
The digital audio interface operates in slave mode and sampling rates including 32, 40, 44.1, and 48 kHz. The
supports 3 different audio data formats: digital audio interface enables low-power operation by
eliminating the need for redundant DACs and ADCs on
1. I2S
the audio baseband processor. The sampling rate is
2. Left-Justified selected using the DIGITAL_INPUT_SAMPLE_RATE
3. DSP Mode property.
5.16.1. Audio Data Formats The device supports DCLK frequencies above 1 MHz.
In I2S mode, the MSB is captured on the second rising After powerup the DIGITAL_INPUT_SAMPLE_RATE
edge of DCLK following each DFS transition. The property defaults to 0 (disabled). After DCLK is
remaining bits of the word are sent in order, down to the supplied, the DIGITAL_INPUT_SAMPLE_RATE
LSB. The Left Channel is transferred first when the DFS property should be set to the desired audio sample rate
is low, and the Right Channel is transferred when the such as 32, 40, 44.1, or 48 kHz. The
DFS is high. DIGITAL_INPUT_SAMPLE_RATE property must be set
to 0 before DCLK is removed or the DCLK frequency
drops below 1 MHz. A device reset is required if this
requirement is not followed.

(IFALL = 1) INVERTED
DCLK

(IFALL = 0) DCLK

DFS LEFT CHANNEL RIGHT CHANNEL

I2S
(IMODE = 0000)
1 DCLK 1 DCLK

DIN/DOUT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

MSB LSB MSB LSB

Figure 21. I2S Digital Audio Format

30 Rev. 1.0
 Si4720/21-B20

(IFALL = 1) INVERTED
DCLK

(IFALL = 0) DCLK

DFS LEFT CHANNEL RIGHT CHANNEL

Left-Justified
(IMODE = 0110)
DIN/DOUT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

MSB LSB MSB LSB

Figure 22. Left-Justified Digital Audio Format

(IFALL = 0) DCLK

DFS

LEFT CHANNEL RIGHT CHANNEL

(IMODE = 1100) DIN/DOUT 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

st
(MSB at 1 rising edge)
MSB LSB MSB LSB
1 DCLK LEFT CHANNEL RIGHT CHANNEL
DIN/DOUT
nd 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n
(IMODE = 1000) (MSB at 2 rising edge)
MSB LSB MSB LSB

Figure 23. DSP Digital Audio Format

5.17. Line Input The line attenuation code is chosen by picking the
lowest Peak Input Voltage in Table 18 that is just above
The Si4720/21 provides left and right channel line inputs
the expected peak input voltage coming from the audio
(LIN and RIN). The inputs are high-impedance and low-
baseband processor. For example, if the expected peak
capacitance, suited to receiving line level signals from
input voltage from the audio baseband processor is
external audio baseband processors. Both line inputs
400 mV, the user chooses LIATTEN[1:0] = 10 since the
are low-noise inputs with programmable attenuation.
Peak Input Voltage of 416 mV associated with
Passive and active anti-aliasing filters are incorporated
LIATTEN[1:0] = 10 is just greater than the expected
to prevent high frequencies from aliasing into the audio
peak input voltage of 400 mV. The user also enters
band and degrading performance.
400 mV into the LILEVEL[9:0] to associate this input
To ensure optimal audio performance, the Si4720/21 level to the maximum frequency deviation level
has a TX_LINE_INPUT_LEVEL property that allows the programmed into the audio deviation property. Note that
user to specify the peak amplitude of the analog input selecting a particular value of LIATTEN[1:0] changes
(LILEVEL[9:0]) required to reach the maximum the input resistance of the LIN and RIN pins. This
deviation level programmed in the audio deviation feature is used for cases where the expected peak input
property, TX_AUDIO_DEVIATION. A corresponding line level exceeds the maximum input level of the LIN and
input attenuation code, LIATTEN[1:0], is also selected RIN pins.
by the expected peak amplitude level. Table 18 shows
The maximum analog input level is 636 mVpK. If the
the line attenuation codes.
analog input level from the audio baseband processor
Table 18. Line Attenuation Codes exceeds this voltage, series resistors must be inserted
in front of the LIN and RIN pins to attenuate the voltage
LIATTEN[1:0] Peak Input RIN/LIN Input such that it is within the allowable operating range. For
Voltage [mV] Resistance [k] example, if the audio baseband's expected peak
amplitude is 900 mV and the VIO supply voltage is 1.8 V,
00 190 396
the designer can use 30 k series resistors in front of
01 301 100 the LIN and RIN pins and select LIATTEN[1:0] = 11. The
10 416 74 resulting expected peak input voltage at the LIN/RIN
pins is 600 mV, since this is just a voltage divider
11 636 60 between the LIN/RIN input resistance (see Table 18,
60 k for this example) and the external resistor. Note
that the Peak Input Voltage corresponding to the chosen

Rev. 1.0 31
Si4720/21-B20
LIATTEN[1:0] code still needs to satisfy the condition of
being just greater than the attenuated voltage. In this Input [dBFS]
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
example, a line attenuation code of LIATTEN[1:0] = 11
has a Peak Input Voltage of 636 mV, which is just Compression
2:1 dB –10
greater than the expected peak attenuated voltage of
600 mV. Also, the expected peak attenuated voltage is Threshold
–20
= –40 dB
entered into the LILEVEL[9:0] parameter. Again, in this
example, 600 mV is entered into LILVEVEL[9:0]. This No –30
example shows one possible solution, but many other Compression

Output [dBFS]
M=1 –40
solutions exist. The optimal solution is to apply the
largest possible voltage to the LIN and RIN pins for –50
signal-to-noise considerations; however, practical
resistor values may limit the choices. M=1 –60
Gain
Note that the TX_LINE_INPUT_LEVEL parameter will = 20 dB –70
affect the high-pass filter characteristics of the ac-
coupling capacitors and the resistance of the audio –80
inputs.
–90
The Si4720/21 has a programmable low audio level and
high audio level indicators that allows the user to Figure 24. Audio Dynamic Range Transfer
selectively enable and disable the carrier based on the Function
presence of audio content. The TX_ASQ_LEVEL_LOW For input signals below the threshold of –40 dBFS, the
and TX_ASQ_LEVEL_HIGH parameters set the low output signal is amplified or gained up by 20 dB relative
level and high level thresholds in dBFS, respectively. to an uncompressed signal. Audio inputs above the
The time required for the audio level to be below the low threshold are compressed by a 2 to 1 dB ratio, meaning
threshold is set with the TX_ASQ_DURATION_LOW that every 2 dB increase in audio input level above the
parameter, and similarly, the time required for the audio threshold results in an audio output increase of 1 dB. In
level to be above the high threshold is set with the this example, the input dynamic range of 90 dB is
TX_ASQ_DURATION_HIGH parameter. reduced to an output dynamic range of 70 dB.
5.18. Audio Dynamic Range Control Figure 25 shows the time domain characteristics of the
audio dynamic range controller. The attack rate sets the
The Si4720/21 includes digital audio dynamic range
speed with which the audio dynamic range controller
control with programmable gain, threshold, attack rate,
responds to changes in the input level, and the release
and release rate. The total dynamic range reduction is
rate sets the speed with which the audio dynamic range
set by the gain value and the audio output compression
controller returns to no compression once the audio
above the threshold is equal to
input level drops below the threshold.
Threshold/(Gain + Threshold) in dB. The gain specified
cannot be larger than the absolute value of the
threshold. This feature can also be disabled if audio Threshold
compression is not desired. Audio
The audio dynamic range control can be used to reduce Input
the dynamic range of the audio signal, which improves
the listening experience on the FM receiver. Audio
dynamic range reduction increases the transmit volume
by decreasing the peak amplitudes of audio signals and
increasing the root mean square content of the audio Audio
signal. In other words, it amplifies signals below a Output
threshold by a fixed gain and compresses audio signals
above a threshold by the ratio of
Threshold/(Gain + Threshold). Figure 24 shows an
example transfer function of an audio dynamic range Attack Release
controller with the threshold set at –40 dBFS and a time time
Gain = 20 dB relative to an uncompressed transfer Figure 25. Time Domain Characteristics of the
function. Audio Dynamic Range Controller

32 Rev. 1.0
 Si4720/21-B20
5.19. Audio Limiter controller to burst data into the BCD buffer, which
The 4720/21 also includes a digital audio limiter. The emulates a FIFO. The data does not repeat, but, when
audio limiter prevents over-modulation of the FM the buffer is nearly empty, the Si4721 signals the
transmit output by dynamically attenuating peaks in the outside device to initiate another data burst. This mode
audio input signal that exceed a programmable permits the outside device to use any RDS functionality
threshold. The limiter threshold is set to the (including open data applications) that it wants.
programmed audio deviation + ten percent. The *Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
threshold ensures that the output signal audio deviation
does not exceed the programmed levels, avoiding 5.22. Tuning
audible artifacts or distortion in the target FM receiver, The frequency synthesizer uses Silicon Laboratories’
and complying with FCC or ETSI regulatory standards. proven technology including a completely integrated
The limiter performs as a peak detector with an attack VCO. The frequency synthesizer generates the
rate set to one audio sample, resulting in an almost quadrature local oscillator signal used to upconvert the
immediate attenuation of the input peak. The recover low intermediate frequency to RF. The VCO frequency
rate is programmable to the customer’s preference, and is locked to the reference clock and adjusted with an
is set by default to 5 ms. This is the recommended automatic frequency control (AFC) servo loop during
setting to avoid audible pumping or popping. Refer to transmission. The tuning frequency can be directly
“AN332: Universal Programming Guide.” programmed with commands. For example, to tune to
98.1 MHz, the user writes the TX_TUNE_FREQ
5.20. Pre-emphasis and De-emphasis command with an argument = 9810. The Si4720/21
Pre-emphasis and de-emphasis is a technique used by supports channel spacing of 50, 100, or 200 kHz.
FM broadcasters to improve the signal-to-noise ratio of
FM receivers by reducing the effects of high-frequency
5.23. Reference Clock
interference and noise. When the FM signal is The Si4720/21 reference clock is programmable,
transmitted, a pre-emphasis filter is applied to supporting RCLK frequencies from 31.130 kHz to
accentuate the high audio frequencies. All FM receivers 40 MHz. The RCLK frequency divided by an integer
incorporate a de-emphasis filter that attenuates high number (the prescaler value) must fall in the range of
frequencies to restore a flat frequency response. Two 31,130 to 34,406 Hz. Therefore, the range of RCLK
time constants are used in various regions. The pre- frequencies is not continuous below frequencies of
emphasis time constant is programmable to 50 or 75 µs 311.3 kHz. The default RCLK frequency is 32.768 kHz.
and is set by using the TX_PREEMPHASIS property. Please refer to “AN332: Universal Programming Guide”
for using other RCLK frequencies.
5.21. RDS/RBDS Processor (Si4721 Only)
5.24. Control Interface
The Si4721 implements an RDS/RBDS* processor for
symbol encoding, block synchronization, and error A serial port slave interface is provided; this allows an
correction. Digital data can be transmitted with the external controller to send commands to the Si4720/21
Si4721 RDS/RBDS encoding feature. and receive responses from the device. The serial port
can operate in three bus modes: 2-wire mode, SPI
RDS transmission is supported with three different
mode, or 3-wire mode. The Si4720/21 selects the bus
modes. The first mode is the simplest mode and
mode by sampling the state of the GPO1 and
requires no additional user support except for pre-
GPO2/INT pins on the rising edge of RST. The GPO1
loading the desired RDS PI and PTY codes and up to
pin includes an internal pull-up resistor that is
12 8-byte PS character strings. The Si4721 will transmit
connected while RST is low, and the GPO2/INT pin
the PI code and rotate through the transmission of the
includes an internal pull-down resistor that is connected
PS character strings with no further control required
while RST is low. Therefore, it is only necessary for the
from outside the device. The second mode allows for
user to actively drive pins that differ from these states.
more complicated transmissions. The PI and PTY
codes are written to the device as in mode 1. The Table 19. Bus Mode Select on Rising Edge of
remaining blocks (B, C, and D) are written to a 252 byte RST
buffer. This buffer can hold 42 sets of BCD blocks. The
Si4721 creates RDS groups by creating block A from Bus Mode GPO1 GPO2/INT
the PI code, concatenating blocks BCD from the buffer, 2-Wire 1 0
and rotating through the buffer. The BCD buffer is SPI 1 1 (must drive)
circular; so, the pattern is repeated until the buffer is
3-Wire 0 (must drive) 0
changed. Finally, the third mode allows the outside

Rev. 1.0 33
Si4720/21-B20
After the rising edge of RST, the pins, GPO1 and and Write Timing Diagram,” on page 9.
GPO2/INT, are used as general-purpose output (O) pins 5.24.2. SPI Control Interface Mode
as described in Section “5.15. GPO Outputs”. In any
When selecting SPI mode, the user must ensure that a
bus mode, commands may only be sent after VIO and
rising edge of SCLK does not occur within 300 ns
VDD supplies are applied.
before the rising edge of RST.
5.24.1. 2-Wire Control Interface Mode
SPI bus mode uses the SCLK, SDIO, and SEN pins for
When selecting 2-wire mode, the user must ensure that read/write operations. For reads, the user can choose to
SCLK is high during the rising edge of RST, and stays receive data from the device on either SDIO or GPO1. A
high until after the first start condition. Also, a start transaction begins when the user drives SEN low. The
condition must not occur within 300 ns before the rising user then pulses SCLK eight times while driving an 8-bit
edge of RST. control byte (MSB first) serially on SDIO. The device
2-wire bus mode uses only the SCLK and SDIO pins for captures the data on rising edges of SCLK. The control
signaling. A transaction begins with the START byte must have one of these values:
condition, which occurs when SDIO falls while SCLK is 0x48 = write eight command/argument bytes (user
high. Next, the user drives an 8-bit control word serially drives write data on SDIO)
on SDIO, which is captured by the device on rising 0x80 = read status byte (device drives read data on
edges of SCLK. The control word consists of a seven bit SDIO)
device address followed by a read/write bit (read = 1,
0xA0 = read status byte (device drives read data on
write = 0). The Si4720/21 acknowledges the control
GPO1)
word by driving SDIO low on the next falling edge of
SCLK. 0xC0 = read 16 response bytes (device drives read data
on SDIO)
Although the Si4720/21 responds to only a single
device address, this address can be changed with the 0xE0 = read 16 response bytes (device drives read data
SEN pin (note that the SEN pin is not used for signaling on GPO1)
in 2-wire mode). When SEN = 0, the seven-bit device When writing a command, after the control byte has
address is 0010001. When SEN = 1, the address is been written, the user must drive exactly eight data
1100011. bytes (a command byte and seven argument bytes) on
For write operations, the user then sends an eight bit SDIO. The data will be captured by the device on the
data byte on SDIO, which is captured by the device on rising edges of SCLK. After all eight data bytes have
rising edges of SCLK. The Si4720/21 acknowledges been written, the user raises SEN after the last falling
edge of SCLK to end the transaction.
each data byte by driving SDIO low for one cycle, on the
next falling edge of SCLK. The user may write up to In any bus mode, before sending a command or reading
eight data bytes in a single two-wire transaction. The a response, the user must first read the status byte to
first byte is a command, and the next seven bytes are ensure that the device is ready (CTS bit is high). In SPI
arguments. mode, this is done by sending control byte 0x80 or
For read operations, after the Si4720/21 has 0xA0, followed by reading a single byte on SDIO or
acknowledged the control byte, it drives an eight-bit GPO1. The Si4720/21 changes the state of SDIO or
data byte on SDIO, changing the state of SDIO on the GPO1 after the falling edges of SCLK. Data should be
falling edge of SCLK. The user acknowledges each data captured by the user on the rising edges of SCLK. After
byte by driving SDIO low for one cycle, on the next the status byte has been read, the user raises SEN after
falling edge of SCLK. If a data byte is not the last falling edge of SCLK to end the transaction.
acknowledged, the transaction ends. The user may When reading a response, the user must read exactly
read up to 16 data bytes in a single two-wire 16 data bytes after sending the control byte. It is
transaction. These bytes contain the response data recommended that the user keep SEN low until all bytes
from the Si4720/21. have transferred. However, it will not disrupt the
A 2-wire transaction ends with the STOP condition, protocol if SEN temporarily goes high at any time, as
which occurs when SDIO rises while SCLK is high. long as the user does not change the state of SCLK
while SEN is high. After 16 bytes have been read, the
For details on timing specifications and diagrams, refer user raises SEN after the last falling edge of SCLK to
to Table 5, “2-Wire Control Interface end the transaction.
Characteristics1,2,3,” on page 8, Figure 2, “2-Wire
Control Interface Read and Write Timing Parameters,” At the end of any SPI transaction, the user must drive
on page 9, and Figure 3, “2-Wire Control Interface Read SEN high after the final falling edge of SCLK. At any

34 Rev. 1.0
 Si4720/21-B20
time during a transaction, if SEN is sampled high by the 5.26. Reset, Powerup, and Powerdown
device on a rising edge of SCLK, the transaction will be
Setting the RST pin low will disable analog and digital
aborted. When SEN is high, SCLK may toggle without
circuitry, reset the registers to their default settings, and
affecting the device.
disable the bus. Setting the RST pin high will bring the
For details on timing specifications and diagrams, refer device out of reset and place it in powerdown mode.
to Figure 6 and Figure 7 on page 11.
A powerdown mode is available to reduce power
5.24.3. 3-Wire Control Interface Mode consumption when the part is idle. Putting the device in
When selecting 3-wire mode, the user must ensure that powerdown mode will disable analog and digital circuitry
a rising edge of SCLK does not occur within 300 ns and keep the bus active. For more information
before the rising edge of RST. concerning Reset, Powerup, Powerdown, and
Initialization, refer to “AN332: Universal Programming
3-wire bus mode uses the SCLK, SDIO and SEN pins.
Guide.”
A transaction begins when the system controller drives
SEN low. Next, the system controller drives a 9-bit 5.27. Programming with Commands
control word on SDIO, which is captured by the device
To ease development time and offer maximum
on rising edges of SCLK. The control word is comprised
customization, the Si4720/21 provides a simple yet
of a three bit chip address (A7:A5 = 101b), a read/write
powerful software interface to program the transmitter.
bit (write = 0, read = 1), the chip address (A4 = 0), and a
The device is programmed using commands,
four bit register address (A3:A0).
arguments, properties, and responses.
For write operations, the control word is followed by a
To perform an action, the user writes a command byte
16-bit data word, which is captured by the device on
and associated arguments causing the chip to execute
rising edges of SCLK.
the given command. Commands control actions, such
For read operations, the control word is followed by a as powering up the device, shutting down the device, or
delay of one-half SCLK cycle for bus turnaround. Next, tuning to a station. Arguments are specific to a given
the Si4720/21 drives the 16-bit read data word serially command and are used to modify the command. For
on SDIO, changing the state of SDIO on each rising example, after the TX_TUNE_FREQ command,
edge of SCLK. arguments are required to set the tune frequency. A
A transaction ends when the user sets SEN high, then complete list of commands is available in Table 17,
pulses SCLK high and low one final time. SCLK may “Si471x Command Summary,” on page 30.
either stop or continue to toggle while SEN is high. Properties are a special command argument used to
In 3-wire mode, commands are sent by first writing each modify the default chip operation and are generally
argument to register(s) 0xA1–0xA3, then writing the configured immediately after powerup. Examples of
command word to register 0xA0. A response is properties are TX_PREEMPHASIS and
retrieved by reading registers 0xA8–0xAF. GPO_CONFIGURE. A complete list of properties is
For details on timing specifications and diagrams, refer available in Table 21, “Si472x Property Summary,” on
to Table 6, “3-Wire Control Interface Characteristics,” on page 37.
page 10, Figure 4, “3-Wire Control Interface Write Responses provide the user information and are
Timing Parameters,” on page 10, and Figure 5, “3-Wire echoed after a command and associated arguments are
Control Interface Read Timing Parameters,” on page issued. At a minimum, all commands provide a one-byte
10. status update indicating interrupt and clear-to-send
status information. For a detailed description of using
5.25. GPO Outputs the commands and properties of the Si4720/21, see
The Si4720/21 provides three general-purpose output “AN332: Universal Programming Guide.”
pins. The GPO pins can be configured to output a
constant low, constant high, or high-Z. The GPO pins
are multiplexed with the bus mode pins or DCLK
depending on the application schematic of the device.
GPO2/INT can be configured to provide interrupts for
seek and tune complete, receive signal quality, and
RDS.

Rev. 1.0 35
Si4720/21-B20
6. Commands and Properties

Table 20. Si472x Command Summary

Cmd Name Description
Transmit Commands
Power up device and mode selection. Modes include FM transmit
0x01 POWER_UP
and analog/digital audio interface configuration.
0x10 GET_REV Returns revision information on the device.
0x11 POWER_DOWN Power down device.
0x12 SET_PROPERTY Sets the value of a property.
0x13 GET_PROPERTY Retrieves a property’s value.
0x14 GET_INT_STATUS Read interrupt status bits.
0x15 PATCH_ARGS Reserved command used for patch file downloads.
0x16 PATCH_DATA Reserved command used for patch file downloads.
0x30 TX_TUNE_FREQ Tunes to given transmit frequency.
0x31 TX_TUNE_POWER Sets the output power level and tunes the antenna capacitor.
0x32 TX_TUNE_MEASURE Measure the received noise level at the specified frequency.
Queries the status of a previously sent TX Tune Freq, TX Tune
0x33 TX_TUNE_STATUS
Power, or TX Tune Measure command.
0x34 TX_ASQ_STATUS Queries the TX status and input audio signal metrics.
Queries the status of the RDS Group Buffer and loads new data into
0x35 TX_RDS_BUFF
buffer.
0x36 TX_RDS_PS Set up default PS strings.
0x80 GPIO_CTL Configures GPO1, 2, and 3 as output or Hi-Z.
0x81 GPIO_SET Sets GPO1, 2, and 3 output level (low or high).
Receive Commands
0x01 POWER_UP Power up device and mode selection.
0x10 GET_REV Returns revision information on the device.
0x11 POWER_DOWN Power down device.
0x12 SET_PROPERTY Sets the value of a property.
0x13 GET_PROPERTY Retrieves a property’s value.
0x14 GET_INT_STATUS Reads interrupt status bits.
0x15 PATCH_ARGS Reserved command used for patch file downloads.
0x16 PATCH_DATA Reserved command used for patch file downloads.
0x20 FM_TUNE_FREQ Selects the FM tuning frequency.
0x21 FM_SEEK_START Begins searching for a valid frequency.
Queries the status of previous FM_TUNE_FREQ or FM_-
0x22 FM_TUNE_STATUS
SEEK_START command.
Queries the status of the Received Signal Quality (RSQ) of the cur-
0x23 FM_RSQ_STATUS
rent channel.

36 Rev. 1.0
 Si4720/21-B20
Table 20. Si472x Command Summary (Continued)
Returns RDS information for current channel and reads an entry
0x24 FM_RDS_STATUS
from RDS FIFO (Si4721 only).
0x27 FM_AGC_STATUS Queries the current AGC settings
0x28 FM_AGC_OVERRIDE Override AGC setting by disabling and forcing it to a fixed value
0x80 GPIO_CTL Configures GPO1, 2, and 3 as output or Hi-Z.
0x81 GPIO_SET Sets GPO1, 2, and 3 output level (low or high).

Table 21. Si472x Property Summary

Prop Name Description Default
Transmit Properties
0x0001 GPO_IEN Enables interrupt sources. 0x0000
0x0101 DIGITAL_INPUT _FORMAT Configures the digital input format. 0x0000
Configures the digital input sample rate in 1 Hz steps.
0x0103 DIGITAL_INPUT _SAMPLE_RATE 0x0000
Default is 0.
Sets frequency of the reference clock in Hz. The range is
0x0201 REFCLK_FREQ 31130 to 34406 Hz, or 0 to disable the AFC. Default is 0x8000
32768 Hz.
0x0202 REFCLK_PRESCALE Sets the prescaler value for the reference clock. 0x0001
Enable transmit multiplex signal components.
0x2100 TX_COMPONENT_ENABLE 0x0003
Default has pilot and L-R enabled.
Configures audio frequency deviation level. Units are in
0x2101 TX_AUDIO_DEVIATION 0x1AA9
10 Hz increments. Default is 6825 (68.25 kHz).
Configures pilot tone frequency deviation level. Units are
0x2102 TX_PILOT_DEVIATION 0x02A3
in 10 Hz increments. Default is 675 (6.75 kHz)
Si4721 Only. Configures the RDS/RBDS frequency
0x2103 TX_RDS_DEVIATION deviation level. Units are in 10 Hz increments. Default is 0x00C8
2 kHz.
Configures maximum analog line input level to the
LIN/RIN pins to reach the maximum deviation level pro-
0x2104 TX_LINE_INPUT_LEVEL 0x327C
grammed into the audio deviation property TX Audio
Deviation. Default is 636 mVPK.
Sets line input mute. L and R inputs may be inde-
0x2105 TX_LINE_INPUT_MUTE 0x0000
pendently muted. Default is not muted.
Configures pre-emphasis time constant.
0x2106 TX_PREEMPHASIS 0x0000
Default is 0 (75 µS).
Configures the frequency of the stereo pilot. Default is
0x2107 TX_PILOT_FREQUENCY 0x4A38
19000 Hz.
Enables audio dynamic range control and limiter.
0x2200 TX_ACOMP_ENABLE Default is 2 (limiter is enabled, audio dynamic range 0x0002
control is disabled).
Sets the threshold level for audio dynamic range control.
0x2201 TX_ACOMP_THRESHOLD 0xFFD8
Default is –40 dB.
Sets the attack time for audio dynamic range control.
0x2202 TX_ACOMP_ATTACK_TIME 0x0000
Default is 0 (0.5 ms).

Rev. 1.0 37
Si4720/21-B20
Table 21. Si472x Property Summary (Continued)
Prop Name Description Default
Sets the release time for audio dynamic range control.
0x2203 TX_ACOMP_RELEASE_TIME 0x0004
Default is 4 (1000 ms).
Sets the gain for audio dynamic range control.
0x2204 TX_ACOMP_GAIN 0x000F
Default is 15 dB.
0x2205 TX_LIMITER_RELEASE_TIME Sets the limiter release time. Default is 102 (5.01 ms) 0x0066
Configures measurements related to signal quality met-
0x2300 TX_ASQ_INTERRUPT_SOURCE 0x0000
rics. Default is none selected.
Configures low audio input level detection threshold.
0x2301 TX_ASQ_LEVEL_LOW This threshold can be used to detect silence on the 0x0000
incoming audio.
Configures the duration which the input audio level must
0x2302 TX_ASQ_DURATION_LOW be below the low threshold in order to detect a low audio 0x0000
condition.
Configures high audio input level detection threshold.
0x2303 TX_ASQ_LEVEL_HIGH This threshold can be used to detect activity on the 0x0000
incoming audio.
Configures the duration which the input audio level must
0x2304 TX_ASQ_DURATION_HIGH be above the high threshold in order to detect a high 0x0000
audio condition.
Si4721 Only. Configure RDS interrupt sources. Default
0x2C00 TX_RDS_INTERRUPT_SOURCE 0x0000
is none selected.
0x2C01 TX_RDS_PI Si4721 Only. Sets transmit RDS program identifier. 0x40A7
Si4721 Only. Configures mix of RDS PS Group with
0x2C02 TX_RDS_PS_MIX 0x0003
RDS Group Buffer.
Si4721 Only. Miscellaneous bits to transmit along with
0x2C03 TX_RDS_PS_MISC 0x1008
RDS_PS Groups.
Si4721 Only. Number of times to repeat transmission of
0x2C04 TX_RDS_PS_REPEAT_COUNT a PS message before transmitting the next PS mes- 0x0003
sage.
0x2C05 TX_RDS_PS_MESSAGE_COUNT Si4721 Only. Number of PS messages in use. 0x0001
Si4721 Only. RDS Program Service Alternate Fre-
quency. This provides the ability to inform the receiver of
0x2C06 TX_RDS_PS_AF 0xE0E0
a single alternate frequency using AF Method A coding
and is transmitted along with the RDS_PS Groups.
Si4721 Only. Number of blocks reserved for the FIFO.
0x2C07 TX_RDS_FIFO_SIZE Note that the value written must be one larger than the 0x0000
desired FIFO size.
Receive Properties
0x0001 GPO_IEN Enables interrupt sources. 0x0000
DIGITAL_OUTPUT_
0x0102 Configure digital audio outputs (Si4721 only) 0x0000
FORMAT
DIGITAL_OUTPUT_
0x0104 Configure digital audio output sample rate (Si4721 only) 0x0000
SAMPLE_RATE

38 Rev. 1.0
 Si4720/21-B20
Table 21. Si472x Property Summary (Continued)
Prop Name Description Default
Sets frequency of reference clock in Hz. The range is
0x0201 REFCLK_FREQ 31130 to 34406 Hz, or 0 to disable the AFC. Default is 0x8000
32768 Hz.
0x0202 REFCLK_PRESCALE Sets the prescaler value for RCLK input. 0x0001
0x1100 FM_DEEMPHASIS Sets deemphasis time constant. Default is 75 µs. 0x0002
Sets RSSI threshold for stereo blend (Full stereo above
FM_BLEND_STEREO_THRESH- threshold, blend below threshold). To force stereo set this
0x1105 0x0031
OLD to 0. To force mono set this to 127. Default value is
49 dBµV.
Sets RSSI threshold for mono blend (Full mono below
FM_BLEND_MONO_ threshold, blend above threshold). To force stereo set this
0x1106 0x001E
THRESHOLD to 0. To force mono set this to 127. Default value is
30 dBµV.
Selects the antenna type and the pin to which it is con-
0x1107 FM_ANTENNA_INPUT 0x0000
nected. (Si4721 only).
FM_MAX_TUNE_ Sets the maximum freq error allowed before setting the
0x1108 0x001E
ERROR AFC rail (AFCRL) indicator. Default value is 30 kHz.
FM_RSQ_INT_ Configures interrupt related to Received Signal Quality
0x1200 0x0000
SOURCE metrics.
FM_RSQ_SNR_HI_
0x1201 Sets high threshold for SNR interrupt. 0x007F
THRESHOLD
FM_RSQ_SNR_LO_
0x1202 Sets low threshold for SNR interrupt. 0x0000
THRESHOLD
FM_RSQ_RSSI_HI_
0x1203 Sets high threshold for RSSI interrupt. 0x007F
THRESHOLD
FM_RSQ_RSSI_LO_
0x1204 Sets low threshold for RSSI interrupt. 0x0000
THRESHOLD
FM_RSQ_BLEND_ Sets the blend threshold for blend interrupt when bound-
0x1207 0x0081
THRESHOLD ary is crossed.
Sets the attack and decay rates when entering and leav-
0x1300 FM_SOFT_MUTE_RATE 0x0040
ing soft mute.
FM_SOFT_MUTE_ Sets maximum attenuation during soft mute (dB). Set to 0
0x1302 0x0010
MAX_ATTENUATION to disable soft mute. Default is 16 dB.
FM_SOFT_MUTE_
0x1303 Sets SNR threshold to engage soft mute. Default is 4 dB. 0x0004
SNR_THRESHOLD
FM_SEEK_BAND_ Sets the bottom of the FM band for seek.
0x1400 0x222E
BOTTOM Default is 8750 (87.5 MHz).
Sets the top of the FM band for seek.
0x1401 FM_SEEK_BAND_TOP 0x2A26
Default is 10790 (107.9 MHz).
FM_SEEK_FREQ_ Selects frequency spacing for FM seek.
0x1402 0x000A
SPACING Default value is 10 (100 kHz).
FM_SEEK_TUNE_ Sets the SNR threshold for a valid FM Seek/Tune.
0x1403 0x0003
SNR_THRESHOLD Default value is 3 dB.
FM_SEEK_TUNE_ Sets the RSSI threshold for a valid FM Seek/Tune.
0x1404 0x0014
RSSI_TRESHOLD Default value is 20 dBµV.

Rev. 1.0 39
Si4720/21-B20
Table 21. Si472x Property Summary (Continued)
Prop Name Description Default
0x1500 RDS_INT_SOURCE Configures RDS interrupt behavior (Si4721 only). 0x0000
Sets the minimum number of RDS groups stored in the
RDS_INT_FIFO_
0x1501 receive FIFO required before RDSRECV is set (Si4721 0x0000
COUNT
only).
0x1502 RDS_CONFIG Configures RDS setting (Si4721 only). 0x0000
0x4000 RX_VOLUME Sets the output volume. 0x003F
Mutes the audio output. L and R audio outputs may be
0x4001 RX_HARD_MUTE 0x0000
muted independently.

40 Rev. 1.0
 Si4720/21-B20
7. Pin Descriptions: Si4720/21-GM

GPO3/DCLK
GPO2/INT

LIN/DFS
GPO1
NC
NC 1 20 19 18 17 16
FMI 2 15 RIN/DOUT
RFGND 3 GND 14 LOUT/DFS
TXO 4 PAD 13 ROUT/DIN
RST 5 12 GND
6 7 8 9 10 11 VDD
SEN

SCLK

RCLK

VIO
SDIO

Pin Number(s) Name Description

1, 20 NC No connect. Leave floating.
2 FMI FM RF input.
3 RFGND RF ground. Connect to ground plane on PCB.
4 TXO FM transmit output connection to transmit antenna.
5 RST Device reset (active low) input.
6 SEN Serial enable input (active low).
7 SCLK Serial clock input.
8 SDIO Serial data input/output.
9 RCLK External reference oscillator input.
10 VIO I/O supply voltage.
11 VDD Supply voltage. May be connected directly to battery.
13 ROUT/DIN Right audio line output—digital input data.
14 LOUT/DFS Left audio line output—digital frame synchronization.
15 RIN/DOUT Right audio line input—digital output data.
16 LIN/DFS Left audio line input—digital frame synchronization.
17 GPO3/DCLK General purpose output—digital bit synchronous clock.
18 GPO2/INT General purpose output—interrupt request.
19 GPO1 General purpose output.
12, GND PAD GND Ground. Connect to ground plane on PCB.

Rev. 1.0 41
Si4720/21-B20
8. Ordering Guide

Part Number* Description Package Operating

Type Temperature
Si4720-B20-GM Broadcast FM Radio Transceiver for Portable Applica- QFN –20 to 85 °C
tions Pb-free
Si4721-B20-GM Broadcast FM Radio Transceiver for Portable Applica- QFN –20 to 85 °C
tions with RDS/RBDS Encoder/Decoder Pb-free
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.

42 Rev. 1.0
 Si4720/21-B20
9. Package Markings (Top Marks)
9.1. Top Mark Explanation

Mark Method: YAG Laser

Line 1 Marking: Part Number 20 = Si4720; 21 = Si4721
Firmware Revision 20 = Firmware Revision 2.0
Line 2 Marking: Die Revision B = Revision B Die
TTT = Internal Code Internal tracking code.
Line 3 Marking: Circle = 0.5 mm Diameter Pin 1 Identifier
(Bottom-Left Justified)
Y = Year Assigned by the Assembly House. Corresponds to the last
WW = ‘Workweek significant digit of the year and workweek of the mold date.

9.2. Si4720/21 Top Mark

9.3. Si4721 Top Mark

Rev. 1.0 43
Si4720/21-B20
10. Package Outline: Si4720/21-GM
Figure 26 illustrates the package details for the Si4720. Table 22 lists the values for the dimensions shown in the
illustration.

Figure 26. 20-Pin Quad Flat No-Lead (QFN)

Table 22. Package Dimensions

Symbol Millimeters Symbol Millimeters
Min Nom Max Min Nom Max
A 0.50 0.55 0.60 f 2.53 BSC
A1 0.00 0.02 0.05 L 0.35 0.40 0.45
b 0.20 0.25 0.30 L1 0.00 — 0.10
c 0.27 0.32 0.37 aaa — — 0.05
D 3.00 BSC bbb — — 0.05
D2 1.65 1.70 1.75 ccc — — 0.08
e 0.50 BSC ddd — — 0.10
E 3.00 BSC eee — — 0.10
E2 1.65 1.70 1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

44 Rev. 1.0
 Si4720/21-B20
11. PCB Land Pattern: Si4720/21-GM
Figure 27 illustrates the PCB land pattern details for the Si4720-GM. Table 23 lists the values for the dimensions
shown in the illustration.

Figure 27. PCB Land Pattern

Rev. 1.0 45
Si4720/21-B20

Table 23. PCB Land Pattern Dimensions

Symbol Millimeters Symbol Millimeters
Min Max Min Max
D 2.71 REF GE 2.10 —
D2 1.60 1.80 W — 0.34
e 0.50 BSC X — 0.28
E 2.71 REF Y 0.61 REF
E2 1.60 1.80 ZE — 3.31
f 2.53 BSC ZD — 3.31
GD 2.10 —
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing is per the ANSI Y14.5M-1994 specification.
3. This land pattern design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a fabrication allowance of 0.05 mm.

Note: Solder Mask Design

1. All metal pads are to be non-solder-mask-defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 mm minimum, all the way around the pad.

Notes: Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component standoff.

Notes: Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for small body components.

46 Rev. 1.0
 Si4720/21-B20
12. Additional Reference Resources
 Si47xx Evaluation Board User’s Guide
 AN307: Si4712/13/20/21 Receive Power Scan
 AN332: Universal Programming Guide
 AN341: Si4720/21 Evalution Board Quick Start Guide
 AN383: Universal Antenna Selection and Layout Guidelines
 AN388: Universal Evaluation Board Test Procedure
 Si4720/21 Customer Support Site: www.mysilabs.com
This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA
is required for access. To request access, send mysilabs user name and request for access to
fminfo@silabs.com.

Rev. 1.0 47
 Smart.
Connected.
Energy-Friendly.

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Disclaimer
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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without
further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Without prior
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disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of a Silicon Labs product in such unauthorized applications.

Trademark Information
Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, ClockBuilder®, CMEMS®, DSPLL®, EFM®,
EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®,
Gecko®, Gecko OS, Gecko OS Studio, ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® , Zentri, the Zentri logo and Zentri
DMS, Z-Wave®, and others are trademarks or registered trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings.
Keil is a registered trademark of ARM Limited. Wi-Fi is a registered trademark of the Wi-Fi Alliance. All other products or brand names mentioned herein are trademarks of their respective
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