Freescale Semiconductor, Inc.

MOTOROLA Document order number: MC33888

Rev 3.0, 10/2004
SEMICONDUCTOR TECHNICAL DATA

Product Preview 33888

Quad High-Side and Octal Low-Side 33888A
Switch for Automotive
The 33888 is a single-package combination of a power die with four
discrete high-side MOSFETs (two 10 mΩ and two 40 mΩ) and an integrated SOLID STATE RELAY FOR
IC control die consisting of eight low-side drivers (600 mΩ each) with AUTOMOTIVE APPLICATIONS
appropriate control, protection, and diagnostic features.
Programming, control, and diagnostics are accomplished using a 16-bit SPI
interface. Additionally, each high-side output has its own parallel input for
pulse-width modulation (PWM) control if desired. The low sides share a single
configurable direct input.
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The 33888 is available in two power packages.

Features
• Dual 10 mΩ High Side, Dual 40 mΩ High Side, Octal 600 mΩ Low Side Bottom View Top View
• Full Operating Voltage of 6.0 V to 27 V
• SPI Control of High-Side Overcurrent Limit, High Side Current Sense, PNB SUFFIX FB SUFFIX
APNB SUFFIX CASE 1315-03
Output OFF Open Load Detection, Output ON/OFF Control, Watchdog CASE 1438-06 64-TERMINAL PQFP
Timeout 36-TERMINAL PQFN
• SPI Reporting of Program Status and Fault (12 x 12)
• High-Side Analog Current Feedback with Selectable Ratio
• Enhanced 16 V Reverse Polarity VPWR Protection ORDERING INFORMATION
Temperature
Device Package
Range (TA)

PC33888PNB/R2
36 PQFN
PC33888APNB/R2 -40°C to 125°C
MC33888FB/R2 64 PQFP

33888 Simplified Application Diagram

VPWR

+5.0 V +5.0 V 8 x Relay or LED

33888
FS VDD VPWR
4
IHS0:IHS3 LS4:LS11 Loads
ILS
MCU 4 RST
SPI HS3
WDIN HS2
A/D CSNS2-3 HS1
A/D CSNS0-1 HS0
FSI GND

This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

© Motorola, Inc. 2004 For More Information On This Product,

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Table 1. Features Comparison: 33888 and 33888A

For details,
Parameter Symbol Condition 33888 33888A
see page

Undervoltage Low-Side Output Shutdown VPWRUV – 5.0 V 3.0 V 11

Low-Side Drain-to-Source ON Resistance RDS(ON) VPWR = 4.5 V; Not specified 8.0 Ω 14

VDD = 3.5 V

Recommended Frequency of SPI Operation f SPI Extended Mode, Not specified 2.1 MHz 17
VDD = 3.4 V (max)

VDD VPWR

VIC
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Internal Over/Undervoltage
IUP Regulator Protection

10 mΩ
CS
SCLK
Gate Driver
IDWN SPI
3.0 MHz
Selectable Current Limit HS0
SO
SI
RST Open Load
Detection
WAKE
FS Overtemperature
Logic Detection
IN0 HS0
IN1
IN2 Selectable Output Current
CSNS0-1
Recopy (Analog MUX)
IN3 Gate Control and Fault 10 mΩ
ILS HS1
HS1

Gate Control and Fault 40 mΩ

HS2
HS2
RDWN IDWN
Selectable Output Current
Recopy (Analog MUX)
CSNS2-3

Gate Control and Fault 40 mΩ

HS3 HS3
VIC
WDIN Watchdog
Gate Clamp LS4
Control LS5
FSI LS6
Over-
temperature LS7
LS8
ILIM LS9
LS10
Open Load
LS11
x8

GND

Figure 1. 33888 Simplified Internal Block Diagram

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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Transparent Top View of Package

VPWR
LS11

LS10
GND

GND
VDD

LS9

LS8

LS7

LS6

LS5

LS4
SO

FS
14 13 12 11 10 9 8 7 6 5 4 3 2 1

CS 16 36 WDIN
15 GND
SCLK 17 35 FSI

SI 18 34 RST
(Control Die)
ILS 19 33 WAKE

GND 20 32 GND

IHS3 21 31 IHS1
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IHS2 22 30 IHS0
Internally Connected to VPWR
CSNS2-3 23 29 CSNS0-1

(Power Die)
24 VPWR

25 26 27 28
HS1
HS3

HS2
HS0

TERMINAL DEFINITIONS FOR PQFN

Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Terminal Formal Name Definition
Name
1 FS Fault Status This output terminal is an open drain indication that goes active low when a fault
(Active Low) mode is detected by the device. Specific device fault indication is given via the SO
terminal.

2, 24 VPWR Positive Power Supply These terminal connects to the positive power supply and are the source input of
operational power for the device.

3 LS4 Low-Side Output 4 Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
6 LS6 Low-Side Output 6 current through the connected loads. Each of the outputs is actively clamped at
8 LS8 Low-Side Output 8 53 V. These outputs are current and thermal overload protected. Maximum steady
10 LS10 Low-Side Output 10 state current through each of these outputs is 500 mA.

4, 11, 15, GND Ground These terminals serve as the ground for the source of the low-side output
20, 32 transistors as well as the logic portion of the device.
5 LS5 Low-Side Output 5 Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
7 LS7 Low-Side Output 7 current through the connected loads. Each of the outputs is actively clamped at
9 LS9 Low-Side Output 9 53 V. These outputs are current and thermal overload protected. Maximum steady
12 LS11 Low-Side Output 11 state current through each of these outputs is 800 mA.
13 VDD Digital Drain Voltage (Power) This is an external input terminal used to supply power to the SPI circuit.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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TERMINAL DEFINITIONS FOR PQFN (continued)

Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Terminal Formal Name Definition
Name
14 SO Serial Output This is an output terminal connected to the SPI Serial Data Input terminal of the
MCU or to the SI terminal of the next device in a daisy chain. This output will remain
tri-stated unless the device is selected by a low CS terminal. The output signal
generated will have CMOS logic levels and the output data will transition on the
rising edges of SCLK. The serial output data provides fault information for each
output and is returned MSB first when the device is addressed. OD11 through OD0
are output fault bits for outputs 11 through 0, respectively.
16 CS Chip Select This is an input terminal connected to a chip select output of a microcontroller
(Active Low) (MCU). This IC controls which device is addressed (selected) by pulling the CS
terminal of the desired device logic Low, enabling the SPI communication with the
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device, while other devices on the serial link keep their serial outputs tri-stated. This
input has an internal active pullup and requires CMOS logic levels.
17 SCLK Serial Clock This input terminal is connected to the SCLK terminal of the master MCU, which is
a bit (shift) clock for the SPI port. It transitions one time per bit transferred at an
operating frequency, fSPI, and is idle between command transfers. It is 50% duty
cycle and has CMOS logic levels. This signal is used to shift data to and from the
33888.
18 SI Serial Input This input terminal is connected to the SPI Serial Data Output terminal of the MCU
from which it receives output command data. This input has an internal active
pull-down and requires CMOS logic levels. The serial data transmitted on this line
is a 16-bit control command sent MSB first, which controls the twelve output
channels. Bits D3:D0 control the high-side outputs HS3:HS0, respectively. Bits
D11:D4 control the low-side outputs LS11:LS4, respectively. The MUC will ensure
that data is available on the falling edge of SCLK.
19 ILS Low-Side Input This input terminal is used to directly control a number of the low-side devices as
configured by SPI. This terminal may or may not be activated depending on the
configured state of the internal logic.

21 IHS3 High-Side Input 3 Each high-side input terminal is used to directly control only one designated high-
22 IHS2 High-Side Input 2 side output. These inputs may or may not be activated depending on the configured
30 IHS0 High-Side Input 0 state of the internal logic.
31 IHS1 High-Side Input 1
23 CSNS2-3 Current Sense 2-3 These terminals deliver a ratioed amount of the high-side output current that can be
29 CSNS0-1 Current Sense 0-1 used to generate signal ground referenced output voltages for use by the MCU.
Each respective CSNS terminal can be configured via SPI to deliver current from
either of the two assigned outputs, or the currents could be the sum of the two.
Current from HS0 and/or HS1 are sensed via CSNS0-1. Current from HS2 and/or
HS3 are sensed via CSNS2-3.

25 HS3 High-Side Output 3 Each terminal is the source of a 40 mΩ MOSFET high-side driver, which delivers
28 HS2 High-Side Output 2 current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS2 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.

26 HS1 High-Side Output 1 Each terminal is the source of a 10 mΩ MOSFET high-side driver, which delivers
27 HS0 High-Side Output 0 current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS0 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
33 WAKE Wake This terminal is used to input a logic [1] signal in order to enable the watchdog timer
function. An internal clamp protects the terminal from high voltages when current is
limited with an external resistor. This input has a passive internal pulldown.

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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TERMINAL DEFINITIONS FOR PQFN (continued)

Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Terminal Formal Name Definition
Name
34 RST Reset (Active Low) This input terminal is used to initialize the device configuration and fault registers,
as well as place the device in a low current standby mode. This terminal also starts
the watchdog timeout when transitioned from logic [0] to logic [1]. This terminal
should not be allowed to be at logic [1] until VDD is in regulation. This input has an
internal passive pulldown.
35 FSI Fail-Safe Input The Fail-Safe input terminal level determines the state of the outputs after a
watchdog timeout occurs. This terminal has an internal pullup. If the FSI terminal is
left to float to a logic [1], then HS0 and HS2 will turn on when in the Fail-Safe state.
If the FSI terminal is tied to GND, the watchdog circuit and fail-safe operation will be
disabled, thus allowing operation without a watchdog signal.
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36 WDIN Watchdog Input This input terminal is a CMOS logic level input that is used to monitor system
operation. If the incoming watchdog signal does not transition within the normal
watchdog timeout range, the device will operate in the Fail-Safe mode. This input
has an active internal pulldown.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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CSNS0-1
WAKE

VPWR

VPWR
IHS1
IHS0

HS2
HS2
RST

NC
NC
NC
64
63
62
61
60
59

58
57
56
55
54
53
FSI 1 52 NC
WDIN 2 51 NC
FS 3 50 NC
VPWR 4 49 HS0
LS4 5 48 HS0
GND 6 47 HS0
LS5 7 46 HS0
LS6 8 45 HS0
GND 9 44 HS0
LS7 10 43 HS0
LS8 11 42 HS1
GND 12 41 HS1
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LS9 13 40 HS1
LS10 14 39 HS1
GND 15 38 HS1
LS11 16 37 HS1
VDD 17 36 HS1
SO 18 35 NC
CS 19 34 NC
SCLK 20 33 NC

VPWR 27
HS3 28
HS3 29
NC 30
NC 31
NC 32
SI 21
ILS 22
IHS3 23
IHS2 24
CSNS2-3 25
VPWR 26

TERMINAL DEFINITIONS FOR PQFP

Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Terminal Formal Name Definition
Name
1 FSI Fail-Safe Input The Fail-Safe input terminal level determines the state of the outputs after a
watchdog timeout occurs. This terminal has an internal pullup. If the FSI terminal is
left to float to a logic [1], then HS0 and HS2 will turn on when in the Fail-Safe state.
If the FSI terminal is tied to GND, the watchdog circuit and fail-safe operation will be
disabled, thus allowing operation without a watchdog signal.
2 WDIN Watchdog Input This input terminal is a CMOS logic level input that is used to monitor system
operation. If the incoming watchdog signal does not transition within the normal
watchdog timeout range, the device will operate in the Fail-Safe mode. This input
has an active internal pulldown.
3 FS Fault Status This output terminal is an open drain indication that goes active low when a fault
(Active Low) mode is detected by the device. Specific device fault indication is given via the SO
terminal.

4, 26, 27, VPWR Positive Power Supply These terminal connects to the positive power supply and are the source input of
58, 59 operational power for the device.

5 LS4 Low-Side Output 4 Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
8 LS6 Low-Side Output 6 current through the connected loads. Each of the outputs is actively clamped at
11 LS8 Low-Side Output 8 53 V. These outputs are current and thermal overload protected. Maximum steady
14 LS10 Low-Side Output 10 state current through each of these outputs is 500 mA.

6, 9, 12, 15 GND Ground These terminals serve as the ground for the source of the low-side output
transistors as well as the logic portion of the device.

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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TERMINAL DEFINITIONS FOR PQFP (continued)

Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Terminal Formal Name Definition
Name
7 LS5 Low-Side Output 5 Each low-side terminal is one 0.6 Ω low-side output MOSFET drain, which pulls
10 LS7 Low-Side Output 7 current through the connected loads. Each of the outputs is actively clamped at
13 LS9 Low-Side Output 9 53 V. These outputs are current and thermal overload protected. Maximum steady
16 LS11 Low-Side Output 11 state current through each of these outputs is 800 mA.
17 VDD Digital Drain Voltage (Power) This is an external input terminal used to supply power to the SPI circuit.

18 SO Serial Output This is an output terminal connected to the SPI Serial Data Input terminal of the
MCU or to the SI terminal of the next device in a daisy chain. This output will remain
tri-stated unless the device is selected by a low CS terminal. The output signal
generated will have CMOS logic levels and the output data will transition on the
Freescale Semiconductor, Inc...

rising edges of SCLK. The serial output data provides fault information for each
output and is returned MSB first when the device is addressed. OD11 through OD0
are output fault bits for outputs 11 through 0, respectively.
19 CS Chip Select This is an input terminal connected to a chip select output of a microcontroller
(Active Low) (MCU). This IC controls which device is addressed (selected) by pulling the CS
terminal of the desired device logic Low, enabling the SPI communication with the
device, while other devices on the serial link keep their serial outputs tri-stated. This
input has an internal active pullup and requires CMOS logic levels.
20 SCLK Serial Clock This input terminal is connected to the SCLK terminal of the master MCU, which is
a bit (shift) clock for the SPI port. It transitions one time per bit transferred at an
operating frequency, fSPI, and is idle between command transfers. It is 50% duty
cycle and has CMOS logic levels. This signal is used to shift data to and from the
33888.
21 SI Serial Input This input terminal is connected to the SPI Serial Data Output terminal of the MCU
from which it receives output command data. This input has an internal active
pull-down and requires CMOS logic levels. The serial data transmitted on this line
is a 16-bit control command sent MSB first, which controls the twelve output
channels. Bits D3:D0 control the high-side outputs HS3:HS0, respectively. Bits
D11:D4 control the low-side outputs LS11:LS4, respectively. The MUC will ensure
that data is available on the falling edge of SCLK.
22 ILS Low-Side Input This input terminal is used to directly control a number of the low-side devices as
configured by SPI. This terminal may or may not be activated depending on the
configured state of the internal logic.

23 IHS3 High-Side Input 3 Each high-side input terminal is used to directly control only one designated high-
24 IHS2 High-Side Input 2 side output. These inputs may or may not be activated depending on the configured
61 IHS0 High-Side Input 0 state of the internal logic.
62 IHS1 High-Side Input 1
25 CSNS2-3 Current Sense 2-3 These terminals deliver a ratioed amount of the high-side output current that can be
60 CSNS0-1 Current Sense 0-1 used to generate signal ground referenced output voltages for use by the MCU.
Each respective CSNS terminal can be configured via SPI to deliver current from
either of the two assigned outputs, or the currents could be the sum of the two.
Current from HS0 and/or HS1 are sensed via CSNS0-1. Current from HS2 and/or
HS3 are sensed via CSNS2-3.

28, 29 HS3 High-Side Output 3 Each terminal is the source of a 40 mΩ MOSFET high-side driver, which delivers
56, 57 HS2 High-Side Output 2 current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS2 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
30–35, NC Not Connected These terminals are not connected internally.
50–55

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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TERMINAL DEFINITIONS FOR PQFP (continued)

Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Terminal Formal Name Definition
Name

36–42 HS1 High-Side Output 1 Each terminal is the source of a 10 mΩ MOSFET high-side driver, which delivers
43–49 HS0 High-Side Output 0 current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS0 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
63 WAKE Wake This terminal is used to input a logic [1] signal in order to enable the watchdog timer
function. An internal clamp protects the terminal from high voltages when current is
limited with an external resistor. This input has a passive internal pulldown.
64 RST Reset (Active Low) This input terminal is used to initialize the device configuration and fault registers,
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as well as place the device in a low current standby mode. This terminal also starts
the watchdog timeout when transitioned from logic [0] to logic [1]. This terminal
should not be allowed to be at logic [1] until VDD is in regulation. This input has an
internal passive pulldown.

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating Symbol Value Unit

ELECTRICAL RATINGS
Power Supply Voltage VPWR V
Steady State -16 to 41

Input Terminal Voltage (Note 1) VIN -0.3 to 7.0 V

WAKE Input Terminal Clamp Current IWICI 2.5 mA

Continuous per Output Current (Note 2) IOUTLS mA

Low-Sides 4, 6, 8, 10 500
Low-Sides 5, 7, 9, 11 800
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Continuous per Output Current (Note 3) IOUTHS A

High-Sides 0, 1 10
High-Sides 2, 3 5.0

Output Clamp Energy mJ

High-Sides 0, 1 (Note 4) EHS 450
High-Sides 2, 3 (Note 5) EHS 120
Low-Sides (Note 6) ELS 50

ESD Voltage V
Human Body Model (Note 7) VESD1 ±2000
Machine Model (Note 8) VESD2 ±200

Notes
1. Exceeding voltage limits on SCLK, SI, CS, WDIN, RST, IHS, FSI, or ILS terminals may cause a malfunction or permanent damage to the
device.
2. Continuous low-side output current rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient
temperature will require calculation of maximum output current using package thermal resistance.
3. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Operation at 125°C ambient
temperature will require calculation of maximum output current using package thermal resistance.
4. Active HS0 and HS1 clamp energy using the following conditions: single nonrepetitive pulse, VPWR = 16.0 V, L = 40 mH, TJ = 150°C.
5. Active HS2 and HS3 clamp energy using the following conditions: single nonrepetitive pulse, VPWR = 16.0 V, L = 10 mH, TJ = 150°C.
6. Active low-side clamp energy using the following conditions: single nonrepetitive pulse, 450 mA, TJ = 150°C.
7. ESD1 testing is performed in accordance with the Human Body Model (CZAP =100 pF, RZAP = 1500 Ω).
8. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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MAXIMUM RATINGS (continued)

All voltages are with respect to ground unless otherwise noted.
Rating Symbol Value Unit

THERMAL RATINGS
Operating Temperature °C
Ambient TA -40 to 125
Junction TJ -40 to 150

Storage Temperature TSTG -55 to 150 °C

Control Die Thermal Resistance (Note 9) RθCJC °C/W

PQFP
One Low-Side ON 12.5
Two Low-Side ON 9.3
Three Low-Side ON 7.3
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Four Low Side ON 5.9

All Low-Sides ON 3.2
PQFN
One Low-Side ON 8.6
Two Low-Side ON 6.0
Three Low-Side ON 4.6
Four Low Side ON 3.8
All Low-Sides ON 2.0

Power Die Thermal Resistance (Note 9) RθPJC °C/W

PQFP
One High-Side 2, 3 ON 0.5
All High-Sides ON 0.15
PQFN
One High-Side 2, 3 ON 0.5
All High-Sides ON 0.1

Thermal Resistance, Junction to Ambient, Natural Convection, Four-Layer RθJA °C/W

Board (Note 9) 33
PQFP 37
PQFN
Peak Terminal Reflow Temperature During Solder Mounting (Note 10) TSOLDER °C
PQFP 225
PQFN 240

Notes
9. Board dimensions are 8.0 cm x 8.0 cm x 1.5 mm with a 300 mm2 copper area on the bottom layer.
10. Terminal soldering temperature limit is 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.

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STATIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

POWER INPUT
Supply Voltage Range VPWR V
Fully Operational 6.0 – 27

VPWR Supply Current IPWR(ON) mA

TJ > 125°C – 17 25

TJ ≤ 125°C – – 20

VPWR Standby Current (All Outputs OFF, Open Load Detection Disabled, IPWR(SBY) mA
WAKE = H, RST = H)
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TJ > 125°C – 4.2 7.0

TJ ≤ 125°C – 2.9 5.0

Sleep State Supply Current (VPWR < 12.6 V, RST < 0.5 V, WAKE < 0.5 V, IPWR(SS) µA
HS[0:3] = 0 V) (Note 11)
TJ = 85°C – – 80
TJ = 25°C – 1.0 25

Logic Supply Voltage Range VDD 4.5 5.0 5.5 V

Logic Supply Current IDD(ON) mA

TJ > 125°C – 4.2 7.0
TJ ≤ 125°C – 2.9 5.0

Logic Supply Sleep State Current IDD(SS) – – 5.0 µA

Sleep State Low-Side Output Leakage Current (per Low-Side Output, ISLK(SS) µA
RST = LOW)
TJ = 85°C – – 3.0
TJ = 25°C – – 1.0

Overvoltage Shutdown Threshold VPWROV 28.5 32 36 V

Overvoltage Shutdown Hysteresis VPWROV(HYS) 0.2 0.6 1.5 V

Undervoltage High-Side Output Shutdown (Note 12) VPWRUV 5.0 5.6 6.0 V

Undervoltage Low-Side Output Shutdown VPWRUV V

APNB Suffix Only (Note 12) 3.0 4.0 4.4
PNB and FB Suffixes 5.0 5.6 6.0

Undervoltage High-Side Shutdown Hysteresis VPWRUV(HYS) 0.1 0.3 0.5 V

Notes
11. This parameter is tested at 125°C with a maximum value of 10 µA.
12. SPI/IO and internal logic operational. Outputs will recover in instructed state when VPWR voltage level returns to normal as long as the level
does not go below VPWRUV.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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STATIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

POWER INPUT (continued)

Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) CSR[0:1] –
CSNS0-1/HS0, CSNS0-1/HS1 – 1/1400 –

Current Sense Ratio (CSR[0:1] ) Accuracy CSR[0:1]_ACC %

HS[0:1] Output Current
1.0 A -35 – 35
2.0 A -19 – 19
5.0 A -14 – 14
6.5 A -12 – 12
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10 A -12 – 12

Current Sense Ratio (VPWR = 9.0 V – 16 V, CSNS < 4.5 V) CSR –

CSNS2-3/HS2, CSNS2-3/HS3 – 1/880 –

Current Sense Ratio (CSR[2:3] ) Accuracy CSR[2:3]_ACC %

HS[2:3] Output Current
0.5 A -30 – 30
1.0 A -19 – 19
3.0 A -13.5 – 13.5
3.7 A -12 – 12
5.0 A -9.0 – 9.0

Current Sense Clamp Voltage VSENSE V

ICNS = 15 mA Generated by the Device 4.5 6.0 7.0

HS0 AND HS1 POWER OUTPUTS

Drain-to-Source ON Resistance (IOUT = 5.5 A) RDS(ON) Ω
TJ = 25°C
VPWR = 6.0 V – – 0.02
VPWR = 9.0 V – – 0.01
VPWR = 13 V – – 0.01
TJ = 150°C
VPWR = 6.0 V – – 0.034
VPWR = 9.0 V – – 0.017
VPWR = 13 V – – 0.017

Reverse Battery Source-to-Drain ON Resistance (IOUT = -5.5 A, TJ = 25°C) RDS(ON)REV Ω

VPWR = -12 V – – 0.02

Output Self-Limiting Peak Current ILIM(PK) A

Outputs ON, VOUT = VPWR -2.0 V 33 49 66

Output Self-Limiting Sustain Current ILIM(SUS) A

Outputs ON, VOUT = VPWR -2.0 V 13 25 34

Open Load Detection Current (Note 13) IOLDC 30 – 100 µA

Notes
13. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.

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STATIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

HS0 AND HS1 POWER OUTPUTS (continued)

Output Fault Detection Threshold (Note 14) VOFD(THRES) V
Output Programmed OFF 2.0 3.0 4.0

Output Negative Clamp Voltage VCL V

0.5 A < IOUT < 2.0 A, Output OFF -20 – –

Overtemperature Shutdown (Outputs OFF) (Note 15) TSD 160 175 190 °C

Overtemperature Shutdown Hysteresis (Note 15) TSD(HYS) 10 – 30 °C

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HS2 AND HS3 POWER OUTPUTS

Drain-to-Source ON Resistance (IOUT = 4.5 A) RDS(ON) Ω
TJ = 25°C
VPWR = 6.0 V – – 0.08
VPWR = 9.0 V – – 0.04
VPWR = 13 V – – 0.04
TJ = 150°C
VPWR = 6.0 V – – 0.136
VPWR = 9.0 V – – 0.068
VPWR = 13 V – – 0.068

Reverse Battery Source-to-Drain ON Resistance (IOUT = 4.5 A, TJ = 25°C) RDS(ON)REV Ω

VPWR = -12 V – – 0.08

Output Self-Limiting Peak Current ILIM(PK) A

Outputs ON, VOUT = VPWR -2.0 V 15 23 35

Output Self-Limiting Sustain Current ILIM(SUS) A

Outputs ON, VOUT = VPWR -2.0 V 6.0 10 15

Open Load Detection Current (Note 16) IOLDC 25 – 100 µA

Output Fault Detection Threshold (Note 17) VOFD(THRES) V

Outputs Programmed OFF 2.0 3.0 4.0

Output Negative Clamp Voltage VCL V

0.5 A < IOUT < 2.0 A, Outputs OFF -20 – –

Overtemperature Shutdown (Outputs OFF) (Note 18) TSD 160 170 190 °C

Overtemperature Shutdown Hysteresis (Note 18) TSD(HYS) 10 – 30 °C

Notes
14. Output fault detection threshold with outputs programmed OFF. For the Low-Side Outputs, fault detection thresholds are the same for output
open and battery shorts.
15. Guaranteed by design. Not production tested.
16. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.
17. Output fault detection threshold with outputs programmed OFF.
18. Guaranteed by design. Not production tested.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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STATIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

LOW-SIDE POWER OUTPUTS

Drain-to-Source ON Resistance (IOUT = 0.3 A) RDS(ON) Ω
TJ = 25°C
VPWR = 4.5 V; VDD = 3.5 V, 33888A Only – – 8.0
VPWR = 6.0 V – – 1.0
VPWR = 9.0 V – – 0.7
VPWR = 13 V – – 0.6
TJ = 150°C
VPWR = 4.5 V; VDD = 3.5 V, 33888A Only – – 8.0
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VPWR = 6.0 V – – 1.8

VPWR = 9.0 V – – 1.1
VPWR = 13 V – – 0.9

Output Self-Limiting Current (Outputs Programmed ON, VOUT = 3.0 V) ILIM A

Low-Side 4, 6, 8, 10 0.5 0.9 1.5
Low-Side 5, 7, 9, 11 0.8 1.3 2.0

Output OFF Open Load Detection Current (Note 19) IOLDC µA

Output Programmed OFF, VOUT = 3.0 V 25 50 100

Output Fault Detection Threshold (Note 20) VOFD(THRES) V

Output Programmed OFF 2.0 3.0 4.0

Output Clamp Voltage VCL V

2.0 mA < IOUT < 200 mA, Outputs OFF 41 53 60

Low-Side Body Diode Voltage (I = -300 mA, TJ = 125°C) VBD 0.5 0.7 0.9 V

Overtemperature Shutdown (Outputs OFF) (Note 21) TLIM 160 170 190 °C

Overtemperature Shutdown Hysteresis (Note 21) TLIM(HYS) 10 20 30 °C

Notes
19. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.
20. Output fault detection threshold with outputs programmed OFF. For the low-side outputs, fault detection thresholds are the same for output
open and battery shorts.
21. Guaranteed by design. Not production tested.

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STATIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

CONTROL INTERFACE
Input Logic High Voltage (Note 22) VIH 0.7 VDD – – V

Input Logic Low Voltage (Note 22) VIL – – 1.0 V

Input Logic Voltage Hysteresis (SI, CS, SCLK, IHS[0:3], ILS) (Note 23) VIN(HYS) 100 350 750 mV

Input Logic Pulldown Current (SI, SCLK, IHS[0:3], ILS, WDIN) IDWN 5.0 – 20 µA

Input Logic Pulldown Resistor (WAKE, RST) RDWN 100 200 400 kΩ

Input Logic Pullup Current (CS, VIN = 0.7 VDD) (Note 24) IUPC 5.0 – 20 µA
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Input Logic Pullup Current (FSI, VIN = 3.5 V) IUPF 5.0 – 20 µA

Wake Input Clamp Voltage (IWICI < 2.5 mA) (Note 25) VWIC 7.0 – 14 V

Wake Input Forward Voltage (IWICI = -2.5 mA) VWIF -2.0 – -0.3 V

SO High-State Output Voltage (IOH = 1.0 mA) VSOH 0.8 VDD – – V

FS, SO Low-State Output Voltage (IOL = -1.6 mA) VSOL – 0.2 0.4 V

SO Tri-State Leakage Current (CS ≥ 3.5 V) ISOLK -5.0 0 5.0 µA

Input Capacitance (Note 26) CIN – 4.0 12 pF

SO, FS Tri-State Capacitance (Note 23) CSO – – 20 pF

Notes
22. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IHS[0:3], ILS, WAKE, and WDIN input signals. The WAKE,
FSI, and RST signals are derived from an internal supply.
23. Parameter is guaranteed by design but is not production tested.
24. CS is pulled up to VDD.
25. The current must be limited by a series resistor when using voltages higher than the WICV.
26. Input capacitance of SI, CS, SCLK, RST, IHS[0:3], ILS, WAKE, and WDIN. This parameter is guaranteed by process monitoring but is not
production tested.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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DYNAMIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

POWER OUTPUT TIMING

High-Side Output Rising Fast Slew Rate (Note 27) SRR_FAST V/µs
6.0 V < VPWR < 9.0 V 0.03 – 0.6
9.0 V < VPWR < 16 V 0.05 0.5 0.8
16 V < VPWR < 27 V 0.1 – 1.1

High-Side Output Rising Slow Slew Rate (Note 28) SRR_SLOW V/µs
6.0 V < VPWR < 9.0 V 0.01 – 0.14
9.0 V < VPWR < 16 V 0.01 0.08 0.18
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16 V < VPWR < 27 V 0.01 – 0.2

High-Side Output Falling Fast Slew Rate (Note 27) SRF_FAST V/µs
6.0 V < VPWR < 9.0 V 0.2 – 1.0
9.0 V < VPWR < 16 V 0.3 0.8 1.5
16 V < VPWR < 27 V 0.5 – 2.2

High-Side Output Falling Slow Slew Rate (Note 28) SRF_SLOW V/µs
6.0 V < VPWR < 9.0 V 0.05 – 0.3
9.0 V < VPWR < 16 V 0.08 0.15 0.4
16 V < VPWR < 27 V 0.08 – 0.5

High-Side Output Turn ON Delay Time (Note 29) t DLY(ON) 5.0 30 150 µs

High-Side Output Turn OFF Delay Time (Note 30) t DLY(OFF) 5.0 80 150 µs

Low-Side Output Falling Slew Rate (Note 31) SRF 0.5 3.0 10 V/µs

Low-Side Output Rising Slew Rate (Note 31) SRR 1.0 6.0 20 V/µs

Low-Side Output Turn ON Delay Time (Note 32) t DLY(ON) 0.5 2.0 10 µs

Low-Side Output Turn OFF Delay Time (Note 33) t DLY(OFF) 0.5 4.0 10 µs

Low-Side Output Fault Delay Timer (Note 34) t DLY(FS) 70 150 250 µs

Watchdog Timeout (Note 35) t WDTO 340 584 770 ms

Notes
27. High-side output rise and fall fast slew rates measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR -3.0 V (see Figure 2,
page 18). These parameters are guaranteed by process monitoring.
28. High-side output rise and fall slow slew rates measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR -3.0 V (see
Figure 2, page 18). These parameters are guaranteed by process monitoring.
29. High-side output turn-ON delay time measured from 50% of the rising IHS to 0.5 V of output OFF with RL = 27 Ω resistive load (see Figure 2,
page 18).
30. High-side output turn-OFF delay time measured from 50% of the falling IHS to VPWR -2.0 V of the output OFF with RL = 27 Ω resistive load
(see Figure 2, page 18).
31. Low-side output rise and fall slew rates measured across a 5.0 Ω resistive load at low-side output = 10% to 90% (see Figure 3, page 18).
32. Low-side output turn-ON delay time measured from 50% of the rising ILS to 90% of VOUT with RL = 27 Ω resistive load (see Figure 3,
page 18).
33. Low-side output turn-OFF delay time measured from 50% of the falling ILS to 10% of VOUT with RL = 27 Ω resistive load (see Figure 3,
page 18). These parameters are guaranteed by process monitoring.
34. Propagation time of Short Fault Disable Report Delay measured from rising edge of CS to output disabled, low-side = 5.0 V, and device
configured for low-side output overcurrent latchoff using CLOCCR.
35. Watchdog timeout delay is measured from the rising edge of WAKE or RST from the sleep state to the HS[0:1] turn-ON with the outputs
driven OFF and the FSI floating. The accuracy of t WDTO is maintained for all configured watchdog timeouts.

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DYNAMIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 27 V, 4.5 V ≤ VDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

POWER OUTPUT TIMING (continued)

Peak Current Limit Timer (Note 36) t PCT 40 70 100 ms

Direct Input Switching Frequency (Note 37) f PWM – 125 – Hz

SPI INTERFACE TIMING (Note 38)

Recommended Frequency of SPI Operation f SPI MHz
Normal Mode – – 3.0
Extended Mode: VDD = 3.4 V; VPWR = 4.5 V, APNB Suffix Only – – 2.1
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Required Low State Duration for RST (Note 39) t WRST – 50 167 ns

Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 40) t CS – – 300 ns

Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 40) t ENBL – – 5.0 µs

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 40) t LEAD – 50 167 ns

Required High State Duration of SCLK (Required Setup Time) (Note 40) t WSCLKh – – 167 ns

Required Low State Duration of SCLK (Required Setup Time) (Note 40) t WSCLKl – – 167 ns

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 40) t LAG – 50 167 ns

SI to Falling Edge of SCLK (Required Setup Time) (Note 40) t SI(SU) – 25 83 ns

Falling Edge of SCLK to SI (Required Hold Time) (Note 40) t SI(HOLD) – 25 83 ns

SO Rise Time t RSO ns

CL = 200 pF – 25 50

SO Fall Time t FSO ns

CL = 200 pF – 25 50

SI, CS, SCLK, Incoming Signal Rise Time (Note 41) t RSI – – 50 ns

SI, CS, SCLK, Incoming Signal Fall Time (Note 41) t FSI – – 50 ns

Time from Falling Edge of CS to SO Low Impedance (Note 42) t SO(EN) – – 145 ns

Time from Rising Edge of CS to SO High Impedance (Note 43) t SO(DIS) – 65 145 ns

Time from Rising Edge of SCLK to SO Data Valid (Note 44) t VALID ns
0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF – 65 105

Notes
36. t PCT measured from the rising edge of CS to 90% of ILIMPKHS[x,x] when the peak current limit is enabled.
37. This frequency is a typical value. Maximum switching frequencies are dictated by the turn-ON delay, turn-OFF delay, output rise and fall
times, and the maximum allowable junction temperature.
38. Symmetrical 50% duty cycle SCLK clock period of 333 ns.
39. RST low duration measured with outputs enabled and going to OFF or disabled condition.
40. Maximum setup time required for the 33888 is the minimum guaranteed time needed from the MCU.
41. Rise and fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
42. Time required for output status data to be available for use at SO. 1.0 kΩ pullup on CS.
43. Time required for output status data to be terminated at SO. 1.0 kΩ pullup on CS.
44. Time required to obtain valid data out from SO following the rise of SCLK.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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Timing Diagrams

Direct input
Direct Inputor
or spi
SPI bit
Bit

V PWR
VPWR
VVPWR - 0.5V
PWR -0.5 V SRF_SLOW
SRf_slow
SRR_SLOW
SRr_slow
VPWR
VPWR -3.0- 3V
V
SR
SRf_fast
F_FAST

SRr_fast
SRR_FAST
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0.5 V
0.5V

t DLY(ON) Tdly(off)
t DLY(OFF)
Tdly (on)
Figure 2. Output Slew Rates and Time Delays, High Side

Direct input
Direct Inputor
orSPI bit
SPI Bit

V
PWR
VPWR
90%
90%

SRf
SRF
SRr
SRR

10%
10%

Tdly(on)
t DLY(ON) tTdly(off)
DLY(OFF)

Figure 3. Output Slew Rates and Time Delays, Low Side

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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
This 33888 is a single-package combination of a power die simplified application diagram, page 2). The device is useful in
with four discrete high-side MOSFETs and an integrated IC body control, instrumentation, and other high-power switching
control die consisting of eight low-side drivers with appropriate applications and systems.
control, protection, and diagnostic features. The high-side
The 33888 is available in two packages: a power-enhanced
drivers are useful for both internal and external vehicle lighting
12 x 12 nonleaded Power QFN package with exposed tabs and
applications as well as capable of driving inductive solenoid
a 64-lead Power QFP plastic package. Both packages are
loads. The low-side drivers are capable of controlling low-
intended to be soldered directly onto the printed circuit board.
current on/off type inductive loads, such as relays and
solenoids as well as LED indicators and small lamps (see The 33888 differs from the 33888A as explained in Table 1,
page 2.

FUNCTIONAL DESCRIPTION
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SPI Interface and Protocol Description Serial Output (SO)

The SPI interface has full duplex, three-wire synchronous The SO data terminal is a tri-stateable output from the shift
data transfer and has four I/O lines associated with it: Serial register. The SO terminal remains in a high-impedance state
Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip until the CS terminal is put into a logic [0] state. The SO data
Select (CS). report the status of the outputs as well as provide the capability
to reflect the state of the direct inputs. The SO terminal changes
The SI/SO terminals of the 33888 follow a first-in first-out states on the rising edge of SCLK and reads out on the falling
(D15/D0) protocol with both input and output words transferring edge of SCLK. When an output is ON or OFF and not faulted,
the most significant bit first. All inputs are compatible with 5.0 V the corresponding SO bit, OD11:OD0, is a logic [0]. If the output
CMOS logic levels. During SPI output control, a logic [0] in a is faulted, the corresponding SO state is a logic [1]. SO
message word will result in the designated output being turned OD14:OD12 reflect the state of six various inputs (three at a
off. Similarly, a logic [1] will turn on a corresponding output. time) depending upon the reported state of the previously
The SPI lines perform the following functions: written watchdog bit OD15.

Serial Clock (SCLK) Chip Select (CS)

The SCLK terminal clocks the internal shift registers of the The CS terminal enables communication with the master
33888. The serial input (SI) terminal accepts data into the input microcontroller (MCU). When this terminal is in a logic [0] state,
shift register on the falling edge of the SCLK signal while the the 33888 is capable of transferring information to and receiving
serial output terminal (SO) shifts data information out of the SO information from the MCU. The 33888 latches in data from the
line driver on the rising edge of the SCLK signal. It is important input shift registers to the addressed registers on the rising
that the SCLK terminal be in a logic [0] state whenever the chip edge of CS. The 33888 transfers status information from the
select (CS) makes any transition. For this reason, it is power outputs to the shift registers on the falling edge of CS.
recommended that the SCLK terminal be kept in a logic [0] state The output driver on the SO terminal is enabled when CS is
as long as the device is not accessed (CS in logic [1] state). logic [0]. CS is only transitioned from a logic [1] state to a
SCLK has an active internal pulldown, IDWN. When CS is logic [0] state when SCLK is a logic [0]. CS has an active
logic [1], signals at the SCLK and SI terminals are ignored and internal pullup, IUP.
SO is tri-stated (high impedance). (See Figures 4 and 5 on The 33888 is capable of communicating directly with the
page 20.) MCU via the 16-bit SPI protocol as described in the next
section.
Serial Interface (SI)
This is a serial interface (SI) command data input terminal.
Each SI bit is read on the falling edge of SCLK. A 16-bit stream
of serial data is required on the SI terminal, starting with D15 to
D0. The 12 outputs of the 33888 are configured and controlled
using the 3-bit addressing scheme and the 12 assigned data
bits designed into the 33888. SI has an active internal pulldown,
IDWN.

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CSB
CS

SCLK

SI D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SO OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0

Notes 1. RST is in a logic [1] state during the above operation.

2. D15:D0 relate to the most recent ordered entry of program data into the 33888.
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3. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the 33888.

Figure 4. Single 16-Bit Word SPI Communication

CS
CSB

SCLK

SI D15 D14 D13 D2 D1 D0 D15* D14* D13* D2* D1* D0*

SO OD15 OD14 OD13 OD2 OD1 OD0 D15 D14 D13 D2 D1 D0

Notes 1. RST is a logic [1] state during the above operation.

2. D15:D0 relate to the most recent ordered entry of program data into the 33888.
3. D15*:D0* relate to the first 16 bits of ordered entry data out of the 33888.
4. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the 33888.

Figure 5. Multiple 16-Bit Word SPI Communication

Serial Input Communication

SPI communication is accomplished using 16-bit messages. Multiple messages can be transmitted in succession to
A message is transmitted by the MCU starting with the MSB, accommodate those applications where daisy chaining is
D15, and ending with the LSB, D0 (refer to Table 2, page 21). desirable or to confirm transmitted data, as long as the
Each incoming command message on the SI terminal can be messages are all multiples of 16 bits. Any attempt made to latch
interpreted using the following bit assignments: the first twelve in a message that is not 16 bits will be ignored.
LSBs, D11:D0, control each of the twelve outputs; the next
The 33888 has six registers that are used to configure the
three bits, D14:D12, determine the command mode; and the
device and control the state of the four high-side and eight
MSB, D15, is the watchdog bit.
low-side outputs (Table 3, page 21). The registers are
addressed via D14:D12 of the incoming SPI word (Table 2,
page 21).

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. Table 2. SI Message Bit Assignment (continued)

Table 2. SI Message Bit Assignment
Bit Sig SI Msg Bit Message Bit Description
Bit Sig SI Msg Bit Message Bit Description
D5 Used to configure Low-Side Output LS5
MSB D15 Watchdog in: toggled to satisfy watchdog (Watchdog timeout MSB during WDCSCR
requirements. configuration).
D14:12 Register address bits. D4 Used to configure Low-Side Output LS4
(Watchdog timeout LSB during WDCSCR
D11 Used to configure Low-Side Output LS11.
configuration).
D10 Used to configure Low-Side Output LS10. D3 Used to configure High-Side Output HS3.
D9 Used to configure Low-Side Output LS9. D2 Used to configure High-Side Output HS2.
D8 Used to configure Low-Side Output LS8. D1 Used to configure High-Side Output HS1.
D7 Used to configure Low-Side Output LS7. LSB D0 Used to configure High-Side Output HS0.
D6 Used to configure Low-Side Output LS6.
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Table 3. Serial Input Address and Configuration Bit Map

SI WD Address Low-Side High-Side

Register D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SOCR x 0 0 0 LS11 LS10 LS9 LS8 LS7 LS6 LS5 LS4 HS3 HS2 HS1 HS0
DICR x 1 0 0 PWB11 PWB10 PWB9 PWB8 PWB7 PWB6 PWB5 PWB4 PWB3 PWB2 PWB1 PWB0
LFCR x 0 1 0 A/OB11 A/OB10 A/OB9 A/OB8 A/OB7 A/OB6 A/OB5 A/OB4 A/OB3 A/OB2 A/OB1 A/OB0
WDCSCR x 1 1 0 NA NA NA NA NA NA WDH WDL CS3 CS2 CS1 CS0
OLCR x 0 0 1 OL11 OL10 OL9 OL8 OL7 OL6 OL5 OL4 OLB3 OLB2 OLB1 OLB0
CLOCCR x 1 0 1 OC11 OC10 OC9 OC8 OC7 OC6 OC5 OC4 ILIM3 ILIM2 ILIM1 ILIM0
NOT
x 0 1 1 – – – – – – – – – – – –
USED
TEST x 1 1 1 – – – – – – – – ILIMPK WD ILIM OT

x=Don’t care.
NA=Not applicable.

Device Register Addressing

The following section describes the possible register Address 010—Logic Function Control Register (LFCR)
addresses and their impact on device operation.
The LFCR register is used by the MCU to configure the
relationship between SOCR bits D11:D0 and the direct inputs
Address 000—SPI Output Control Register (SOCR)
IHS[0:3] and ILS. While addressing this register (if the direct
The SOCR register allows the MCU to control the outputs via inputs were enabled for direct control with the DICR), a logic [1]
the SPI. Incoming message bits D3:D0 reflect the desired on any or all of the D3:D0 bits will result in a Boolean AND of
states of high-side outputs HS3:HS0. Message bits D11:D4 the IHS[0:3] terminal(s) with its (their) corresponding D3:D0
reflect the desired state of low-side outputs LS11:LS4, message bit(s) when addressing the SOCR. A logic [1] on any
respectively. or all of the D11:D4 bits will result in a Boolean AND of the ILS
and the corresponding D11:D4 message bits when addressing
Address 100—Direct Input Control Register (DICR) the SOCR. Similarly, a logic [0] on the D3:D0 bits will result in
a Boolean OR of the IHS[0:3] terminal(s) with their
The DICR register is used by the MCU to enable direct input corresponding message bits when addressing the SOCR
control of the outputs. For the outputs, a logic [0] on bits D11:D0 register, and the ILS will be Boolean ORed with message bits
will enable the corresponding output for direct control. A D11:D4 when addressing the SOCR register (if ILS is enabled).
logic [1] on a D11:D0 bit will disable the output from direct
control.

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Address 110—Watchdog and Current Sense Configuration Address 001—Open Load Configuration Register (OLCR)
Register (WDCSCR)
The OLCR register allows the MCU to configure each of the
The WDCSCR register is used by the MCU to configure the outputs for open load fault detection. While in this mode, a
watchdog timeout and the CSNS0-1 and CSNS2-3 terminals. logic [1] on any of the D3:D0 message bits will disable the
The watchdog timeout is configured using bits D4 and D5. The corresponding outputs’ circuitry that allows the device to detect
state of D4 and D5 determine the divided value of the WDTO. open load faults while the output is OFF. For the low-side
For example, if D5 and D4 are logic [0] and logic [0], drivers, a logic [1] on any of the D11:D4 bits will enable the
respectively, then the WDTO will be in the default state as open load detection circuitry. This feature allows the MCU to
specified in Table 3, page 21. A D5 and a D4 of logic [0] and minimize load current in some applications and may be useful
logic [1] will result in a watchdog timeout of WDTO ÷ 2. to diagnose output shorts to battery (for HS).
Similarly, a D5 and a D4 of logic [1] and logic [0] result in a
watchdog timeout of WDTO ÷ 4, and a D5 and a D4 of logic [1] Address 101—Current Limit Overcurrent Configuration
and logic [1] result in a watchdog timeout of WDTO ÷ 8. Note Register (CLOCCR)
that when D5 and D4 bits are programmed for the desired
watchdog timeout period, the WD bit (D15) should be toggled The CLOCCR register allows the MCU to individually
as well to ensure that the new timeout period is programmed at override the peak current limit levels for each of the high-side
outputs. A logic [1] on any or all of the D3:D0 bit(s) results in the
Freescale Semiconductor, Inc...

the beginning of a new count sequence.

corresponding HS3:HS0 output terminals to current limit at the
CSNS0-1 is the current sense output for the HS0 and HS1 sustain current limit level. This register also allows the MCU to
outputs. Similarly, the CSNS2-3 terminal is the current sense enable or disable the overcurrent shutdown of the low-side
output for the HS2 and HS3 outputs. In this mode, a logic [1] on output terminals. A logic [1] on any or all of the D11:D4
any or all of the message bits that control the high-side outputs message bit(s) will result in the corresponding LS11:LS4
will result in the sensed current from the corresponding output terminals latching off if the current exceeds ILIM after a timeout
being directed out of the appropriate CSNS output. For of t DLY(FS).
example, if D1 and D0 are both logic [1], then the sensed
current from HS0 and HS1 will be summed into the CSNS0-1.
Address 011—Not Used
If D2 is logic [1] and D3 is logic [0], then only the sensed current
from HS2 will be directed out of CSNS2-3. Not currently used.

Address 111—TEST
The TEST register is reserved for test and is not accessible
via SPI during normal operation.

Serial Output Communication (Devise Status

Return Data)
When the CS terminal is pulled low, the output status register bits indicating that the respective output experienced a fault
for each output is loaded into the output register and the fault condition prior to the CS transition. Any bits clocked out of the
data is clocked out MSB (OD15) first as the new message data SO terminal after the first 16 will be representative of the initial
is clocked into the SI terminal. message bits that were clocked into the SI terminal since the CS
terminal first transitioned to a logic [0]. This feature is useful for
OD15 reflects the state of the watchdog bit (D15) that was
daisy chaining devices as well as message verification.
addressed during the prior SOCR communication (refer to
Table 4, page 23). If bit OD15 is logic [0], then the three MSBs Following a CS transition logic [0] to logic [1], the device
OD14:OD12 will reflect the logic states of the IHS0, IHS1, and determines if the message was of a valid length (a valid
FSI terminals, respectively. If bit OD15 is logic [1], then the message length is one that is a multiple of 16 bits) and if so,
same three MSB bits will reflect the logic states of the IHS2, latches the data into the appropriate registers. At this time, the
IHS3, and WAKE terminals. The next twelve bits clocked out of SO terminal is tri-stated and the fault status register is now able
SO following a low transition of the CS terminal (OD11:OD0) to accept new fault status information.
will reflect the state of each output, with a logic [1] in any of the

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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Table 4. Serial Output Bit Assignment Table 4. Serial Output Bit Assignment (continued)
SO Message Bit Description
SO Message Bit Description Bit Sig
Bit Sig Msg Bit
Msg Bit
MSB OD9 Reports the absence or presence of a fault on LS9.
OD15 Reflects the state of the Watchdog bit from the
previously clocked-in message. OD8 Reports the absence or presence of a fault on LS8.
OD14 If OD15 is logic [0], then this bit will reflect the state OD7 Reports the absence or presence of a fault on LS7.
of the direct input IHS0. If OD15 is logic [1], then this
bit will reflect the state of IHS2. OD6 Reports the absence or presence of a fault on LS6.

OD13 If OD15 is logic [0], then this bit will reflect the state OD5 Reports the absence or presence of a fault on LS5.
of the direct input IHS1. If OD15 is logic [1], then this
bit will reflect the state of IHS3. OD4 Reports the absence or presence of a fault on LS4.

OD12 If OD15 is logic [0], then this bit will reflect the state OD3 Reports the absence or presence of a fault on HS3.
of the input FSI. If OD15 is logic [1], then this bit will OD2 Reports the absence or presence of a fault on HS2.
reflect the state of the input WAKE.
Freescale Semiconductor, Inc...

OD1 Reports the absence or presence of a fault on HS1.

OD11 Reports the absence or presence of a fault on LS11.
LSB OD0 Reports the absence or presence of a fault on HS0.
OD10 Reports the absence or presence of a fault on LS10.

MODES OF OPERATION

Watchdog and Fail-Safe Operation

Table 5. Fail-Safe Operation and Transitions
The watchdog is enabled and a timeout is started when the to Other 33888 Modes
WAKE or RST transitions from logic [0] to logic [1]. The WAKE
LS[4:11], Comments
input is capable of being pulled up to VPWR with a series limiting WAKE RST WDTO HS0 HS2
HS[1,3]
resistance that limits the internal clamp current. The timeout is
a multiple of an internal oscillator. As long as the WDIN terminal 0 0 x OFF OFF OFF Device in Sleep mode.
or the WD bit (D15) of an incoming SPI message is toggled 1 0 NO OFF OFF OFF All outputs are OFF.
within the minimum watchdog timeout, WDTO (or a divided When RST transitions
value configured during a WDCSCR message), then the device to logic [1], device is in
will operate normally. If the watchdog timeout occurs before the default.
WD bit or the WDIN terminal is toggled, then the device will
revert to a Fail-Safe mode until the device is reinitialized (if the 1 0 YES ON ON OFF Fail-Safe mode.
Device reset into
FSI terminal is left disconnected).
Default mode by
During Fail-Safe mode, all outputs will be OFF except for transitioning WAKE to
HS0 and HS2, which will be driven ON regardless of the state logic [0].
of the various direct inputs and modes (Table 5). The device 0 1 NO S S S Device in Normal
can be brought out of the Fail-Safe mode by transitioning the operating mode.
WAKE and RST terminals from logic [1] to logic [0]. In the event
0 1 YES ON ON OFF Fail-Safe mode.
the WAKE terminal was not transitioned to a logic [1] during
Device reset into
normal operation and the watchdog times out, then the device
Default mode by
can be brought out of fail-safe by bringing the RST to a logic [0]. transitioning RST to
If the FSI terminal is tied to GND, then the watchdog, and logic [0].
therefore fail-safe operation, will be disabled.
1 1 NO S S S Device in Normal
operating mode.

1 1 YES ON ON OFF Fail-Safe mode.

Device reset into
Default mode by
transitioning RST and
WAKE to logic [0].

Assumptions: Normal operating voltage and junction temperatures,

FSI terminal floating.
x=Don’t care.
S=State determined by SPI and/or direct input configurations.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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Default Mode Overtemperature Fault

The default mode describes the state of the device after first The 33888 incorporates overtemperature detection and
applying VPWR voltage or a reset transition from logic [0] to shutdown circuitry into each individual output structure.
logic [1] prior to SPI communication. In the default mode, all Overtemperature detection occurs when an output is in the ON
outputs will be off (assuming that the direct inputs ILS and state. When an output is shut down due to an overtemperature
IHS[0:3] and the WAKE terminal are at logic [0]). All of the condition, no other output is affected. The output experiencing
specific terminal functions will operate as though all of the the fault is shut down to protect itself from damage. A fault bit is
addressable configuration register bits were set to logic [0]. This loaded into the status register if the overtemperature condition
means, for example, that all of the low-side outputs will be is removed, and the fault bit is cleared upon the rising edge of
controllable by the ILS terminal, and that all high-side outputs CS.
will be controllable via their respective IHS terminals. During the For the low-side outputs, the faulted output is latched OFF
default mode, all high-side drivers will default with open load during an overtemperature condition. If the temperature falls
detection enabled. All low-side drivers will default with open below the recovery level, TLIM(HYS), then the output can be
load detection disabled. This mode allows limited control of the
turned back ON only after the output has first been commanded
33888 with the direct inputs in the absence of an SPI.
OFF either through the SPI or the ILS, depending on the logic
configuration.
Freescale Semiconductor, Inc...

Returning the device to the default state after a period of

normal operation, followed by the removal of the VPWR voltage,
For the high-side output(s), an overtemperature condition will
requires that the RST input be held at a logic [0] state until VPWR result in the output(s) turning OFF until the temperature falls
falls to a level below 2.0 V. If the RST and VDD input levels are below the TLIM(HYS). This cycle will continue indefinitely until
normal, then failure to allow VPWR to fall below 2.0 V will result action is taken by the MCU to shut the output(s) OFF.
in an internal bias circuit clamping the VPWR terminal to
approximately 3.5 V. Once VPWR falls below 2.0 V, the RST can Overvoltage Fault
be returned to 5.0 V without re-enabling the bias circuit. The 33888 shuts down all outputs during an overvoltage
condition on the VPWR terminal. The outputs remain in the OFF
Fault Logic Requirements state until the overvoltage condition is removed. Fault status for
The 33888 indicates all of the following faults as they occur: all outputs is latched into the status register. Following an
overvoltage condition, the next write cycle sent by the SO
• Overtemperature Fault terminal of the 33888 is logic [1] on OD11:OD0, indicating all
• Overvoltage Fault outputs have shut down. If the overvoltage condition is
• Open Load Fault removed, the status register can be cleared by a rising edge on
• Overcurrent Fault CS.
With the exception of the overvoltage, these faults are output
Open Load Fault
specific. The overvoltage fault is a global fault. The overcurrent
fault is only reported for the low-side outputs. The 33888 incorporates open load detection circuitry on
every output. A high-side or low-side output open load fault is
The 33888 low-side outputs incorporate an internal fault
detected and reported as a fault condition when the
filter, t DLY(FS). The fault timer filters noise and switching
corresponding output is disabled (OFF) if it was configured for
transients for overcurrent faults when the output is ON and
open load detection by setting the appropriate bit to logic [0]
open load faults when the output is OFF. All faults are latched (HS3:HS0) or logic [1] (LS11:LS4) in the OLFCR register
and indicated by a logic [1] for each output in the 33888 status
(Figure 6, page 25).
word (Table 4, page 23). If the fault is removed, the status bit for
the faulted output will be cleared by a rising edge on CS. The high-side open load fault is detected and latched into the
status register after the internal gate voltage is pulled low
The FS terminal is driven to a logic [0] when a fault exists on enough to turn off the output. If the open load fault is removed
any of the outputs. FS provides real time monitoring of the
or if the faulted output is commanded ON, the status register
overvoltage fault. For the high-side outputs, FS provides real can be cleared by a rising edge on CS. Note that the device
time monitoring of the open load and overtemperature. For the
default state will enable the high-side open load detection and
low-side outputs, the FS is latched to a logic [0] for open load, disable the low-side open load detection circuits, respectively.
overtemperature, and overcurrent faults. The latch is cleared by
toggling the state of the faulted output or by bringing RST low.

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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VPWR VPWR
33888
RL RL
LOW = Logic 0
MOSFET
+ OUT OUTPUT

– 50 mA

VTHRES VOFD(THRES)LS
2.0 V–4.0 V

Figure 6. Low-Side Output OFF Open Load Detection

Freescale Semiconductor, Inc...

Overcurrent Fault Requirements: Low-Side Output Note that each pair of low-side drivers, LS4:LS5, LS6:LS7,
LS8:LS9, and LS10:LS11, consists of a 500 mA and a 800 mA
An overcurrent condition is defined as any current value
output. Each pair of outputs shares ground bondwires. The
greater than ILIM (500 mA minimum value for LS5, LS7, LS9,
bondwires are not rated to handle both outputs in current limit
LS11, and 800 mA minimum value for LS4, LS6, LS8, LS10). mode simultaneously.
The status of the corresponding bit in the CLOCCR register
determines whether a specific output shuts down or continues Overcurrent Fault Requirements: High-Side Output
to operate in an analog current limited mode until either the
overcurrent condition is removed or the thermal shutdown limit For the high-side output of interest, the output current is
is reached (Figure 7, page 26). If the overcurrent shutdown limited to one of four levels depending on the type of high-side
mode is disabled, the fault reporting is disabled as well. output, the amount of time that has elapsed since the output
was switched on, and the state of the CLOCCR register.
For the low-side output of interest, if a D11:D4 bit was set to Assuming that bits D3:D0 of the CLOCCR register are at
a logic [1] in the OLCR register, the overcurrent protection logic [0], the current limit levels of the outputs will be initially at
shutdown circuitry will be enabled for that output. When a low- their peak levels as specified by the ILIM(PK)HS[0:3]. After the
side output is commanded ON either from the SPI or the ILS
high-side output is switched on, the peak current timer starts.
terminal, the drain of the low-side driver will be monitored for a
After a period of time t PCT, the current limit level changes to the
voltage greater than the fault detection threshold (3.0 V typical).
If the drain voltage exceeds this threshold, a timer will start and sustain levels ILIMSUSHS[x,x].
the output will be turned off and a fault latched in the status For the high-side output of interest, if a D3:D0 bit of the
register after the timeout expires. The faulted output can be CLOCCR is at logic [1], then the assigned output will only
retried only by commanding the output OFF and back ON either current limit at the sustain level specified by ILIMSUSHS[x,x].
through the SPI or the ILS terminal, depending on the logic
configuration. If the fault is gone, the retried output will return to Current is limited until the overtemperature circuitry shuts
normal operation and the status register can be cleared on a OFF the device. The device turns ON automatically when the
rising edge of CS. If the fault remains, the retried output will temperature fails below the TLIM(HYS). This cycle continues
latch off after the fault timer expires and the fault bit will remain indefinitely until action is taken by the master to shut the
set in the status register. output(s) OFF.
For the low-side output of interest, if a D11:D4 bit was set to
a logic [0] in the OLCR register, the output experiencing an Reverse Battery Requirements
overcurrent condition is not disabled until an overtemperature
The low-side and high-side outputs survive the application of
fault threshold has been reached. The specific output goes into
reverse battery as low as -16 V.
an analog current limit mode of operation, ILIM. The 33888 uses
overtemperature shutdown to protect all outputs in this mode of
operation. If the overcurrent condition is removed before the Ground Disconnect Protection
output has reached its overtemperature limit, the output will In the event that the 33888 ground is disconnected from load
function as if no fault has occurred. ground, the device protects itself and safely turns OFF the
outputs, regardless of the state of the output at the time of
disconnection.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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 Freescale Semiconductor, Inc.

33888 VPWR

HIGH = Fault RL
MOSFET ON
+ OUT

–
Digital

–
Analog
VREF
Freescale Semiconductor, Inc...

VTHRES VOFD(THRES)LS
2.0 V–4.0 V

Figure 7. Low-Side Short Circuit Detection and Analog Current Limit

Undervoltage Shutdown Requirements Output Voltage Clamping

All outputs turn off at some battery voltage below 6.0 V; For Each output has an internal clamp to provide protection and
the A version, the low side shutdown at a lower value, VPWRUV. dissipate the energy stored in inductive loads. Each clamp
however, as long as the level stays above 5.0 V, the internal independently limits the drain-to-source voltage to the range
logic states within the device are designed to be sustained. This specified in the Power Outputs section of the STATIC
ensures that when the battery level then rises above 6.0 V, the ELECTRICAL CHARACTERISTICS table beginning on
device will return to the state that it was in prior to the excursion page 12. Also see Figure 8.
between 5.0 V and 6.0 V (assuming that there was no SPI
communication or direct input changes during the event). If the Drain-Source
Clamp Voltage
battery voltage falls to a level below 5.0 V, then the internal (VCL = 53 V)
logic is reinitialized and the device is then in the default state Drain Voltage
upon the return of levels in excess of 6.0 V.
Drain Current Clamp Energy
(ID = 0.5 A) (EJ = IA x VCL x t)

Drain-Source
ON Voltage
(VDS(ON)) VPWR
Current
Area (IA)
GND Time

Figure 8. Low-Side Output Voltage Clamping

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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PACKAGE INFORMATION

Soldering Information The maximum peak temperature during the soldering

process should not exceed 230°C. The time at maximum
The 33888 is packaged in a surface mount power package temperature should range from 10 seconds to 40 seconds
intended to be soldered directly onto the printed circuit board. maximum.
The device was qualified in accordance with JEDEC
standards JESD22-A113-B and J-STD-020A. The
recommended reflow conditions are as follows:
• Convection: 225°C +5.0°C/-0°C
• Vapor Phase Reflow (VPR): 215°C to 219°C
• Infrared (IR)/Convection: 225°C +5.0°C/-0°C

APPLICATIONS
Freescale Semiconductor, Inc...

Typical Application
Figure 9 shows a typical application for the 33888.

VPWR

+5.0 V +5.0 V
8 x Relay or LED

VDD
10 kΩ 33888
FS VDD VPWR
4 Loads
IHS0:IHS3 8 x 0.5 Ω
ILS
RST
4
MCU SPI 40 mΩ
WDIN 40 mΩ 21 W 5.0 W
A/D CSNS2-3 10 mΩ 21 W 5.0 W
65 W
A/D CSNS0-1 10 mΩ
RC2 65 W
FSI GND
RC1

Figure 9. 33888 Typical Application Diagram

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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PACKAGE DIMENSIONS

PNB SUFFIX
APNB SUFFIX
36-TERMINAL PQFN
NONLEADED PACKAGE
CASE 1438-06
ISSUE E

(Top View)

12 A

14 1 0.1 C M
16 36
Freescale Semiconductor, Inc...

PIN 1
INDEX AREA

12

23 29

25 28
M
2X 0.1 C PIN NUMBER
B REFERENCE ONLY

0.1 C

2.2 2.20
2.0 1.95 0.05 C 4

DETAIL G

0.05
0.00 C SEATING PLANE
7.3 DETAIL G
6.9
0.1 A B C 30X
0.62
1.60 0.48
10X
1.35 2X 4.05 0.1 M C A B
6 0.05 M C
0.4 0.90
1.20 4X
10X
0.95 0.65
1 13X 0.8 14

36
16

2 PLACES 0.4±0.2 5 3.85

6 7X 0.8 X0.5±0.2 3.45
0.1 A B C 0.1 A B C
1 2.875 NOTES:
15
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
6X
1.25 1.45 Y14.5M, 1994.
1.00 1.05 4.45 3. THE COMPLETE JEDEC DESIGNATOR FOR
0.6 29 4.05
3 23 THIS PACKAGE IS: HF-PQFP-N.
1.625 0.1 A B C 4. COPLANARITY APPLIES TO LEADS AND
CORNER LEADS.
24 5. METAL PADS CONNECTED TO THE GND.
6. MINIMUM METAL GAP SHOULD BE 0.25MM.
2X
2.8
2.3

28 27 26 25 0.2 2.0
(0.25) 4X
0.0 4X
1.5
(2X 1.25) 2X
2.2
1.8
0.5 (2X 0.5) 0.1 M C A B
(2X 0.75) (2X 0.75)
0.05 M C
2X 3.75 2X
2.95
(0.05) 2.55
8.70
8.30 0.1 M C A B
0.1 A B C 0.05 M C
(0.3)
11.7
11.3
0.1 A B C

VIEW M-M
(Bottom View) CASE 1438-06
ISSUE E

33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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FB SUFFIX
64-TERMINAL PQFP
PLASTIC PACKAGE
CASE 1315-03
ISSUE B

4
E1 A 6
PIN ONE h
ID 2X
64 E2 53

h
D4 D3
1 52 58X
e
Freescale Semiconductor, Inc...

E3
D1 D2 D
BOTTOM VIEW
bbb M C B
4 2X
e/2

c c1
20 33

b1
6 SECTION W-W
B 21 4X 32
e1

E NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
bbb M C A PER ASME Y14.5M, 1994.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DIMENSIONS "D1" AND "E1" DO NOT INCLUDE
DETAIL Y MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.15 PER SIDE. DIMENSION "D1" AND "E1" DO
DATUM INCLUDE MOLD MISMATCH AND ARE
3 H PLANE DETERMINED AT DATUM PLANE -H-.
5. DIMENSION "b" DOES NOT INCLUDE DAMBAR
A A2 PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION.
64X 6. DATUMS -A- AND -B- TO BE DETERMINED AT
SEATING 5 b DATUM PLANE -H-.
C PLANE A4
aaa M C A B
MILLIMETERS
E3 DIM MIN MAX
A --- 3.15
A1 --- 0.25
A2 2.5 2.9
A3 0 0.1
A4 0.8 1
D 16.95 17.45
D1 13.9 14.1
D2 12.5 12.9
W D3 9.3 9.7
D4 13.4 13.6
GAUGE
PLANE 0.35 E 16.95 17.45
E1 13.9 14.1
E2 2.35 2.65
E3 9.3 9.7
A1 ccc L 0.8 1.1
θ W A3 b 0.22 0.38
L b1 0.22 0.33
c 0.23 0.32
(1.6) c1 0.23 0.29
e 0.65 BSC
e1 2.925 BSC
DETAIL Y h --- 0.8
θ 0˚ 7˚
aaa 0.12
bbb 0.2
ccc 0.1

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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NOTES
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33888 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

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NOTES
Freescale Semiconductor, Inc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33888

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
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© Motorola, Inc. 2004

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