TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.

27, 2013

PART NO. : OEL9M1009-W-E

This specification maybe changed without any notice in order to improve performance or
quality etc.
Please contact TRULY Semiconductors LTD. OLED R&D department for update
specification and product status before design for this product or release the order.

TRULY SEMICONDUCTORS LTD. P.1 / 28

 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013

PRODUCT CONTENTS
n PHYSICAL DATA
n ABSOLUTE MAXIMUM RATINGS
n EXTERNAL DIMENSIONS
n ELECTRICAL CHARACTERISTICS
n TIMING OF POWER SUPPLY
n ELECTRO-OPTICAL CHARACTERISTICS
n INTERFACE PIN CONNECTIONS
n COMMAND TABLE
n INITIALIZATION CODE
n SCHEMATIC EXAMPLE
n RELIABILITY TESTS
n OUTGOING QUALITY CONTROL SPECIFICATION
n CAUTIONS IN USING OLED MODULE

Customer

Written by He Kai Approved by

Checked by Yang Xueyu

Approved by Zhang Weicang

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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013
REVISION HISTORY

Rev. Contents Date

0.1 Preliminary 2013-09-02
1.0 Initial release. 2013-10-27

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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013
n PHYSICAL DATA
No. Items: Specification: Unit
1 Diagonal Size 1.50 Inch
2 Resolution 128 (H) x 128(V) Dots
3 Active Area 26.86 (W) x 26.86(H) mm2
4 Outline Dimension (Panel) 33.90 (W) x 37.30(H) mm2
5 Pixel Pitch 0.210 (W) x 0.210 (H) mm2
6 Pixel Size 0.185 W) x 0.185 (H) mm2
7 Driver IC SH1107G -
8 Display Color White -
9 Gray scale 1 Bit
10 Interface Parallel / SPI / I2C -
11 IC package type COG -
12 Thickness 1.45±0.1 mm
13 Weight TBD g
14 Duty 1/128 -

n ABSOLUTE MAXIMUM RATINGS

Unless otherwise specified, VSS = 0V ( Ta = 25℃ )
Items Symbol Min Typ. Max Unit
Supply Logic VDD -0.3 - 3.6 V
Voltage Driving VPP -0.3 - 17.0 V
Operating Temperature Top -30 - 80 ℃
Storage Temperature Tst -40 - 85 ℃
Humidity - - - 90 %RH

NOTE:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational
sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

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 T hese draw ings and specifications are the exclusive properties of TR U LY ,
w hich are furnished for evaluation only on a confidential basis.
H A Z A R D O U S SU B STA N C ES
M A N A G EM EN T ST A N D A R D
R OH S CO M PLIAN T
R OH S C O M PLIAN T A ND H AL OG EN -FREE
__________R ESTR IC TE D SU BSTA NC E CONTROL
STA ND AR D. (V E R SIO N ： _________ )

TRULY SEMICONDUCTORS LTD.

R E M O V E TA P E 1 7.5M M* 8.0M M FPC Pin Assignm ent
n EXTERNAL DIMENSION

S ilicon glue
1 48
U V glue
TRULY SEMICONDUCTORS LTD.

C O N TA CT S IDE S TIFF E NE R
"A "---D ots D etail
1 24 scale 10X

N O T ES:
1. O PE R A T IN G T EM P:-30° C TO 80° C
2. STO R A G E TE M P: -40° C TO 85° C
3. V IEW IN G D IR EC TIO N :A LL
4. O L ED D R IV E IC :SH 1107
Rev : 1.0

5. D ISPLA Y C O LO R :W hite
6. U N SPEC IFIE D T O LER A N C ES: ± 0.2m m .
7. ( ) M EA N S: D IM EN SIO N FO R R EFER EN C E
8. T H E PR O TE C TIV E FILM O N FR O N T SID E O F O LED
M U ST B E R EM O V ED B EFO R E A SSEM B LY B Y
C U STO M ER
1/ 1

P.5 / 28
Oct.27, 2013
 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013
n ELECTRICAL CHARACTERISTICS
◆DC Characteristics
Unless otherwise specified, VSS = 0V, VDD=1.65 V to 3.5V, AVDD=2.4 V to 3.5V
( Ta = +25℃ )

Items Symbol Min Typ. Max Unit

Supply Logic VDD 1.65 - 3.5 V

Voltage Operating VPP 7.0 - 16.5 V

Input High Voltage VIH 0.8 x VDD - VDD V

Voltage Low Voltage VIL VSS - 0.2 x VDD V

Output High Voltage VOH 0.8 x VDD - VDD V

Voltage Low Voltage VOL VSS - 0.2 x VDD V

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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013
◆AC Characteristics
(1) System buses Read/Write characteristics 1 (For the 8080 Series Interface MPU)

A0

tAS8 tAH8

CS tF tR
tCYC8

WR , RD tCCLW tCCHW
tCCLR tCCHR

tDS8 tDH8

D0~D7
(WRITE)

tACC8 tCH8

D0~D7
(READ)

(VDD = 1.65V – 2.4V, TA = +25°C)

Symbol Parameter Min. Typ. Max. Unit Condition

tCYC8 System cycle time 300 - - ns

tAS8 Address setup time 0 - - ns

tAH8 Address hold time 0 - - ns

tDS8 Data setup time 40 - - ns

tDH8 Data hold time 30 - - ns

tCH8 Output disable time 10 - 70 ns CL = 100pF

tACC8 RD access time - - 280 ns CL = 100pF

tCCLW Control L pulse width (WR) 100 - - ns

tCCLR Control L pulse width (RD) 120 - - ns

tCCHW Control H pulse width (WR) 100 - - ns

tCCHR Control H pulse width (RD) 100 - - ns

tR Rise time - - 15 ns

tF Fall time - - 15 ns

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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013

(VDD = 2.4V – 3.5V, TA = +25°C)

Symb
Parameter Min. Typ. Max. Unit Condition
ol
tCYC8 System cycle time 300 - - ns

tAS8 Address setup time 0 - - ns

tAH8 Address hold time 0 - - ns

tDS8 Data setup time 40 - - ns

tDH8 Data hold time 15 - - ns

tCH8 Output disable time 10 - 70 ns CL = 100pF

tACC8 RD access time - - 140 ns CL = 100pF

tCCLW Control L pulse width (WR) 100 - - ns

tCCLR Control L pulse width (RD) 120 - - ns

tCCHW Control H pulse width (WR) 100 - - ns

tCCHR Control H pulse width (RD) 100 - - ns

tR Rise time - - 15 ns

tF Fall time - - 15 ns

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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013
(2) System buses Read/Write Characteristics 2 (For the 6800 Series Interface MPU)

A0

R/W
tAS6 tAH6

CS
tF tR
tCYC6
tEWHW tEWHR
E

tEWLW tEWLR

tDS6 tDH6

D0~D7
(WRITE)

tACC6 tOH6

D0~D7
(READ)

(VDD = 1.65 – 2.4V, TA = +25°C)

Symbol Parameter Min. Typ. Max. Unit Condition

tCYC6 System cycle time 300 - - ns
tAS6 Address setup time 0 - - ns
tAH6 Address hold time 0 - - ns
tDS6 Data setup time 40 - - ns
tDH6 Data hold time 30 - - ns
tOH6 Output disable time 10 - 70 ns CL = 100pF
tACC6 Access time - - 280 ns CL = 100pF
tEWHW Enable H pulse width (Write) 100 - - ns
tEWHR Enable H pulse width (Read) 120 - - ns
tEWLW Enable L pulse width (Write) 100 - - ns
tEWLR Enable L pulse width (Read) 100 - - ns
tR Rise time - - 15 ns
tF Fall time - - 15 ns

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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013

(VDD = 2.4 – 3.5V, TA = +25°C)

Symbol Parameter Min. Typ. Max. Unit Condition
tCYC6 System cycle time 300 - - ns
tAS6 Address setup time 0 - - ns
tAH6 Address hold time 0 - - ns
tDS6 Data setup time 40 - - ns
tDH6 Data hold time 15 - - ns
tOH6 Output disable time 10 - 70 ns CL = 100pF
tACC6 Access time - - 140 ns CL = 100pF
tEWHW Enable H pulse width (Write) 100 - - ns
tEWHR Enable H pulse width (Read) 120 - - ns
tEWLW Enable L pulse width (Write) 100 - - ns
tEWLR Enable L pulse width (Read) 100 - - ns
tR Rise time - - 15 ns
tF Fall time - - 15 ns

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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013

(3) System buses Write characteristics 3 (For 4 wire SPI)

CS tCSS tCSH

tSAS tSAH

A0

tSCYC
tSLW
SCL
tSHW

tF tR tF

tSDS tSDH

SI

(VDD1 = 1.65 – 2.4V, TA = +25°C)

Symbol Parameter Min. Typ. Max. Unit Condition
tSCYC Serial clock cycle 500 - - ns
tSAS Address setup time 300 - - ns
tSAH Address hold time 300 - - ns
tSDS Data setup time 200 - - ns
tSDH Data hold time 200 - - ns
tCSS CS setup time 240 - - ns
tCSH CS hold time time 120 - - ns
tSHW Serial clock H pulse width 200 - - ns
tSLW Serial clock L pulse width 200 - - ns
tR Rise time - - 30 ns
tF Fall time - - 30 ns

(VDD1 = 2.4 - 3.5V, TA = +25°C)

Symbol Parameter Min. Typ. Max. Unit Condition

tSCYC Serial clock cycle 250 - - ns
tSAS Address setup time 150 - - ns
tSAH Address hold time 150 - - ns
tSDS Data setup time 100 - - ns
tSDH Data hold time 100 - - ns
tCSS CS setup time 120 - - ns
tCSH CS hold time time 60 - - ns
tSHW Serial clock H pulse width 100 - - ns
tSLW Serial clock L pulse width 100 - - ns
tR Rise time - - 15 ns
tF Fall time - - 15 ns

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2
(4) I C interface characteristics

SDA

tBUF
tF
tLOW

SCL

tHD:START tR tHD:DATA tSU:DATA

tHIGH

SDA

tSU:START tSU:STOP

(VDD = 1.65 - 3.5V, TA = +25°C)

Symbol Parameter Min. Typ. Max. Unit Condition

fSCL SCL clock frequency DC - 400 kHz
TLOW SCL clock Low pulse width 1.3 - - µs
THIGH SCL clock H pulse width 0.6 - - µs
TSU:DATA data setup time 100 - - ns
THD:DATA data hold time 0 - 0.9 µs
TR SCL SDA rise time 20+0.1Cb - 300 ns

TF SCL SDA fall time 20+0.1Cb - 300 ns

Capacity load on each bus
Cb - - 400 pF
line
TSU:START Setup timefor re-START 0.6 - - µs
THD:START START Hold time 0.6 - - µs
TSU:STOP Setup time for STOP 0.6 - - µs
Bus free times between STOP
TBUF 1.3 - - µs
and START condition

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(5) Reset Timing

tRW

RES
tR

Internal circuit
status During reset End of reset

(VDD = 1.65 - 3.5V, TA = +25°C)

Symbol Parameter Min. Typ. Max. Unit Condition

tR Reset time - - 2.0 µs
tRW Reset low pulse width 10.0 - - µs

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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013
n TIMING OF POWER SUPPLY
◆Power ON sequence:
1. Power ON VCI, VDDIO.
2. After VCI, VDDIO becomes stable, set wait time at least 1ms (t0) for internal VDD become
stable. Then set RES# pin LOW (logic low) for at least 100us (t1) (4) and then HIGH (logic
high).
3. After set RES# pin LOW (logic low), wait for at least 100us (t2). Then Power ON VCC.(1)
4. After VCC become stable, send command AFh for display ON. SEG/COM will be ON after
200ms (tAF).
Power on sequence
ON VCI, VDDIO RES# ON VCC Send AFh command for Display ON

VCI,, VDDIO
t0
OFF
t1

RES#

GND
t2
VCC

OFF
tAF

ON
SEG/COM
OFF

◆Power OFF sequence:

1. Send command AEh for display OFF.
2. Power OFF VCC.(1), (2), (3)
3. Wait for tOFF. Power OFF VCI, VDDIO.(where Minimum tOFF=0ms (5), Typical tOFF=100ms)
Power off sequence
Send command AEh for display OFF OFF VCC OFF VCI ,VDDIO
VCC

OFF
tOFF
VCI, VDDIO
OFF

Note:
(1)
Since an ESD protection circuit is connected between VCI, VDDIO and VCC, VCC becomes
lower than VCI whenever VCI, VDDIO is ON and VCC is OFF as shown in the dotted line of VCC
in Figure above.
(2)
VCC should be kept float (disable) when it is OFF.
(3)
Power pins (VCI, VCC) can never be pulled to ground under any circumstance.
(4)
The register values are reset after t1.
(5)
VCI, VDDIO should not be Power OFF before VCC Power OFF.
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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013
n ELECTRO-OPTICAL CHARACTERISTICS (Ta=25℃)
Items Symbol Min. Typ. Max. Unit Remark
Operating Luminance L 80 100* - cd /m2 White
Power Consumption P - 200 240 mW 30% pixels ON

Frame Frequency Fr - 100 - Hz

CIE x 0.25 0.29 0.33
Color Coordinate White CIE1931 Darkroom
CIE y 0.29 0.33 0.37
Rise Tr - - 0.02 ms -
Response Time
Decay Td - - 0.02 ms -
Contrast Ratio* Cr 10000:1 - - Darkroom
Viewing Angle △θ 160 - - Degree -
Operating Life Time* Top 20,000 - - Hours L=100cd/ m2

Note:
1. 100cd/ m2 is based on VDD=3.0V, VPP=13V, contrast command setting 0XDF;
2. Contrast Ratio is defined as follows:
Photo – detector output with OLED being “white”
Contrast ratio =
Photo – detector output with OLED being “black”
3. Life Time is defined when the Luminance has decayed to less than 50% of the initial
Luminance specification. (Odd and even chess board alternately displayed), (The initial value
should be closed to the typical value after adjusting.).

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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013
n INTERFACE PIN CONNECTIONS
No Symbol Description
1 NC No connection
2 VSS Ground
3 VSS Ground
4 NC No connection
5 VDD 1.65 - 3.5V Power supply for logic and input.
6 IM1 MPU interface mode select pads.
7 IM2 MPU interface mode select pads.
This pad is the chip select input. When CSB = “L”, then the chip select
8 CSB
becomes active, and data/command I/O is enabled.
This is a reset signal input pad. When RESB is set to “L”, the settings are
9 RESB
initialized. The reset operation is performed by the RES signal level.
This is the Data/Command control pad that determines whether the data
bits are data or a command.
A0 = “H”: the inputs at D0 to D7 are treated as display data.
10 A0
A0 = “L”: the inputs at D0 to D7 are transferred to the command registers.
In I2C interface, this pad serves as SA0 to distinguish the different address
of OLED driver.
This is a MPU interface input pad.
When connected to an 8080 MPU, this is active LOW. This pad connects
to the 8080 MPU WR signal. The signals on the data bus are latched at the
rising edge of the WR signal.
11 WRB
When connected to a 6800 Series MPU: This is the read/write control
signal input terminal.
When R/W = “H”: Read.
When R/W = “L”: Write.
This is a MPU interface input pad.
When connected to an 8080 series MPU, it is active LOW. This pad is
connected to the RDB signal of the 8080 series MPU, and the data bus is
12 RDB
in an output status when this signal is “L”.
When connected to a 6800 series MPU, this is active HIGH. This is used
as an enable clock input of the 6800 series MPU.
This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit
standard MPU data bus. When the serial interface is selected, then D0
serves as the serial clock input pad (SCL) and D1 serves as the serial data
13~20 D0~D7 input pad (SI). At this time, D2 to D7 are set to high impedance.
When the I2C interface is selected, then D0 serves as the serial clock input
pad (SCL) and D1 serves as the serial data input pad (SDA). At this time,
D2 to D7 are set to high impedance.
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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013
This is a segment current reference pad. A resistor should be connected
21 IREF
between this pad and VSS. Set the current at 15.625mA.
This is a pad for the voltage output high level for common signals. A
22 VCOMH
capacitor should be connected between this pad and VSS.
This is the most positive voltage supply pad of the chip. It should be
23 VPP
supplied externally.
24 NC No connection

These are the MPU interface mode select pads.

8080 I2C 6800 4-wire SPI
IM1 1 1 0 0
IM2 1 0 1 0
Note: 0 is connected to VSS
1 is connected to VDD

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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013
n COMMAND TABLE
Code
Command Function
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Sets 4 lower bits of column
1. Set Column Address
0 1 0 0 0 0 0 Lower column address address of display RAM in
4 lower bits
register. (POR = 00H)
Sets 4 higher bits of column
2.Set Column Address Higher column
0 1 0 0 0 0 1 0 address of display RAM in
4 higher bits address
register. (POR = 10H)
D = 1, Vertical Addressing
3.Set memory Mode
0 1 0 0 0 1 0 0 0 0 D
addressing mode D = 0, Page Addressing
Mode (POR=20H)
4. The Contrast This command is to set Contrast
0 1 0 1 0 0 0 0 0 0 1
Control Mode Set Setting of the display.
Contrast Data The chip has 256 contrast steps
0 1 0 Contrast Data from 00 to FF. (POR = 80H)
Register Set
5. Set Segment The down (0) or up (1)
0 1 0 1 0 1 0 0 0 0 ADC
Re-map (ADC) rotation. (POR = A0H)
Selects normal display (0) or
6. Set Entire Display
0 1 0 1 0 1 0 0 1 0 D Entire Display ON (1). (POR
OFF/ON
= A4H)
Normal indication (0) when
7. Set Normal/
0 1 0 1 0 1 0 0 1 1 D low, but reverse indication (1)
Reverse Display
when high. (POR = A6H)

8. DC-DC Control 0 1 0 1 0 1 0 1 1 0 1 This command is to control

Mode Set the DC-DC voltage DC-DC
will be turned on when display
DC-DC Setting 0 1 0 1 0 0 0 F2 F1 F0 D on converter (1) or DC-DC
Mode Set OFF (0). (POR = 81H)

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Command Table (Continued)

Code
Command Function
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
Turns on OLED panel (1) or
9. Display OFF/ON 0 1 0 1 0 1 0 1 1 1 D
turns off (0). (POR = AEH)
Specifies page address to
load display RAM data to
10. Set Page Address 0 1 0 1 0 1 1 Page Address
page address register. (POR
= B0H)
11 Set Common Scan from COM0 to COM [N
Output Scan 0 1 0 1 1 0 0 D * * * - 1] (0) or Scan from COM [N
Direction -1] to COM0 (1). (POR = C0H)
12. Set Display Divide This command is used to set
Ratio/Oscillator the frequency of the internal
0 1 0 1 1 0 1 0 1 0 1
Frequency Mode display clocks.
Set (POR = 50H)
Divide Ratio/Oscillator
0 1 0 Oscillator Frequency Divide Ratio
Frequency Data Set
13. Dis-charge / This command is used to set
Pre-charge Period 0 1 0 1 1 0 1 1 0 0 1 the duration of the
Mode Set dis-charge and pre-charge
Dis-charge period. (POR = 22H)
/Pre-charge Period 0 1 0 Dis-charge Period Pre-charge Period
Data Set
14. VCOM Deselect 0 1 0 1 1 0 1 1 0 1 1 This command is to set the
Level Mode Set common pad output voltage
VCOM Deselect 0 1 0 VCOM = (β1 X VREF) level at deselect stage.
Level Data Set (POR = 35H)
17. Read-Modify-Write 0 1 0 1 1 1 0 0 0 0 0 Read-Modify-Write start.
18. End 0 1 0 1 1 1 0 1 1 1 0 Read-Modify-Write end.
19. NOP 0 1 0 1 1 1 0 0 0 1 1 Non-Operation Command
20 Write Display Data 1 1 0 Write RAM data
ON/
21 Read ID 0 0 1 BUSY
OFF
ID

22. Read Display Data 1 0 1 Read RAM data

Note: Do not use any other command, or the system malfunction may result.

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n INTIALIZATION CODE
void Initial_1107()
{
WMLCDCOM(0xAE);//Display OFF

WMLCDCOM(0x0F);//Set Column Address 4 lower bits

WMLCDCOM(0x17);//Set Column Address 4 higher bits

WMLCDCOM(0xA0);//Set Segment Re-map

WMLCDCOM(0xD9);//Set Dis-charge/Pre-charge Period

WMLCDCOM(0x89);

WMLCDCOM(0xD5); //Set Display Clock Divide Ratio/Oscillator Frequency

WMLCDCOM(0xB0);

WMLCDCOM(0x20);//Set Page Addressing Mode

WMLCDCOM(0xDB);//Set VCOM
WMLCDCOM(0x35);

WMLCDCOM(0x81);//Set Contrast
WMLCDCOM(CONTRAST);

WMLCDCOM(0xC0);//Set Common Output Scan Direction

WMLCDCOM(0xA4);//Set Entire Display OFF

WMLCDCOM(0xA6);//Set Normal/Reverse Display

WMLCDCOM(0xAD);//Set DC-DC OFF

WMLCDCOM(0x80);
Clear();
WMLCDCOM(0xAF);
}

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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013
n SCHEMATIC EXAMPLE
◆8080 Parallel Interface Application Circuit:

Note:
C1: 4.7UF C2~ C3:4.7UF/35V+/-10% tantalum capacitor（suggest）
R1: about 750 KΩ, R1 = (Voltage at IREF - VSS)/IREF
◆4-wire SPI Serial Interface Application Circuit:

Note:
C1: 4.7UF C2~ C3:4.7UF/35V+/-10% tantalum capacitor（suggest）.
R1: Recommend 750 KΩ.
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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013
2
◆I C Interface Application Circuit:

Note:
C1: 4.7UF C2~ C3:4.7UF/35V+/-10% tantalum capacitor（suggest）
R1: Recommend 750 KΩ
The least significant bit of the slave address is set by connecting the input SA0 to either
logic 0(VSS) or 1(VDD)
The positive supply of pull-up resistor must equal to the value of VDD.
Recommend the value of resistor Rp equal to 1.5 KΩ

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n RELIABILITY TESTS
Item Condition Criterion
1. After testing, the
High Temperature Storage function test is ok.
85±2℃, 200 hours
(HTS) 2. After testing, no
addition to the defect.
3. After testing, the
High Temperature Operating change of luminance
80±2℃, 96 hours
(HTO) should be within +/-
50% of initial value.
4. After testing, the
Low Temperature Storage
-40±2℃, 200 hours change for the mono
(LTS) and area color must be
within (+/-0.02, +/-
0.02) and for the full
Low Temperature Operating
-30±2℃, 96 hours color it must be within
(LTO) (+/-0.04, +/-0.04) of
initial value based on
High Temperature / High Humidity 1931 CIE coordinates.
Storage 50±3℃, 90%±3%RH, 120 5. After testing, the
hours change of total current
(HTHHS) consumption should be
-20±2℃ ~ 25℃ ~ 70±2℃ within +/- 50% of
Thermal Shock (Non-operation)
(30min) (5min) (30min) initial value.
(TS) 10cycles
10~55~10Hz,amplitu
Vibration
de 1.5mm, 1 hour for
(Packing)
each direction x, y, z 1. One box for each test.
2. No addition to the cosmetic and the electrical defects.
Drop Height : 1 m, each
(Packing) time for 6 sides, 3
edges, 1 angle
1. After testing, cosmetic and electrical defects should not
ESD
±4kV (R: 330Ω C: happen.
(finished
150pF , 10times, air 2. In case of malfunction or defect caused by ESD
product
discharge) damage, it would be judged as a good part if it would be
housing)
recovered to normal state after resetting.

Note：1) For each reliability test, the sample quantity is 3, and only for one test item.
2) The HTHHS test is requested the Pure Water(Resistance＞10MΩ).
3) The test should be done after 2 hours of recovery time in normal environment.

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n OUTGOING QUALITY CONTROL SPECIFICATION
◆Standard
According to GB/T2828.1-2003/ISO 2859-1：1999 and ANSI/ASQC Z1.4-1993,
General Inspection Level II.
◆Definition
1 Major defect: The defect that greatly affect the usability of product.
2 Minor defect: The other defects, such as cosmetic defects, etc.
3 Definition of inspection zone:

A B C

Zone A: Active Area

Zone B: Viewing Area except Zone A
Zone C: Outside Viewing Area
Note: As a general rule, visual defects in Zone C are permissible, when it is no trouble of
quality and assembly to customer’s product.
◆Inspection Methods
1 The general inspection: under 20W x 2 or 40W fluorescent light, about 30cm viewing
distance, within 45º viewing angle, under 25±5℃.

2 The luminance and color coordinate inspection: By PR705 or BM-7 or the equal
equipments, in the dark room, under 25±5℃.
◆Inspection Criteria
1 Major defect: AQL= 0.65
Item Criterion
1. No display or abnormal display is not accepted
Function Defect
2. Open or short is not accepted.
3. Power consumption exceeding the spec is not accepted.
Outline Dimension Outline dimension exceeding the spec is not accepted.
Glass Crack Glass crack tends to enlarge is not accepted.

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2 Minor Defect: AQL= 1.5
Item Criterion
Size (mm) Accepted Qty
Spot Area A + Area B Area C
Defect
Φ≦0.07 Ignored
(dimming
Y 0.07＜Φ≦0.10 3
and
lighting 0.10＜Φ≦0. 15 1 Ignored
X
spot) 0.15＜Φ 0
Note : Φ= ( x + y ) / 2
Line L ( Length ) : mm W ( Width ) : mm Area A + Area B Area C
Defect / W≦0.02 Ignored
(dimming
L≦3.0 0.02＜W≦0.03 2
and
L≦2.0 0.03＜W≦0.05 1 Ignored
lighting
line) / 0.05＜W As spot defect
Remarks: The total of spot defect and line defect shall not exceed 4 pcs. The
distance between two lines defects must exceed 1 mm
Polarizer Stain which can be wiped off lightly with a soft cloth or similar
Stain cleaning is accepted, otherwise, according to the Spot Defect and the
Line Defect.
1. If scratch can be seen during operation, according to the criterions
of the Spot Defect and the Line Defect.
2. If scratch can be seen only under non-operation or some special
angle, the criterion is as below :
Polarizer L ( Length ) : mm W ( Width ) : mm Area A + Area B Area C
Scratch / W≦0.02 Ignore
3.0＜L≦5.0 0.02＜W≦0.04 2
L≦3.0 0.04＜W≦0.06 1 Ignore
/ 0.06＜W 0
Size Area A + Area B Area C
Φ≦0.20 Ignored
Polarizer Y 0.20＜Φ≦0.30 2
Air Bubble
0.30＜Φ≦0.50 1 Ignored
X
0.50＜Φ 0

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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013
1. On the corner
(mm)

x ≤ 1.5
y ≤ 1.5
z ≤t

2. On the bonding edge

Glass
Defect (mm)
(Glass
Chiped ) x ≤a/4
y ≤ s / 3 &≤0.7
z ≤t

3. On the other edges

(mm)

x ≤a/8
y ≤ 0.7
z ≤t

Note: t: glass thickness ; s: pad width ; a: the length of the edge

TCP
Crack, deep fold and deep pressure mark on the TCP are not accepted
Defect
The tolerance of display pixel dimension should be within ±20% of
Pixel Size
the spec
Luminance Refer to the spec or the reference sample

Color Refer to the spec or the reference sample

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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013
n CAUTIONS IN USING OLED MODULE
◆Precautions For Handling OLED Module:
1. OLED module consists of glass and polarizer. Pay attention to the following items when
handling:
i. Avoid drop from high, avoid excessive impact and pressure.
ii. Do not touch, push or rub the exposed polarizes with anything harder than an HB
pencil lead.
iii. If the surface becomes dirty, breathe on the surface and gently wipe it off with a soft
dry cloth. If it is terrible dirty, moisten the soft cloth with Isopropyl alcohol or Ethyl
alcohol. Other solvents may damage the polarizer. Especially water, Ketone and
Aromatic solvents.
iv. Wipe off saliva or water drops immediately, contact the polarizer with water over
a long period of time may cause deformation.
v. Please keep the temperature within specified range for use and storage.
Polarization degradation, bubble generation or polarizer peeling-off may occur
with high temperature and high humidity.
vi. Condensation on the surface and the terminals due to cold or anything will damage,
stain or dirty the polarizer, so make it clean as the way of iii.
2. Do not attempt to disassemble or process the OLED Module.
3. Make sure the TCP or the FPC of the Module is free of twisting, warping and distortion,
do not pull or bend them forcefully, especially the soldering pins. On the other side, the
SLIT part of the TCP is made to bend in the necessary case.
4. When assembling the module into other equipment, give the glass enough space to
avoid excessive pressure on the glass, especially the glass cover which is much more
fragile.
5. Be sure to keep the air pressure under 120 kPa, otherwise the glass cover is to be cracked.
6. Be careful to prevent damage by static electricity:
i. Be sure to ground the body when handling the OLED Modules.
ii. All machines and tools required for assembling, such as soldering irons, must be
properly grounded.
iii. Do not assemble and do no other work under dry conditions to reduce the amount of
static electricity generated. A relative humidity of 50%-60% is recommended.
iv. Peel off the protective film slowly to avoid the amount of static electricity generated.
v. Avoid to touch the circuit, the soldering pins and the IC on the Module by the body.
vi. Be sure to use anti-static package.
7. Contamination on terminals can cause an electrochemical reaction and corrade the
terminal circuit, so make it clean anytime.
8. All terminals should be open, do not attach any conductor or semiconductor on the
terminals.
9. When the logic circuit power is off, do not apply the input signals.
10. Power on sequence: VDD → VPP, and power off sequence: VPP → VDD.
11. Be sure to keep temperature, humidity and voltage within the ranges of the spec,
otherwise shorten Module’s life time, even make it damaged.
12. Be sure to drive the OLED Module following the Specification and datasheet of IC
controller, otherwise something wrong may be seen.
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 TRULY SEMICONDUCTORS LTD. Rev : 1.0 Oct.27, 2013
13.When displaying images, keep them rolling, and avoid one fixed image displaying more
than 30 seconds, otherwise the residue image is to be seen. This is the speciality of OLED.

◆Precautions For Soldering OLED Module:

1. Soldering temperature : 260°C ± 10°C.
2. Soldering time : 3-4 sec.
3. Repeating time : no more than 3 times.
4. If soldering flux is used, be sure to remove any remaining flux after finishing soldering
operation. (This does not apply in the case of a non-halogen type of flux.) It is
recommended to protect the surface with a cover during soldering to prevent any damage
due to flux spatters.

◆ Precautions For Storing OLED Module:

1. Be sure to store the OLED Module in the vacuum bag with dessicant.
2. If the Module can not be used up in 1 month after the bag being opened, make sure to
seal the Module in the vacuum bag with dessicant again.
3. Store the Module in a dark place, do not expose to sunlight or fluorescent light.
4. The polarizer surface should not touch any other objects. It is recommended to store the
Module in the shipping container.
5. It is recommended to keep the temperature between 0°C and 30°C , the relative humidity
not over 60%.

◆ Limited Warranty
Unless relevant quality agreements signed with customer and law enforcement, for a period of
12 months from date of production, all products (except automotive products) TRULY will
replace or repair any of its OLED modules which are found to be functional defect when
inspected in accordance with TRULY OLED acceptance standards (copies available upon
request). Cosmetic/visual defects must be returned to TRULY within 90 days of shipment.
Confirmation of such date should be based on freight documents. The warranty liability of
TRULY is limited to repair and/or replacement on the terms above. TRULY will not be
responsible for any subsequent or consequential events.

◆Return OLED Module Under Warranty:

1. No warranty in the case that the precautions are disregarded.
2. Module repairs will be invoiced to the customer upon mutual agreement. Modules
must be returned with sufficient description of the failures or defects.

◆PRIOR CONSULT MATTER

1. For TRULY standard products , we keep the right to change material ,process … for
improving the product property without any notice on our customer.
2. If you have special requirement about reliability condition, please let us know before
you start the test on our samples.

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