A

REPORT ON
“Circuit For 4 Bit Adder”
SUBMITTED TO THE
SHIVAJI POLYTECHNIC, ATPADI
IN THE PARTIAL FULFILLMENT OF THE REQUIREMENTS
OF
DIPLOMA IN
COMPUTER TECNOLOGY
SUBMITTED BY
Name: Shweta Sunil Randive Exam seat No:-

Suraj Mohan Shende Exam seat No:-

Karan Arjun Pujari Exam seat No:-

UNDER THE GUIDANCE OF

Prof. Ms. Hegade N.M

DEPARTMENT OF COMPUTER TECNOLOGY

SHIVAJI POLYTECHNIC, ATPADI

(2023-2024)

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 SHIVAJI POLYTECHNIC, ATPADI

CERTIFICATE

This is to certify that Ms. Shweta Sunil Randive of class SY(Computer) as

per the curriculum laid down by the Maharashtra State Board of
Technical Education, Mumbai have successfully completed Micro project
entitled under our guidance in satisfactory manner as a part of academic
syllabus during the academic year 2023-2024.

Date:
Place: Atpadi

Prof. Ms. Hegade N.M Prof. Ms.Belsare A.T

(Guide) (HOD )

Prof. Mr. Kulkarni O.G

(Principal)

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 Acknowledgments

It is matter of great pleasure for me to submit this micro project report

on "Circuit For 4 Bit Adder" as a part of curriculum for award of Diploma in
Computer Technology Maharashtra State Board Of Technical Education,
Mumbai.
Firstly, I would like to express my gratitude to my guide Prof. Ms.
Hegade N.M mam her inspiration, adroit guidance, constant supervision,
direction and discussion in successful completion of this Micro project.
I am thankful to Head of Department Prof. Ms. Belsare A.T for guiding
and helpingme right from the beginning,
I am thankful to my Principal Prof. Mr. Kulkarni O.G and to all our
staff members who encouraged me to do this micro project.
Also I extend my thanks to all my colleagues those who have helped me
directly or indirectly in completion of this micro project and last but not least,
I am thankful to my parents, who had inspired me with their blessings.

Name :- Shweta Sunil Randive

Exam Seat No:

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 Table of Contents

SR CONTENTS PAGE
NO. NO.
1. CIRCUIT FOR BIT ADDER 5

2. 1-BIT ADDER CONFIGURATION 8

AND TESTING

3. 4-BIT ADDER CONFIGURATION 10

AND TESTING

4. CONCLUSION 14

5. REFERENCES 15

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 CIRCUIT FOR 4-BIT ADDER

Objective: Design a high speed of 4-bit adder.

Circuit Configuration

The targeted adder circuit configuration is shown in figure 1. It consists

of three blocks---PG, C-chain, and SUM.

Figure 1. Adder Circuit Configuration

PG Block

In the PG block, Pi (propagation) and Gi (generation) can be obtained

by the functions below:

Pi = Ai 
Bi Gi =
Ai Bi

C-chain Circuit Characteristics and Simulation

The C-Chain is constructed in Figure 2. We design a C_chain circuit with

a voltage from Vdd to Vss, which is a little bit different from the circuit in
textbook. This circuit function is ,
when P =1, G = 0, G' = 1, Transistor M2 and M4 are off, M3 is on, the TG is
conducting, and Cin is transmitted to the output Cout = Cin.
when P = 0, P' = 1, the TG is cut off, M4 is on Cout = G.

The schematic simulation and the final simulation after the layout
extraction are shown in Figure 3 and Figure 4. The layout of c-chain is
shown in Appendix 1.

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 Figure 2. Circuit of C-Chain

Figure 3. Simulation of C-Chain Schematic

Figure 4. Simulation of C-Chain After Layout Extraction

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2 SUM Block

The function of Sum is Si = Pi + Ci-1. Its implementation is very simple, so the

simulation result is omitted here.

In above two simulations, we can see that their functions are the same and the
waveforms are consistent.

2. 2 XNOR Circuit Description and simulation

Because of request for faster

and/or more compact circuit
structures, here we select the
mirror circuit to implement
XNOR, in which the N-MOS
and P-MOS arrays have the
exactly the same structure
and have the same
characteristics as series-
parallel logic formation and
easy to layout. Figure 5 shows
the XNOR mirror circuit.
This circuit is of interest
because it has shorter
switching time. The time Figure 5. X-NOR Mirror Circuit
constant in Figure 5 is given
by:
 = R C + 2R C
p p 2 p out

p is less than its corresponding series-parallel logic. In addition, the

layout is simpler because of the symmetry of the four branches. The
mirror circuit we design is illustrated in Figure 6.

Figure 6: X-NOR Circuit

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Appendix 2 shows the layout of XNOR and the schematic simulation as
well as the simulation after the layout extraction is shown in Figure 7
and Figure 8.

Figure 7. XNOR schematic Simulation

Figure 8. Simulation after Extraction of layout

1-Bit Adder Configuration and Testing

Structure and Simulation of 1Bit Adder

In design, we use C-chain, XNOR, Inverter, and NAND gates to build up

1-bit adder. The 4-bit adder is built by assembling four 1-bit adder. The
characteristics of building blocks are verified first.

Figure 9 shows the 1-bit-adder circuit. Its simulation is shown in Figure

10. The logic is correct. The layout is shown in Appendix 4. Layout
simulation is shown in Figure 11, the result is almost the same as
schematic simulation.

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 Figure 9: Circuit of 1-Bit Adder Schematic

Figure 10: Schematic simulation of 1-Bit Adder

Figure 11: Simulation After Layout Extraction

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 Noise Margin Testing

The circuit below (Figure 12) is used to test noise margin of 1-bit adder.
Cin connects to Vss, A connects to Vdd. B is input signal, which is used to test
and analysis DC characteristics. Its DC character is shown in Appendix 3.

Figure 12. Noise Margin Testing

Noise Margin can be calculated from the data in Appendix 3.

NMH = |VIlmax – VOLmax| = | 1.37 - 0.0 | = 1.37

V ; NML = |VlHmin – VOHmin| = | 1.36 - 3.3 | =
1.94 V.

3. 4-Bit Adder Configuration and Testing

4-Bit Adder Configuration

Figure 13: 4-Bit Adder circuit

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The structure of 4-bit adder is composed of four 1-bit adder as shown
in Figure 13.

4-Bit Adder Testing

Figure 14: Testing of 4-Bit Adder

Layout of 4-Bit Adder

From layout figure in Appendix 4. Area = 107.2 102.42=10977.282

Logic Simulation of Layout

The logic simulation waveforms of are in Appendix 5.

Layout With PAD

The layout with PAD is show in Appendix 6.

4. Worst Case Testing of Adder

Description of Worst Case

The worst case occurs when P0 P1 P2 P3 all equal to “1”, Cin is

propagated to Cout and SUM3 is determined by C2, etc. The testing circuit
is shown in Figure 13. Here all A input set to “1” and all B input set to “0”,
when Cin changes the longest delay can be obtained from SUM3 or Cout.

Simulation for Worst Case

The worst case testing circuit and the simulation results of schematic and
layout are shown in Figure 15 and Figure 16 respectively. In layout
simulation in Figure 17(also in Appendix 7, 8). The longest propagate
delay occur on Cin to Cout

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because of the line delay in layout. We can get the longest propagate delay
from the waveform in Appendix 7.

tdr = 1.09 ns , tdf = 1.24 ns

Td_avg = 0.5 ( tdr + tdf ) ns =1.165 ns

The longest rise and fall time happened on SUM out and can be obtained
from Appendix 8.
tr = 0.588 ns , tf = 0.688 ns

The rise time and fall time is less than 1.5ns, which satisfy design
requirement.

Figure 15. Testing for Worst Case

Figure 16. Schematic simulation of Worse Case

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Figure 17. Layout simulation of Worse Case

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 CONCLUSION

The Half Adder and Full Adder are the elementary unit of different computerized
circuits, for example, PCs, Calculators, advanced digital systems. The benefit of
utilizing Adders is that it is the piece of the advanced circuit. What's more, logic gates
shape the foundation of the advanced circuit, and they process the input extremely fast. The
swiftness by logic gates is in microseconds, and we require quick calculation of results in
relatively every application, and in this way, we utilize adders.

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 REFERENCES

1. Neil H. E Weste, Principles of CMOS VLSI Design --- A systems

Perspective 2nd, Kamran Eshraghian, 1994.
2. Jan M. Rabaey, Digital Integrated Circuits --- A Design Perspective,
Prentice- Hall, 1996.
3. John P. uyemura, CMOS Logic Circuit Design, Kluwer Academic Publishers,

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