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HX8369A

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( DOC No.

HX8369-A00-DS )

HX8369-A00
480RGB x 864 dot, 16.7M color,
with internal GRAM,
TFT Mobile Single Chip Driver
Version 02 October, 2010
HX8369-A00
480RGB x 864 dot, 16.7M color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Contents October, 2010

1. General Description ..........................................................................................................................10

2. Features .............................................................................................................................................11
2.1 Display........................................................................................................................................11
2.2 Display module...........................................................................................................................11
2.3 Display / Control interface ..........................................................................................................12
2.4 Input power.................................................................................................................................12
2.5 Miscellaneous.............................................................................................................................12
3. Device Overview ...............................................................................................................................13
3.1 Block diagram.............................................................................................................................13
3.2 Pin description............................................................................................................................14
3.3 Pin assignment...........................................................................................................................18
3.4 PAD coordinates.........................................................................................................................19
3.4.1 Bump arrangement ................................................................................................................27
4. Interface .............................................................................................................................................29
4.1 System interface.........................................................................................................................29
4.1.1 DBI-A / DBI-B interface ..........................................................................................................31
4.2 Serial data transfer interface (DBI-C) .........................................................................................42
4.2.2 DPI interface (Display Pixel Interface) ...................................................................................46
5. Function Description ........................................................................................................................52
5.1 Display data GRAM....................................................................................................................52
5.2 Address counter (AC).................................................................................................................52
5.3 Source, gate and memory map..................................................................................................53
5.3.1 480RGB x 864 resolution.......................................................................................................53
5.3.2 480RGB x 854 resolution.......................................................................................................54
5.3.3 480RGB x 800 resolution.......................................................................................................55
5.3.4 480RGB x 640 resolution.......................................................................................................56
5.3.5 360RGB x 640 resolution.......................................................................................................57
5.3.6 480RGB x 720 resolution.......................................................................................................58
5.4 MCU to memory write / read direction........................................................................................59
5.5 Fully display, partial display, vertical scrolling display ................................................................61
5.5.1 Fully display ...........................................................................................................................61
5.5.2 Vertical scrolling display.........................................................................................................67
5.5.3 Tearing effect output line........................................................................................................70
5.6 Color depth conversion ..............................................................................................................74
5.6.1 Color depth conversion Look-up tables .................................................................................74
5.7 Oscillator.....................................................................................................................................80
5.8 Source driver ..............................................................................................................................81
5.9 LCD power generation scheme..................................................................................................82
5.10 DC/DC converter circuit..............................................................................................................83
5.10.1 Use PFM DC/DC converter ...............................................................................................83
5.10.2 Use HX5186-A...................................................................................................................84
5.11 Idle display .................................................................................................................................85
5.12 Gamma characteristic correction function..................................................................................86
5.13 Characteristics of I/O................................................................................................................128
5.13.1 Output or bi-directional (I/O) pins ....................................................................................128
5.13.2 Input pins .........................................................................................................................128
5.14 GIP control singal .....................................................................................................................129
5.15 Sleep Out –command and self-diagnostic functions of the display module.............................130
5.15.1 Register loading detection ...............................................................................................130
5.15.2 Functionality detection .....................................................................................................131

Himax Confidential - P.2-

List of Contents October, 2010

5.16 Power on/off sequence.............................................................................................................132
5.16.1 Case 1: RESX line is held high or unstable by host at power on ....................................133
5.16.2 Case 2: RESX line is held low by host at power on ........................................................134
5.17 Uncontrolled power off .............................................................................................................134
5.18 Content adaptive brightness control (CABC) function .............................................................135
5.18.1 Module architectures .......................................................................................................136
5.18.2 CABC block .....................................................................................................................137
5.18.3 Brightness control block ..................................................................................................138
5.18.4 Minimum brightness setting of CABC function ................................................................139
5.19 OTP programing .......................................................................................................................140
5.19.1 OTP table.........................................................................................................................140
5.19.2 OTP programming flow....................................................................................................143
5.19.3 Programming sequence ..................................................................................................144
5.19.4 OTP Programming example of VCOM setting VCMC_F and VCMC_B .........................145
5.19.5 OTP Programming example of ID1, ID2 and ID3 ............................................................146
5.19.6 OTP read example of 0x1Bh (VCOM setting re-load) .....................................................147
5.19.7 OTP read example of VCMC_F1.....................................................................................148
5.20 Temperature sensor control......................................................................................................149
6. Command.........................................................................................................................................150
6.1 Command list ...........................................................................................................................150
6.1.1 Standard command..............................................................................................................150
6.1.2 User define command list table............................................................................................154
6.2 Command description ..............................................................................................................158
6.2.1 NOP (00h) ............................................................................................................................158
6.2.2 Software reset (01h) ............................................................................................................159
6.2.3 RDNUMPE: Read number of the parity errors (05h) ...........................................................160
6.2.4 Get_red_channel (06h) ........................................................................................................161
6.2.5 Get_green_channel (07h) ....................................................................................................162
6.2.6 Get_blue_channel (08h) ......................................................................................................163
6.2.7 Get_power_mode (0Ah).......................................................................................................164
6.2.8 Read display MADCTL (0Bh)...............................................................................................165
6.2.9 Get_pixel_format (0Ch)........................................................................................................167
6.2.10 Get_display_mode (0Dh).................................................................................................169
6.2.11 Get_signal_mode (0Eh)...................................................................................................170
6.2.12 Get_diagnostic_result (0Fh) ............................................................................................171
6.2.13 Enter_sleep_mode (10h) .................................................................................................172
6.2.14 Exit_sleep_omde (11h) ....................................................................................................173
6.2.15 Enter_partial_mode (12h) ................................................................................................174
6.2.16 Enter_normal_mode (13h)...............................................................................................175
6.2.17 Exit_inversion_mode (20h)..............................................................................................176
6.2.18 Enter_inversion_mode (21h) ...........................................................................................177
6.2.19 Set_gamma_curve (26h) .................................................................................................178
6.2.20 Set_display_off (28h).......................................................................................................179
6.2.21 Set_display_on (29h).......................................................................................................180
6.2.22 Set_clumn_address (2Ah) ...............................................................................................181
6.2.23 Set_page_address (2Bh).................................................................................................182
6.2.24 Write_memory_start (2Ch) ..............................................................................................183
6.2.25 Colour Set (2Dh)..............................................................................................................184
6.2.26 Raed_memory_start (2Eh) ..............................................................................................187
6.2.27 Set_partial_area (30h) .....................................................................................................188
6.2.28 Set_scroll_area (33h) ......................................................................................................190
6.2.29 Tearing effect line off (34h) ..............................................................................................193
6.2.30 Set_tear_on (35h)............................................................................................................194
6.2.31 Set_address_mode (36h) ................................................................................................195
Himax Confidential - P.3-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGB x 864 dot, 16.7M color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Contents October, 2010

6.2.32 Set_scroll_start (37h).......................................................................................................197
6.2.33 Idle mode off (38h)...........................................................................................................198
6.2.34 Enter_Idle_mode (39h) ....................................................................................................199
6.2.35 Set_pixel_format (3Ah) ....................................................................................................200
6.2.36 Write_memory_contiune (3Ch)........................................................................................201
6.2.37 Raed_memory_continue (3Eh)........................................................................................202
6.2.38 Set tear scan lines (44h)..................................................................................................203
6.2.39 Get the current scanline(45h) ..........................................................................................204
6.2.40 Write display brightness (51h) .........................................................................................205
6.2.41 Read display brightness value (52h) ...............................................................................206
6.2.42 Write CTRL display (53h) ................................................................................................207
6.2.43 Read CTRL value display (54h) ......................................................................................208
6.2.44 Write content adaptive brightness control (55h) ..............................................................209
6.2.45 Read content adaptive brightness control (56h)..............................................................210
6.2.46 Write CABC minimum brightness (5Eh) ..........................................................................211
6.2.47 Read CABC minimum brightness (5Fh) ..........................................................................212
6.2.48 Read automatic brightness control self-diagnostic result (68h) ......................................213
6.2.49 Read_DDB_start (A1h)....................................................................................................214
6.2.50 Read_DDB_continue (A8h) .............................................................................................216
6.2.51 Read ID1 (DAh) ...............................................................................................................217
6.2.52 Read ID2 (DBh) ...............................................................................................................218
6.2.53 Read ID3 (DCh) ...............................................................................................................219
6.2.54 SETOSC: Set internal oscillator (B0h).............................................................................220
6.2.55 SETPOWER: Set power (B1h) ........................................................................................221
6.2.56 SETDISP: Set display related register (B2h)...................................................................230
6.2.57 SETRGBIF: Set RGB interface related register (B3h).....................................................233
6.2.58 SETCYC: Set display waveform cycle (B4h)...................................................................234
6.2.59 SETVCOM: Set VCOM voltage (B6h) .............................................................................237
6.2.60 SETEXTC: Set extension command (B9h) .....................................................................240
6.2.61 SETOTP: Set OTP (BBh) ................................................................................................241
6.2.62 SETDGCLUT: Set DGC LUT (C1h) .................................................................................242
6.2.63 SETID: Set ID (C3h) ........................................................................................................244
6.2.64 SETCABC: Set CABC Control (C9h)...............................................................................245
6.2.65 SETPANEL (CCh)............................................................................................................247
6.2.66 SETGIP (D5h)..................................................................................................................248
6.2.67 SETTPSNR (D8h)............................................................................................................255
6.2.68 SETGAMMA: Set gamma curve related setting (E0h) ....................................................260
6.2.69 SETOTPKEY (E9h) .........................................................................................................262
6.2.70 GETHXID (F4h) ...............................................................................................................263
6.2.71 SETCNCD/GETCNCD (FDh) ..........................................................................................264
6.2.72 SET SPI READ INDEX (FEh) ..........................................................................................265
6.2.73 GETSPIREAD: Read command data (FFh) ....................................................................266
7. Power Supply ..................................................................................................................................267
7.1 Power supply setup ..................................................................................................................267
7.1.1 Architecture 1 with PFM circuit ............................................................................................267
7.1.2 Architecture 2 with HX5186-A..............................................................................................268
7.2 Voltage configuration................................................................................................................269
8. Electrical Characteristics ...............................................................................................................270
8.1 Absolute maximum ratings .......................................................................................................270
8.2 ESD protection level.................................................................................................................270
8.3 DC characteristics ....................................................................................................................271

Himax Confidential - P.4-

List of Contents October, 2010

8.4 AC characteristics ....................................................................................................................272
8.4.1 DBI Type A interface characteristics ....................................................................................272
8.4.2 DBI Type B interface characteristics ....................................................................................273
8.4.3 DBI Type C interface characteristics....................................................................................274
8.4.4 DPI interface characteristics ................................................................................................275
8.4.5 Reset input timing ................................................................................................................279
8.4.6 DPI Interface Power On/Off Timing......................................................................................280
9. Layout Recommendation ...............................................................................................................282
10. Maximum Layout Resistance.........................................................................................................283
11. Ordering Information ......................................................................................................................284
12. Revision History..............................................................................................................................284

Himax Confidential - P.5-

List of Figures October, 2010

Figure 4.1: DBI-A system interface protocol, write to register or GRAM ...................................31
Figure 4.2: DBI-A system interface protocol, read from register or GRAM................................31
Figure 4.3: DBI-B system interface protocol, write to register or GRAM ...................................32
Figure 4.4: DBI-B system interface protocol, read from register or GRAM................................32
Figure 4.5 Example of DBI-B system 24-bit parallel bus interface.............................................33
Figure 4.6: Write data for RGB 8-8-8 (16.7M colours) bit Input in 24-bit parallel interface........33
Figure 4.7: Example of DBI-A- / DBI-B system 18-bit parallel bus interface..............................34
Figure 4.8: Write data for RGB 5-6-5 (65k colours) bit input in 18-bit parallel interface ............34
Figure 4.9: Write data for RGB 6-6-6(262k colours) bit input in 18-bit parallel interface ...........34
Figure 4.10: Write data for RGB 8-8-8 (16.7M colours) bit input in 18-bit parallel interface......35
Figure 4.11: Example of DBI-A- / DBI-B system 16-bit bus interface.........................................36
Figure 4.12: Write data for RGB 5-6-5 (65k colours) bit input in 16-bit parallel interface ..........36
Figure 4.13: Write data for RGB 6-6-6 (262k colours) bit input in 16-bit parallel interface ........37
Figure 4.14: Write data for RGB 8-8-8-bit (16.7M colours) input in 16-bit parallel interface......37
Figure 4.15: Example of DBI-A- / DBI-B- system 9-bit bus interface .........................................38
Figure 4.16: Write data for RGB 5-6-5(65k colours) bit input in 9-bit parallel interface .............38
Figure 4.17: Write data for RGB 6-6-6-bit (262k colours) input in 9-bit parallel interface..........39
Figure 4.18: Write data for RGB 8-8-8-bit (16.7 M colours) input in 9-bit parallel interface.......39
Figure 4.19: Example of DBI-A- / DBI-B-system 8-bit bus interface ..........................................40
Figure 4.20: Write data for RGB 5-6-5 (65k colours) bit input in 8-bit parallel interface ............40
Figure 4.21: Write data for RGB 6-6-6-bit (262k colours) input in 8-bit parallel interface..........41
Figure 4.22: Write data for RGB 8-8-8-bit (16.7 M colours) input in 8-bit parallel interface.......41
Figure 4.23: Serial data stream, write mode ..............................................................................42
Figure 4.24: DBI Type C: Serial interface protocol 3-wire/4-wire, write mode ...........................43
Figure 4.25: Type C:Serial interface protocol 3-wire/4-wire read mode.....................................44
Figure 4.26: Display module data transfer recovery ..................................................................45
Figure 4.27: PCLK cycle.............................................................................................................46
Figure 4.28: General timing diagram..........................................................................................47
Figure 4.29: DPI (480RGB x 864) timing diagram .....................................................................47
Figure 4.30: 16-bit / pixel 65K colours order on the DPI I/F.......................................................49
Figure 4.31: 18-bit / pixel: 262k colours order on the DPI I/F ....................................................50
Figure 4.32: 24-bit / pixel color order on the RGB I/F ................................................................51
Figure 5.1: MCU to Memory write / read direction .....................................................................59
Figure 5.2: MY, MX, MV setting of 480RGB x 864 dot ..............................................................59
Figure 5.3: MY, MX, MV setting of 480RGB x 864 dot ..............................................................59
Figure 5.4: Address direction settings........................................................................................60
Figure 5.5: 480RGB x 864 resolution.........................................................................................61
Figure 5.6: 480RGB x 854 resolution.........................................................................................62
Figure 5.7: 480RGB x 800 resolution.........................................................................................63
Figure 5.8: 480RGB x 640 resolution.........................................................................................64
Figure 5.9: 360RGB x 640 resolution.........................................................................................65
Figure 5.10: 480RGB x 720 resolution.......................................................................................66
Figure 5.11: Vertical scrolling .....................................................................................................67
Figure 5.12: Memory map of vertical scrolling 1 ........................................................................67
Figure 5.13: Memory map of vertical scrolling 2 ........................................................................68
Figure 5.14: Vertical scroll example 1 ........................................................................................69
Figure 5.15: Vertical scroll example 2 ........................................................................................69
Figure 5.16: Tearing effect output line–mode 1..........................................................................70
Figure 5.17: Tearing effect output line–mode 2..........................................................................70
Figure 5.18: Tearing effect output line–timing diagrm ................................................................70
Figure 5.19: Tearing effect output line –tearing effect line timing...............................................71
Figure 5.20: Tearing effect output line–definition of tf, tr ............................................................71
Figure 5.21: Tearing effect output line–example 1 (Timing) .......................................................72
Figure 5.22: Tearing effect output line–example 1 (Image)........................................................72
Figure 5.23: Tearing effect output line–example 2 (Timing) .......................................................73
Himax Confidential - P.6-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGB x 864 dot, 16.7M color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Figures October, 2010

Figure 5.24: Tearing effect output line–example 2 (Image)........................................................73

Figure 5.25: OSC aritecture .......................................................................................................80
Figure 5.26: LCD power generation scheme .............................................................................82
Figure 5.27: DC/DC converter circuit (PFM Type C)–PCCS=10................................................83
Figure 5.28: DC/DC converter circuit (HX5186-A) .....................................................................84
Figure 5.29: Idle mode grayscale control ...................................................................................85
Figure 5.30: Grayscale control ...................................................................................................86
Figure 5.31: Gamma resister stream and gamma reference voltage ........................................88
Figure 5.32: Gamma resister stream .........................................................................................89
Figure 5.33: Sleep out flow chart–command and self-diagnostic functions.............................130
Figure 5.34: Sleep out flow chart internal function detection ...................................................131
Figure 5.35: Case 1: RESX line is held high or unstable by host at power on ........................133
Figure 5.36: Case 2: RESX line is held low by host at power on.............................................134
Figure 5.37: CABC block diagram............................................................................................135
Figure 5.38: Module architecture .............................................................................................136
Figure 5.39: CABC gain / CABC duty generation ....................................................................137
Figure 5.40: CABC_PWM_OUT output duty............................................................................138
Figure 5.41: OTP programming sequence...............................................................................143
Figure 5.42: OTP programming sequence example 1. ............................................................145
Figure 5.43: OTP programming sequence example 2. ............................................................146
Figure 5.44: OTP programming sequence index 0x1Bh read flow. .........................................147
Figure 5.45: OTP programming sequence read flow. ..............................................................148
Figure 5.46: Temperature sensor .............................................................................................149
Figure 7.1: Power supply with PFM circuit ...............................................................................267
Figure 7.2: Power supply with HX5186-A ................................................................................268
Figure 8.1: DBI Type A interface characteristics(CLK-E mode) ...............................................272
Figure 8.2: DBI Type B interface characteristics ......................................................................273
Figure 8.3: DBI Type C interface characteristics......................................................................274
Figure 8.4: DPI interface characteristics ..................................................................................275
Figure 8.5: Vertical Timings for RGB I/F...................................................................................277
Figure 8.6: Horizontal Timing for RGB I/F ................................................................................278
Figure 8.7: Reset input timing ..................................................................................................279
Figure 8.8 Power On Timing ....................................................................................................280
Figure 8.9 Power Off Timing ....................................................................................................281
Figure 9.1: Layout recommendation ........................................................................................282

Himax Confidential - P.7-

List of Tables October, 2010

Table 4.1: Interface selection .....................................................................................................29
Table 4.2: Pin connection based on different interface ..............................................................30
Table 5.1: Addresses counter range...........................................................................................52
Table 5.2: Memory map of 480RGB x 864 resolution ................................................................53
Table 5.3: Memory map of 480RGB x 854 resolution ................................................................54
Table 5.4: Memory map of 480RGB x 800 resolution ................................................................55
Table 5.5: Memory map of 480RGB x 640 resolution ................................................................56
Table 5.6: Memory map of 360RGB x640 resolution .................................................................57
Table 5.7: Memory map of 480RGB x 720 resolution ................................................................58
Table 5.8: 480RGB x 864 resolution (SRAM assignment) .........................................................61
Table 5.9: 480RGB x 854 resolution (SRAM assignment) .........................................................62
Table 5.10: 480RGB x 800 resolution (SRAM assignment) .......................................................63
Table 5.11: 480RGB x 640 resolution (SRAM assignment) .......................................................64
Table 5.12: 360RGB x 640 resolution (SRAM assignment) .......................................................65
Table 5.13: 480RGB x 720 resolution (SRAM assignment) .......................................................66
Table 5.14: AC characteristics of tearing effect signal ...............................................................71
Table 5.15: Look-up tables-1 ......................................................................................................74
Table 5.16: Look-up tables-2 ......................................................................................................75
Table 5.17: Look-up tables-3 ......................................................................................................76
Table 5.18: Look-up tables-4 ......................................................................................................77
Table 5.19: Look-up tables-5 ......................................................................................................78
Table 5.20: Look-up tables-6 ......................................................................................................79
Table 5.21: Gamma-Adjustment registers..................................................................................87
Table 5.22: Offset adjustment 0~5 .............................................................................................90
Table 5.23: Center adjustment ...................................................................................................90
Table 5.24: VinP0 .......................................................................................................................91
Table 5.25: VinP1 .......................................................................................................................92
Table 5.26: VinP2 .......................................................................................................................93
Table 5.27: VinP14 .....................................................................................................................94
Table 5.28: VinP15 .....................................................................................................................95
Table 5.29: VinP16 .....................................................................................................................96
Table 5.30: VinP5 .......................................................................................................................98
Table 5.31: VinP11 ...................................................................................................................100
Table 5.32: VinP3 .....................................................................................................................101
Table 5.33: VinP4 .....................................................................................................................102
Table 5.34: VinP6 .....................................................................................................................102
Table 5.35: VinP7 .....................................................................................................................103
Table 5.36: VinP8 .....................................................................................................................103
Table 5.37: VinP9 .....................................................................................................................104
Table 5.38: VinP10 ...................................................................................................................104
Table 5.39: VinP12 ...................................................................................................................105
Table 5.40: VinP13 ...................................................................................................................105
Table 5.41: VinN0 .....................................................................................................................106
Table 5.42: VinN1 .....................................................................................................................107
Table 5.43: VinN2 .....................................................................................................................108
Table 5.44: VinN14 ...................................................................................................................109
Table 5.45: VinN15 ...................................................................................................................110
Table 5.46: VinN16 ................................................................................................................... 111
Table 5.47: VinN5 .....................................................................................................................113
Table 5.48: VinN11 ...................................................................................................................115
Table 5.49: VinN3 .....................................................................................................................116
Table 5.50: VinN4 .....................................................................................................................117
Table 5.51: VinN6 .....................................................................................................................117
Table 5.52: VinN7 .....................................................................................................................118
Table 5.53: VinN8 .....................................................................................................................118
Himax Confidential - P.8-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGB x 864 dot, 16.7M color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Tables October, 2010

Table 5.54: VinN9 .....................................................................................................................119
Table 5.55: VinN10 ...................................................................................................................119
Table 5.56: VinN12 ...................................................................................................................120
Table 5.57: VinN13 ...................................................................................................................120
Table 5.58: Voltage calculation formula of 64-grayscale voltage (positive polarity).................122
Table 5.59: Voltage calculation formula of 64-grayscale voltage (negative polarity) ...............124
Table 5.60: Voltage calculation formula of 256-grayscale voltage (positive/negative polarity)127
Table 5.61 Characteristics of output or bi-directional (I/O) pins ...............................................128
Table 5.62 Characteristics of input pins ...................................................................................128
Table 5.63 CABC timing table ..................................................................................................138
Table 5.64: OTP Programming sequence ................................................................................144
Table 7.1: Adoptability of component .......................................................................................269
Table 8.1: Absolute maximum rating ........................................................................................270
Table 8.2: ESD protection level ................................................................................................270
Table 8.3: DC characteristic .....................................................................................................271
Table 8.4: DBI Type A interface characteristics ........................................................................272
Table 8.5: DBI Type B interface characteristics........................................................................273
Table 8.6: DBI Type C interface characteristics .......................................................................274
Table 8.7: DPI interface characteristics....................................................................................276
Table 8.8 Vertical Timings for RGB I/F .....................................................................................277
Table 8.9 Horizontal Timings for RGB I/F.................................................................................278
Table 8.10: Reset timing...........................................................................................................279
Table 10.1: Maximum layout resistance ...................................................................................283

Himax Confidential - P.9-

Version 02 October, 2010

1. General Description
This document describes Himax’s HX8369-A00 supports WVGA resolution driving
controller. The HX8369-A00 is designed to provide a single-chip solution that
combines a source driver, power supply circuit to drive a TFT dot matrix LCD with
480RGBx864 dots at maximum.

The HX8369-A00 can be operated in low-voltage condition for the interface and
integrated internal boosters that produce the liquid crystal voltage, breeder resistance
and the voltage follower circuit for liquid crystal driver. In addition, The HX8369-A00
also supports various functions to reduce the power consumption of a LCD system
via software control.

The HX8369-A00 supports several interface modes, including MPU DBI Type A/Type
B interface mode, RGB DBI Type C interface mode. The interface mode is selected
by the external hardware pins BS3~0.

The HX8369-A00 is suitable for any small portable battery-driven and long-term
driving products, such as small PDAs, digital cellular phones and bi-directional
pagers.

Himax Confidential -P.10-

2. Features
2.1 Display

Single chip solution for a WVGA GIP (Gate In Panel) type TFT LCD display
Resolution:
480RGB x 864
480RGB x 854
480RGB x 800
480RGB x 640
480RGB x 720
360RGB x 640
Display color modes
Full color mode:
16.7M colours (24-bit 8(R):8(G):8(B))
Reduce color mode:
262k colours (18-bit 6(R):6(G):6(B))
65k colours (16-bit 5(R):6(G):5(B))
8 colors (Idle mode on): 8 colors (3-bit binary mode)

2.2 Display module

Support 1440 source channel outputs

Internal level shifter for GIP gate control
Supports 1-dot / 2-dot / column / Zig-Zag inversion
Gamma correction (1 preset gamma curve)
On module VCOM control (-2 to 0V common electrode output voltage range)
On module DC/DC converter
VSP=4.7 to 5.7V
VSN=-5.7 to -4.7V
Positive source output voltage level: VSPR=3.5V to 5V
Negative source output voltage level: VSNR=-5V to -3.5V
Positive gate driver output voltage level: VGH=+9V to +20V
Negative gate driver output voltage level: VGL=-6V to -13.5V
GIP most negative reference voltage: LVGL=VGL –VDD3
VCOM=-2.0V to 0V, a step=16mV
Frame memory area 480 (H) x 864 (V) x 24-bit

Himax Confidential -P.11-

2.3 Display / Control interface

Display interface types supported

MPU mode
DBI Type B (80 System) interface (16- / 18- / 24-bit bus)
DBI Type A (68 System) interface (16- / 18- bit bus)
DBI Type C (Serial data transfer interface) interface

RGB mode
16 bit/pixel R(5), G(6), B(5)
18 bit/pixel R(6), G(6), B(6)
24 bit/pixel R(8), G(8), B(8)

2.4 Input power

I/O and interface power supply (VDD1): 1.65V to 3.3V

Analog power supply (VDD2): 2.3V to 4.8V
Logic power supply (VDD3): 2.3V to 4.8V
DSI power supply (DSI_VCC): 1.65V to 3.3V
MDDI power supply (DSI_VCC): 2.3V to 3.3V
OTP programming voltage (VPP): 7.5V ± 0.2V

2.5 Miscellaneous

Partial display mode

Software programmable color depth mode
Oscillator for display clock generation
Low power consumption, suitable for battery operated systems
CMOS compatible inputs
Proprietary multi phase driving for lower power consumption
GAS function for preventing image sticking when abnormal power off
Optimized layout for COG assembly
Temperature range: -40 to +85 °C
HBM ESD (Human Body Mode)>2KV, MM(Machine Mode)>±200V and
Latch up>±200mA
Support inversion mode
DC/DC converter for source
Support DC COM driving
VCOM voltage generator
On-chip OTP program voltage generator
OTP memory to store initialization register settings
3 times MTP for VCOM setting ,ID setting
Support CABC (Content Adaptive Brightness Control) function
Support DGC (Digital Gamma Correction) function
Temperature Sensor Control

Himax Confidential -P.12-

3. Device Overview
3.1 Block diagram

Note: MPU I/F display data path

RGB I/F display data path PWM_OUT S1 ~ S1441
VDD1
VDD2
VDD3

OTP
VPP
BS3-0 4 ABC function
Source
MPU I/F driver
CSX
RDX_E 24-bit
Internal
WRX_DCX 18-bit
register
16-bit
DCX_SCL
9-bit
DB23~0 D/A Converter
24 8-bit
circuit
SDI
SPI I/F
SDO 3-wire GRAM
24-bit control
VSYNC_TE Digital Data Latch
RGB I/F display Gamma
HSYNC data
16-bit Correction
PCLK
18-bit GRAM
DE
24-bit V0~255
RESX Grayscale voltage
generator VGS
DSI_LDO_ENB/ 24-bit
MDDI_LDO_ENB display Mode
DSI_CLKP data selection CABC function
(MDDI_STBP) /
DSI_CLKN
2
(MDDI_STBN) VTESTOUTP /
DSI_D0P Gamma adjusting circuit
VTESTOUTN
(MDDI_D1P)/ 2
DSI_D0N 2 DSI / MDDI
(MDDI_D1N) Interface TE
Timing
DSI_D1P
Control
(MDDI_D0P)/
DSI_D1N 2
(MDDI_D0N)
DSI_VCC / Gate GOUTL_1~
MDDI_VCC Control GOUTL_10
DSI_VSS/ Temperature
Generator Unit
MDDI_VSS sensor control 20
Timing GOUTR1~
OSC RC OSC
GOUTR_10
TEST2~1

VCI
PFM DC / DC Converter VCOM Cricuit Voltage reference
VSSA

VSSAC
VSSD
V COM R

DSI_LDO
VSN

C21AP / C21AN
C22AP / C22AN
C23AP / C23AN
C24AP / C24AN

C41AP / C41AN

VSPR
VSNR

VDDD
VDDDN
VSP

VREF
VCSW1
VCSW2

LVGL
V GH
V GL

V COM

Himax Confidential -P.13-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
3.2 Pin description
Host interface pins
Connected
Signals I/O Pin no. Description
with
Select the MPU interface mode as listed below:
Display
BS3 BS2 BS1 BS0 MPU interface mode DB pins
mode
DBI TYPE-A 8-bit DB23-DB8: Unused,
0 0 0 0 Type 1
(CLK-E) DB7-DB0: Data
DBI TYPE-A 9-bit DB23-DB9:Unused,
0 0 0 1 Type 1
(CLK-E) DB8-DB0: Data
DBI TYPE-A 16-bit DB23-DB16: Unused,
0 0 1 0 Type 1
(CLK-E) DB15-DB0: Data
DBI TYPE-A 18-bit DB23-DB18: Unused,
0 0 1 1 Type 1
(CLK-E) DB17-DB0: Data
DB23-DB8: Unused
0 1 0 0 DBI TYPE-B 8-bit Type 1
DB7-DB0: Data
DB23-DB9:Unused,
0 1 0 1 DBI TYPE-B 9-bit Type 1
DB8-DB0: Data
VSSD / DB23-DB16: Unused,
BS3 ~ BS0 I 4 0 1 1 0 DBI TYPE-B 16-bit Type 1
VDD1 DB15-DB0: Data
DB23-DB18: Unused,
0 1 1 1 DBI TYPE-B 18-bit Type 1
DB17-DB0: Data
1 0 0 0 - - -
1 0 0 1 - - -
1 0 1 0 DBI TYPE-B 24-bit DB23-DB0: Data Type 1
1 1 0 0 - - -
DPI/DBI TYPE-C SDI/SDO,
1 1 0 1 Type 3
Option 1 DB23-DB0
DPI/DBI TYPE-C SDI/SDO,
1 1 1 0 Type 3
Option 2 DB23-DB0
DPI/DBI TYPE-C SDI/SDO,
1 1 1 1 Type 3
Option 3 DB23-DB0
Pixel format (RGB565 / RGB666 / RGB888) is selected by DCS command (0x3Ah)
Note 1: 3-wire serial Interface only active on MDDI / Hibernation mode.
Must be connected to VSSD or VDD1.
Chip select signal.
Low: chip can be accessed;
CSX I 1 MPU
High: chip cannot be accessed.
If this pin is not used, please connect it to VSSD or VDD1.
MPU or Reset pin. Setting either pin low initializes the LSI. Must be reset after
RESX I 1
reset circuit power is supplied (Must be connected to VSSD or VDD1).
DBI Type-A: 0: Read/Write disable, 1: Read / Write enable.
RDX_E I 1 MPU DBI Type-B: Serves as a read signal and read data at the low level.
If not use, let it open or connected to VDD1.
DBI Type-A/B: Data / Command Selection pin
DCX_SCL I 1 MPU DBI Type-C: it servers as SCL (Serial Clock)
If not use, let it open or connected to VDD1.
DBI Type-B mode: Serves as a write signal and write data at the low level.
WRX_DCX I 1 MPU DBI Type-A mode: 0: Read/Write disable, 1: Read / Write enable.
If not use, let it open or connected to VDD1.
DBI type interface:
Data bus Used Unused
8-bit bus DB7-0 DB23-8
9-bit bus DB8-0 DB23-9
16-bit bus DB15-0 DB23-16
18-bit bus DB17-0 DB23-18
24-bit bus DB23-0 -
DPI type interface:
DB23~0 I/O 24 MPU Data bus Used Unused
DB21-17, DB23-22,
16-bit bus DB13-8, DB16-14,
DB5-1 DB7-6, DB0
DB21-16, DB23-22,
18-bit bus DB13-8, DB15-14,
DB5-0 DB7-6
24-bit bus DB23-0 -
Let the unused pins open for each mode.
Himax Confidential -P.14-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
SDO O 1 MPU Serial data output. Let it to open in MPU interface mode.
SDI I 1 MPU Serial data input pin in serial interface operation.
Clock input and RGB interface
Line synchronizing signal.
HSYNC I 1 MPU
Must be connected to VSSD or VDD1 if not used.
A data enable signal in RGB I/F mode. Has to be fixed to VSSD level in
DE I 1 MPU
MPU interface mode.
Serves VS signal pin on RGB interface. (Input pad).
VSYNC I 1 MPU
Must be connected to VSSD or VDD1 if not used.
Dot clock signal.
PCLK I 1 MPU
Must be connected to VSSD or VDD1 if not used.
Source driver output pins
Output voltages applied to the liquid crystal.
RGB resolution Source channels
S1 to S1441 O 1441 LCD 360RGB S1 ~ S540, S901 ~ S1440
480RGB S1 to S1440
480RGB+Z inversion S1 to S1441
TE O 1 MPU Serves TE (Tearing Effect ) pin on MPU interface.
GIP control singal and bias voltage
CGOUT1_L
CGOUT2_L
CGOUT3_L
CGOUT4_L
CGOUT5_L Signals for right side GIP on panel view (Left side in IC bump view),
O 14 GIP
CGOUT6_L Unused pins should be left open.
CGOUT7_L
CGOUT8_L
CGOUT9_L
CGOUT10_L
CGOUT1_R
CGOUT2_R
CGOUT3_R
CGOUT4_R
CGOUT5_R Signals for Right side GIP on panel view (Right side in IC bump view),
O 14 GIP
CGOUT6_R Unused pins should be left open.
CGOUT7_R
CGOUT8_R
CGOUT9_R
CGOUT10_R
VBIAS O 2 GIP Bias voltage for some special GIP circuits. If not used, leave this pin open.
Power supply pins
Select the VSP/VSN bumping method as listed below:
PCCS1 PCCS0 Driving mode
0 0 Setting invalid
VSSD / 0 1 Setting invalid
PCCS0 ~ PCCS1 I 2
VDD3 1 0 PFM one Inductor Mode (Type C)
1 1 Charge Bump Mode(Use HX5186-A)
Must be connected to VSSD or VDD3.
Power
VDD1 I 5 A power supply for the I/O circuit. VDD1=1.65 to 3.3V
supply
A power supply for the analog power. VDD2=2.3 to 4.8V
Power
VDD2 I 6 VDD2 input level should be same as VDD3 input level to avoid the
supply
level-mismatching at internal level shifter circuit.
Power
VDD3 I 6 A power supply for the logic power, DC/DC converter VDD3=2.3 to 4.8V.
supply
Power Analoge ground. VSSA=0V. When using the COG method, connect to
VSSA P 6
supply VSSD on the FPC to prevent noise.
Power
VSSAC P 2 Analoge ground. Must connect to VSSA on the FPC.
supply
Power Ground for the internal logic. VSSD=0V. When using the COG method,
VSSD P 16
supply connect to VSSA on the FPC to prevent noise.
Power External high voltage pin used in OTP mode and operates at 7.5V.
VPP I 2
supply If not used, let it open.

Himax Confidential -P.15-

Himax Confidential -P.16-

Himax Confidential -P.17-

(A1)

DUMMY17
S1441
NO.1760
NO.1 S1440
S1439
S1438
DUMMY1
CGOUT1_L
CGOUT2_L
CGOUT3_L
CGOUT4_L
CGOUT5_L
CGOUT5_L
CGOUT6_L
CGOUT6_L
CGOUT7_L
CGOUT7_L
CGOUT8_L
CGOUT8_L
CGOUT9_L

Chip Size : 22430 x 1701 um CGOUT10_L

VGL
VGL
VGL
VBIAS
LVGL

(Include scribe line = 80 um) LVGL

LVGL
DUMMY2
VCOM
VCOM
VCOM

Chip thickness: 250 um ± 25 um DUMMY3

DUMMYR1
DUMMYR2
DUMMY4
VGL
VGL
VGL
LVGL
LVGL
Pad Location:PAD Center LVGL
LVGL
LVGL
Coordinate Origin: Chip Center VCOM
VCOM
VCOM

Au Bump Size: VCOM

C41AP
C41AP
C41AP
C41AN
C41AN
C41AN
1. 50 um x 80 um VGH
VGH
VGH

Input: VGH
VGH
VGH

No.1 ~ No.312 C21AP

C21AP
C21AP
C21AP
C21AN
C21AN
C21AN
2. 15 um x 95 um C21AN
C23AP
C23AP

Staggered LCD output side C23AP

C23AP
C23AN

No.313 ~ No.1760 C23AN

C23AN
C23AN
C22AP
C22AP
C22AP
C22AP
C22AN
C22AN
C22AN

The chip size includes the core size C22AN

C24AP
C24AP
C24AP
seal ring size, and scribe line size C24AP
C24AN
C24AN
C24AN

Au bump pitch: Refer to Pad Coordinate

. C24AN
VPP
VPP

Au bump height : 12 um ± 3 um VDDDN

VDDDN
VDDDN
VDDDN
Numbers in the figure corresponds to VDDDN
VDD2
VDD2
pad coordinate numbers. VDD2
VDD2
VDD2
VDD2
VREF
VREF
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDD1
VDD1
VDD1
VDD1
VDD1
CABC_PWM_OUT
TE
TEST1
TEST2
BS0

Top View BS1

BS2
BS3
RESX
IOGNDDUM
DB23/TS7
DB22/TS6
DB21/TS5
Face Up
BUMP DB20/TS4
DB19/TS3
DB18/TS2
(Bump View)
DB17/TS1
DB16/TS0
HX8369-A00 Pin
Chip DB15
DB14
DB13
DB12
DB11
Assignment
DB10
DB9 S722
DB8 S721
DB7 DUMMY14
DB6
DUMMY13
DB5
DUMMY12
DB4
DB3
DB2
DB1
Y DUMMY11
S720
S719
DB0
IOGNDDUM NO.1033
RDX_E
WRX_DCX
DCX_SCL
CSX
IOGNDDUM
SDI
SDO
VSYNC
HSYNC
X
DE
PCLK
DSI_LDO_ENB/MDDI_LDO_ENB
DUMMY5
OSC
PCCS0
PCCS1
DSI_VSS/MDDI_VSS
DSI_D0N/MDDI_D1N
DSI_D0N/MDDI_D1N
DSI_D0N/MDDI_D1N
DSI_D0P/MDDI_D1P
DSI_D0P/MDDI_D1P
DSI_D0P/MDDI_D1P
DSI_VSS/MDDI_VSS
DSI_CLKN/MDDI_STBN
DSI_CLKN/MDDI_STBN
DSI_CLKN/MDDI_STBN
DSI_CLKP/MDDI_STBP
DSI_CLKP/MDDI_STBP
DSI_CLKP/MDDI_STBP
DSI_VSS/MDDI_VSS
DSI_D1N/MDDI_D0N
DSI_D1N/MDDI_D0N
DSI_D1N/MDDI_D0N
DSI_D1P/MDDI_D0P
DSI_D1P/MDDI_D0P
DSI_D1P/MDDI_D0P
DSI_VSS/MDDI_VSS
DSI_LDO/MDDI_LDO
DSI_LDO/MDDI_LDO
DSI_VCC/MDDI_VCC
DSI_VCC/MDDI_VCC
DSI_VCC/MDDI_VCC
DSI_VCC/MDDI_VCC
DSI_VCC/MDDI_VCC
DSI_VSS/MDDI_VSS
DSI_VSS/MDDI_VSS
DSI_VSS/MDDI_VSS
DSI_VSS/MDDI_VSS
DSI_VSS/MDDI_VSS
VSSAC
VSSAC
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VSPR
VSPR
VSPC
VSP
VSP
VSP
VSP
VSP
VSP
VSP
VCSW1
VCSW1
VCSW1
VCSW1
VCSW2
VCSW2
VCSW2
VCSW2
VSNR
VSNR
VSNC
VSN
VSN
VSN
VSN
VSN
VSN
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VGH
VGH
VGH
VGH
VCOM
VCOM
VCOM
VCOM
LVGL
LVGL
LVGL
LVGL
VTESTOUTP
DUMMY6
VCOMR
VTESTOUTN
VCOM
VCOM
VCOM
DUMMY7
DUMMY8
LVGL
LVGL
LVGL
VBIAS
VGL
VGL
VGL
VGL
CGOUT10_R
CGOUT9_R
CGOUT8_R
CGOUT8_R
CGOUT7_R
CGOUT7_R
CGOUT6_R
CGOUT6_R
CGOUT5_R
CGOUT5_R
CGOUT4_R
CGOUT3_R
CGOUT2_R
NO.312 CGOUT1_R
DUMMY9
DUMMY10

S2
S2
S1
DUMMY16
DUMMY15

NO.313

(A2)

Himax Confidential -P.18-

4 CGOUT3_L -10675 -672 64 -6475 -672 124 VDD1 -2275 -672 184 DSI_D0P / 1925 -672
C23AP MDDI_D1P
5 CGOUT4_L -10605 -672 65 -6405 -672 125 VDD1 -2205 -672 185 DSI_VSS / 1995 -672
C23AP MDDI_VSS
DSI_CN /
6 CGOUT5_L -10535 -672 66 C23AP -6335 -672 126 VDD1 -2135 -672 186 MDDI_STBN 2065 -672
DSI_CN /
7 CGOUT5_L -10465 -672 67 C23AN -6265 -672 127 CABC_PWM_OUT -2065 -672 187 MDDI_STBN 2135 -672

8 CGOUT6_L -10395 -672 68 -6195 -672 128 -1995 -672 188 DSI_CN / 2205 -672
C23AN TE MDDI_STBN
9 CGOUT6_L -10325 -672 69 -6125 -672 129 -1925 -672 189 DSI_CP / 2275 -672
C23AN TEST1 MDDI_STBP
DSI_CP /
10 CGOUT7_L -10255 -672 70 C23AN -6055 -672 130 TEST2 -1855 -672 190 MDDI_STBP 2345 -672

11 CGOUT7_L -10185 -672 71 -5985 -672 131 BS0 -1785 -672 191 DSI_CP / 2415 -672
C22AP MDDI_STBP
12 CGOUT8_L -10115 -672 72 DSI_VSS /
C22AP -5915 -672 132 BS1 -1715 -672 192 MDDI_VSS 2485 -672

13 CGOUT8_L -10045 -672 73 -5845 -672 133 BS2 -1645 -672 193 DSI_D1N / 2555 -672
C22AP MDDI_D0N
DSI_D1N /
14 CGOUT9_L -9975 -672 74 C22AP -5775 -672 134 BS3 -1575 -672 194 MDDI_D0N 2625 -672
DSI_D1N /
15 CGOUT10_L -9905 -672 75 C22AN -5705 -672 135 RESX -1505 -672 195 MDDI_D0N 2695 -672

16 VGL -9835 -672 76 -5635 -672 136 IOGNDDUM -1435 -672 196 DSI_D1P / 2765 -672
C22AN MDDI_D0P
DSI_D1P /
17 VGL -9765 -672 77 C22AN -5565 -672 137 DB23 -1365 -672 197 MDDI_D0P 2835 -672
DSI_D1P /
18 VGL -9695 -672 78 C22AN -5495 -672 138 DB22 -1295 -672 198 2905 -672
MDDI_D0P
DSI_VSS /
19 VBIAS -9625 -672 79 C24AP -5425 -672 139 DB21 -1225 -672 199 2975 -672
MDDI_VSS
DSI_LDO /
20 LVGL -9555 -672 80 C24AP -5355 -672 140 DB20 -1155 -672 200 MDDI_LDO 3045 -672
DSI_LDO /
21 LVGL -9485 -672 81 C24AP -5285 -672 141 DB19 -1085 -672 201 3115 -672
MDDI_LDO
DSI_VCC /
22 LVGL -9415 -672 82 C24AP -5215 -672 142 DB18 -1015 -672 202 3185 -672
MDDI_VCC
23 DUMMY2 -9345 -672 83 -5145 -672 143 DB17 -945 -672 203 DSI_VCC / 3255 -672
C24AN
MDDI_VCC
DSI_VCC /
24 VCOM -9275 -672 84 C24AN -5075 -672 144 DB16 -875 -672 204 3325 -672
MDDI_VCC
DSI_VCC /
25 VCOM -9205 -672 85 C24AN -5005 -672 145 DB15 -805 -672 205 3395 -672
MDDI_VCC
DSI_VCC /
26 VCOM -9135 -672 86 C24AN -4935 -672 146 DB14 -735 -672 206 3465 -672
MDDI_VCC
27 DUMMY3 -9065 -672 87 VPP -4865 -672 147 DB13 -665 -672 207 DSI_VSS / 3535 -672
MDDI_VSS
DSI_VSS /
28 DUMMYR1 -8995 -672 88 VPP -4795 -672 148 DB12 -595 -672 208 MDDI_VSS 3605 -672
DSI_VSS /
29 DUMMYR2 -8925 -672 89 VDDDN -4725 -672 149 DB11 -525 -672 209 3675 -672
MDDI_VSS
DSI_VSS /
30 DUMMY4 -8855 -672 90 VDDDN -4655 -672 150 DB10 -455 -672 210 3745 -672
MDDI_VSS
DSI_VSS /
31 VGL -8785 -672 91 VDDDN -4585 -672 151 DB9 -385 -672 211 MDDI_VSS 3815 -672
32 VGL -8715 -672 92 VDDDN -4515 -672 152 DB8 -315 -672 212 VSSAC 3885 -672
33 VGL -8645 -672 93 VDDDN -4445 -672 153 DB7 -245 -672 213 VSSAC 3955 -672
34 LVGL -8575 -672 94 VDD2 -4375 -672 154 DB6 -175 -672 214 VSSD 4025 -672
35 LVGL -8505 -672 95 VDD2 -4305 -672 155 DB5 -105 -672 215 VSSD 4095 -672
36 LVGL -8435 -672 96 VDD2 -4235 -672 156 DB4 -35 -672 216 VSSD 4165 -672
37 LVGL -8365 -672 97 VDD2 -4165 -672 157 DB3 35 -672 217 VSSD 4235 -672
38 LVGL -8295 -672 98 VDD2 -4095 -672 158 DB2 105 -672 218 VSSD 4305 -672
39 VCOM -8225 -672 99 VDD2 -4025 -672 159 DB1 175 -672 219 VSSD 4375 -672
40 VCOM -8155 -672 100 VREF -3955 -672 160 DB0 245 -672 220 VSSD 4445 -672
41 VCOM -8085 -672 101 VREF -3885 -672 161 IOGNDDUM 315 -672 221 VSSD 4515 -672
42 VCOM -8015 -672 102 VSSA -3815 -672 162 RDX_E 385 -672 222 VDDD 4585 -672
43 C41AP -7945 -672 103 VSSA -3745 -672 163 WRX_DCX 455 -672 223 VDDD 4655 -672
44 C41AP -7875 -672 104 VSSA -3675 -672 164 DCX_SCL 525 -672 224 VDDD 4725 -672
45 C41AP -7805 -672 105 VSSA -3605 -672 165 CSX 595 -672 225 VDDD 4795 -672
46 C41AN -7735 -672 106 VSSA -3535 -672 166 IOGNDDUM 665 -672 226 VDDD 4865 -672
47 C41AN -7665 -672 107 VSSA -3465 -672 167 SDI 735 -672 227 VDDD 4935 -672
48 C41AN -7595 -672 108 VSSD -3395 -672 168 SDO 805 -672 228 VDDD 5005 -672
49 VGH -7525 -672 109 VSSD -3325 -672 169 VSYNC 875 -672 229 VDDD 5075 -672
50 VGH -7455 -672 110 VSSD -3255 -672 170 HSYNC 945 -672 230 VDDD 5145 -672
51 VGH -7385 -672 111 VSSD -3185 -672 171 DE 1015 -672 231 VDDD 5215 -672
52 VGH -7315 -672 112 VSSD -3115 -672 172 PCLK 1085 -672 232 VDDD 5285 -672
53 VGH -7245 -672 113 VSSD -3045 -672 173 DSI_LDO_ENB 1155 -672 233 VDDD 5355 -672
54 VGH -7175 -672 114 VSSD -2975 -672 174 DUMMY5 1225 -672 234 VDDD 5425 -672
55 C21AP -7105 -672 115 VSSD -2905 -672 175 OSC 1295 -672 235 VSPR 5495 -672
56 C21AP -7035 -672 116 VDDD -2835 -672 176 PCCS0 1365 -672 236 VSPR 5565 -672
57 C21AP -6965 -672 117 VDDD -2765 -672 177 PCCS1 1435 -672 237 VSPC 5635 -672
DSI_VSS /
58 C21AP -6895 -672 118 VDDD -2695 -672 178 MDDI_VSS 1505 -672 238 VSP 5705 -672

59 -6825 -672 119 VDDD -2625 -672 179 DSI_D0N / 1575 -672 239 5775 -672
C21AN MDDI_D1N VSP
DSI_D0N /
60 C21AN -6755 -672 120 VDDD -2555 -672 180 MDDI_D1N 1645 -672 240 VSP 5845 -672

Himax Confidential -P.19-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
No. Name X Y No. Name X Y No. Name X Y No. Name X Y
241 VSP 5915 -672 301 CGOUT7_R 10115 -672 361 S47 10230 500 421 S107 9330 500
242 VSP 5985 -672 302 CGOUT7_R 10185 -672 362 S48 10215 613 422 S108 9315 613
243 VSP 6055 -672 303 CGOUT6_R 10255 -672 363 S49 10200 500 423 S109 9300 500
244 VSP 6125 -672 304 CGOUT6_R 10325 -672 364 S50 10185 613 424 S110 9285 613
245 VCSW1 6195 -672 305 CGOUT5_R 10395 -672 365 S51 10170 500 425 S111 9270 500
246 VCSW1 6265 -672 306 CGOUT5_R 10465 -672 366 S52 10155 613 426 S112 9255 613
247 VCSW1 6335 -672 307 CGOUT4_R 10535 -672 367 S53 10140 500 427 S113 9240 500
248 VCSW1 6405 -672 308 CGOUT3_R 10605 -672 368 S54 10125 613 428 S114 9225 613
249 VCSW2 6475 -672 309 CGOUT2_R 10675 -672 369 S55 10110 500 429 S115 9210 500
250 VCSW2 6545 -672 310 CGOUT1_R 10745 -672 370 S56 10095 613 430 S116 9195 613
251 VCSW2 6615 -672 311 DUMMY9 10815 -672 371 S57 10080 500 431 S117 9180 500
252 VCSW2 6685 -672 312 DUMMY10 10885 -672 372 S58 10065 613 432 S118 9165 613
253 VSNR 6755 -672 313 DUMMY15 10950 500 373 S59 10050 500 433 S119 9150 500
254 VSNR 6825 -672 314 DUMMY16 10935 613 374 S60 10035 613 434 S120 9135 613
255 VSNC 6895 -672 315 S1 10920 500 375 S61 10020 500 435 S121 9120 500
256 VSN 6965 -672 316 S2 10905 613 376 S62 10005 613 436 S122 9105 613
257 VSN 7035 -672 317 S3 10890 500 377 S63 9990 500 437 S123 9090 500
258 VSN 7105 -672 318 S4 10875 613 378 S64 9975 613 438 S124 9075 613
259 VSN 7175 -672 319 S5 10860 500 379 S65 9960 500 439 S125 9060 500
260 VSN 7245 -672 320 S6 10845 613 380 S66 9945 613 440 S126 9045 613
261 VSN 7315 -672 321 S7 10830 500 381 S67 9930 500 441 S127 9030 500
262 VDD3 7385 -672 322 S8 10815 613 382 S68 9915 613 442 S128 9015 613
263 VDD3 7455 -672 323 S9 10800 500 383 S69 9900 500 443 S129 9000 500
264 VDD3 7525 -672 324 S10 10785 613 384 S70 9885 613 444 S130 8985 613
265 VDD3 7595 -672 325 S11 10770 500 385 S71 9870 500 445 S131 8970 500
266 VDD3 7665 -672 326 S12 10755 613 386 S72 9855 613 446 S132 8955 613
267 VDD3 7735 -672 327 S13 10740 500 387 S73 9840 500 447 S133 8940 500
268 VGH 7805 -672 328 S14 10725 613 388 S74 9825 613 448 S134 8925 613
269 VGH 7875 -672 329 S15 10710 500 389 S75 9810 500 449 S135 8910 500
270 VGH 7945 -672 330 S16 10695 613 390 S76 9795 613 450 S136 8895 613
271 VGH 8015 -672 331 S17 10680 500 391 S77 9780 500 451 S137 8880 500
272 VCOM 8085 -672 332 S18 10665 613 392 S78 9765 613 452 S138 8865 613
273 VCOM 8155 -672 333 S19 10650 500 393 S79 9750 500 453 S139 8850 500
274 VCOM 8225 -672 334 S20 10635 613 394 S80 9735 613 454 S140 8835 613
275 VCOM 8295 -672 335 S21 10620 500 395 S81 9720 500 455 S141 8820 500
276 LVGL 8365 -672 336 S22 10605 613 396 S82 9705 613 456 S142 8805 613
277 LVGL 8435 -672 337 S23 10590 500 397 S83 9690 500 457 S143 8790 500
278 LVGL 8505 -672 338 S24 10575 613 398 S84 9675 613 458 S144 8775 613
279 LVGL 8575 -672 339 S25 10560 500 399 S85 9660 500 459 S145 8760 500
280 VTESTOUTP 8645 -672 340 S26 10545 613 400 S86 9645 613 460 S146 8745 613
281 DUMMY6 8715 -672 341 S27 10530 500 401 S87 9630 500 461 S147 8730 500
282 VCOMR 8785 -672 342 S28 10515 613 402 S88 9615 613 462 S148 8715 613
283 VTESTOUTN 8855 -672 343 S29 10500 500 403 S89 9600 500 463 S149 8700 500
284 VCOM 8925 -672 344 S30 10485 613 404 S90 9585 613 464 S150 8685 613
285 VCOM 8995 -672 345 S31 10470 500 405 S91 9570 500 465 S151 8670 500
286 VCOM 9065 -672 346 S32 10455 613 406 S92 9555 613 466 S152 8655 613
287 DUMMY7 9135 -672 347 S33 10440 500 407 S93 9540 500 467 S153 8640 500
288 DUMMY8 9205 -672 348 S34 10425 613 408 S94 9525 613 468 S154 8625 613
289 LVGL 9275 -672 349 S35 10410 500 409 S95 9510 500 469 S155 8610 500
290 LVGL 9345 -672 350 S36 10395 613 410 S96 9495 613 470 S156 8595 613
291 LVGL 9415 -672 351 S37 10380 500 411 S97 9480 500 471 S157 8580 500
292 VBIAS 9485 -672 352 S38 10365 613 412 S98 9465 613 472 S158 8565 613
293 VGL 9555 -672 353 S39 10350 500 413 S99 9450 500 473 S159 8550 500
294 VGL 9625 -672 354 S40 10335 613 414 S100 9435 613 474 S160 8535 613
295 VGL 9695 -672 355 S41 10320 500 415 S101 9420 500 475 S161 8520 500
296 VGL 9765 -672 356 S42 10305 613 416 S102 9405 613 476 S162 8505 613
297 CGOUT10_R 9835 -672 357 S43 10290 500 417 S103 9390 500 477 S163 8490 500
298 CGOUT9_R 9905 -672 358 S44 10275 613 418 S104 9375 613 478 S164 8475 613
299 CGOUT8_R 9975 -672 359 S45 10260 500 419 S105 9360 500 479 S165 8460 500
300 CGOUT8_R 10045 -672 360 S46 10245 613 420 S106 9345 613 480 S166 8445 613

Himax Confidential -P.20-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
No. Name X Y No. Name X Y No. Name X Y No. Name X Y
481 S167 8430 500 541 S227 7530 500 601 S287 6630 500 661 S347 5730 500
482 S168 8415 613 542 S228 7515 613 602 S288 6615 613 662 S348 5715 613
483 S169 8400 500 543 S229 7500 500 603 S289 6600 500 663 S349 5700 500
484 S170 8385 613 544 S230 7485 613 604 S290 6585 613 664 S350 5685 613
485 S171 8370 500 545 S231 7470 500 605 S291 6570 500 665 S351 5670 500
486 S172 8355 613 546 S232 7455 613 606 S292 6555 613 666 S352 5655 613
487 S173 8340 500 547 S233 7440 500 607 S293 6540 500 667 S353 5640 500
488 S174 8325 613 548 S234 7425 613 608 S294 6525 613 668 S354 5625 613
489 S175 8310 500 549 S235 7410 500 609 S295 6510 500 669 S355 5610 500
490 S176 8295 613 550 S236 7395 613 610 S296 6495 613 670 S356 5595 613
491 S177 8280 500 551 S237 7380 500 611 S297 6480 500 671 S357 5580 500
492 S178 8265 613 552 S238 7365 613 612 S298 6465 613 672 S358 5565 613
493 S179 8250 500 553 S239 7350 500 613 S299 6450 500 673 S359 5550 500
494 S180 8235 613 554 S240 7335 613 614 S300 6435 613 674 S360 5535 613
495 S181 8220 500 555 S241 7320 500 615 S301 6420 500 675 S361 5520 500
496 S182 8205 613 556 S242 7305 613 616 S302 6405 613 676 S362 5505 613
497 S183 8190 500 557 S243 7290 500 617 S303 6390 500 677 S363 5490 500
498 S184 8175 613 558 S244 7275 613 618 S304 6375 613 678 S364 5475 613
499 S185 8160 500 559 S245 7260 500 619 S305 6360 500 679 S365 5460 500
500 S186 8145 613 560 S246 7245 613 620 S306 6345 613 680 S366 5445 613
501 S187 8130 500 561 S247 7230 500 621 S307 6330 500 681 S367 5430 500
502 S188 8115 613 562 S248 7215 613 622 S308 6315 613 682 S368 5415 613
503 S189 8100 500 563 S249 7200 500 623 S309 6300 500 683 S369 5400 500
504 S190 8085 613 564 S250 7185 613 624 S310 6285 613 684 S370 5385 613
505 S191 8070 500 565 S251 7170 500 625 S311 6270 500 685 S371 5370 500
506 S192 8055 613 566 S252 7155 613 626 S312 6255 613 686 S372 5355 613
507 S193 8040 500 567 S253 7140 500 627 S313 6240 500 687 S373 5340 500
508 S194 8025 613 568 S254 7125 613 628 S314 6225 613 688 S374 5325 613
509 S195 8010 500 569 S255 7110 500 629 S315 6210 500 689 S375 5310 500
510 S196 7995 613 570 S256 7095 613 630 S316 6195 613 690 S376 5295 613
511 S197 7980 500 571 S257 7080 500 631 S317 6180 500 691 S377 5280 500
512 S198 7965 613 572 S258 7065 613 632 S318 6165 613 692 S378 5265 613
513 S199 7950 500 573 S259 7050 500 633 S319 6150 500 693 S379 5250 500
514 S200 7935 613 574 S260 7035 613 634 S320 6135 613 694 S380 5235 613
515 S201 7920 500 575 S261 7020 500 635 S321 6120 500 695 S381 5220 500
516 S202 7905 613 576 S262 7005 613 636 S322 6105 613 696 S382 5205 613
517 S203 7890 500 577 S263 6990 500 637 S323 6090 500 697 S383 5190 500
518 S204 7875 613 578 S264 6975 613 638 S324 6075 613 698 S384 5175 613
519 S205 7860 500 579 S265 6960 500 639 S325 6060 500 699 S385 5160 500
520 S206 7845 613 580 S266 6945 613 640 S326 6045 613 700 S386 5145 613
521 S207 7830 500 581 S267 6930 500 641 S327 6030 500 701 S387 5130 500
522 S208 7815 613 582 S268 6915 613 642 S328 6015 613 702 S388 5115 613
523 S209 7800 500 583 S269 6900 500 643 S329 6000 500 703 S389 5100 500
524 S210 7785 613 584 S270 6885 613 644 S330 5985 613 704 S390 5085 613
525 S211 7770 500 585 S271 6870 500 645 S331 5970 500 705 S391 5070 500
526 S212 7755 613 586 S272 6855 613 646 S332 5955 613 706 S392 5055 613
527 S213 7740 500 587 S273 6840 500 647 S333 5940 500 707 S393 5040 500
528 S214 7725 613 588 S274 6825 613 648 S334 5925 613 708 S394 5025 613
529 S215 7710 500 589 S275 6810 500 649 S335 5910 500 709 S395 5010 500
530 S216 7695 613 590 S276 6795 613 650 S336 5895 613 710 S396 4995 613
531 S217 7680 500 591 S277 6780 500 651 S337 5880 500 711 S397 4980 500
532 S218 7665 613 592 S278 6765 613 652 S338 5865 613 712 S398 4965 613
533 S219 7650 500 593 S279 6750 500 653 S339 5850 500 713 S399 4950 500
534 S220 7635 613 594 S280 6735 613 654 S340 5835 613 714 S400 4935 613
535 S221 7620 500 595 S281 6720 500 655 S341 5820 500 715 S401 4920 500
536 S222 7605 613 596 S282 6705 613 656 S342 5805 613 716 S402 4905 613
537 S223 7590 500 597 S283 6690 500 657 S343 5790 500 717 S403 4890 500
538 S224 7575 613 598 S284 6675 613 658 S344 5775 613 718 S404 4875 613
539 S225 7560 500 599 S285 6660 500 659 S345 5760 500 719 S405 4860 500
540 S226 7545 613 600 S286 6645 613 660 S346 5745 613 720 S406 4845 613

Himax Confidential -P.21-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
No. Name X Y No. Name X Y No. Name X Y No. Name X Y
721 S407 4830 500 781 S467 3930 500 841 S527 3030 500 901 S587 2130 500
722 S408 4815 613 782 S468 3915 613 842 S528 3015 613 902 S588 2115 613
723 S409 4800 500 783 S469 3900 500 843 S529 3000 500 903 S589 2100 500
724 S410 4785 613 784 S470 3885 613 844 S530 2985 613 904 S590 2085 613
725 S411 4770 500 785 S471 3870 500 845 S531 2970 500 905 S591 2070 500
726 S412 4755 613 786 S472 3855 613 846 S532 2955 613 906 S592 2055 613
727 S413 4740 500 787 S473 3840 500 847 S533 2940 500 907 S593 2040 500
728 S414 4725 613 788 S474 3825 613 848 S534 2925 613 908 S594 2025 613
729 S415 4710 500 789 S475 3810 500 849 S535 2910 500 909 S595 2010 500
730 S416 4695 613 790 S476 3795 613 850 S536 2895 613 910 S596 1995 613
731 S417 4680 500 791 S477 3780 500 851 S537 2880 500 911 S597 1980 500
732 S418 4665 613 792 S478 3765 613 852 S538 2865 613 912 S598 1965 613
733 S419 4650 500 793 S479 3750 500 853 S539 2850 500 913 S599 1950 500
734 S420 4635 613 794 S480 3735 613 854 S540 2835 613 914 S600 1935 613
735 S421 4620 500 795 S481 3720 500 855 S541 2820 500 915 S601 1920 500
736 S422 4605 613 796 S482 3705 613 856 S542 2805 613 916 S602 1905 613
737 S423 4590 500 797 S483 3690 500 857 S543 2790 500 917 S603 1890 500
738 S424 4575 613 798 S484 3675 613 858 S544 2775 613 918 S604 1875 613
739 S425 4560 500 799 S485 3660 500 859 S545 2760 500 919 S605 1860 500
740 S426 4545 613 800 S486 3645 613 860 S546 2745 613 920 S606 1845 613
741 S427 4530 500 801 S487 3630 500 861 S547 2730 500 921 S607 1830 500
742 S428 4515 613 802 S488 3615 613 862 S548 2715 613 922 S608 1815 613
743 S429 4500 500 803 S489 3600 500 863 S549 2700 500 923 S609 1800 500
744 S430 4485 613 804 S490 3585 613 864 S550 2685 613 924 S610 1785 613
745 S431 4470 500 805 S491 3570 500 865 S551 2670 500 925 S611 1770 500
746 S432 4455 613 806 S492 3555 613 866 S552 2655 613 926 S612 1755 613
747 S433 4440 500 807 S493 3540 500 867 S553 2640 500 927 S613 1740 500
748 S434 4425 613 808 S494 3525 613 868 S554 2625 613 928 S614 1725 613
749 S435 4410 500 809 S495 3510 500 869 S555 2610 500 929 S615 1710 500
750 S436 4395 613 810 S496 3495 613 870 S556 2595 613 930 S616 1695 613
751 S437 4380 500 811 S497 3480 500 871 S557 2580 500 931 S617 1680 500
752 S438 4365 613 812 S498 3465 613 872 S558 2565 613 932 S618 1665 613
753 S439 4350 500 813 S499 3450 500 873 S559 2550 500 933 S619 1650 500
754 S440 4335 613 814 S500 3435 613 874 S560 2535 613 934 S620 1635 613
755 S441 4320 500 815 S501 3420 500 875 S561 2520 500 935 S621 1620 500
756 S442 4305 613 816 S502 3405 613 876 S562 2505 613 936 S622 1605 613
757 S443 4290 500 817 S503 3390 500 877 S563 2490 500 937 S623 1590 500
758 S444 4275 613 818 S504 3375 613 878 S564 2475 613 938 S624 1575 613
759 S445 4260 500 819 S505 3360 500 879 S565 2460 500 939 S625 1560 500
760 S446 4245 613 820 S506 3345 613 880 S566 2445 613 940 S626 1545 613
761 S447 4230 500 821 S507 3330 500 881 S567 2430 500 941 S627 1530 500
762 S448 4215 613 822 S508 3315 613 882 S568 2415 613 942 S628 1515 613
763 S449 4200 500 823 S509 3300 500 883 S569 2400 500 943 S629 1500 500
764 S450 4185 613 824 S510 3285 613 884 S570 2385 613 944 S630 1485 613
765 S451 4170 500 825 S511 3270 500 885 S571 2370 500 945 S631 1470 500
766 S452 4155 613 826 S512 3255 613 886 S572 2355 613 946 S632 1455 613
767 S453 4140 500 827 S513 3240 500 887 S573 2340 500 947 S633 1440 500
768 S454 4125 613 828 S514 3225 613 888 S574 2325 613 948 S634 1425 613
769 S455 4110 500 829 S515 3210 500 889 S575 2310 500 949 S635 1410 500
770 S456 4095 613 830 S516 3195 613 890 S576 2295 613 950 S636 1395 613
771 S457 4080 500 831 S517 3180 500 891 S577 2280 500 951 S637 1380 500
772 S458 4065 613 832 S518 3165 613 892 S578 2265 613 952 S638 1365 613
773 S459 4050 500 833 S519 3150 500 893 S579 2250 500 953 S639 1350 500
774 S460 4035 613 834 S520 3135 613 894 S580 2235 613 954 S640 1335 613
775 S461 4020 500 835 S521 3120 500 895 S581 2220 500 955 S641 1320 500
776 S462 4005 613 836 S522 3105 613 896 S582 2205 613 956 S642 1305 613
777 S463 3990 500 837 S523 3090 500 897 S583 2190 500 957 S643 1290 500
778 S464 3975 613 838 S524 3075 613 898 S584 2175 613 958 S644 1275 613
779 S465 3960 500 839 S525 3060 500 899 S585 2160 500 959 S645 1260 500
780 S466 3945 613 840 S526 3045 613 900 S586 2145 613 960 S646 1245 613

Himax Confidential -P.22-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
No. Name X Y No. Name X Y No. Name X Y No. Name X Y
961 S647 1230 500 1021 S707 330 500 1081 S763 -765 613 1141 S823 -1665 613
962 S648 1215 613 1022 S708 315 613 1082 S764 -780 500 1142 S824 -1680 500
963 S649 1200 500 1023 S709 300 500 1083 S765 -795 613 1143 S825 -1695 613
964 S650 1185 613 1024 S710 285 613 1084 S766 -810 500 1144 S826 -1710 500
965 S651 1170 500 1025 S711 270 500 1085 S767 -825 613 1145 S827 -1725 613
966 S652 1155 613 1026 S712 255 613 1086 S768 -840 500 1146 S828 -1740 500
967 S653 1140 500 1027 S713 240 500 1087 S769 -855 613 1147 S829 -1755 613
968 S654 1125 613 1028 S714 225 613 1088 S770 -870 500 1148 S830 -1770 500
969 S655 1110 500 1029 S715 210 500 1089 S771 -885 613 1149 S831 -1785 613
970 S656 1095 613 1030 S716 195 613 1090 S772 -900 500 1150 S832 -1800 500
971 S657 1080 500 1031 S717 180 500 1091 S773 -915 613 1151 S833 -1815 613
972 S658 1065 613 1032 S718 165 613 1092 S774 -930 500 1152 S834 -1830 500
973 S659 1050 500 1033 S719 150 500 1093 S775 -945 613 1153 S835 -1845 613
974 S660 1035 613 1034 S720 135 613 1094 S776 -960 500 1154 S836 -1860 500
975 S661 1020 500 1035 DUMMY11 90 613 1095 S777 -975 613 1155 S837 -1875 613
976 S662 1005 613 1036 DUMMY12 30 613 1096 S778 -990 500 1156 S838 -1890 500
977 S663 990 500 1037 DUMMY13 -30 613 1097 S779 -1005 613 1157 S839 -1905 613
978 S664 975 613 1038 DUMMY14 -90 613 1098 S780 -1020 500 1158 S840 -1920 500
979 S665 960 500 1039 S721 -135 613 1099 S781 -1035 613 1159 S841 -1935 613
980 S666 945 613 1040 S722 -150 500 1100 S782 -1050 500 1160 S842 -1950 500
981 S667 930 500 1041 S723 -165 613 1101 S783 -1065 613 1161 S843 -1965 613
982 S668 915 613 1042 S724 -180 500 1102 S784 -1080 500 1162 S844 -1980 500
983 S669 900 500 1043 S725 -195 613 1103 S785 -1095 613 1163 S845 -1995 613
984 S670 885 613 1044 S726 -210 500 1104 S786 -1110 500 1164 S846 -2010 500
985 S671 870 500 1045 S727 -225 613 1105 S787 -1125 613 1165 S847 -2025 613
986 S672 855 613 1046 S728 -240 500 1106 S788 -1140 500 1166 S848 -2040 500
987 S673 840 500 1047 S729 -255 613 1107 S789 -1155 613 1167 S849 -2055 613
988 S674 825 613 1048 S730 -270 500 1108 S790 -1170 500 1168 S850 -2070 500
989 S675 810 500 1049 S731 -285 613 1109 S791 -1185 613 1169 S851 -2085 613
990 S676 795 613 1050 S732 -300 500 1110 S792 -1200 500 1170 S852 -2100 500
991 S677 780 500 1051 S733 -315 613 1111 S793 -1215 613 1171 S853 -2115 613
992 S678 765 613 1052 S734 -330 500 1112 S794 -1230 500 1172 S854 -2130 500
993 S679 750 500 1053 S735 -345 613 1113 S795 -1245 613 1173 S855 -2145 613
994 S680 735 613 1054 S736 -360 500 1114 S796 -1260 500 1174 S856 -2160 500
995 S681 720 500 1055 S737 -375 613 1115 S797 -1275 613 1175 S857 -2175 613
996 S682 705 613 1056 S738 -390 500 1116 S798 -1290 500 1176 S858 -2190 500
997 S683 690 500 1057 S739 -405 613 1117 S799 -1305 613 1177 S859 -2205 613
998 S684 675 613 1058 S740 -420 500 1118 S800 -1320 500 1178 S860 -2220 500
999 S685 660 500 1059 S741 -435 613 1119 S801 -1335 613 1179 S861 -2235 613
1000 S686 645 613 1060 S742 -450 500 1120 S802 -1350 500 1180 S862 -2250 500
1001 S687 630 500 1061 S743 -465 613 1121 S803 -1365 613 1181 S863 -2265 613
1002 S688 615 613 1062 S744 -480 500 1122 S804 -1380 500 1182 S864 -2280 500
1003 S689 600 500 1063 S745 -495 613 1123 S805 -1395 613 1183 S865 -2295 613
1004 S690 585 613 1064 S746 -510 500 1124 S806 -1410 500 1184 S866 -2310 500
1005 S691 570 500 1065 S747 -525 613 1125 S807 -1425 613 1185 S867 -2325 613
1006 S692 555 613 1066 S748 -540 500 1126 S808 -1440 500 1186 S868 -2340 500
1007 S693 540 500 1067 S749 -555 613 1127 S809 -1455 613 1187 S869 -2355 613
1008 S694 525 613 1068 S750 -570 500 1128 S810 -1470 500 1188 S870 -2370 500
1009 S695 510 500 1069 S751 -585 613 1129 S811 -1485 613 1189 S871 -2385 613
1010 S696 495 613 1070 S752 -600 500 1130 S812 -1500 500 1190 S872 -2400 500
1011 S697 480 500 1071 S753 -615 613 1131 S813 -1515 613 1191 S873 -2415 613
1012 S698 465 613 1072 S754 -630 500 1132 S814 -1530 500 1192 S874 -2430 500
1013 S699 450 500 1073 S755 -645 613 1133 S815 -1545 613 1193 S875 -2445 613
1014 S700 435 613 1074 S756 -660 500 1134 S816 -1560 500 1194 S876 -2460 500
1015 S701 420 500 1075 S757 -675 613 1135 S817 -1575 613 1195 S877 -2475 613
1016 S702 405 613 1076 S758 -690 500 1136 S818 -1590 500 1196 S878 -2490 500
1017 S703 390 500 1077 S759 -705 613 1137 S819 -1605 613 1197 S879 -2505 613
1018 S704 375 613 1078 S760 -720 500 1138 S820 -1620 500 1198 S880 -2520 500
1019 S705 360 500 1079 S761 -735 613 1139 S821 -1635 613 1199 S881 -2535 613
1020 S706 345 613 1080 S762 -750 500 1140 S822 -1650 500 1200 S882 -2550 500

Himax Confidential -P.23-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
No. Name X Y No. Name X Y No. Name X Y No. Name X Y
1201 S883 -2565 613 1261 S943 -3465 613 1321 S1003 -4365 613 1381 S1063 -5265 613
1202 S884 -2580 500 1262 S944 -3480 500 1322 S1004 -4380 500 1382 S1064 -5280 500
1203 S885 -2595 613 1263 S945 -3495 613 1323 S1005 -4395 613 1383 S1065 -5295 613
1204 S886 -2610 500 1264 S946 -3510 500 1324 S1006 -4410 500 1384 S1066 -5310 500
1205 S887 -2625 613 1265 S947 -3525 613 1325 S1007 -4425 613 1385 S1067 -5325 613
1206 S888 -2640 500 1266 S948 -3540 500 1326 S1008 -4440 500 1386 S1068 -5340 500
1207 S889 -2655 613 1267 S949 -3555 613 1327 S1009 -4455 613 1387 S1069 -5355 613
1208 S890 -2670 500 1268 S950 -3570 500 1328 S1010 -4470 500 1388 S1070 -5370 500
1209 S891 -2685 613 1269 S951 -3585 613 1329 S1011 -4485 613 1389 S1071 -5385 613
1210 S892 -2700 500 1270 S952 -3600 500 1330 S1012 -4500 500 1390 S1072 -5400 500
1211 S893 -2715 613 1271 S953 -3615 613 1331 S1013 -4515 613 1391 S1073 -5415 613
1212 S894 -2730 500 1272 S954 -3630 500 1332 S1014 -4530 500 1392 S1074 -5430 500
1213 S895 -2745 613 1273 S955 -3645 613 1333 S1015 -4545 613 1393 S1075 -5445 613
1214 S896 -2760 500 1274 S956 -3660 500 1334 S1016 -4560 500 1394 S1076 -5460 500
1215 S897 -2775 613 1275 S957 -3675 613 1335 S1017 -4575 613 1395 S1077 -5475 613
1216 S898 -2790 500 1276 S958 -3690 500 1336 S1018 -4590 500 1396 S1078 -5490 500
1217 S899 -2805 613 1277 S959 -3705 613 1337 S1019 -4605 613 1397 S1079 -5505 613
1218 S900 -2820 500 1278 S960 -3720 500 1338 S1020 -4620 500 1398 S1080 -5520 500
1219 S901 -2835 613 1279 S961 -3735 613 1339 S1021 -4635 613 1399 S1081 -5535 613
1220 S902 -2850 500 1280 S962 -3750 500 1340 S1022 -4650 500 1400 S1082 -5550 500
1221 S903 -2865 613 1281 S963 -3765 613 1341 S1023 -4665 613 1401 S1083 -5565 613
1222 S904 -2880 500 1282 S964 -3780 500 1342 S1024 -4680 500 1402 S1084 -5580 500
1223 S905 -2895 613 1283 S965 -3795 613 1343 S1025 -4695 613 1403 S1085 -5595 613
1224 S906 -2910 500 1284 S966 -3810 500 1344 S1026 -4710 500 1404 S1086 -5610 500
1225 S907 -2925 613 1285 S967 -3825 613 1345 S1027 -4725 613 1405 S1087 -5625 613
1226 S908 -2940 500 1286 S968 -3840 500 1346 S1028 -4740 500 1406 S1088 -5640 500
1227 S909 -2955 613 1287 S969 -3855 613 1347 S1029 -4755 613 1407 S1089 -5655 613
1228 S910 -2970 500 1288 S970 -3870 500 1348 S1030 -4770 500 1408 S1090 -5670 500
1229 S911 -2985 613 1289 S971 -3885 613 1349 S1031 -4785 613 1409 S1091 -5685 613
1230 S912 -3000 500 1290 S972 -3900 500 1350 S1032 -4800 500 1410 S1092 -5700 500
1231 S913 -3015 613 1291 S973 -3915 613 1351 S1033 -4815 613 1411 S1093 -5715 613
1232 S914 -3030 500 1292 S974 -3930 500 1352 S1034 -4830 500 1412 S1094 -5730 500
1233 S915 -3045 613 1293 S975 -3945 613 1353 S1035 -4845 613 1413 S1095 -5745 613
1234 S916 -3060 500 1294 S976 -3960 500 1354 S1036 -4860 500 1414 S1096 -5760 500
1235 S917 -3075 613 1295 S977 -3975 613 1355 S1037 -4875 613 1415 S1097 -5775 613
1236 S918 -3090 500 1296 S978 -3990 500 1356 S1038 -4890 500 1416 S1098 -5790 500
1237 S919 -3105 613 1297 S979 -4005 613 1357 S1039 -4905 613 1417 S1099 -5805 613
1238 S920 -3120 500 1298 S980 -4020 500 1358 S1040 -4920 500 1418 S1100 -5820 500
1239 S921 -3135 613 1299 S981 -4035 613 1359 S1041 -4935 613 1419 S1101 -5835 613
1240 S922 -3150 500 1300 S982 -4050 500 1360 S1042 -4950 500 1420 S1102 -5850 500
1241 S923 -3165 613 1301 S983 -4065 613 1361 S1043 -4965 613 1421 S1103 -5865 613
1242 S924 -3180 500 1302 S984 -4080 500 1362 S1044 -4980 500 1422 S1104 -5880 500
1243 S925 -3195 613 1303 S985 -4095 613 1363 S1045 -4995 613 1423 S1105 -5895 613
1244 S926 -3210 500 1304 S986 -4110 500 1364 S1046 -5010 500 1424 S1106 -5910 500
1245 S927 -3225 613 1305 S987 -4125 613 1365 S1047 -5025 613 1425 S1107 -5925 613
1246 S928 -3240 500 1306 S988 -4140 500 1366 S1048 -5040 500 1426 S1108 -5940 500
1247 S929 -3255 613 1307 S989 -4155 613 1367 S1049 -5055 613 1427 S1109 -5955 613
1248 S930 -3270 500 1308 S990 -4170 500 1368 S1050 -5070 500 1428 S1110 -5970 500
1249 S931 -3285 613 1309 S991 -4185 613 1369 S1051 -5085 613 1429 S1111 -5985 613
1250 S932 -3300 500 1310 S992 -4200 500 1370 S1052 -5100 500 1430 S1112 -6000 500
1251 S933 -3315 613 1311 S993 -4215 613 1371 S1053 -5115 613 1431 S1113 -6015 613
1252 S934 -3330 500 1312 S994 -4230 500 1372 S1054 -5130 500 1432 S1114 -6030 500
1253 S935 -3345 613 1313 S995 -4245 613 1373 S1055 -5145 613 1433 S1115 -6045 613
1254 S936 -3360 500 1314 S996 -4260 500 1374 S1056 -5160 500 1434 S1116 -6060 500
1255 S937 -3375 613 1315 S997 -4275 613 1375 S1057 -5175 613 1435 S1117 -6075 613
1256 S938 -3390 500 1316 S998 -4290 500 1376 S1058 -5190 500 1436 S1118 -6090 500
1257 S939 -3405 613 1317 S999 -4305 613 1377 S1059 -5205 613 1437 S1119 -6105 613
1258 S940 -3420 500 1318 S1000 -4320 500 1378 S1060 -5220 500 1438 S1120 -6120 500
1259 S941 -3435 613 1319 S1001 -4335 613 1379 S1061 -5235 613 1439 S1121 -6135 613
1260 S942 -3450 500 1320 S1002 -4350 500 1380 S1062 -5250 500 1440 S1122 -6150 500

Himax Confidential -P.24-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
No. Name X Y No. Name X Y No. Name X Y No. Name X Y
1441 S1123 -6165 613 1501 S1183 -7065 613 1561 S1243 -7965 613 1621 S1303 -8865 613
1442 S1124 -6180 500 1502 S1184 -7080 500 1562 S1244 -7980 500 1622 S1304 -8880 500
1443 S1125 -6195 613 1503 S1185 -7095 613 1563 S1245 -7995 613 1623 S1305 -8895 613
1444 S1126 -6210 500 1504 S1186 -7110 500 1564 S1246 -8010 500 1624 S1306 -8910 500
1445 S1127 -6225 613 1505 S1187 -7125 613 1565 S1247 -8025 613 1625 S1307 -8925 613
1446 S1128 -6240 500 1506 S1188 -7140 500 1566 S1248 -8040 500 1626 S1308 -8940 500
1447 S1129 -6255 613 1507 S1189 -7155 613 1567 S1249 -8055 613 1627 S1309 -8955 613
1448 S1130 -6270 500 1508 S1190 -7170 500 1568 S1250 -8070 500 1628 S1310 -8970 500
1449 S1131 -6285 613 1509 S1191 -7185 613 1569 S1251 -8085 613 1629 S1311 -8985 613
1450 S1132 -6300 500 1510 S1192 -7200 500 1570 S1252 -8100 500 1630 S1312 -9000 500
1451 S1133 -6315 613 1511 S1193 -7215 613 1571 S1253 -8115 613 1631 S1313 -9015 613
1452 S1134 -6330 500 1512 S1194 -7230 500 1572 S1254 -8130 500 1632 S1314 -9030 500
1453 S1135 -6345 613 1513 S1195 -7245 613 1573 S1255 -8145 613 1633 S1315 -9045 613
1454 S1136 -6360 500 1514 S1196 -7260 500 1574 S1256 -8160 500 1634 S1316 -9060 500
1455 S1137 -6375 613 1515 S1197 -7275 613 1575 S1257 -8175 613 1635 S1317 -9075 613
1456 S1138 -6390 500 1516 S1198 -7290 500 1576 S1258 -8190 500 1636 S1318 -9090 500
1457 S1139 -6405 613 1517 S1199 -7305 613 1577 S1259 -8205 613 1637 S1319 -9105 613
1458 S1140 -6420 500 1518 S1200 -7320 500 1578 S1260 -8220 500 1638 S1320 -9120 500
1459 S1141 -6435 613 1519 S1201 -7335 613 1579 S1261 -8235 613 1639 S1321 -9135 613
1460 S1142 -6450 500 1520 S1202 -7350 500 1580 S1262 -8250 500 1640 S1322 -9150 500
1461 S1143 -6465 613 1521 S1203 -7365 613 1581 S1263 -8265 613 1641 S1323 -9165 613
1462 S1144 -6480 500 1522 S1204 -7380 500 1582 S1264 -8280 500 1642 S1324 -9180 500
1463 S1145 -6495 613 1523 S1205 -7395 613 1583 S1265 -8295 613 1643 S1325 -9195 613
1464 S1146 -6510 500 1524 S1206 -7410 500 1584 S1266 -8310 500 1644 S1326 -9210 500
1465 S1147 -6525 613 1525 S1207 -7425 613 1585 S1267 -8325 613 1645 S1327 -9225 613
1466 S1148 -6540 500 1526 S1208 -7440 500 1586 S1268 -8340 500 1646 S1328 -9240 500
1467 S1149 -6555 613 1527 S1209 -7455 613 1587 S1269 -8355 613 1647 S1329 -9255 613
1468 S1150 -6570 500 1528 S1210 -7470 500 1588 S1270 -8370 500 1648 S1330 -9270 500
1469 S1151 -6585 613 1529 S1211 -7485 613 1589 S1271 -8385 613 1649 S1331 -9285 613
1470 S1152 -6600 500 1530 S1212 -7500 500 1590 S1272 -8400 500 1650 S1332 -9300 500
1471 S1153 -6615 613 1531 S1213 -7515 613 1591 S1273 -8415 613 1651 S1333 -9315 613
1472 S1154 -6630 500 1532 S1214 -7530 500 1592 S1274 -8430 500 1652 S1334 -9330 500
1473 S1155 -6645 613 1533 S1215 -7545 613 1593 S1275 -8445 613 1653 S1335 -9345 613
1474 S1156 -6660 500 1534 S1216 -7560 500 1594 S1276 -8460 500 1654 S1336 -9360 500
1475 S1157 -6675 613 1535 S1217 -7575 613 1595 S1277 -8475 613 1655 S1337 -9375 613
1476 S1158 -6690 500 1536 S1218 -7590 500 1596 S1278 -8490 500 1656 S1338 -9390 500
1477 S1159 -6705 613 1537 S1219 -7605 613 1597 S1279 -8505 613 1657 S1339 -9405 613
1478 S1160 -6720 500 1538 S1220 -7620 500 1598 S1280 -8520 500 1658 S1340 -9420 500
1479 S1161 -6735 613 1539 S1221 -7635 613 1599 S1281 -8535 613 1659 S1341 -9435 613
1480 S1162 -6750 500 1540 S1222 -7650 500 1600 S1282 -8550 500 1660 S1342 -9450 500
1481 S1163 -6765 613 1541 S1223 -7665 613 1601 S1283 -8565 613 1661 S1343 -9465 613
1482 S1164 -6780 500 1542 S1224 -7680 500 1602 S1284 -8580 500 1662 S1344 -9480 500
1483 S1165 -6795 613 1543 S1225 -7695 613 1603 S1285 -8595 613 1663 S1345 -9495 613
1484 S1166 -6810 500 1544 S1226 -7710 500 1604 S1286 -8610 500 1664 S1346 -9510 500
1485 S1167 -6825 613 1545 S1227 -7725 613 1605 S1287 -8625 613 1665 S1347 -9525 613
1486 S1168 -6840 500 1546 S1228 -7740 500 1606 S1288 -8640 500 1666 S1348 -9540 500
1487 S1169 -6855 613 1547 S1229 -7755 613 1607 S1289 -8655 613 1667 S1349 -9555 613
1488 S1170 -6870 500 1548 S1230 -7770 500 1608 S1290 -8670 500 1668 S1350 -9570 500
1489 S1171 -6885 613 1549 S1231 -7785 613 1609 S1291 -8685 613 1669 S1351 -9585 613
1490 S1172 -6900 500 1550 S1232 -7800 500 1610 S1292 -8700 500 1670 S1352 -9600 500
1491 S1173 -6915 613 1551 S1233 -7815 613 1611 S1293 -8715 613 1671 S1353 -9615 613
1492 S1174 -6930 500 1552 S1234 -7830 500 1612 S1294 -8730 500 1672 S1354 -9630 500
1493 S1175 -6945 613 1553 S1235 -7845 613 1613 S1295 -8745 613 1673 S1355 -9645 613
1494 S1176 -6960 500 1554 S1236 -7860 500 1614 S1296 -8760 500 1674 S1356 -9660 500
1495 S1177 -6975 613 1555 S1237 -7875 613 1615 S1297 -8775 613 1675 S1357 -9675 613
1496 S1178 -6990 500 1556 S1238 -7890 500 1616 S1298 -8790 500 1676 S1358 -9690 500
1497 S1179 -7005 613 1557 S1239 -7905 613 1617 S1299 -8805 613 1677 S1359 -9705 613
1498 S1180 -7020 500 1558 S1240 -7920 500 1618 S1300 -8820 500 1678 S1360 -9720 500
1499 S1181 -7035 613 1559 S1241 -7935 613 1619 S1301 -8835 613 1679 S1361 -9735 613
1500 S1182 -7050 500 1560 S1242 -7950 500 1620 S1302 -8850 500 1680 S1362 -9750 500

Himax Confidential -P.25-

S1441 (for
1699 S1381 -10035 613 1759 Zig-Zag) -10935 613

1700 S1382 -10050 500 1760 Dummy17 -10950 500

1701 S1383 -10065 613
1702 S1384 -10080 500
1703 S1385 -10095 613
1704 S1386 -10110 500
1705 S1387 -10125 613
1706 S1388 -10140 500
1707 S1389 -10155 613
1708 S1390 -10170 500
1709 S1391 -10185 613
1710 S1392 -10200 500
1711 S1393 -10215 613
1712 S1394 -10230 500
1713 S1395 -10245 613
1714 S1396 -10260 500
1715 S1397 -10275 613
1716 S1398 -10290 500
1717 S1399 -10305 613
1718 S1400 -10320 500
1719 S1401 -10335 613
1720 S1402 -10350 500
1721 S1403 -10365 613
1722 S1404 -10380 500
1723 S1405 -10395 613
1724 S1406 -10410 500
1725 S1407 -10425 613
1726 S1408 -10440 500
1727 S1409 -10455 613
1728 S1410 -10470 500
1729 S1411 -10485 613
1730 S1412 -10500 500
1731 S1413 -10515 613
1732 S1414 -10530 500
1733 S1415 -10545 613
1734 S1416 -10560 500
1735 S1417 -10575 613
1736 S1418 -10590 500
1737 S1419 -10605 613
1738 S1420 -10620 500
1739 S1421 -10635 613
1740 S1422 -10650 500

Himax Confidential -P.26-

15 15 15

95
I/O pins

208
113

18
(No. 313-1760)

95
2
15 15 15 Bump area = 1425 um

50 Bump area = 4000 um2

I/O pins
80

(No. 1-312)

Himax Confidential -P.27-

Himax Confidential -P.28-

The HX8369-A00 supports DBI (Display Bus Interface) and DPI (Display Pixel
Interface). Where DBI supports (16-/9-/8-bit interface) Parallel Interface (Type A, Type
B) and Serial interface (Type C). The interface mode can be selected by BS3-0 pins
setting as show in Table 4.1.

BS3 BS2 BS1 BS0 Interface Display data Display mode

0 0 0 0 DBI TYPE-A 8-bit (CLK-E) GRAM Type 1
0 0 0 1 DBI TYPE-A 9-bit (CLK-E) GRAM Type 1
0 0 1 0 DBI TYPE-A 16-bit (CLK-E) GRAM Type 1
0 0 1 1 DBI TYPE-A 18-bit (CLK-E) GRAM Type 1
0 1 0 0 DBI TYPE-B 8-bit GRAM Type 1
0 1 0 1 DBI TYPE-B 9-bit GRAM Type 1
0 1 1 0 DBI TYPE-B 16-bit GRAM Type 1
0 1 1 1 DBI TYPE-B 18-bit GRAM Type 1
1 0 0 0 - - -
1 0 0 1 - - -
1 0 1 0 DBI TYPE-B 24-bit GRAM Type 1
1 1 0 0 - - -
1 1 0 1 DPI / DBI TYPE-C Option 1 DPI / GRAM Type 3
1 1 1 0 DPI / DBI TYPE-C Option 2 DPI / GRAM Type 3
1 1 1 1 DPI / DBI TYPE-C Option 3 DPI / GRAM Type 3
Table 4.1: Interface selection

The HX8369-A00 includes an index register (IR), which is stored the index data of
internal control register and GRAM. When DCX=”L”, the command via DBI interface
write into register. When DCX=”H”, GRAM data via R2Ch register can be written
through data bus. When the data is written into the GRAM from the MPU, it is first
written into the write-data latch and then automatically written into the GRAM by
internal operation. Data is read through the read-data latch when reading from the
GRAM.

When data is read from the GRAM to the MPU, it is first read from GRAM to the
read-data latch and then data is read to MPU through the read-data latch in next read
operation. Therefore, the read data in data bus in first read operation is invalid, and
the read data in data bus in second and the following read operation is valid.

Himax Confidential -P.29-

Interface RDX_E WRX_DCX DCX_SCL D23–D0 or other input pin

DB23–DB0: 24-bit data bus
DB21–DB16, DB13-DB8,
DBI Type C 3-wire serial DB5-DB0: 18-bit data bus
Unused Unused SCL
interface + DPI interface DB21–DB17, DB13-DB8,
DB5-DB1: 16-bit data bus
SDI/SDO
DB23–DB8: Unused,
DBI Type A 8-bit parallel E RW DCX
DB7–DB0: 8-bit data bus
DB23–DB9: Unused,
DBI Type A 9-bit parallel E RW DCX
DB8–DB0: 9-bit data bus
DB23–DB16: Unused,
DBI Type A 16-bit parallel E RW DCX
DB15–DB0: 16-bit data bus
DB23–DB18: Unused,
DBI Type A 18-bit parallel E RW DCX
DB17–DB0: 18-bit data bus
DB23–DB0: 24-bit data bus
DB21–DB16, DB13-DB8,
DBI Type C 4-wire serial DB5-DB0: 18-bit data bus
Unused DCX SCL
interface + DPI interface DB21–DB17, DB13-DB8,
DB5-DB1: 16-bit data bus
SDI/SDO
DB23–DB8: Unused,
DBI Type B 8-bit parallel RDX WRX DCX
D7–D0: 8-bit data bus
DB23–DB9: Unused,
DBI Type B 9-bit parallel RDX WRX DCX
DB8–DB0: 9-bit data bus
DB23–DB16: Unused,
DBI Type B 16-bit parallel RDX WRX DCX
DB15–DB0: 16-bit data bus
DB23–DB18: Unused,
DBI Type B 18-bit parallel RDX WRX DCX
DB17–DB0: 18-bit data bus
DBI Type B 24-bit parallel RDX WRX DCX DB23–DB0: 24-bit data bus

Table 4.2: Pin connection based on different interface

Himax Confidential -P.30-

The selection of DBI interface is by BS3 pin. When this pin is low state (VSSD), the
interface is use DBI system. And use BS2 to BS0 pins to selsect DBI interfacr mode.
The parallel interface timing diagram is described in Figure 4.1 to Figure 4.4.

Figure 4.1: DBI-A system interface protocol, write to register or GRAM

Figure 4.2: DBI-A system interface protocol, read from register or GRAM

Himax Confidential -P.31-

Figure 4.3: DBI-B system interface protocol, write to register or GRAM

Figure 4.4: DBI-B system interface protocol, read from register or GRAM

Himax Confidential -P.32-

The DBI-B system 24-bit bus parallel data transfer can be used by setting “BS3-0”
pins to “1010”. The Figure 4.5 is the example of interface with 18-bit DBI-A / DBI-B
microcomputer system interface.

Figure 4.5 Example of DBI-B system 24-bit parallel bus interface

There are one type data format to write display data at 24-bit bus Interface. See
Figure 4.6.

Figure 4.6: Write data for RGB 8-8-8 (16.7M colours) bit Input in 24-bit parallel interface

Himax Confidential -P.33-

The DBI-A system 18-bit bus parallel data transfer can be used by setting “BS3-0” pins
to “0011”. And the DBI-B system 18-bit bus parallel data transfer can be used by setting
“BS3-0”pins to “0111”. The Figure 4.7 is the example of interface with 18-bit DBI-A /
DBI-B microcomputer system interface.

Figure 4.7: Example of DBI-A- / DBI-B system 18-bit parallel bus interface

There are three types data format to write display data at 18-bit bus Interface. See
Figure 4.8 to Figure 4.10. Under this type, the data format can select as 16- / 18- /
24-bit by register R3Ah. (set_pixel_format)

65k Color
DCX D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 GRAM Write
Data
MEMWR 0 GRAM Write command code -
1st write 1 x x R14 R13 R12 R11 R10 G15 G14 G13 G12 G11 G10 B14 B13 B12 B11 B10 1st pixel (R1/G1/B1)
2nd write 1 x x R24 R23 R22 R21 R20 G25 G24 G23 G22 G21 G20 B24 B23 B22 B21 B20 2nd pixel (R2/G2/B2)

16-bit 16-bit

Look-Up Table for 65k Color data mapping (16-bit to 24-bit)

24-bit 24-bit
GRAM

R1 G1 B1 R2 G2 B2 R3 G3 B3

Figure 4.8: Write data for RGB 5-6-5 (65k colours) bit input in 18-bit parallel interface
262k Color
DCX D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 GRAM Write
Data
MEMWR 0 GRAM Write command code -
1st write 1 R15 R14 R13 R12 R11 R10 G15 G14 G13 G12 G11 G10 B15 B14 B13 B12 B11 B10 1st pixel (R1/G1/B1)
2nd write 1 R25 R24 R23 R22 R21 R20 G25 G24 G23 G22 G21 G20 B25 B24 B23 B22 B21 B20 2nd pixel (R2/G2/B2)

18-bit 18-bit

Look-Up Table for 262k Color data mapping (18-bit to 24-bit)

24-bit 24-bit
GRAM

R1 G1 B1 R2 G2 B2 R3 G3 B3

Figure 4.9: Write data for RGB 6-6-6(262k colours) bit input in 18-bit parallel interface
Himax Confidential -P.34-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02

16.7M Color DCX

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 GRAM Write
Data
MEMWR 0 GRAM Write command code -
1st write 1 R17 R1 6 R1 5 R1 4 R1 3 R1 2 R1 1 R1 0 x x G17 G16 G15 G14 G13 G12 G11 G10 1st pixel (R1/G1/B1)
2nd write 1 B17 B16 B15 B14 B13 B12 B11 B10 x x R27 R26 R25 R24 R23 R22 R21 R20 x
3rd write 1 G2 7 G2 6 G2 5 G2 4 G23 G22 G21 G2 0 x x B27 B26 B25 B24 B23 B22 B21 B20 2nd pixel (R2/G2/B2)

24-bit 24-bit
GRAM

R1 G1 B1 R2 G2 B2 R3 G3 B3

16.7M Color DCX D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 GRAM Write
Data
MEMWR 0 GRAM Write command code -
1st write 1 R17 R16 R15 R14 R13 R12
R11 R10 x x G17 G16 G15 G14 G13 G12 G11 G10 1st pixel (R1/G1/B1)
2nd write 1 B17 B16 B15 B14 B13 B12
B11 B10 x x R27 R26 R25 R24 R23 R22 R21 R20 -
- 0 The other command -
MEMWR 0 GRAM Write command code -
1st write 1 R2 7 R2 6 R2 5 R2 4 R2 3 R2 2 R2 1 R2 0 x x G2 7 G2 6 G2 5 G2 4 G2 3 G22 G21 G20 2nd pixel (R2/G2/B2)
2nd write 1 B27 B26 B25 B24 B23 B22 B21 B20 x x R3 7 R3 6 R3 5 R3 4 R33 R32 R31 R30 -
3rd write 1 G37 G36 G35 G34 G33 G32 G31 G30 x x B37 B36 B35 B34 B33 B32 B31 B30 3rd pixel (R3/G3/B3)

24-bit 24-bit R27 ~ R20 will be neglected and are not used
GRAM

R1 G1 B1 R2 G2 B2 R3 G3 B3

Figure 4.10: Write data for RGB 8-8-8 (16.7M colours) bit input in 18-bit parallel interface

Himax Confidential -P.35-

The DBI-A system 16-bit bus parallel data transfer can be used by setting “BS3-0”
pins to “0010”. And the DBI-B system 16-bit bus parallel data transfer can be used by
setting “BS3-0” pins to “0110”. The Figure 4.11 is the example of interface with 16-bit
DBI-A / DBI-B microcomputer system interface.

Figure 4.11: Example of DBI-A- / DBI-B system 16-bit bus interface

There are three types data format to write display data at 16-bit bus Interface. See
Figure 4.12 to Figure 4. 14. Under this type, the data format can select as 16- / 18- /
24-bit by register R3Ah. (set_pixel_format)

65k Color
DCX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 GRAM Write
Data
MEMWR 0 GRAM Write command code -
1st write 1 R14 R13 R12 R11 R10 G15 G14 G13 G12 G11 G10 B14 B13 B12 B11 B10 1st pixel (R1/G1/B1)
2nd write 1 R24 R23 R22 R21 R20 G25 G24 G23 G22 G21 G20 B24 B23 B22 B21 B20 2nd pixel (R2/G2/B2)

16-bit 16-bit

Look-Up Table for 65k Color data mapping (16-bit to 24-bit)

24-bit 24-bit
GRAM

R1 G1 B1 R2 G2 B2 R3 G3 B3

Figure 4.12: Write data for RGB 5-6-5 (65k colours) bit input in 16-bit parallel interface

Himax Confidential -P.36-

R1 G1 B1 R2 G2 B2 R3 G3 B3

Figure 4.22: Write data for RGB 8-8-8-bit (16.7 M colours) input in 8-bit parallel interface

Himax Confidential -P.41-

The HX8369-A00 supports three type serial data transfer interface, the interface
selection by setting BS3-0 pins. The BS3-0 set “1101” is select 3-wire option 1 serial
bus. The BS3-0 set “1110” is select 3-wire option 2 serial bus. The BS3-0 is set “1111”
when select 4-wire option 3 serial bus.

The 3-wire serial bus is use: chip select line (CSX), serial input/output data (SDI and
SDO) and the serial transfer clock line (DCX_SCL).The 4-wire serial bus is use: chip
select line (CSX), data/command select (WRX_DCX), serial input/output data (SDI
and SDO) and the serial transfer clock line (DCX_SCL).

4.2.1.1 Serial data write mode

The 3-pin serial data packet contains a control bit D/CX and a transmission byte and
in 4-pin serial case, data packet contains just transmission byte and control signal
D/CX is transferred by WRX_DCX pin. If DCX is low, the transmission byte is
command byte. If D/CX is high, the transmission byte is stored in to command register
or GRAM. The MSB is transmitted first. The serial interface is initialized when CSX is
high. In this state, SCL clock pulse or serial input/output data (SDI and SDO) have no
effect. A falling edge on CSX enables the serial interface and indicates the start of
data transmission. Where 3-wire serial write format include two types (8-/16-bit) is
according command code.

Figure 4.23: Serial data stream, write mode

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Figure 4.24: DBI Type C: Serial interface protocol 3-wire/4-wire, write mode

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The micro-controller first has to send a command and then the following byte is
transmitted in the opposite direction. The 3-wire serial read data format which just
needs 8-bit.

Figure 4.25: Type C:Serial interface protocol 3-wire/4-wire read mode

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Figure 4.26: Display module data transfer recovery

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The HX8369-A00 uses 16 or 18-bit or 24-bit parallel RGB interface which includes:
HS, VSYNC, DE, PCLK, DB23~DB0. The interface is active after Power On sequence.
Pixel clock (PCLK) is running all the time without stopping and it is used to entering
HSYNC, VSYNC, DE and DB23~DB0– lines states when there is a rising edge of the
PCLK. The PCLK cannot be used as continue internal clock for other functions of the
display module e.g. Sleep In– mode etc. Vertical synchronization (VSYNC) is used to
tell when there is received a new frame of the display. This is negative (“-“, “0”, low)
active and its state is read to the display module by a rising edge of the PCLK-line.
Horizontal synchronization (HSYNC) is used to tell when there is received a new line
of the frame. This is negative (“-“, “0”, low) active and its state is read to the display
module by a rising edge of the PCLK- line. Data enable (DE) is used to tell when there
is received RGB information that should be transferred on the display. This is positive
(“+”, “1”, high) active and its state is read to the display module by a rising edge of the
PCLK-line. DB23~DB0 (24 bit: R7-R0, G7-G0 and B7-B0; 18 bit: R5- R0, G5-G0 and
B5-B0; 16 bit: R4- R0, G5-G0 and B4-B0) are used to tell what is the information of
the image that is transferred on the display (when DE=1 and there is a rising edge of
PCLK). DB23~DB0– lines can be set to “0” (low) or “1” (high). These lines are read by
a rising edge of the PCLK-line.

The pixel clock cycle is described in the following figure.

Note: PCLK is an unsynchronized signal (It can be stopped).

Figure 4.27: PCLK cycle

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Vertical Sync.
0 1

Invisble Image
Vsync
= Timing information what is not possible to see on the display
= Blanking Time
VBP
DE = 0 (Low)

Display Area
(VAdr + HAdr) – period
when valid display data are
VAdr transferred from host to
display module

DE = 1 (High)

VFP

1
Horizontal Sync. 0
Hsync HBP HAdr HFP

Figure 4.28: General timing diagram

Figure 4.29: DPI (480RGB x 864) timing diagram

The image information must be correct on the display, when the timings are in range
on the interface. However, the image information can be incorrect on the display,
when timings are out of the range on the interface (Out of the range timings cannot
cause any damage on the display module or it cannot cause any damage on the host
side). The correct image information must be displayed automatically (by the display
module) on the next frame (vertical sync.), when there is returned from out of the
range to in range interface timings.

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DPI interface displaying moving pictures can be selected to rewrite into the GRAM or
not through GRAM. The selection is set by register DM[1:0] and RM.

RM setting is enabled from the next frame. Wait 1 frame to transfer data after setting.

RM Interface for RAM access

0 DBI Interface (CPU)
1 DPI Interface (RGB)

DM[1:0] The bit is used to select display operation mode. The setting allows switching
between display operation in synchronization with internal oscillation clock, VSYNC,
or DPI signal.
Note that switching between VSYNC and DPI operation is prohibited.

DM 1 DM 0 Display Mode
0 0 Internal oscillation clock
0 1 DPI signal (VSYNC+HSYNC)
1 0 VSYNC signal only
1 1 RGB data bypass GRAM mode

Frame Memory Access Display Operation Mode

Operation Mode
Setting (RM) (DM[1:0])
Internal clock operation MPU interface Internal clock operation
(displaying still pictures) (RM=0) (DM[1:0]=00)
RGB interface : capture mode 1 RGB interface RGB interface : VS & HS
(displaying moving pictures) (RM=1) (DM[1:0]=01)
RGB interface : capture mode 2
MPU interface RGB interface : VS & HS
(rewriting still pictures while
(RM=0) (DM[1:0]=01)
displaying moving pictures)
RGB interface : through mode RGB interface : VS & HS
Bypass frame memory
(displaying moving pictures) (DM[1:0]=11)
Internal clock operation RGB interface Internal clock operation
RGB data format (RM=1) (DM[1:0]=00)
Note: RGB interface capture mode is only for 24-bit / pixel color order.

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Note: The data order is shown as follows, MSB=DB23, LSB=DB0 and picture data is MSB=Bit5, LSB=Bit0 for
Green data and MSB=Bit4, LSB=Bit0 for Red and Blue data. Un-used pin DB23, DB22, DB16, DB15, DB14,
DB7, DB6 and DB0 are set to open.

Figure 4.30: 16-bit / pixel 65K colours order on the DPI I/F

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Note: The Data order is shown as follows, MSB = DB23, LSB = DB0 and Picture Data is MSB = Bit5, LSB = Bit0 for
Red, Green and Blue data. Un-used pin DB23, DB22, DB15, DB14, DB7 and DB6 are set to open.

Figure 4.31: 18-bit / pixel: 262k colours order on the DPI I/F

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Note: The Data order is shown as follows, MSB = DB23, LSB = DB0 and Picture Data is MSB = Bit7, LSB = Bit0 for
Red, Green and Blue data.

Figure 4.32: 24-bit / pixel color order on the RGB I/F

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HX8369-A00 support the display data RAM that stores display dots and consists of
9,953,280 bits (480x864x24 bits). There is no restriction on access to the RAM even
when the display data on the same address is loaded to DAC There will be no
abnormal visible effect on the display when there is a simultaneous Panel Read and
Interface Read or Write to the same location of the Frame Memory.

5.2 Address counter (AC)

The HX8369-A00 contains an address counter (AC) which assigns address for
writing/reading pixel data to/from GRAM. The address pointers set the position of
GRAM whose addresses range:

RES_SEL2 RES_SEL 1 RES_SEL 0 MV X range Y range Panel resolution

0 0~479d. 0~863d.
0 0 0 480RGBX864 dot
1 0~863d. 0~479d.
0 0~479d.. 0~853d.
0 0 1 480RGBX854 dot
1 0~853d. 0~479d.
0 0~479d. 0~799d.
0 1 0 480RGBX800 dot
1 0~799d. 0~479d.
0 0~479d. 0~639d.
0 1 1 480RGBX640 dot
1 0~639d. 0~479d.
0 0~359d. 0~639d.
1 0 0 360 RGBX640 dot
1 0~639d. 0~359d.
0 0~479d. 0~719d.
1 0 1 480RGBX720 dot
1 0~719d. 0~479d.

Table 5.1: Addresses counter range

CA
MX=0 0 1 --- 358 359
MX=1 359 358 --- 1 0

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Source Out S1 S2 S3 S4 S5 S6 --- S1435 S1436 S1437 S1438 S1439 S1440

RGB=1

RGB=1
RGB=0

RGB=0

RGB=0
RA SA
MY=0 MY=1 ML=0 ML=1
0 719 R0 7-0 G0 7-0 B0 7-0 R1 7-0 G1 7-0 B1 7-0 --- R478 7-0 G478 7-0 B478 7-0 R479 7-0 G479 7-0 B479 7-0 0 719
1 718 --- 1 718
2 717 --- 2 717
3 716 --- 3 716
4 715 --- 4 715
5 714 --- 5 714
6 713 --- 6 713
7 712 --- 7 712
8 711 --- 8 711
9 710 --- 9 710
: : : : : : : : : : : : : : : : :

: : : : : : : : : : : : : : : : :

: : : : : : : : : : : : : : : : :
712 7 --- 712 7
713 6 --- 713 6
714 5 --- 714 5
715 4 --- 715 4
716 3 --- 716 3
717 2 --- 717 2
718 1 --- 718 1
719 0 --- 719 0

CA
MX=0 0 1 --- 478 479
MX=1 479 478 --- 1 0

Note:RA=Row Address
CA=Colum Address
SA=Scan Address
MX=Colum address direction parameter
MY=Row address direction parameter
ML=Scan direction parameter
RGB=Red,Green and Blue pixel position change

Table 5.7: Memory map of 480RGB x 720 resolution

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B Data stream from MCU is like

this figure

E
Figure 5.1: MCU to Memory write / read direction

The data is written in the order as illustrated above. The counter that dictates which
physical memory the data is to be written is controlled by “Memory Access Control”
Command, Bits MY, MX, MV as described below.
MY

MV
Physical Row Pointer

Figure 5.2: MY, MX, MV setting of 480RGB x 864 dot

MV MX MY CASET PASET
0 0 0 Direct to Physical Column Pointer Direct to Physical Row Pointer
Direct to (863-Physical Row Pointer)
0 0 1 Direct to Physical Column Pointer
with SC
0 1 0 Direct to (479-Physical Column Pointer) Direct to Physical Row Pointer
0 1 1 Direct to (479-Physical Column Pointer) Direct to (863-Physical Row Pointer)
1 0 0 Direct to Physical Row Pointer Direct to Physical Column Pointer
1 0 1 Direct to (863-Physical Row Pointer) Direct to Physical Column Pointer
1 1 0 Direct to Physical Row Pointer Direct to (479-Physical Column Pointer)
1 1 1 Direct to (863-Physical Row Pointer) Direct to (479-Physical Column Pointer)
Figure 5.3: MY, MX, MV setting of 480RGB x 864 dot

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Memory Access
Display Data
Control Image in the Host Image in the Driver (GRAM)
Direction
MV MX MY
B H/W Position (0,0) B

X,Y address (0,0)

X: CASET
Normal 0 0 0 Y: RASET

E
E
B
H/W Position (0,0) E

Y-Mirror 0 0 1
X,Y address (0,0)
X: CASET
Y: RASET
E B

X-Mirror 0 1 0

E
B

X-Mirror
0 1 1
Y-Mirror

E
B
H/W Position (0,0) B

X-Y X,Y address (0,0)

1 0 0 X: CASET
Exchange Y: RASET

E E

B H/W Position (0,0) E

X-Y
Exchange 1 0 1
X,Y address (0,0)
Y-Mirror X: CASET
Y: RASET
B
E
B H/W Position (0,0) B X,Y address (0,0)
X: CASET
X-Y Y: RASET

Exchange 1 1 0
X-Mirror
E
E
B H/W Position (0,0) E
X-Y
Exchange
1 1 1
X-Mirror X,Y address (0,0)
X: CASET
Y-Mirror B Y: RASET
E
Figure 5.4: Address direction settings

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5.5.1 Fully display

Example: (1) 480RGBx864 dot display mode.

(2) NORON (Normal Display Mode On) instruction (R13h).
(3) SC=0x000h, EC=0x1DFh (R2Ah) and SP=0x000h, EP=0x35Fh (R2Bh), ML=0.

000h 001h --------- 1DEh 1DFh

GRAM DB---DB DB---DB DB---DB DB---DB
---------
23 ---0 23 ---0 23 ---0 23 ---0
000h 000000H 000001H --------- 0001DEH 0001DFH
001h 001000H 001001H --------- 0011DEH 0011DFH
002h 002000H 002001H --------- 0021DEH 0021DFH
003h 003000H 003001H --------- 0031DEH 0031DFH
004h 004000H 004001H --------- 0041DEH 0041DFH
005h 005000H 005001H --------- 0051DEH 0051DFH
-------

-------

-------
---------

35Ah 35A000H 35A001H --------- 35A1DEH 35A1DFH

35Bh 35B000H 35B001H --------- 35B1DEH 35B1DFH
35Ch 35C000H 35C001H --------- 35C1DEH 35C1DFH
35Dh 35D000H 35D001H --------- 35D1DEH 35D1DFH
35Eh 35E000H 35E001H --------- 35E1DEH 35E1DFH
35Fh 35F000H 35F001H --------- 35F1DEH 35F1DFH
Table 5.8: 480RGB x 864 resolution (SRAM assignment)

480 columns
1DDh

1DDh
1DEh

1DFh

1DEh
00h

1DFh
01h

00h

01h

00h 00 01 02 03 04 05 0V 0W 0X 0Y 0Z 00h 00 01 02 03 04 05 0V 0W 0X 0Y 0Z

01h 10 11 12 13 14 1W 1X 1Y 1Z 01h 10 11 12 13 14 1W 1X 1Y 1Z
20 21 22 23 2X 2Y 2Z 20 21 22 23 2X 2Y 2Z
30 31 32 3Y 3Z 30 31 32 3Y 3Z
864lines

864lines

480 x 864 x24bit 480 x 864

Frame memory LCD panel

W0 W1 WX WY WZ W0 W1 WX WY WZ
35Dh X0 X1 X2 XW XX XY XZ 35Dh X0 X1 X2 XW XX XY XZ
35Eh Y0 Y1 Y2 Y3 YW YX YY YZ 35Eh Y0 Y1 Y2 Y3 YW YX YY YZ
35Fh Z0 Z1 Z2 Z3 Z4 Z5 ZV ZW ZX ZY ZZ 35Fh Z0 Z1 Z2 Z3 Z4 Z5 ZV ZW ZX ZY ZZ

480 columns

Figure 5.5: 480RGB x 864 resolution

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000h 001h --------- 1DEh 1DFh

DB---DB DB---DB DB---DB DB---DB

GRAM
---------
23 ---0 23 ---0 23 ---0 23 ---0

000h 000000H 000001H --------- 0001DEH 0001DFH

001h 001000H 001001H --------- 0011DEH 0011DFH
002h 002000H 002001H --------- 0021DEH 0021DFH
003h 003000H 003001H --------- 0031DEH 0031DFH
004h 004000H 004001H --------- 0041DEH 0041DFH
005h 005000H 005001H --------- 0051DEH 0051DFH
-------

-------

-------
---------

350h 350000H 350001H --------- 3501DEH 3501DFH

351h 351000H 351001H --------- 3511DEH 3511DFH
352h 352000H 352001H --------- 3521DEH 3521DFH
353h 353000H 353001H --------- 3531DEH 3531DFH
354h 354000H 354001H --------- 3541DEH 3541DFH
355h 355000H 355001H --------- 3551DEH 3551DFH

Table 5.9: 480RGB x 854 resolution (SRAM assignment)

1DDh

1DDh
1DEh

1DFh

1DEh
00h

1DFh
01h

00h

01h
854 lines

854 lines

Figure 5.6: 480RGB x 854 resolution

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000h 001h --------- 1DEh 1DFh

-------

-------
---------

31Ah 31A000H 31A001H --------- 31A1DEH 31A1DFH

31Bh 31B000H 31B001H --------- 31B1DEH 31B1DFH
31Ch 31C000H 31C001H --------- 31C1DEH 31C1DFH
31Dh 31D000H 31D001H --------- 31D1DEH 31D1DFH
31Eh 31E000H 31E001H --------- 31E1DEH 31E1DFH
31Fh 31F000H 31F001H --------- 31F1DEH 31F1DFH
Table 5.10: 480RGB x 800 resolution (SRAM assignment)

Figure 5.7: 480RGB x 800 resolution

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000h 001h --------- 1DEh 1DFh

-------

-------
---------

27Ah 27A000H 27A001H --------- 27A1DEH 27A1DFH

27Bh 27B000H 27B001H --------- 27B1DEH 27B1DFH
27Ch 27C000H 27C001H --------- 27C1DEH 27C1DFH
27Dh 27D000H 27D001H --------- 27D1DEH 27D1DFH
27Eh 27E000H 27E001H --------- 27E1DEH 27E1DFH
27Fh 27F000H 27F001H --------- 27F1DEH 27F1DFH
Table 5.11: 480RGB x 640 resolution (SRAM assignment)
1DDh

1DDh
1DEh

1DFh

1DEh
00h

1DFh
01h

00h

01h
640lines

640lines

Figure 5.8: 480RGB x 640 resolution

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Example: (1) 360RGBx640 dot display mode.

(2) NORON (Normal Display Mode On) instruction (R13h).
(3) SC=0x000h, EC=0x167h (R2Ah) and SP=0x000h, EP=0x27Fh (R2Bh), ML=0.

000h 001h --------- 166h 167h

GRAM DB---DB DB---DB DB---DB DB---DB
---------
23 ---0 23 ---0 23 ---0 23 ---0
000h 000000H 000001H --------- 000166H 000167H
001h 001000H 001001H --------- 001166H 001167H
002h 002000H 002001H --------- 002166H 002167H
003h 003000H 003001H --------- 003166H 003167H
004h 004000H 004001H --------- 004166H 004167H
005h 005000H 005001H --------- 005166H 005167H
-------

-------

-------
---------

27Ah 27A000H 27A001H --------- 27A166H 27A167H

27Bh 27B000H 27B001H --------- 27B166H 27B167H
27Ch 27C000H 27C001H --------- 27C166H 27C167H
27Dh 27D000H 27D001H --------- 27D166H 27D167H
27Eh 27E000H 27E001H --------- 27E166H 27E167H
27Fh 27F000H 27F001H --------- 27F166H 27F167H
Table 5.12: 360RGB x 640 resolution (SRAM assignment)

Figure 5.9: 360RGB x 640 resolution

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000h 001h --------- 1DEh 1DFh

-------

-------
---------

2CAh 2CA000H 2CA001H --------- 2CA1DEH 2CA1DFH

2CBh 2CB000H 2CB001H --------- 2CB1DEH 2CB1DFH
2CCh 2CC000H 2CC001H --------- 2CC1DEH 2CC1DFH
2CDh 2CD000H 2CD001H --------- 2CD1DEH 2CD1DFH
2CEh 2CE000H 2CE001H --------- 2CE1DEH 2CE1DFH
2CFh 2CF000H 2CF001H --------- 2CF1DEH 2CF1DFH
Table 5.13: 480RGB x 720 resolution (SRAM assignment)

Figure 5.10: 480RGB x 720 resolution

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The vertical scrolling display is specified by VSCRDEF instruction (R33h) and

VSCRSADD instruction (R37h).

Original Scrolling

TFA

VSA

BFA

Figure 5.11: Vertical scrolling

When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=Panel total scan

lines. In this case, scrolling is applied as shown below.

5.5.2.1 Example: 480RGB X 864

When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=864. In this case,

scrolling is applied as shown below.

Example (1) TFA=2, VSA=862, BFA=0 when MADCTL B4=0

Figure 5.12: Memory map of vertical scrolling 1

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Figure 5.13: Memory map of vertical scrolling 2

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There are 2 types of vertical scrolling, which are determined by the commands
“Vertical Scrolling Definition” (33h) and “Vertical Scrolling Start Address” (37h).

Case 1: TFA + VSA + BFA≠864

Do not set TFA + VSA + BFA≠864. In that case, unexpected picture will be shown.

Case 2: TFA + VSA + BFA=864 (Scrolling)

Example (1) When TFA=0, VSA=864, BFA=0 and VSCRSADD=40.MADCTL
parameter B4=”0”

M e m o r y P h ysica l A x is P h y s ic a l L in e
D isp la y
(0 ,0 ) P o in t e r
A xis ( 0 , 0 )

1
V S CRS A DD 1

2
F ra m e D is p la y
M e m o ry
In cr e m e n t
V S CRS A DD

P h y s ic a l L in e
D isp la y
P o in t e r
A xis ( 0 ,0 )

1
2

V S CRS A DD

2
1

F ra m e D is p la y
M e m o ry
Figure 5.14: Vertical scroll example 1

Example (2) TFA=30, VSA=834, BFA=0 and VSCRSADD =80. MADCTRL parameter B4=”1”
Physical Line
Memory Physical Axis
(0,0) Pointer Display
Axis (0,0)
2

VSCRSADD
3

TFA TFA
1

Frame
Memory Display
Increment
VSCRSADD

Physical Line
Memory Physical Axis
Pointer Display
(0,0)
Axis (0,0)
2

VSCRSADD
3
3

2 1

TFA TFA
1

Frame Display
Memory
Figure 5.15: Vertical scroll example 2

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The Tearing Effect output line supplies to the MPU a Panel synchronization signal.
This signal can be enabled or disabled by the Tearing Effect Line Off & On commands.
The mode of the Tearing Effect signal is defined by the parameter of the Tearing
Effect Line On command. The signal can be used by the MPU to synchronize Frame
Memory Writing when displaying video images.

Tearing Effect Line Modes

Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:

tvdl tvdh

Figure 5.16: Tearing effect output line–mode 1

tvdh=The LCD display is not updated from the Frame Memory

tvdl=The LCD display is updated from the Frame Memory (except Invisible Line – see below)

Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking
Information, there is one V-sync and N H-sync pulses per field.
N: If RES_SEL [2:0] set to = 3’b000, the resolution is 480 RGB X 864, the N=864.

Figure 5.17: Tearing effect output line–mode 2

thdh=The LCD display is not updated from the Frame Memory

thdl=The LCD display is updated from the Frame Memory (except Invisible Line – see above)
Bottom
Line

Top Line

2nd Line

TE (Mode 2)

TE (Mode 1) tvdh

Note: During Sleep In Mode, the Tearing Output Pin is active Low.

Figure 5.18: Tearing effect output line–timing diagrm

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The Tearing Effect signal is described below:

tvdl tvdh

Vertical Timing

Horizontal Timing

thdl thdh

Figure 5.19: Tearing effect output line –tearing effect line timing

Idle Mode Off (Resolution 480x800 RGB, Frame Rate = 60.5 Hz)
Symbol Parameter Min. Max. Unit
tvdl Vertical Timing Low Duration 15 - ms
tvdh Vertical Timing High Duration 1000 - us
thdl Horizontal Timing Low Duration 18 - us
thdh Horizontal Timing High Duration 0.13 500 us
tr Rise time - 15 ns
tf Fall time - 15 ns
Note: The timings in Table 5.13 apply when MADCTL ML=0 and ML=1

Table 5.14: AC characteristics of tearing effect signal

The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.

tr tf

0.8*VDD1 0.8*VDD1

0.2*VDD1 0.2*VDD1

Figure 5.20: Tearing effect output line–definition of tf, tr

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Example 1: MPU write is faster than panel read.

Figure 5.21: Tearing effect output line–example 1 (Timing)

Data write to Frame Memory is now synchronized to the Panel Scan. It should be
written during the vertical sync pulse of the Tearing Effect Output Line. This ensures
that data is always written ahead of the panel scan and each Panel Frame refresh has
a complete new image:

Data to be sent

a b c d

Image on LCD

Figure 5.22: Tearing effect output line–example 1 (Image)

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MCU to Memory
1st 864th
Time

TE output signal
Time

Memory to LCD
Time
1st 864th

Image on LCD a b c d e f
Figure 5.23: Tearing effect output line–example 2 (Timing)

The MPU to Frame Memory write begins just after Panel Read has commenced i.e.
after one horizontal sync pulse of the Tearing Effect Output Line. This allows time for
the image to download behind the Panel Read pointer and finishing download during
the subsequent Frame before the Read Pointer “catches” the MPU to Frame memory
write position.

Data to be sent

a b c d e f

Image on LCD

Figure 5.24: Tearing effect output line–example 2 (Image)

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5.6.1 Color depth conversion Look-up tables

R input (5-bit) R input (6-bit) R output (8-bit)

16-bit / pixel 18-bit / pixel 24-bit / pixel
RGBSET
mode mode mode
Parameter
65,536 262,144 16,777,216
colours colours colours
00000 000000 R007 R006R005 R004R003R002R001R000 1
00001 000001 R017R016R015R014R013R012R011R010 2
00010 000010 R027R026R025R024R023R022R021R020 3
00011 000011 R037R036R035R034R033R032R031R030 4
00100 000100 R047R046R045R044R043R042R041R040 5
00101 000101 R057R056R055R054R053R052R051R050 6
00110 000110 R067R066R065R064R063R062R061R060 7
00111 000111 R077R076R075R074R073R072R071R070 8
01000 001000 R087R086R085R084R083R082R081R080 9
01001 001001 R097R096R095R094R093R092R091R090 10
01010 001010 R107R106R105R104R103R102R101R100 11
01011 001011 R117R116R115R114R113R112R111R110 12
01100 001100 R127R126R125R124R123R122R121R120 13
01101 001101 R137R136R135R134R133R132R131R130 14
01110 001110 R147R146R145R144R143R142R141R140 15
01111 001111 R157R156R155R154R153R152R151R150 16
10000 010000 R167 R166R165 R164R163R162R161R160 17
10001 010001 R177R176R175R174R173R172R171R170 18
10010 010010 R187R186R185R184R183R182R181R180 19
10011 010011 R197R196R195R194R193R192R191R190 20
10100 010100 R207R206R205R204R203R202R201R200 21
10101 010101 R217R216R215R214R213R212R211R210 22
10110 010110 R227R226R225R224R223R222R221R220 23
10111 010111 R237R236R235R234R233R232R231R230 24
11000 011000 R247R246R245R244R243R242R241R240 25
11001 011001 R257R256R255R254R253R252R251R250 26
11010 011010 R267R266R265R264R263R262R261R260 27
11011 011011 R277R276R275R274R273R272R271R270 28
11100 011100 R287R286R285R284R283R282R281R280 29
11101 011101 R297R296R295R294R293R292R291R290 30
11110 011110 R307R306R305R304R303R302R301R300 31
11111 011111 R317R316R315R314R313R312R311R310 32
Table 5.15: Look-up tables-1

Himax Confidential -P.74-

R input (5-bit) R input (6-bit) R output (8-bit)

16-bit / pixel 18-bit / pixel 24-bit / pixel
RGBSET
mode mode mode
Parameter
65,536 262,144 16,777,216
colours colours colours
No Input 100000 R327 R326R325 R324R323R322R321R320 33
No Input 100001 R337R336R335R334R333R332R331R330 34
No Input 100010 R347R346R345R344R343R342R341R340 35
No Input 100011 R357R356R355R354R353R352R351R350 36
No Input 100100 R367R366R365R364R363R362R361R360 37
No Input 100101 R377R376R375R374R373R372R371R370 38
No Input 100110 R387R386R385R384R383R382R381R380 39
No Input 100111 R397R396R395R394R393R392R391R390 40
No Input 101000 R407R406R405R404R403R402R401R400 41
No Input 101001 R417R416R415R414R413R412R411R410 42
No Input 101010 R427R426R425R424R423R422R421R420 43
No Input 101011 R437R436R435R434R433R432R431R430 44
No Input 101100 R447R446R445R444R443R442R441R440 45
No Input 101101 R457R456R455R454R453R452R451R450 46
No Input 101110 R467R466R465R464R463R462R461R460 47
No Input 101111 R477R476R475R474R473R472R471R470 48
No Input 110000 R487 R486R485 R484R483R482R481R480 49
No Input 110001 R497R496R495R494R493R492R491R490 50
No Input 110010 R507R506R505R504R503R502R501R500 51
No Input 110011 R517R516R515R514R513R512R511R510 52
No Input 110100 R527R526R525R524R523R522R521R520 53
No Input 110101 R537R536R535R534R533R532R531R530 54
No Input 110110 R547R546R545R544R543R542R541R540 55
No Input 110111 R557R556R555R554R553R552R551R550 56
No Input 111000 R567R566R565R564R563R562R561R560 57
No Input 111001 R577R576R575R574R573R572R571R570 58
No Input 111010 R587R586R585R584R583R582R581R580 59
No Input 111011 R597R596R595R594R593R592R591R590 60
No Input 111100 R607R606R605R604R603R602R601R600 61
No Input 111101 R617R616R615R614R613R612R611R610 62
No Input 111110 R627R626R625R624R623R622R621R620 63
No Input 111111 R637R636R635R634R633R632R631R630 64
Table 5.16: Look-up tables-2

Himax Confidential -P.75-

G input (5-bit) G input (6-bit) G output (8-bit)

16-bit / pixel 18-bit / pixel 24-bit / pixel RGBSET
mode mode mode Parameter
65,536 262,144 16,777,216
colours colours colours
000000 000000 G007 G006G005 G004G003G002G001G000 65
000001 000001 G017G016G015G014G013G012G011G010 66
000010 000010 G027G026G025G024G023G022G021G020 67
000011 000011 G037G036G035G034G033G032G031G030 68
000100 000100 G047G046G045G044G043G042G041G040 69
000101 000101 G057G056G055G054G053G052G051G050 70
000110 000110 G067G066G065G064G063G062G061G060 71
000111 000111 G077G076G075G074G073G072G071G070 72
001000 001000 G087G086G085G084G083G082G081G080 73
001001 001001 G097G096G095G094G093G092G091G090 74
001010 001010 G107G106G105G104G103G102G101G100 75
001011 001011 G117G116G115G114G113G112G111G110 76
001100 001100 G127G126G125G124G123G122G121G120 77
001101 001101 G137G136G135G134G133G132G131G130 78
001110 001110 G147G146G145G144G143G142G141G140 79
001111 001111 G157G156G155G154G153G152G151G150 80
010000 010000 G167 G166G165 G164G163G162G161G160 81
010001 010001 G177G176G175G174G173G172G171G170 82
010010 010010 G187G186G185G184G183G182G181G180 83
010011 010011 G197G196G195G194G193G192G191G190 84
010100 010100 G207G206G205G204G203G202G201G200 85
010101 010101 G217G216G215G214G213G212G211G210 86
010110 010110 G227G226G225G224G223G222G221G220 87
010111 010111 G237G236G235G234G233G232G231G230 88
011000 011000 G247G246G245G244G243G242G241G240 89
011001 011001 G257G256G255G254G253G252G251G250 90
011010 011010 G267G266G265G264G263G262G261G260 91
011011 011011 G277G276G275G274G273G272G271G270 92
011100 011100 G287G286G285G284G283G282G281G280 93
011101 011101 G297G296G295G294G293G292G291G290 94
011110 011110 G307G306G305G304G303G302G301G300 95
011111 011111 G317G316G315G314G313G312G311G310 96
Table 5.17: Look-up tables-3

Himax Confidential -P.76-

G input (5-bit) G input (6-bit) G output (8-bit)

16-bit / pixel 18-bit / pixel 24-bit / pixel RGBSET
mode mode mode Parameter
65,536 262,144 16,777,216
colours colours colours
100000 100000 G327 G326G325 G324G323G322G321G320 97
100001 100001 G337G336G335G334G333G332G331G330 98
100010 100010 G347G346G345G344G343G342G341G340 99
100011 100011 G357G356G355G354G353G352G351G350 100
100100 100100 G367G366G365G364G363G362G361G360 101
100101 100101 G377G376G375G374G373G372G371G370 102
100110 100110 G387G386G385G384G383G382G381G380 103
100111 100111 G397G396G395G394G393G392G391G390 104
101000 101000 G407G406G405G404G403G402G401G400 105
101001 101001 G417G416G415G414G413G412G411G410 106
101010 101010 G427G426G425G424G423G422G421G420 107
101011 101011 G437G436G435G434G433G432G431G430 108
101100 101100 G447G446G445G444G443G442G441G440 109
101101 101101 G457G456G455G454G453G452G451G450 110
101110 101110 G467G466G465G464G463G462G461G460 111
101111 101111 G477G476G475G474G473G472G471G470 112
110000 110000 G487 G486G485 G484G483G482G481G480 113
110001 110001 G497G496G495G494G493G492G491G490 114
110010 110010 G507G506G505G504G503G502G501G500 115
110011 110011 G517G516G515G514G513G512G511G510 116
110100 110100 G527G526G525G524G523G522G521G520 117
110101 110101 G537G536G535G534G533G532G531G530 118
110110 110110 G547G546G545G544G543G542G541G540 119
110111 110111 G557G556G555G554G553G552G551G550 120
111000 111000 G567G566G565G564G563G562G561G560 121
111001 111001 G577G576G575G574G573G572G571G570 122
111010 111010 G587G586G585G584G583G582G581G580 123
111011 111011 G597G596G595G594G593G592G591G590 124
111100 111100 G607G606G605G604G603G602G601G600 125
111101 111101 G617G616G615G614G613G612G611G610 126
111110 111110 G627G626G625G624G623G622G621G620 127
111111 111111 G637G636G635G634G633G632G631G630 128
Table 5.18: Look-up tables-4

Himax Confidential -P.77-

B input (5-bit) B input (6-bit) B output (8-bit)

16-bit / pixel 18-bit / pixel 24-bit / pixel RGBSET
mode mode mode Parameter
65,536 262,144 16,777,216
colours colours colours
00000 000000 B007 B006B005 B004B003B002B001B000 129
00001 000001 B017B016B015B014B013B012B011B010 130
00010 000010 B027B026B025B024B023B022B021B020 131
00011 000011 B037B036B035B034B033B032B031B030 132
00100 000100 B047B046B045B044B043B042B041B040 133
00101 000101 B057B056B055B054B053B052B051B050 134
00110 000110 B067B066B065B064B063B062B061B060 135
00111 000111 B077B076B075B074B073B072B071B070 136
01000 001000 B087B086B085B084B083B082B081B080 137
01001 001001 B097B096B095B094B093B092B091B090 138
01010 001010 B107B106B105B104B103B102B101B100 139
01011 001011 B117B116B115B114B113B112B111B110 140
01100 001100 B127B126B125B124B123B122B121B120 141
01101 001101 B137B136B135B134B133B132B131B130 142
01110 001110 B147B146B145B144B143B142B141B140 143
01111 001111 B157B156B155B154B153B152B151B150 144
10000 010000 B167 B166B165 B164B163B162B161B160 145
10001 010001 B177B176B175B174B173B172B171B170 146
10010 010010 B187B186B185B184B183B182B181B180 147
10011 010011 B197B196B195B194B193B192B191B190 148
10100 010100 B207B206B205B204B203B202B201B200 149
10101 010101 B217B216B215B214B213B212B211B210 150
10110 010110 B227B226B225B224B223B222B221B220 151
10111 010111 B237B236B235B234B233B232B231B230 152
11000 011000 B247B246B245B244B243B242B241B240 153
11001 011001 B257B256B255B254B253B252B251B250 154
11010 011010 B267B266B265B264B263B262B261B260 155
11011 011011 B277B276B275B274B273B272B271B270 156
11100 011100 B287B286B285B284B283B282B281B280 157
11101 011101 B297B296B295B294B293B292B291B290 158
11110 011110 B307B306B305B304B303B302B301B300 159
11111 011111 B317B316B315B314B313B312B311B310 160
Table 5.19: Look-up tables-5

Himax Confidential -P.78-

B input (5-bit) B input (6-bit) B output (8-bit)

16-bit / pixel 18-bit / pixel 24-bit / pixel RGBSET
mode mode mode Parameter
65,536 262,144 16,777,216
colours colours colours
No Input 100000 B327 B326B325 B324B323B322B321B320 161
No Input 100001 B337B336B335B334B333B332B331B330 162
No Input 100010 B347B346B345B344B343B342B341B340 163
No Input 100011 B357B356B355B354B353B352B351B350 164
No Input 100100 B367B366B365B364B363B362B361B360 165
No Input 100101 B377B376B375B374B373B372B371B370 166
No Input 100110 B387B386B385B384B383B382B381B380 167
No Input 100111 B397B396B395B394B393B392B391B390 168
No Input 101000 B407B406B405B404B403B402B401B400 169
No Input 101001 B417B416B415B414B413B412B411B410 170
No Input 101010 B427B426B425B424B423B422B421B420 171
No Input 101011 B437B436B435B434B433B432B431B430 172
No Input 101100 B447B446B445B444B443B442B441B440 173
No Input 101101 B457B456B455B454B453B452B451B450 174
No Input 101110 B467B466B465B464B463B462B461B460 175
No Input 101111 B477B476B475B474B473B472B471B470 176
No Input 110000 B487 B486B485 B484B483B482B481B480 177
No Input 110001 B497B496B495B494B493B492B491B490 178
No Input 110010 B507B506B505B504B503B502B501B500 179
No Input 110011 B517B516B515B514B513B512B511B510 180
No Input 110100 B527B526B525B524B523B522B521B520 181
No Input 110101 B537B536B535B534B533B532B531B530 182
No Input 110110 B547B546B545B544B543B542B541B540 183
No Input 110111 B557B556B555B554B553B552B551B550 184
No Input 111000 B567B566B565B564B563B562B561B560 185
No Input 111001 B577B576B575B574B573B572B571B570 186
No Input 111010 B587B586B585B584B583B582B581B580 187
No Input 111011 B597B596B595B594B593B592B591B590 188
No Input 111100 B607B606B605B604B603B602B601B600 189
No Input 111101 B617B616B615B614B613B612B611B610 190
No Input 111110 B627B626B625B624B623B622B621B620 191
No Input 111111 B637B636B635B634B633B632B631B630 192
Table 5.20: Look-up tables-6

Himax Confidential -P.79-

The HX8369-A00 can oscillate an internal R-C oscillator with an internal oscillation
resistor (Rf). The oscillation frequency is changed according to the UADJ[3:0] internal
register. Please refer to OSC control register (RB0h). The default frequency is
15MHz.

RGB Display Mode

PCLK

Display
Controller

Internal Display Mode

Oscillator
15MHz
15MHz fosc Frequency
UADJ[
UADJ[3:0] Divider 2 Step up Circuit
Clock ( for VGH,
VGH,VGL)
VGL)
FS1
FS1[1:0]

PCLK
RGB Display Mode

CABC_
CABC_PWM_
PWM_CLK
(for Backlight CABC)
CABC)

Figure 5.25: OSC aritecture

Himax Confidential -P.80-

The HX8369-A00 contains a 1440 channels of source driver (normal S1~S1440;

Zig-zag S1~S1441) which is used for driving the source line of TFT LCD panel. The
source driver converts the digital data from GRAM into the analog voltage for 1440
channels and generates corresponding gray scale voltage output, which can realize a
16.7M colors display simultaneously. Since the output circuit of this source driver
incorporates an operational amplifier, a positive and a negative voltage can be
alternately outputted from each channel.

Normal type Column inversion ZigZag type

Date Date Date Date Date Date Date Date Date Date Date Date Date
Line Line Line Line Line Line Line Line Line Line Line Line Line
#1 #2 #3 #1438 #1439 #1440 #1 #2 #3 #1438 #1439 #1440 #1441

1 2 3 1438 1439 1440 1 2 3 1438 1439 1440

... ...
Gate#1 Gate#1
1 2 3 1438 1439 1440 2 3 4 1439 1440 1441
... ...
Gate#2 Gate#2
1 2 3 1438 1439 1440 1 2 3 1438 1439 1440
... ...
Gate#3 Gate#3
1 2 3 1438 1439 1440 2 3 4 1439 1440 1441
... ...
Gate#4 Gate#4

Date Date Date Date Date Date Date Date Date Date Date Date Date
Line Line Line Line Line Line Line Line Line Line Line Line Line
#1 #2 #3 #1438 #1439 #1440 #1 #2 #3 #1438 #1439 #1440 #1441

+ - + - + - + - + - + -
... ...
Gate#1 Gate#1
+ - + - + - - + - + - +
... ...
Gate#2 Gate#2
+ - + - + - + - + - + -
... ...
Gate#3 Gate#3
+ - + - + - - + - + - +
... ...
Gate#4 Gate#4

Himax Confidential -P.81-

VGH (+14V~ +20V)

VSP, VSPC (4.7V ~ 5.5V)

VSPR(3.5V ~ (VSP-0.5V))

DC/DC
converter
VDD2, VDD3
(2.3V ~ 3.3V)

VDD1 (1.65V ~ 3.3V) DSI_VCC (1.65V ~ 3.3V)

VREF (1.8V)
VDDD (1.6V ~ 2.0V)
DSI_LDO (1.2V ~ 1.3V)
VSSD,VSSA

DC/DC
converter
VCOM(-2V ~ 0V)

VDDDN (-2.5V) VSNR (-3.5V ~ (VSN+0.5V))

VSN, VSNC
(-4.7V ~ -5.5V)

VGL(-7V~ -13.5V)

Figure 5.26: LCD power generation scheme

Himax Confidential -P.82-

5.10.1 Use PFM DC/DC converter

The PFM DC-DC converter generates the high voltage level VSP/VSN required for
source drivers. HX8369-A00 contains sub-circuits of the PFM boost converter,
including a precision 1.8V reference voltage, comparator, PFM controlling logic, and
the output buffer. The boost converter uses a external power transistor to provide
maximum efficiency and to minimize the number of external components. The output
voltage of the boost converter can be set from 4.7 to 5.5 (VSP) and -4.7 to -5.5V
(VSN)

VDD3
o
VCSW2

VSNC

VSN D2
PFM VREF L1
Controller D1
VSP
VSPC D3
VCSW1
SW1

Figure 5.27: DC/DC converter circuit (PFM Type C)–PCCS=10

Himax Confidential -P.83-

The HX5186-A is highly efficient switching voltage generator circuits that generate the
high voltage level VSP/VSN required for source drivers. HX8369-A00 contains
Charge Pump Controller for HX5186-A, including a comparator for VSP/VSN
feedback control. HX5186-A can provide maximum efficiency and use minimum
number of external components. The output voltage of the boost converter can be set
from 4.7 to 5.5 (VSP) and -4.7 to -5.5V (VSN)

Figure 5.28: DC/DC converter circuit (HX5186-A)

Himax Confidential -P.84-

The HX8369-A00 supports an idle display mode. The grayscale level to be used is V0
and V64 with R7, G7, B7 decoding, and the other levels (V1-V63) are halted to reduce
power consumption. In idle display mode, the Gamma-micro-adjustment registers are
invalid and only the upper bits of RGB are used for display.

Positive Polarity Register

Graphics
(Input data) G1_VRP0[5:0]
G1_VRP1[5:0]
G1_VRP2[5:0]

R R R R R R R R G G G G G G GG B B B B B B B B G1_VRP3[5:0]
76543210 76543210 76 543210 G1_VRP4[5:0]
G1_VRP5[5:0]
G1_PRP0[6:0]
G1_PRP1[6:0]
G1_CGMP0[1:0] G1_ PKP0[4:0]
G1_CGMP1[1:0] G1_PKP1[4:0]
G1_CGMP2[1:0] G1_PKP2[4:0]
1 1 1 G1_CGMP3[1:0] G1_PKP3[4:0]
G1_CGMP5 G1_CGMP4 G1_PKP4[4:0]
G1_PKP5[4:0]
G1_PKP6[4:0]
G1_PKP7[4:0]
V0P/V0N G1_PKP8[4:0]
8- bit Grayscale 8- bit Grayscale 8- bit Grayscale
D/ A Converter D/ A Converter
V1P/V1N Grayscale
D/ A Converter
< R> < G> Voltage
V255P/V255N Generator
Negative Polarity Register
Output Driver Output Driver Output Driver

G1_VRN0[5:0]
G1_VRN1[5:0]
G1_VRN2[5:0]
G1_VRN3[5:0]
G1_VRN4[5:0]
G1_VRN5[5:0]
R G B G1_PRN0[6:0]
G1_PRN1[6:0]
LCD G1_CGMN0[1:0] G1_ PKN0[4:0]
G1_CGMN1[1:0] G1_PKN1[4:0]
G1_CGMN2[1:0] G1_PKN2[4:0]
G1_CGMN3[1:0] G1_PKN3[4:0]
G1_CGMN5 G1_CGMN4 G1_PKN4[4:0]
G1_PKN5[4:0]
G1_PKN6[4:0]
G1_PKN7[4:0]
G1_PKN8[4:0]

Figure 5.29: Idle mode grayscale control

Himax Confidential -P.85-

The HX8369-A00 incorporates gamma adjustment function for the 16,777,216-color

display (256 grayscale for each R, G, B color). Gamma adjustment operation is
implemented by deciding the16 grayscale levels firstly in gamma adjustment control
registers to match the LCD panel. Then total 512 grayscale levels are generated in
grayscale voltage generator. These registers are available for both polarities.

Positive Polarity Register

Graphics
(Input data) G1_VRP0[5:0]
G1_VRP1[5:0]
G1_VRP2[5:0]

R R R R R R R R G G G G G G GG B B B B B B B B G1_VRP3[5:0]
76543210 76543210 76 543210 G1_VRP4[5:0]
G1_VRP5[5:0]
G1_PRP0[6:0]
G1_PRP1[6:0]
G1_CGMP0[1:0] G1_ PKP0[4:0]
G1_CGMP1[1:0] G1_PKP1[4:0]
G1_CGMP2[1:0] G1_PKP2[4:0]
8 8 8 G1_CGMP3[1:0] G1_PKP3[4:0]
G1_CGMP5 G1_CGMP4 G1_PKP4[4:0]
G1_PKP5[4:0]
G1_PKP6[4:0]
G1_PKP7[4:0]
V0P/V0N G1_PKP8[4:0]
8- bit Grayscale 8- bit Grayscale 8- bit Grayscale
D/ A Converter D/ A Converter
V1P/V1N Grayscale
D/ A Converter
< R> < G> Voltage
V255P/V255N Generator
Negative Polarity Register
Output Driver Output Driver Output Driver

Figure 5.30: Grayscale control

Himax Confidential -P.86-

This HX8369-A00 has register groups for specifying a series grayscale voltage that
meets the Gamma-characteristics for the LCD panel used. These registers are divided
into two groups, which correspond to the gradient, amplitude, and macro adjustment of
the voltage for the grayscale characteristics. The polarity of each register can be
specified independently.

(1) Offset adjustment registers

The offset adjustment variable registers are used to adjust the amplitude of the
grayscale voltage. This function is implemented by controlling these variable resisters in
the top and bottom of the gamma resister stream for reference gamma voltage
generation. These registers are available for both positive and negative polarities.

(2) Gamma center adjustment registers

The gamma center adjustment registers are used to adjust the reference gamma
voltage in the middle level of grayscale without changing the dynamic range. This
function is implemented by choosing one input of 88 to 1 selector in the gamma resister
stream for reference gamma voltage generation. These registers are available for both
positive and negative polarities.

(3) Gamma macro adjustment registers

The gamma macro adjustment registers can be used for fine adjustment of the
reference gamma voltage. This function is implemented by controlling the 32-to-1
selectors (PKP/N0~5), each of which has 5 inputs and generates one reference voltage
output (Vg(P/N)3, 7, 19, 25, 32, 38, 44, 56, 60).

Register Positive Negative

Description
Groups Polarity Polarity
Center PRP0 6-0 PRN0 6-0 Variable resistor (PRP/N0) for center adjustment
Adjustment PRP1 6-0 PRN1 6-0 Variable resistor (PRP/N1)for center adjustment
PKP0 4-0 PKN0 4-0 32-to-1 selector (voltage level of grayscale 3)
PKP1 4-0 PKN1 4-0 32-to-1 selector (voltage level of grayscale 7)
PKP2 4-0 PKN2 4-0 32-to-1 selector (voltage level of grayscale 19)
PKP3 4-0 PKN3 4-0 32-to-1 selector (voltage level of grayscale 25)
Macro 32-to-1 selector (voltage level of grayscale 32 for positive
PKP4 4-0 PKN4 4-0
Adjustment polarity and grayscale 31 for negative polarity)
PKP5 4-0 PKN5 4-0 32-to-1 selector (voltage level of grayscale 38)
PKP6 4-0 PKN6 4-0 32-to-1 selector (voltage level of grayscale 44)
PKP7 4-0 PKN7 4-0 32-to-1 selector (voltage level of grayscale 56)
PKP8 4-0 PKN8 4-0 32-to-1 selector (voltage level of grayscale 60)
VRP0 5-0 VRN0 5-0 Variable resistor (VRP/N0)for offset adjustment
VRP1 5-0 VRN1 5-0 Variable resistor (VRP/N1)for offset adjustment
Offset VRP2 5-0 VRN2 5-0 Variable resistor (VRP/N2)for offset adjustment
Adjustment VRP3 5-0 VRN3 5-0 Variable resistor (VRP/N3)for offset adjustment
VRP4 5-0 VRN4 5-0 Variable resistor (VRP/N4)for offset adjustment
VRP5 5-0 VRN5 5-0 Variable resistor (VRP/N5)for offset adjustment
Table 5.21: Gamma-Adjustment registers

Himax Confidential -P.87-

Figure 5.31: Gamma resister stream and gamma reference voltage

Himax Confidential -P.88-

CGMP/N2 0 1 2 3 CGMP/N3 0 1 2 3
V7 V50
1R 3R 4R 4.5R 1R 2.5R 2.5R 2.5R
V8 V51
1R 3R 3R 4R 1R 2.5R 2.5R 2.5R
V9 V52
1R 2.5R 3R 3R 1R 2.5R 3R 3R
V10 V53
1R 2.5R 3R 3R 1R 2.5R 3R 3R
V11 V54
1R 2.5R 2.5R 2.5R 1R 3R 3R 4R
V12 V55
1R 2.5R 2.5R 2.5R 1R 3R 4R 4.5R
V13 V56

CGMP/N4 0 1 CGMP/N5 0 1
V13 V44
1R 1.5R 1R 1R
V14 V45
1R 1R 1R 1R
V15 V46
1R 1R 1R 1R
V16 V47
1R 1R 1R 1R
V17 V48
1R 1R 1R 1R
V18 V49
1R 1R 1R 1.5R
V19 V50

Figure 5.32: Gamma resister stream

Himax Confidential -P.89-

Value in
Value in Register Resistance Value in Register Resistance Resistance
Register
VR(P/N)0 5-0 VR(P/N)0 VR(P/N)1 5-0 VR(P/N)1 VR(P/N)2
VR(P/N)2 5-0
000000 0R 000000 0R 000000 0R
000001 20R 000001 2R 000001 2R
000010 22R 000010 4R 000010 4R
000011 24R 000011 6R 000011 6R
• • • • • •
• • • • • •
011101 76R 011101 58R 011101 58R
011110 78R 011110 60R 011110 60R
011111 80R 011111 62R 011111 62R
100000 82R 100000 64R 100000 64R
100001 84R 100001 66R 100001 66R
100010 86R 100010 68R 100010 68R
• • • • • •
• • • • • •
111101 140R 111101 122R 111101 122R
111110 142R 111110 124R 111110 124R
111111 144R 111111 126R 111111 126R

Value in
Value in Register Resistance Value in Register Resistance Resistance
Register
VR(P/N)3 5-0 VR(P/N)3 VR(P/N)4 5-0 VR(P/N)4 VR(P/N)2
VR(P/N)5 5-0
000000 0R 000000 0R 000000 0R
000001 2R 000001 2R 000001 2R
000010 4R 000010 4R 000010 4R
• • • • • •
• • • • • •
011101 58R 011101 58R 011101 58R
011110 60R 011110 60R 011110 60R
011111 62R 011111 62R 011111 62R
100000 64R 100000 64R 100000 64R
100001 66R 100001 66R 100001 66R
100010 68R 100010 68R 100010 68R
• • • • • •
• • • • • •
111100 120R 111100 120R 111100 120R
111101 122R 111101 122R 111101 122R
111110 124R 111110 124R 111110 124R
111111 126R 111111 126R 111111 144R

Table 5.22: Offset adjustment 0~5

Value in Register Resistance Value in Register Resistance

PR(P/N)0 6-0 PR(P/N)0 PR(P/N)1 6-0 PR(P/N)1
0000000 0R 0000000 0R
0000001 2R 0000001 2R
0000010 4R 0000010 4R
• • • •
• • • •
1010101 170R 1010101 170R
1010110 172R 1010110 172R
1010111 174R 1010111 174R

Table 5.23: Center adjustment

Himax Confidential -P.90-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
The grayscale levels are determined by the following formulas:
Reference
Macro adjustment value VinP0 formula
voltage
VRP0 5-0 = 000000 VSPR
VRP0 5-0 = 000001 ((450R - 20R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 000010 ((450R - 22R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 000011 ((450R - 24R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 000100 ((450R - 26R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 000101 ((450R - 28R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 000110 ((450R - 30R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 000111 ((450R - 32R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 001000 ((450R - 34R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 001001 ((450R - 36R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 001010 ((450R - 38R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 001011 ((450R - 40R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 001100 ((450R - 42R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 001101 ((450R - 44R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 001110 ((450R - 46R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 001111 ((450R - 48R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 010000 ((450R - 50R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 010001 ((450R - 52R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 010010 ((450R - 54R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 010011 ((450R - 56R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 010100 ((450R - 58R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 010101 ((450R - 60R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 010110 ((450R - 62R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 010111 ((450R - 64R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 011000 ((450R - 66R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 011001 ((450R - 68R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 011010 ((450R - 70R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 011011 ((450R - 72R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 011100 ((450R - 74R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 011101 ((450R - 76R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 011110 ((450R - 78R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 011111 ((450R - 80R ) / 450R) * (VSPR - VGSP) + VGSP
VinP0
VRP0 5-0 = 100000 ((450R - 82R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 100001 ((450R - 84R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 100010 ((450R - 86R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 100011 ((450R - 88R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 100100 ((450R - 90R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 100101 ((450R - 92R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 100110 ((450R - 94R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 100111 ((450R - 96R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 101000 ((450R - 98R ) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 101001 ((450R - 100R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 101010 ((450R - 102R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 101011 ((450R - 104R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 101100 ((450R - 106R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 101101 ((450R - 108R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 101110 ((450R - 110R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 101111 ((450R - 112R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 110000 ((450R - 114R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 110001 ((450R - 116R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 110010 ((450R - 118R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 110011 ((450R - 120R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 110100 ((450R - 122R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 110101 ((450R - 124R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 110110 ((450R - 126R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 110111 ((450R - 128R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 111000 ((450R - 130R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 111001 ((450R - 132R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 111010 ((450R - 134R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 111011 ((450R - 136R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 111100 ((450R - 138R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 111101 ((450R - 140R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 111110 ((450R - 142R) / 450R) * (VSPR - VGSP) + VGSP
VRP0 5-0 = 111111 ((450R - 144R) / 450R) * (VSPR - VGSP) + VGSP
Table 5.24: VinP0
Himax Confidential -P.91-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02

Reference
Macro adjustment value VinP1 formula
voltage
VRP1 5-0 = 000000 (430R / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 000001 ((430R - 2R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 000010 ((430R - 4R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 000011 ((430R - 6R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 000100 ((430R - 8R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 000101 ((430R - 10R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 000110 ((430R - 12R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 000111 ((430R - 14R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 001000 ((430R - 16R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 001001 ((430R - 18R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 001010 ((430R - 20R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 001011 ((430R - 22R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 001100 ((430R - 24R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 001101 ((430R - 26R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 001110 ((430R - 28R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 001111 ((430R - 30R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 010000 ((430R - 32R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 010001 ((430R - 34R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 010010 ((430R - 36R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 010011 ((430R - 38R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 010100 ((430R - 40R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 010101 ((430R - 42R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 010110 ((430R - 44R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 010111 ((430R - 46R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 011000 ((430R - 48R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 011001 ((430R - 50R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 011010 ((430R - 52R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 011011 ((430R - 54R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 011100 ((430R - 56R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 011101 ((430R - 58R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 011110 ((430R - 60R ) / 450R) * (VSPR - VGSP) + VGSP
VinP1 VRP1 5-0 = 011111 ((430R - 62R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 100000 ((430R - 64R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 100001 ((430R - 66R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 100010 ((430R - 68R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 100011 ((430R - 70R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 100100 ((430R - 72R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 100101 ((430R - 74R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 100110 ((430R - 76R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 100111 ((430R - 78R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 101000 ((430R - 80R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 101001 ((430R - 82R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 101010 ((430R - 84R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 101011 ((430R - 86R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 101100 ((430R - 88R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 101101 ((430R - 90R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 101110 ((430R - 92R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 101111 ((430R - 94R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 110000 ((430R - 96R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 110001 ((430R - 98R ) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 110010 ((430R - 100R) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 110011 ((430R - 102R) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 110100 ((430R - 104R) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 110101 ((430R - 106R) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 110110 ((430R - 108R) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 110111 ((430R - 110R) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 111000 ((430R - 112R) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 111001 ((430R - 114R) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 111010 ((430R - 116R) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 111011 ((430R - 118R) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 111100 ((430R - 120R) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 111101 ((430R - 122R) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 111110 ((430R - 124R) / 450R) * (VSPR - VGSP) + VGSP
VRP1 5-0 = 111111 ((430R - 126R) / 450R) * (VSPR - VGSP) + VGSP
Table 5.25: VinP1

Himax Confidential -P.92-

Reference
Macro adjustment value VinP2 formula
voltage
VRP2 5-0 = 000000 (420R / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 000001 ((420R - 2R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 000010 ((420R - 4R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 000011 ((420R - 6R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 000100 ((420R - 8R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 000101 ((420R - 10R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 000110 ((420R - 12R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 000111 ((420R - 14R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 001000 ((420R - 16R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 001001 ((420R - 18R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 001010 ((420R - 20R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 001011 ((420R - 22R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 001100 ((420R - 24R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 001101 ((420R - 26R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 001110 ((420R - 28R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 001111 ((420R - 30R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 010000 ((420R - 32R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 010001 ((420R - 34R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 010010 ((420R - 36R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 010011 ((420R - 38R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 010100 ((420R - 40R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 010101 ((420R - 42R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 010110 ((420R - 44R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 010111 ((420R - 46R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 011000 ((420R - 48R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 011001 ((420R - 50R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 011010 ((420R - 52R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 011011 ((420R - 54R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 011100 ((420R - 56R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 011101 ((420R - 58R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 011110 ((420R - 60R ) / 450R) * (VSPR - VGSP) + VGSP
VinP2 VRP2 5-0 = 011111 ((420R - 62R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 100000 ((420R - 64R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 100001 ((420R - 66R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 100010 ((420R - 68R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 100011 ((420R - 70R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 100100 ((420R - 72R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 100101 ((420R - 74R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 100110 ((420R - 76R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 100111 ((420R - 78R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 101000 ((420R - 80R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 101001 ((420R - 82R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 101010 ((420R - 84R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 101011 ((420R - 86R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 101100 ((420R - 88R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 101101 ((420R - 90R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 101110 ((420R - 92R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 101111 ((420R - 94R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 110000 ((420R - 96R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 110001 ((420R - 98R ) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 110010 ((420R - 100R) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 110011 ((420R - 102R) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 110100 ((420R - 104R) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 110101 ((420R - 106R) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 110110 ((420R - 108R) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 110111 ((420R - 110R) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 111000 ((420R - 112R) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 111001 ((420R - 114R) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 111010 ((420R - 116R) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 111011 ((420R - 118R) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 111100 ((420R - 120R) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 111101 ((420R - 122R) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 111110 ((420R - 124R) / 450R) * (VSPR - VGSP) + VGSP
VRP2 5-0 = 111111 ((420R - 126R) / 450R) * (VSPR - VGSP) + VGSP

Table 5.26: VinP2

Himax Confidential -P.93-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
Reference
Macro adjustment value VinP14 formula
voltage
VRP3 5-0 = 000000 (156R / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 000001 ((156R - 2R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 000010 ((156R - 4R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 000011 ((156R - 6R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 000100 ((156R - 8R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 000101 ((156R - 10R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 000110 ((156R - 12R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 000111 ((156R - 14R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 001000 ((156R - 16R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 001001 ((156R - 18R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 001010 ((156R - 20R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 001011 ((156R - 22R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 001100 ((156R - 24R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 001101 ((156R - 26R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 001110 ((156R - 28R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 001111 ((156R - 30R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 010000 ((156R - 32R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 010001 ((156R - 34R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 010010 ((156R - 36R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 010011 ((156R - 38R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 010100 ((156R - 40R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 010101 ((156R - 42R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 010110 ((156R - 44R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 010111 ((156R - 46R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 011000 ((156R - 48R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 011001 ((156R - 50R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 011010 ((156R - 52R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 011011 ((156R - 54R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 011100 ((156R - 56R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 011101 ((156R - 58R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 011110 ((156R - 60R ) / 450R) * (VSPR - VGSP) + VGSP
VinP14 VRP3 5-0 = 011111 ((156R - 62R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 100000 ((156R - 64R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 100001 ((156R - 66R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 100010 ((156R - 68R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 100011 ((156R - 70R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 100100 ((156R - 72R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 100101 ((156R - 74R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 100110 ((156R - 76R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 100111 ((156R - 78R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 101000 ((156R - 80R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 101001 ((156R - 82R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 101010 ((156R - 84R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 101011 ((156R - 86R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 101100 ((156R - 88R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 101101 ((156R - 90R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 101110 ((156R - 92R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 101111 ((156R - 94R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 110000 ((156R - 96R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 110001 ((156R - 98R ) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 110010 ((156R - 100R) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 110011 ((156R - 102R) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 110100 ((156R - 104R) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 110101 ((156R - 106R) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 110110 ((156R - 108R) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 110111 ((156R - 110R) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 111000 ((156R - 112R) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 111001 ((156R - 114R) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 111010 ((156R - 116R) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 111011 ((156R - 118R) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 111100 ((156R - 120R) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 111101 ((156R - 122R) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 111110 ((156R - 124R) / 450R) * (VSPR - VGSP) + VGSP
VRP3 5-0 = 111111 ((156R - 126R) / 450R) * (VSPR - VGSP) + VGSP

Table 5.27: VinP14

Himax Confidential -P.94-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
Reference
Macro adjustment value VinP15 formula
voltage
VRP4 5-0 = 000000 (146R / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 000001 ((146R - 2R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 000010 ((146R - 4R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 000011 ((146R - 6R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 000100 ((146R - 8R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 000101 ((146R - 10R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 000110 ((146R - 12R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 000111 ((146R - 14R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 001000 ((146R - 16R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 001001 ((146R - 18R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 001010 ((146R - 20R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 001011 ((146R - 22R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 001100 ((146R - 24R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 001101 ((146R - 26R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 001110 ((146R - 28R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 001111 ((146R - 30R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 010000 ((146R - 32R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 010001 ((146R - 34R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 010010 ((146R - 36R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 010011 ((146R - 38R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 010100 ((146R - 40R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 010101 ((146R - 42R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 010110 ((146R - 44R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 010111 ((146R - 46R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 011000 ((146R - 48R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 011001 ((146R - 50R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 011010 ((146R - 52R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 011011 ((146R - 54R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 011100 ((146R - 56R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 011101 ((146R - 58R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 011110 ((146R - 60R ) / 450R) * (VSPR - VGSP) + VGSP
VinP15 VRP4 5-0 = 011111 ((146R - 62R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 100000 ((146R - 64R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 100001 ((146R - 66R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 100010 ((146R - 68R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 100011 ((146R - 70R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 100100 ((146R - 72R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 100101 ((146R - 74R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 100110 ((146R - 76R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 100111 ((146R - 78R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 101000 ((146R - 80R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 101001 ((146R - 82R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 101010 ((146R - 84R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 101011 ((146R - 86R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 101100 ((146R - 88R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 101101 ((146R - 90R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 101110 ((146R - 92R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 101111 ((146R - 94R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 110000 ((146R - 96R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 110001 ((146R - 98R ) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 110010 ((146R - 100R) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 110011 ((146R - 102R) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 110100 ((146R - 104R) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 110101 ((146R - 106R) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 110110 ((146R - 108R) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 110111 ((146R - 110R) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 111000 ((146R - 112R) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 111001 ((146R - 114R) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 111010 ((146R - 116R) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 111011 ((146R - 118R) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 111100 ((146R - 120R) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 111101 ((146R - 122R) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 111110 ((146R - 124R) / 450R) * (VSPR - VGSP) + VGSP
VRP4 5-0 = 111111 ((146R - 126R) / 450R) * (VSPR - VGSP) + VGSP

Table 5.28: VinP15

Himax Confidential -P.95-

Reference
Macro adjustment value VinP16 formula
voltage
VRP5 5-0 = 000000 (144R / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 000001 ((144R - 2R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 000010 ((144R - 4R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 000011 ((144R - 6R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 000100 ((144R - 8R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 000101 ((144R - 10R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 000110 ((144R - 12R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 000111 ((144R - 14R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 001000 ((144R - 16R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 001001 ((144R - 18R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 001010 ((144R - 20R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 001011 ((144R - 22R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 001100 ((144R - 24R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 001101 ((144R - 26R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 001110 ((144R - 28R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 001111 ((144R - 30R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 010000 ((144R - 32R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 010001 ((144R - 34R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 010010 ((144R - 36R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 010011 ((144R - 38R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 010100 ((144R - 40R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 010101 ((144R - 42R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 010110 ((144R - 44R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 010111 ((144R - 46R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 011000 ((144R - 48R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 011001 ((144R - 50R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 011010 ((144R - 52R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 011011 ((144R - 54R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 011100 ((144R - 56R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 011101 ((144R - 58R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 011110 ((144R - 60R ) / 450R) * (VSPR - VGSP) + VGSP
VinP16 VRP5 5-0 = 011111 ((144R - 62R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 100000 ((144R - 64R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 100001 ((144R - 66R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 100010 ((144R - 68R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 100011 ((144R - 70R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 100100 ((144R - 72R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 100101 ((144R - 74R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 100110 ((144R - 76R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 100111 ((144R - 78R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 101000 ((144R - 80R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 101001 ((144R - 82R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 101010 ((144R - 84R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 101011 ((144R - 86R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 101100 ((144R - 88R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 101101 ((144R - 90R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 101110 ((144R - 92R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 101111 ((144R - 94R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 110000 ((144R - 96R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 110001 ((144R - 98R ) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 110010 ((144R - 100R) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 110011 ((144R - 102R) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 110100 ((144R - 104R) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 110101 ((144R - 106R) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 110110 ((144R - 108R) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 110111 ((144R - 110R) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 111000 ((144R - 112R) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 111001 ((144R - 114R) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 111010 ((144R - 116R) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 111011 ((144R - 118R) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 111100 ((144R - 120R) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 111101 ((144R - 122R) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 111110 ((144R - 124R) / 450R) * (VSPR - VGSP) + VGSP
VRP5 5-0 = 111111 VGSP

Table 5.29: VinP16

Himax Confidential -P.96-

Reference
Macro adjustment value VinP5 formula
voltage
VinP5 PRP0 6-0 = 0000000 (350R / 450R) (VSPR - VGSP) + VGSP
PRP0 6-0 = 0000001 ((350R - 2R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0000010 ((350R - 4R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0000011 ((350R – 6R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0000100 ((350R – 8R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0000101 ((350R – 10R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0000110 ((350R – 12R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0000111 ((350R - 14R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0001000 ((350R – 16R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0001001 ((350R – 18R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0001010 ((350R – 20R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0001011 ((350R – 22R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0001100 ((350R – 24R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0001101 ((350R – 26R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0001110 ((350R – 28R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0001111 ((350R – 30R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0010000 ((350R – 32R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0010001 ((350R - 34R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0010010 ((350R – 36R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0010011 ((350R – 38R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0010100 ((350R – 40R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0010101 ((350R – 42R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0010110 ((350R – 44R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0010111 ((350R – 46R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0011000 ((350R – 48R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0011001 ((350R – 50R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0011010 ((350R – 52R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0011011 ((350R - 54R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0011100 ((350R – 56R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0011101 ((350R – 58R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0011110 ((350R – 60R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0011111 ((350R – 62R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0100000 ((350R - 64R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0100001 ((350R – 66R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0100010 ((350R – 68R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0100011 ((350R – 70R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0100100 ((350R – 72R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0100101 ((350R – 74R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0100110 ((350R – 76R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0100111 ((350R – 78R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0101000 ((350R – 80R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0101001 ((350R – 82R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0101010 ((350R - 84R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0101011 ((350R – 86R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0101100 ((350R – 88R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0101101 ((350R – 90R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0101110 ((350R – 92R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0101111 ((350R – 94R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0110000 ((350R – 96R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0110001 ((350R – 98R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0110010 ((350R – 100R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0110011 ((350R – 102R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0110100 ((350R – 104R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0110101 ((350R – 106R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0110110 ((350R – 108R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0110111 ((350R – 110R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0111000 ((350R – 112R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0111001 ((350R – 114R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0111010 ((350R – 116R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0111011 ((350R – 118R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0111100 ((350R – 120R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0111101 ((350R – 122R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0111110 ((350R - 124R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 0111111 ((350R – 126R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1000000 ((350R – 128R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1000001 ((350R – 130R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1000010 ((350R - 132R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1000011 ((350R – 134R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1000100 ((350R – 136R) / 450R) * (VSPR - VGSP) + VGSP
Himax Confidential -P.97-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
PRP0 6-0 = 1000101 ((350R – 138R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1000110 ((350R – 140R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1000111 ((350R – 142R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1001000 ((350R – 144R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1001001 ((350R – 146R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1001010 ((350R – 148R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1001011 ((350R – 150R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1001100 ((350R - 152R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1001101 ((350R – 154R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1001110 ((350R – 156R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1001111 ((350R – 158R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1010000 ((350R – 160R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1010001 ((350R – 162R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1010010 ((350R – 164R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1010011 ((350R – 166R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1010100 ((350R – 168R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1010101 ((350R – 170R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1010110 ((350R – 172R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1010111 ((350R - 174R) / 450R) * (VSPR - VGSP) + VGSP
PRP0 6-0 = 1011000 inhibit
PRP0 6-0 = 1011001 inhibit
PRP0 6-0 = 1011010 inhibit
PRP0 6-0 = 1011011 inhibit
PRP0 6-0 = 1011100 inhibit
PRP0 6-0 = 1011101 inhibit
PRP0 6-0 = 1011110 inhibit
PRP0 6-0 = 1011111 inhibit
PRP0 6-0 = 1100000 inhibit
PRP0 6-0 = 1100001 inhibit
PRP0 6-0 = 1100010 inhibit
PRP0 6-0 = 1100011 inhibit
PRP0 6-0 = 1100100 inhibit
PRP0 6-0 = 1100101 inhibit
PRP0 6-0 = 1100110 inhibit
PRP0 6-0 = 1100111 inhibit
PRP0 6-0 = 1101000 inhibit
PRP0 6-0 = 1101001 inhibit
PRP0 6-0 = 1101010 inhibit
PRP0 6-0 = 1101011 inhibit
PRP0 6-0 = 1101100 inhibit
PRP0 6-0 = 1101101 inhibit
PRP0 6-0 = 1101110 inhibit
PRP0 6-0 = 1101111 inhibit
PRP0 6-0 = 1110000 inhibit
PRP0 6-0 = 1110001 inhibit
PRP0 6-0 = 1110010 inhibit
PRP0 6-0 = 1110011 inhibit
PRP0 6-0 = 1110100 inhibit
PRP0 6-0 = 1110101 inhibit
PRP0 6-0 = 1110110 inhibit
PRP0 6-0 = 1110111 inhibit
PRP0 6-0 = 1111000 inhibit
PRP0 6-0 = 1111001 inhibit
PRP0 6-0 = 1111010 inhibit
PRP0 6-0 = 1111011 inhibit
PRP0 6-0 = 1111100 inhibit
PRP0 6-0 = 1111101 inhibit
PRP0 6-0 = 1111110 inhibit
PRP0 6-0 = 1111111 inhibit
Table 5.30: VinP5

Himax Confidential -P.98-

Reference
Macro adjustment value VinP11 formula
voltage
VinP11 PRP1 6-0 = 0000000 (274R / 450R) (VSPR - VGSP) + VGSP
PRP1 6-0 = 0000001 ((274R - 2R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0000010 ((274R - 4R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0000011 ((274R – 6R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0000100 ((274R – 8R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0000101 ((274R – 10R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0000110 ((274R – 12R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0000111 ((274R - 14R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0001000 ((274R – 16R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0001001 ((274R – 18R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0001010 ((274R – 20R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0001011 ((274R – 22R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0001100 ((274R – 24R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0001101 ((274R – 26R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0001110 ((274R – 28R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0001111 ((274R – 30R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0010000 ((274R – 32R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0010001 ((274R - 34R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0010010 ((274R – 36R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0010011 ((274R – 38R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0010100 ((274R – 40R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0010101 ((274R – 42R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0010110 ((274R – 44R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0010111 ((274R – 46R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0011000 ((274R – 48R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0011001 ((274R – 50R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0011010 ((274R – 52R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0011011 ((274R - 54R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0011100 ((274R – 56R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0011101 ((274R – 58R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0011110 ((274R – 60R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0011111 ((274R – 62R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0100000 ((274R - 64R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0100001 ((274R – 66R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0100010 ((274R – 68R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0100011 ((274R – 70R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0100100 ((274R – 72R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0100101 ((274R – 74R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0100110 ((274R – 76R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0100111 ((274R – 78R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0101000 ((274R – 80R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0101001 ((274R – 82R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0101010 ((274R - 84R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0101011 ((274R – 86R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0101100 ((274R – 88R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0101101 ((274R – 90R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0101110 ((274R – 92R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0101111 ((274R – 94R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0110000 ((274R – 96R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0110001 ((274R – 98R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0110010 ((274R – 100R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0110011 ((274R – 102R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0110100 ((274R – 104R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0110101 ((274R – 106R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0110110 ((274R – 108R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0110111 ((274R – 110R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0111000 ((274R – 112R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0111001 ((274R – 114R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0111010 ((274R – 116R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0111011 ((274R – 118R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0111100 ((274R – 120R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0111101 ((274R – 122R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0111110 ((274R - 124R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 0111111 ((274R – 126R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1000000 ((274R – 128R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1000001 ((274R – 130R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1000010 ((274R - 132R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1000011 ((274R – 134R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1000100 ((274R – 136R) / 450R) * (VSPR - VGSP) + VGSP
Himax Confidential -P.99-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
PRP1 6-0 = 1000101 ((274R – 138R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1000110 ((274R – 140R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1000111 ((274R – 142R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1001000 ((274R – 144R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1001001 ((274R – 146R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1001010 ((274R – 148R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1001011 ((274R – 150R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1001100 ((274R - 152R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1001101 ((274R – 154R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1001110 ((274R – 156R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1001111 ((274R – 158R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1010000 ((274R – 160R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1010001 ((274R – 162R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1010010 ((274R – 164R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1010011 ((274R – 166R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1010100 ((274R – 168R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1010101 ((274R – 170R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1010110 ((274R – 172R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1010111 ((274R - 174R) / 450R) * (VSPR - VGSP) + VGSP
PRP1 6-0 = 1011000 inhibit
PRP1 6-0 = 1011001 inhibit
PRP1 6-0 = 1011010 inhibit
PRP1 6-0 = 1011011 inhibit
PRP1 6-0 = 1011100 inhibit
PRP1 6-0 = 1011101 inhibit
PRP1 6-0 = 1011110 inhibit
PRP1 6-0 = 1011111 inhibit
PRP1 6-0 = 1100000 inhibit
PRP1 6-0 = 1100001 inhibit
PRP1 6-0 = 1100010 inhibit
PRP1 6-0 = 1100011 inhibit
PRP1 6-0 = 1100100 inhibit
PRP1 6-0 = 1100101 inhibit
PRP1 6-0 = 1100110 inhibit
PRP1 6-0 = 1100111 inhibit
PRP1 6-0 = 1101000 inhibit
PRP1 6-0 = 1101001 inhibit
PRP1 6-0 = 1101010 inhibit
PRP1 6-0 = 1101011 inhibit
PRP1 6-0 = 1101100 inhibit
PRP1 6-0 = 1101101 inhibit
PRP1 6-0 = 1101110 inhibit
PRP1 6-0 = 1101111 inhibit
PRP1 6-0 = 1110000 inhibit
PRP1 6-0 = 1110001 inhibit
PRP1 6-0 = 1110010 inhibit
PRP1 6-0 = 1110011 inhibit
PRP1 6-0 = 1110100 inhibit
PRP1 6-0 = 1110101 inhibit
PRP1 6-0 = 1110110 inhibit
PRP1 6-0 = 1110111 inhibit
PRP1 6-0 = 1111000 inhibit
PRP1 6-0 = 1111001 inhibit
PRP1 6-0 = 1111010 inhibit
PRP1 6-0 = 1111011 inhibit
PRP1 6-0 = 1111100 inhibit
PRP1 6-0 = 1111101 inhibit
PRP1 6-0 = 1111110 inhibit
PRP1 6-0 = 1111111 inhibit
Table 5.31: VinP11

Himax Confidential -P.100-

Reference
Macro adjustment value VinP3 formula
voltage
PKP0 4-0 = 00000 (47R / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 00001 ((47R – 1R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 00010 ((47R – 2R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 00011 ((47R – 3R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 00100 ((47R – 4R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 00101 ((47R – 5R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 00110 ((47R – 6R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 00111 ((47R – 7R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 01000 ((47R – 8R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 01001 ((47R – 9R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 01010 ((47R - 10R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 01011 ((47R - 11R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 01100 ((47R - 12R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 01101 ((47R - 13R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 01110 ((47R - 14R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 01111 ((47R - 15R) / 48R) * (VinP2 - VinP5) + VinP5
VinP3
PKP0 4-0 = 10000 ((47R - 16R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 10001 ((47R - 17R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 10010 ((47R - 18R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 10011 ((47R - 19R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 10100 ((47R - 20R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 10101 ((47R - 21R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 10110 ((47R - 22R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 10111 ((47R - 23R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 11000 ((47R - 24R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 11001 ((47R - 25R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 11010 ((47R - 26R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 11011 ((47R - 27R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 11100 ((47R - 28R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 11101 ((47R - 29R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 11110 ((47R - 30R) / 48R) * (VinP2 - VinP5) + VinP5
PKP0 4-0 = 11111 ((47R - 31R) / 48R) * (VinP2 - VinP5) + VinP5
Table 5.32: VinP3

Himax Confidential -P.101-

Reference
Macro adjustment value VinP6 formula
voltage
PKP2 4-0 = 00000 (220R / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 00001 ((220R - 3R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 00010 ((220R - 6R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 00011 ((220R - 9R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 00100 ((220R - 12R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 00101 ((220R - 15R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 00110 ((220R - 18R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 00111 ((220R - 21R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 01000 ((220R - 24R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 01001 ((220R - 27R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 01010 ((220R - 30R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 01011 ((220R - 33R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 01100 ((220R - 36R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 01101 ((220R - 39R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 01110 ((220R - 42R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 01111 ((220R - 45R) / 223R) * (VinP5 - VinP11) + VinP11
VinP6
PKP2 4-0 = 10000 ((220R - 48R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 10001 ((220R - 51R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 10010 ((220R - 54R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 10011 ((220R - 57R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 10100 ((220R - 60R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 10101 ((220R - 63R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 10110 ((220R - 66R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 10111 ((220R - 69R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 11000 ((220R - 72R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 11001 ((220R - 75R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 11010 ((220R - 78R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 11011 ((220R - 81R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 11100 ((220R - 84R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 11101 ((220R - 87R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 11110 ((220R - 90R) / 223R) * (VinP5 - VinP11) + VinP11
PKP2 4-0 = 11111 ((220R - 93R) / 223R) * (VinP5 - VinP11) + VinP11
Table 5.34: VinP6
Himax Confidential -P.102-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
Reference
Macro adjustment value VinP7 formula
voltage
PKP3 4-0 = 00000 (193R / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 00001 ((193R - 3R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 00010 ((193R - 6R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 00011 ((193R - 9R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 00100 ((193R - 12R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 00101 ((193R - 15R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 00110 ((193R - 18R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 00111 ((193R - 21R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 01000 ((193R - 24R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 01001 ((193R - 27R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 01010 ((193R - 30R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 01011 ((193R - 33R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 01100 ((193R - 36R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 01101 ((193R - 39R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 01110 ((193R - 42R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 01111 ((193R - 45R) / 223R) * (VinP5 - VinP11) + VinP11
VinP7
PKP3 4-0 = 10000 ((193R - 48R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 10001 ((193R - 51R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 10010 ((193R - 54R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 10011 ((193R - 57R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 10100 ((193R - 60R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 10101 ((193R - 63R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 10110 ((193R - 66R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 10111 ((193R - 69R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 11000 ((193R - 72R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 11001 ((193R - 75R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 11010 ((193R - 78R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 11011 ((193R - 81R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 11100 ((193R - 84R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 11101 ((193R - 87R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 11110 ((193R - 90R) / 223R) * (VinP5 - VinP11) + VinP11
PKP3 4-0 = 11111 ((193R - 93R) / 223R) * (VinP5 - VinP11) + VinP11
Table 5.35: VinP7

Reference
Macro adjustment value VinP8 formula
voltage
PKP4 4-0 = 00000 (158R / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 00001 ((158R - 3R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 00010 ((158R - 6R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 00011 ((158R - 9R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 00100 ((158R - 12R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 00101 ((158R - 15R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 00110 ((158R - 18R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 00111 ((158R - 21R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 01000 ((158R - 24R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 01001 ((158R - 27R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 01010 ((158R - 30R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 01011 ((158R - 33R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 01100 ((158R - 36R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 01101 ((158R - 39R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 01110 ((158R - 42R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 01111 ((158R - 45R) / 223R) * (VinP5 - VinP11) + VinP11
VinP8
PKP4 4-0 = 10000 ((158R - 48R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 10001 ((158R - 51R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 10010 ((158R - 54R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 10011 ((158R - 57R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 10100 ((158R - 60R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 10101 ((158R - 63R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 10110 ((158R - 66R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 10111 ((158R - 69R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 11000 ((158R - 72R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 11001 ((158R - 75R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 11010 ((158R - 78R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 11011 ((158R - 81R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 11100 ((158R - 84R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 11101 ((158R - 87R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 11110 ((158R - 90R) / 223R) * (VinP5 - VinP11) + VinP11
PKP4 4-0 = 11111 ((158R - 93R) / 223R) * (VinP5 - VinP11) + VinP11
Table 5.36: VinP8
Himax Confidential -P.103-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
Reference
Macro adjustment value VinP9 formula
voltage
PKP5 4-0 = 00000 (123R / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 00001 ((123R - 3R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 00010 ((123R - 6R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 00011 ((123R - 9R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 00100 ((123R - 12R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 00101 ((123R - 15R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 00110 ((123R - 18R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 00111 ((123R - 21R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 01000 ((123R - 24R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 01001 ((123R - 27R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 01010 ((123R - 30R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 01011 ((123R - 33R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 01100 ((123R - 36R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 01101 ((123R - 39R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 01110 ((123R - 42R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 01111 ((123R - 45R) / 223R) * (VinP5 - VinP11) + VinP11
VinP9
PKP5 4-0 = 10000 ((123R - 48R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 10001 ((123R - 51R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 10010 ((123R - 54R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 10011 ((123R - 57R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 10100 ((123R - 60R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 10101 ((123R - 63R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 10110 ((123R - 66R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 10111 ((123R - 69R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 11000 ((123R - 72R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 11001 ((123R - 75R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 11010 ((123R - 78R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 11011 ((123R - 81R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 11100 ((123R - 84R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 11101 ((123R - 87R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 11110 ((123R - 90R) / 223R) * (VinP5 - VinP11) + VinP11
PKP5 4-0 = 11111 ((123R - 93R) / 223R) * (VinP5 - VinP11) + VinP11
Table 5.37: VinP9

Reference
Macro adjustment value VinP10 formula
voltage
PKP6 4-0 = 00000 (96R / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 00001 ((96R - 3R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 00010 ((96R - 6R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 00011 ((96R - 9R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 00100 ((96R - 12R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 00101 ((96R - 15R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 00110 ((96R - 18R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 00111 ((96R - 21R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 01000 ((96R - 24R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 01001 ((96R - 27R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 01010 ((96R - 30R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 01011 ((96R - 33R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 01100 ((96R - 36R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 01101 ((96R - 39R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 01110 ((96R - 42R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 01111 ((96R - 45R) / 223R) * (VinP5 - VinP11) + VinP11
VinP10
PKP6 4-0 = 10000 ((96R - 48R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 10001 ((96R - 51R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 10010 ((96R - 54R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 10011 ((96R - 57R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 10100 ((96R - 60R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 10101 ((96R - 63R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 10110 ((96R - 66R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 10111 ((96R - 69R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 11000 ((96R - 72R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 11001 ((96R - 75R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 11010 ((96R - 78R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 11011 ((96R - 81R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 11100 ((96R - 84R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 11101 ((96R - 87R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 11110 ((96R - 90R) / 223R) * (VinP5 - VinP11) + VinP11
PKP6 4-0 = 11111 ((96R - 93R) / 223R) * (VinP5 - VinP11) + VinP11
Table 5.38: VinP10
Himax Confidential -P.104-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
Reference
Macro adjustment value VinP12 formula
voltage
PKP7 4-0 = 00000 (47R / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 00001 ((47R - 1R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 00010 ((47R - 2R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 00011 ((47R - 3R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 00100 ((47R - 4R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 00101 ((47R - 5R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 00110 ((47R - 6R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 00111 ((47R - 7R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 01000 ((47R - 8R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 01001 ((47R - 9R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 01010 ((47R - 10R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 01011 ((47R - 11R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 01100 ((47R - 12R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 01101 ((47R - 13R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 01110 ((47R - 14R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 01111 ((47R - 15R) / 48R) * (VinP11 - VinP14) + VinP14
VinP12
PKP7 4-0 = 10000 ((47R - 16R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 10001 ((47R - 17R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 10010 ((47R - 18R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 10011 ((47R - 19R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 10100 ((47R - 20R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 10101 ((47R - 21R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 10110 ((47R - 22R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 10111 ((47R - 23R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 11000 ((47R - 24R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 11001 ((47R - 25R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 11010 ((47R - 26R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 11011 ((47R - 27R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 11100 ((47R - 28R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 11101 ((47R - 29R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 11110 ((47R - 30R) / 48R) * (VinP11 - VinP14) + VinP14
PKP7 4-0 = 11111 ((47R - 31R) / 48R) * (VinP11 - VinP14) + VinP14
Table 5.39: VinP12

Reference
Macro adjustment value VinP13 formula
voltage
PKP8 4-0 = 00000 (32R / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 00001 ((32R - 1R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 00010 ((32R - 2R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 00011 ((32R - 3R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 00100 ((32R - 4R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 00101 ((32R - 5R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 00110 ((32R - 6R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 00111 ((32R - 7R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 01000 ((32R - 8R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 01001 ((32R - 9R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 01010 ((32R - 10R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 01011 ((32R - 11R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 01100 ((32R - 12R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 01101 ((32R - 13R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 01110 ((32R - 14R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 01111 ((32R - 15R) / 48R) * (VinP11 - VinP14) + VinP14
VinP13
PKP8 4-0 = 10000 ((32R - 16R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 10001 ((32R - 17R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 10010 ((32R - 18R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 10011 ((32R - 19R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 10100 ((32R - 20R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 10101 ((32R - 21R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 10110 ((32R - 22R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 10111 ((32R - 23R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 11000 ((32R - 24R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 11001 ((32R - 25R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 11010 ((32R - 26R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 11011 ((32R - 27R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 11100 ((32R - 28R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 11101 ((32R - 29R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 11110 ((32R - 30R) / 48R) * (VinP11 - VinP14) + VinP14
PKP8 4-0 = 11111 ((32R - 31R) / 48R) * (VinP11 - VinP14) + VinP14
Table 5.40: VinP13
Himax Confidential -P.105-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02

Reference
Macro adjustment value VinN0 formula
voltage
VRN0 5-0 = 000000 VSNR
VRN0 5-0 = 000001 ((450R - 20R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 000010 ((450R - 22R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 000011 ((450R - 24R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 000100 ((450R - 26R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 000101 ((450R - 28R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 000110 ((450R - 30R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 000111 ((450R - 32R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 001000 ((450R - 34R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 001001 ((450R - 36R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 001010 ((450R - 38R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 001011 ((450R - 40R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 001100 ((450R - 42R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 001101 ((450R - 44R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 001110 ((450R - 46R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 001111 ((450R - 48R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 010000 ((450R - 50R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 010001 ((450R - 52R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 010010 ((450R - 54R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 010011 ((450R - 56R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 010100 ((450R - 58R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 010101 ((450R - 60R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 010110 ((450R - 62R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 010111 ((450R - 64R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 011000 ((450R - 66R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 011001 ((450R - 68R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 011010 ((450R - 70R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 011011 ((450R - 72R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 011100 ((450R - 74R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 011101 ((450R - 76R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 011110 ((450R - 78R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 011111 ((450R - 80R ) / 450R) * (VSNR - VGSN) + VGSN
VinN0
VRN0 5-0 = 100000 ((450R - 82R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 100001 ((450R - 84R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 100010 ((450R - 86R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 100011 ((450R - 88R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 100100 ((450R - 90R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 100101 ((450R - 92R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 100110 ((450R - 94R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 100111 ((450R - 96R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 101000 ((450R - 98R ) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 101001 ((450R - 100R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 101010 ((450R - 102R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 101011 ((450R - 104R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 101100 ((450R - 106R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 101101 ((450R - 108R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 101110 ((450R - 110R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 101111 ((450R - 112R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 110000 ((450R - 114R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 110001 ((450R - 116R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 110010 ((450R - 118R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 110011 ((450R - 120R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 110100 ((450R - 122R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 110101 ((450R - 124R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 110110 ((450R - 126R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 110111 ((450R - 128R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 111000 ((450R - 130R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 111001 ((450R - 132R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 111010 ((450R - 134R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 111011 ((450R - 136R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 111100 ((450R - 138R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 111101 ((450R - 140R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 111110 ((450R - 142R) / 450R) * (VSNR - VGSN) + VGSN
VRN0 5-0 = 111111 ((450R - 144R) / 450R) * (VSNR - VGSN) + VGSN
Table 5.41: VinN0

Himax Confidential -P.106-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
Reference
Macro adjustment value VinN1 formula
voltage
VRN1 5-0 = 000000 (430R / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 000001 ((430R - 2R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 000010 ((430R - 4R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 000011 ((430R - 6R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 000100 ((430R - 8R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 000101 ((430R - 10R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 000110 ((430R - 12R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 000111 ((430R - 14R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 001000 ((430R - 16R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 001001 ((430R - 18R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 001010 ((430R - 20R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 001011 ((430R - 22R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 001100 ((430R - 24R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 001101 ((430R - 26R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 001110 ((430R - 28R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 001111 ((430R - 30R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 010000 ((430R - 32R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 010001 ((430R - 34R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 010010 ((430R - 36R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 010011 ((430R - 38R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 010100 ((430R - 40R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 010101 ((430R - 42R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 010110 ((430R - 44R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 010111 ((430R - 46R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 011000 ((430R - 48R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 011001 ((430R - 50R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 011010 ((430R - 52R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 011011 ((430R - 54R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 011100 ((430R - 56R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 011101 ((430R - 58R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 011110 ((430R - 60R ) / 450R) * (VSNR - VGSN) + VGSN
VinN1 VRN1 5-0 = 011111 ((430R - 62R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 100000 ((430R - 64R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 100001 ((430R - 66R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 100010 ((430R - 68R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 100011 ((430R - 70R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 100100 ((430R - 72R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 100101 ((430R - 74R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 100110 ((430R - 76R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 100111 ((430R - 78R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 101000 ((430R - 80R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 101001 ((430R - 82R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 101010 ((430R - 84R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 101011 ((430R - 86R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 101100 ((430R - 88R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 101101 ((430R - 90R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 101110 ((430R - 92R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 101111 ((430R - 94R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 110000 ((430R - 96R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 110001 ((430R - 98R ) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 110010 ((430R - 100R) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 110011 ((430R - 102R) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 110100 ((430R - 104R) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 110101 ((430R - 106R) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 110110 ((430R - 108R) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 110111 ((430R - 110R) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 111000 ((430R - 112R) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 111001 ((430R - 114R) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 111010 ((430R - 116R) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 111011 ((430R - 118R) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 111100 ((430R - 120R) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 111101 ((430R - 122R) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 111110 ((430R - 124R) / 450R) * (VSNR - VGSN) + VGSN
VRN1 5-0 = 111111 ((430R - 126R) / 450R) * (VSNR - VGSN) + VGSN
Table 5.42: VinN1

Himax Confidential -P.107-

Reference
Macro adjustment value VinN2 formula
voltage
VRN2 5-0 = 000000 (420R / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 000001 ((420R - 2R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 000010 ((420R - 4R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 000011 ((420R - 6R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 000100 ((420R - 8R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 000101 ((420R - 10R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 000110 ((420R - 12R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 000111 ((420R - 14R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 001000 ((420R - 16R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 001001 ((420R - 18R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 001010 ((420R - 20R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 001011 ((420R - 22R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 001100 ((420R - 24R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 001101 ((420R - 26R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 001110 ((420R - 28R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 001111 ((420R - 30R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 010000 ((420R - 32R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 010001 ((420R - 34R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 010010 ((420R - 36R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 010011 ((420R - 38R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 010100 ((420R - 40R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 010101 ((420R - 42R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 010110 ((420R - 44R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 010111 ((420R - 46R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 011000 ((420R - 48R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 011001 ((420R - 50R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 011010 ((420R - 52R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 011011 ((420R - 54R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 011100 ((420R - 56R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 011101 ((420R - 58R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 011110 ((420R - 60R ) / 450R) * (VSNR - VGSN) + VGSN
VinN2 VRN2 5-0 = 011111 ((420R - 62R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 100000 ((420R - 64R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 100001 ((420R - 66R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 100010 ((420R - 68R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 100011 ((420R - 70R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 100100 ((420R - 72R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 100101 ((420R - 74R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 100110 ((420R - 76R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 100111 ((420R - 78R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 101000 ((420R - 80R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 101001 ((420R - 82R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 101010 ((420R - 84R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 101011 ((420R - 86R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 101100 ((420R - 88R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 101101 ((420R - 90R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 101110 ((420R - 92R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 101111 ((420R - 94R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 110000 ((420R - 96R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 110001 ((420R - 98R ) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 110010 ((420R - 100R) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 110011 ((420R - 102R) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 110100 ((420R - 104R) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 110101 ((420R - 106R) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 110110 ((420R - 108R) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 110111 ((420R - 110R) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 111000 ((420R - 112R) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 111001 ((420R - 114R) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 111010 ((420R - 116R) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 111011 ((420R - 118R) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 111100 ((420R - 120R) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 111101 ((420R - 122R) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 111110 ((420R - 124R) / 450R) * (VSNR - VGSN) + VGSN
VRN2 5-0 = 111111 ((420R - 126R) / 450R) * (VSNR - VGSN) + VGSN

Table 5.43: VinN2

Himax Confidential -P.108-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
Reference
Macro adjustment value VinN14 formula
voltage
VRN3 5-0 = 000000 (156R / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 000001 ((156R - 2R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 000010 ((156R - 4R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 000011 ((156R - 6R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 000100 ((156R - 8R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 000101 ((156R - 10R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 000110 ((156R - 12R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 000111 ((156R - 14R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 001000 ((156R - 16R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 001001 ((156R - 18R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 001010 ((156R - 20R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 001011 ((156R - 22R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 001100 ((156R - 24R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 001101 ((156R - 26R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 001110 ((156R - 28R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 001111 ((156R - 30R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 010000 ((156R - 32R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 010001 ((156R - 34R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 010010 ((156R - 36R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 010011 ((156R - 38R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 010100 ((156R - 40R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 010101 ((156R - 42R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 010110 ((156R - 44R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 010111 ((156R - 46R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 011000 ((156R - 48R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 011001 ((156R - 50R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 011010 ((156R - 52R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 011011 ((156R - 54R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 011100 ((156R - 56R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 011101 ((156R - 58R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 011110 ((156R - 60R ) / 450R) * (VSNR - VGSN) + VGSN
VinN14 VRN3 5-0 = 011111 ((156R - 62R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 100000 ((156R - 64R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 100001 ((156R - 66R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 100010 ((156R - 68R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 100011 ((156R - 70R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 100100 ((156R - 72R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 100101 ((156R - 74R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 100110 ((156R - 76R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 100111 ((156R - 78R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 101000 ((156R - 80R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 101001 ((156R - 82R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 101010 ((156R - 84R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 101011 ((156R - 86R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 101100 ((156R - 88R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 101101 ((156R - 90R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 101110 ((156R - 92R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 101111 ((156R - 94R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 110000 ((156R - 96R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 110001 ((156R - 98R ) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 110010 ((156R - 100R) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 110011 ((156R - 102R) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 110100 ((156R - 104R) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 110101 ((156R - 106R) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 110110 ((156R - 108R) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 110111 ((156R - 110R) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 111000 ((156R - 112R) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 111001 ((156R - 114R) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 111010 ((156R - 116R) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 111011 ((156R - 118R) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 111100 ((156R - 120R) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 111101 ((156R - 122R) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 111110 ((156R - 124R) / 450R) * (VSNR - VGSN) + VGSN
VRN3 5-0 = 111111 ((156R - 126R) / 450R) * (VSNR - VGSN) + VGSN

Table 5.44: VinN14

Himax Confidential -P.109-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
Reference
Macro adjustment value VinN15 formula
voltage
VRN4 5-0 = 000000 (146R / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 000001 ((146R - 2R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 000010 ((146R - 4R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 000011 ((146R - 6R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 000100 ((146R - 8R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 000101 ((146R - 10R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 000110 ((146R - 12R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 000111 ((146R - 14R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 001000 ((146R - 16R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 001001 ((146R - 18R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 001010 ((146R - 20R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 001011 ((146R - 22R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 001100 ((146R - 24R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 001101 ((146R - 26R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 001110 ((146R - 28R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 001111 ((146R - 30R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 010000 ((146R - 32R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 010001 ((146R - 34R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 010010 ((146R - 36R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 010011 ((146R - 38R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 010100 ((146R - 40R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 010101 ((146R - 42R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 010110 ((146R - 44R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 010111 ((146R - 46R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 011000 ((146R - 48R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 011001 ((146R - 50R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 011010 ((146R - 52R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 011011 ((146R - 54R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 011100 ((146R - 56R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 011101 ((146R - 58R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 011110 ((146R - 60R ) / 450R) * (VSNR - VGSN) + VGSN
VinN15 VRN4 5-0 = 011111 ((146R - 62R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 100000 ((146R - 64R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 100001 ((146R - 66R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 100010 ((146R - 68R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 100011 ((146R - 70R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 100100 ((146R - 72R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 100101 ((146R - 74R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 100110 ((146R - 76R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 100111 ((146R - 78R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 101000 ((146R - 80R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 101001 ((146R - 82R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 101010 ((146R - 84R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 101011 ((146R - 86R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 101100 ((146R - 88R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 101101 ((146R - 90R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 101110 ((146R - 92R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 101111 ((146R - 94R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 110000 ((146R - 96R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 110001 ((146R - 98R ) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 110010 ((146R - 100R) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 110011 ((146R - 102R) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 110100 ((146R - 104R) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 110101 ((146R - 106R) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 110110 ((146R - 108R) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 110111 ((146R - 110R) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 111000 ((146R - 112R) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 111001 ((146R - 114R) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 111010 ((146R - 116R) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 111011 ((146R - 118R) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 111100 ((146R - 120R) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 111101 ((146R - 122R) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 111110 ((146R - 124R) / 450R) * (VSNR - VGSN) + VGSN
VRN4 5-0 = 111111 ((146R - 126R) / 450R) * (VSNR - VGSN) + VGSN

Table 5.45: VinN15

Himax Confidential -P.110-

Reference
Macro adjustment value VinN16 formula
voltage
VRN5 5-0 = 000000 (144R / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 000001 ((144R - 2R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 000010 ((144R - 4R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 000011 ((144R - 6R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 000100 ((144R - 8R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 000101 ((144R - 10R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 000110 ((144R - 12R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 000111 ((144R - 14R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 001000 ((144R - 16R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 001001 ((144R - 18R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 001010 ((144R - 20R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 001011 ((144R - 22R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 001100 ((144R - 24R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 001101 ((144R - 26R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 001110 ((144R - 28R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 001111 ((144R - 30R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 010000 ((144R - 32R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 010001 ((144R - 34R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 010010 ((144R - 36R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 010011 ((144R - 38R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 010100 ((144R - 40R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 010101 ((144R - 42R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 010110 ((144R - 44R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 010111 ((144R - 46R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 011000 ((144R - 48R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 011001 ((144R - 50R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 011010 ((144R - 52R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 011011 ((144R - 54R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 011100 ((144R - 56R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 011101 ((144R - 58R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 011110 ((144R - 60R ) / 450R) * (VSNR - VGSN) + VGSN
VinN16 VRN5 5-0 = 011111 ((144R - 62R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 100000 ((144R - 64R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 100001 ((144R - 66R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 100010 ((144R - 68R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 100011 ((144R - 70R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 100100 ((144R - 72R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 100101 ((144R - 74R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 100110 ((144R - 76R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 100111 ((144R - 78R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 101000 ((144R - 80R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 101001 ((144R - 82R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 101010 ((144R - 84R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 101011 ((144R - 86R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 101100 ((144R - 88R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 101101 ((144R - 90R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 101110 ((144R - 92R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 101111 ((144R - 94R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 110000 ((144R - 96R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 110001 ((144R - 98R ) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 110010 ((144R - 100R) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 110011 ((144R - 102R) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 110100 ((144R - 104R) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 110101 ((144R - 106R) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 110110 ((144R - 108R) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 110111 ((144R - 110R) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 111000 ((144R - 112R) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 111001 ((144R - 114R) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 111010 ((144R - 116R) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 111011 ((144R - 118R) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 111100 ((144R - 120R) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 111101 ((144R - 122R) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 111110 ((144R - 124R) / 450R) * (VSNR - VGSN) + VGSN
VRN5 5-0 = 111111 VGSN

Table 5.46: VinN16

Himax Confidential -P.111-

Reference
Macro adjustment value VinN5 formula
voltage
VinN5 PRN0 6-0 = 0000000 (350R / 450R) (VSNR - VGSN) + VGSN
PRN0 6-0 = 0000001 ((350R - 2R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0000010 ((350R - 4R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0000011 ((350R – 6R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0000100 ((350R – 8R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0000101 ((350R – 10R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0000110 ((350R – 12R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0000111 ((350R - 14R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0001000 ((350R – 16R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0001001 ((350R – 18R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0001010 ((350R – 20R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0001011 ((350R – 22R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0001100 ((350R – 24R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0001101 ((350R – 26R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0001110 ((350R – 28R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0001111 ((350R – 30R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0010000 ((350R – 32R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0010001 ((350R - 34R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0010010 ((350R – 36R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0010011 ((350R – 38R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0010100 ((350R – 40R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0010101 ((350R – 42R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0010110 ((350R – 44R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0010111 ((350R – 46R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0011000 ((350R – 48R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0011001 ((350R – 50R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0011010 ((350R – 52R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0011011 ((350R - 54R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0011100 ((350R – 56R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0011101 ((350R – 58R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0011110 ((350R – 60R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0011111 ((350R – 62R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0100000 ((350R - 64R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0100001 ((350R – 66R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0100010 ((350R – 68R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0100011 ((350R – 70R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0100100 ((350R – 72R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0100101 ((350R – 74R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0100110 ((350R – 76R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0100111 ((350R – 78R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0101000 ((350R – 80R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0101001 ((350R – 82R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0101010 ((350R - 84R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0101011 ((350R – 86R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0101100 ((350R – 88R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0101101 ((350R – 90R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0101110 ((350R – 92R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0101111 ((350R – 94R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0110000 ((350R – 96R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0110001 ((350R – 98R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0110010 ((350R – 100R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0110011 ((350R – 102R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0110100 ((350R – 104R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0110101 ((350R – 106R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0110110 ((350R – 108R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0110111 ((350R – 110R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0111000 ((350R – 112R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0111001 ((350R – 114R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0111010 ((350R – 116R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0111011 ((350R – 118R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0111100 ((350R – 120R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0111101 ((350R – 122R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0111110 ((350R - 124R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 0111111 ((350R – 126R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1000000 ((350R – 128R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1000001 ((350R – 130R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1000010 ((350R - 132R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1000011 ((350R – 134R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1000100 ((350R – 136R) / 450R) * (VSNR - VGSN) + VGSN
Himax Confidential -P.112-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
PRN0 6-0 = 1000101 ((350R – 138R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1000110 ((350R – 140R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1000111 ((350R – 142R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1001000 ((350R – 144R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1001001 ((350R – 146R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1001010 ((350R – 148R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1001011 ((350R – 150R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1001100 ((350R - 152R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1001101 ((350R – 154R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1001110 ((350R – 156R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1001111 ((350R – 158R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1010000 ((350R – 160R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1010001 ((350R – 162R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1010010 ((350R – 164R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1010011 ((350R – 166R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1010100 ((350R – 168R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1010101 ((350R – 170R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1010110 ((350R – 172R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1010111 ((350R - 174R) / 450R) * (VSNR - VGSN) + VGSN
PRN0 6-0 = 1011000 inhibit
PRN0 6-0 = 1011001 inhibit
PRN0 6-0 = 1011010 inhibit
PRN0 6-0 = 1011011 inhibit
PRN0 6-0 = 1011100 inhibit
PRN0 6-0 = 1011101 inhibit
PRN0 6-0 = 1011110 inhibit
PRN0 6-0 = 1011111 inhibit
PRN0 6-0 = 1100000 inhibit
PRN0 6-0 = 1100001 inhibit
PRN0 6-0 = 1100010 inhibit
PRN0 6-0 = 1100011 inhibit
PRN0 6-0 = 1100100 inhibit
PRN0 6-0 = 1100101 inhibit
PRN0 6-0 = 1100110 inhibit
PRN0 6-0 = 1100111 inhibit
PRN0 6-0 = 1101000 inhibit
PRN0 6-0 = 1101001 inhibit
PRN0 6-0 = 1101010 inhibit
PRN0 6-0 = 1101011 inhibit
PRN0 6-0 = 1101100 inhibit
PRN0 6-0 = 1101101 inhibit
PRN0 6-0 = 1101110 inhibit
PRN0 6-0 = 1101111 inhibit
PRN0 6-0 = 1110000 inhibit
PRN0 6-0 = 1110001 inhibit
PRN0 6-0 = 1110010 inhibit
PRN0 6-0 = 1110011 inhibit
PRN0 6-0 = 1110100 inhibit
PRN0 6-0 = 1110101 inhibit
PRN0 6-0 = 1110110 inhibit
PRN0 6-0 = 1110111 inhibit
PRN0 6-0 = 1111000 inhibit
PRN0 6-0 = 1111001 inhibit
PRN0 6-0 = 1111010 inhibit
PRN0 6-0 = 1111011 inhibit
PRN0 6-0 = 1111100 inhibit
PRN0 6-0 = 1111101 inhibit
PRN0 6-0 = 1111110 inhibit
PRN0 6-0 = 1111111 inhibit
Table 5.47: VinN5

Himax Confidential -P.113-

Reference
Macro adjustment value VinN11 formula
voltage
VinN11 PRN1 6-0 = 0000000 (274R / 450R) (VSNR - VGSN) + VGSN
PRN1 6-0 = 0000001 ((274R - 2R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0000010 ((274R - 4R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0000011 ((274R – 6R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0000100 ((274R – 8R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0000101 ((274R – 10R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0000110 ((274R – 12R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0000111 ((274R - 14R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0001000 ((274R – 16R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0001001 ((274R – 18R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0001010 ((274R – 20R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0001011 ((274R – 22R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0001100 ((274R – 24R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0001101 ((274R – 26R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0001110 ((274R – 28R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0001111 ((274R – 30R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0010000 ((274R – 32R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0010001 ((274R - 34R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0010010 ((274R – 36R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0010011 ((274R – 38R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0010100 ((274R – 40R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0010101 ((274R – 42R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0010110 ((274R – 44R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0010111 ((274R – 46R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0011000 ((274R – 48R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0011001 ((274R – 50R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0011010 ((274R – 52R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0011011 ((274R - 54R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0011100 ((274R – 56R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0011101 ((274R – 58R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0011110 ((274R – 60R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0011111 ((274R – 62R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0100000 ((274R - 64R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0100001 ((274R – 66R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0100010 ((274R – 68R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0100011 ((274R – 70R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0100100 ((274R – 72R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0100101 ((274R – 74R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0100110 ((274R – 76R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0100111 ((274R – 78R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0101000 ((274R – 80R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0101001 ((274R – 82R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0101010 ((274R - 84R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0101011 ((274R – 86R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0101100 ((274R – 88R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0101101 ((274R – 90R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0101110 ((274R – 92R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0101111 ((274R – 94R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0110000 ((274R – 96R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0110001 ((274R – 98R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0110010 ((274R – 100R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0110011 ((274R – 102R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0110100 ((274R – 104R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0110101 ((274R – 106R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0110110 ((274R – 108R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0110111 ((274R – 110R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0111000 ((274R – 112R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0111001 ((274R – 114R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0111010 ((274R – 116R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0111011 ((274R – 118R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0111100 ((274R – 120R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0111101 ((274R – 122R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0111110 ((274R - 124R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 0111111 ((274R – 126R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1000000 ((274R – 128R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1000001 ((274R – 130R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1000010 ((274R - 132R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1000011 ((274R – 134R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1000100 ((274R – 136R) / 450R) * (VSNR - VGSN) + VGSN
Himax Confidential -P.114-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
PRN1 6-0 = 1000101 ((274R – 138R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1000110 ((274R – 140R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1000111 ((274R – 142R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1001000 ((274R – 144R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1001001 ((274R – 146R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1001010 ((274R – 148R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1001011 ((274R – 150R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1001100 ((274R - 152R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1001101 ((274R – 154R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1001110 ((274R – 156R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1001111 ((274R – 158R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1010000 ((274R – 160R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1010001 ((274R – 162R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1010010 ((274R – 164R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1010011 ((274R – 166R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1010100 ((274R – 168R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1010101 ((274R – 170R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1010110 ((274R – 172R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1010111 ((274R - 174R) / 450R) * (VSNR - VGSN) + VGSN
PRN1 6-0 = 1011000 inhibit
PRN1 6-0 = 1011001 inhibit
PRN1 6-0 = 1011010 inhibit
PRN1 6-0 = 1011011 inhibit
PRN1 6-0 = 1011100 inhibit
PRN1 6-0 = 1011101 inhibit
PRN1 6-0 = 1011110 inhibit
PRN1 6-0 = 1011111 inhibit
PRN1 6-0 = 1100000 inhibit
PRN1 6-0 = 1100001 inhibit
PRN1 6-0 = 1100010 inhibit
PRN1 6-0 = 1100011 inhibit
PRN1 6-0 = 1100100 inhibit
PRN1 6-0 = 1100101 inhibit
PRN1 6-0 = 1100110 inhibit
PRN1 6-0 = 1100111 inhibit
PRN1 6-0 = 1101000 inhibit
PRN1 6-0 = 1101001 inhibit
PRN1 6-0 = 1101010 inhibit
PRN1 6-0 = 1101011 inhibit
PRN1 6-0 = 1101100 inhibit
PRN1 6-0 = 1101101 inhibit
PRN1 6-0 = 1101110 inhibit
PRN1 6-0 = 1101111 inhibit
PRN1 6-0 = 1110000 inhibit
PRN1 6-0 = 1110001 inhibit
PRN1 6-0 = 1110010 inhibit
PRN1 6-0 = 1110011 inhibit
PRN1 6-0 = 1110100 inhibit
PRN1 6-0 = 1110101 inhibit
PRN1 6-0 = 1110110 inhibit
PRN1 6-0 = 1110111 inhibit
PRN1 6-0 = 1111000 inhibit
PRN1 6-0 = 1111001 inhibit
PRN1 6-0 = 1111010 inhibit
PRN1 6-0 = 1111011 inhibit
PRN1 6-0 = 1111100 inhibit
PRN1 6-0 = 1111101 inhibit
PRN1 6-0 = 1111110 inhibit
PRN1 6-0 = 1111111 inhibit
Table 5.48: VinN11

Himax Confidential -P.115-

Reference
Macro adjustment value VinN3 formula
voltage
PKN0 4-0 = 00000 (47R / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 00001 ((47R – 1R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 00010 ((47R – 2R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 00011 ((47R – 3R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 00100 ((47R – 4R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 00101 ((47R – 5R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 00110 ((47R – 6R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 00111 ((47R – 7R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 01000 ((47R – 8R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 01001 ((47R – 9R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 01010 ((47R - 10R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 01011 ((47R - 11R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 01100 ((47R - 12R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 01101 ((47R - 13R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 01110 ((47R - 14R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 01111 ((47R - 15R) / 48R) * (VinN2 - VinN5) + VinN5
VinN3
PKN0 4-0 = 10000 ((47R - 16R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 10001 ((47R - 17R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 10010 ((47R - 18R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 10011 ((47R - 19R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 10100 ((47R - 20R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 10101 ((47R - 21R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 10110 ((47R - 22R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 10111 ((47R - 23R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 11000 ((47R - 24R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 11001 ((47R - 25R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 11010 ((47R - 26R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 11011 ((47R - 27R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 11100 ((47R - 28R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 11101 ((47R - 29R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 11110 ((47R - 30R) / 48R) * (VinN2 - VinN5) + VinN5
PKN0 4-0 = 11111 ((47R - 31R) / 48R) * (VinN2 - VinN5) + VinN5
Table 5.49: VinN3

Himax Confidential -P.116-

Reference
Macro adjustment value VinN6 formula
voltage
PKN2 4-0 = 00000 (220R / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 00001 ((220R - 3R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 00010 ((220R - 6R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 00011 ((220R - 9R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 00100 ((220R - 12R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 00101 ((220R - 15R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 00110 ((220R - 18R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 00111 ((220R - 21R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 01000 ((220R - 24R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 01001 ((220R - 27R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 01010 ((220R - 30R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 01011 ((220R - 33R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 01100 ((220R - 36R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 01101 ((220R - 39R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 01110 ((220R - 42R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 01111 ((220R - 45R) / 223R) * (VinN5 - VinN11) + VinN11
VinN6
PKN2 4-0 = 10000 ((220R - 48R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 10001 ((220R - 51R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 10010 ((220R - 54R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 10011 ((220R - 57R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 10100 ((220R - 60R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 10101 ((220R - 63R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 10110 ((220R - 66R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 10111 ((220R - 69R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 11000 ((220R - 72R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 11001 ((220R - 75R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 11010 ((220R - 78R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 11011 ((220R - 81R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 11100 ((220R - 84R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 11101 ((220R - 87R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 11110 ((220R - 90R) / 223R) * (VinN5 - VinN11) + VinN11
PKN2 4-0 = 11111 ((220R - 93R) / 223R) * (VinN5 - VinN11) + VinN11
Table 5.51: VinN6
Himax Confidential -P.117-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
Reference
Macro adjustment value VinN7 formula
voltage
PKN3 4-0 = 00000 (193R / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 00001 ((193R - 3R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 00010 ((193R - 6R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 00011 ((193R - 9R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 00100 ((193R - 12R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 00101 ((193R - 15R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 00110 ((193R - 18R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 00111 ((193R - 21R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 01000 ((193R - 24R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 01001 ((193R - 27R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 01010 ((193R - 30R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 01011 ((193R - 33R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 01100 ((193R - 36R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 01101 ((193R - 39R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 01110 ((193R - 42R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 01111 ((193R - 45R) / 223R) * (VinN5 - VinN11) + VinN11
VinN7
PKN3 4-0 = 10000 ((193R - 48R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 10001 ((193R - 51R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 10010 ((193R - 54R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 10011 ((193R - 57R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 10100 ((193R - 60R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 10101 ((193R - 63R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 10110 ((193R - 66R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 10111 ((193R - 69R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 11000 ((193R - 72R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 11001 ((193R - 75R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 11010 ((193R - 78R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 11011 ((193R - 81R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 11100 ((193R - 84R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 11101 ((193R - 87R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 11110 ((193R - 90R) / 223R) * (VinN5 - VinN11) + VinN11
PKN3 4-0 = 11111 ((193R - 93R) / 223R) * (VinN5 - VinN11) + VinN11
Table 5.52: VinN7

Reference
Macro adjustment value VinN8 formula
voltage
PKN4 4-0 = 00000 (158R / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 00001 ((158R - 3R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 00010 ((158R - 6R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 00011 ((158R - 9R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 00100 ((158R - 12R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 00101 ((158R - 15R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 00110 ((158R - 18R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 00111 ((158R - 21R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 01000 ((158R - 24R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 01001 ((158R - 27R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 01010 ((158R - 30R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 01011 ((158R - 33R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 01100 ((158R - 36R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 01101 ((158R - 39R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 01110 ((158R - 42R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 01111 ((158R - 45R) / 223R) * (VinN5 - VinN11) + VinN11
VinN8
PKN4 4-0 = 10000 ((158R - 48R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 10001 ((158R - 51R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 10010 ((158R - 54R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 10011 ((158R - 57R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 10100 ((158R - 60R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 10101 ((158R - 63R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 10110 ((158R - 66R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 10111 ((158R - 69R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 11000 ((158R - 72R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 11001 ((158R - 75R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 11010 ((158R - 78R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 11011 ((158R - 81R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 11100 ((158R - 84R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 11101 ((158R - 87R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 11110 ((158R - 90R) / 223R) * (VinN5 - VinN11) + VinN11
PKN4 4-0 = 11111 ((158R - 93R) / 223R) * (VinN5 - VinN11) + VinN11
Table 5.53: VinN8
Himax Confidential -P.118-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
Reference
Macro adjustment value VinN9 formula
voltage
PKN5 4-0 = 00000 (123R / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 00001 ((123R - 3R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 00010 ((123R - 6R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 00011 ((123R - 9R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 00100 ((123R - 12R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 00101 ((123R - 15R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 00110 ((123R - 18R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 00111 ((123R - 21R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 01000 ((123R - 24R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 01001 ((123R - 27R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 01010 ((123R - 30R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 01011 ((123R - 33R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 01100 ((123R - 36R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 01101 ((123R - 39R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 01110 ((123R - 42R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 01111 ((123R - 45R) / 223R) * (VinN5 - VinN11) + VinN11
VinN9
PKN5 4-0 = 10000 ((123R - 48R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 10001 ((123R - 51R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 10010 ((123R - 54R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 10011 ((123R - 57R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 10100 ((123R - 60R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 10101 ((123R - 63R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 10110 ((123R - 66R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 10111 ((123R - 69R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 11000 ((123R - 72R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 11001 ((123R - 75R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 11010 ((123R - 78R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 11011 ((123R - 81R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 11100 ((123R - 84R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 11101 ((123R - 87R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 11110 ((123R - 90R) / 223R) * (VinN5 - VinN11) + VinN11
PKN5 4-0 = 11111 ((123R - 93R) / 223R) * (VinN5 - VinN11) + VinN11
Table 5.54: VinN9

Reference
Macro adjustment value VinN10 formula
voltage
PKN6 4-0 = 00000 (96R / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 00001 ((96R - 3R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 00010 ((96R - 6R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 00011 ((96R - 9R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 00100 ((96R - 12R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 00101 ((96R - 15R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 00110 ((96R - 18R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 00111 ((96R - 21R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 01000 ((96R - 24R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 01001 ((96R - 27R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 01010 ((96R - 30R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 01011 ((96R - 33R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 01100 ((96R - 36R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 01101 ((96R - 39R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 01110 ((96R - 42R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 01111 ((96R - 45R) / 223R) * (VinN5 - VinN11) + VinN11
VinN10
PKN6 4-0 = 10000 ((96R - 48R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 10001 ((96R - 51R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 10010 ((96R - 54R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 10011 ((96R - 57R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 10100 ((96R - 60R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 10101 ((96R - 63R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 10110 ((96R - 66R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 10111 ((96R - 69R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 11000 ((96R - 72R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 11001 ((96R - 75R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 11010 ((96R - 78R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 11011 ((96R - 81R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 11100 ((96R - 84R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 11101 ((96R - 87R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 11110 ((96R - 90R) / 223R) * (VinN5 - VinN11) + VinN11
PKN6 4-0 = 11111 ((96R - 93R) / 223R) * (VinN5 - VinN11) + VinN11
Table 5.55: VinN10
Himax Confidential -P.119-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
Reference
Macro adjustment value VinN12 formula
voltage
PKN7 4-0 = 00000 (47R / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 00001 ((47R - 1R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 00010 ((47R - 2R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 00011 ((47R - 3R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 00100 ((47R - 4R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 00101 ((47R - 5R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 00110 ((47R - 6R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 00111 ((47R - 7R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 01000 ((47R - 8R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 01001 ((47R - 9R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 01010 ((47R - 10R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 01011 ((47R - 11R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 01100 ((47R - 12R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 01101 ((47R - 13R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 01110 ((47R - 14R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 01111 ((47R - 15R) / 48R) * (VinN11 - VinN14) + VinN14
VinN12
PKN7 4-0 = 10000 ((47R - 16R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 10001 ((47R - 17R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 10010 ((47R - 18R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 10011 ((47R - 19R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 10100 ((47R - 20R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 10101 ((47R - 21R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 10110 ((47R - 22R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 10111 ((47R - 23R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 11000 ((47R - 24R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 11001 ((47R - 25R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 11010 ((47R - 26R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 11011 ((47R - 27R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 11100 ((47R - 28R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 11101 ((47R - 29R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 11110 ((47R - 30R) / 48R) * (VinN11 - VinN14) + VinN14
PKN7 4-0 = 11111 ((47R - 31R) / 48R) * (VinN11 - VinN14) + VinN14
Table 5.56: VinN12

Reference
Macro adjustment value VinN13 formula
voltage
PKN8 4-0 = 00000 (32R / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 00001 ((32R - 1R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 00010 ((32R - 2R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 00011 ((32R - 3R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 00100 ((32R - 4R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 00101 ((32R - 5R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 00110 ((32R - 6R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 00111 ((32R - 7R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 01000 ((32R - 8R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 01001 ((32R - 9R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 01010 ((32R - 10R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 01011 ((32R - 11R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 01100 ((32R - 12R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 01101 ((32R - 13R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 01110 ((32R - 14R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 01111 ((32R - 15R) / 48R) * (VinN11 - VinN14) + VinN14
VinN13
PKN8 4-0 = 10000 ((32R - 16R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 10001 ((32R - 17R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 10010 ((32R - 18R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 10011 ((32R - 19R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 10100 ((32R - 20R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 10101 ((32R - 21R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 10110 ((32R - 22R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 10111 ((32R - 23R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 11000 ((32R - 24R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 11001 ((32R - 25R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 11010 ((32R - 26R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 11011 ((32R - 27R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 11100 ((32R - 28R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 11101 ((32R - 29R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 11110 ((32R - 30R) / 48R) * (VinN11 - VinN14) + VinN14
PKN8 4-0 = 11111 ((32R - 31R) / 48R) * (VinN11 - VinN14) + VinN14
Table 5.57: VinN13
Himax Confidential -P.120-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02

Grayscale Grayscale
Formula Formula
voltage voltage
V0 VinP0 CGMP4=0 =VinP5 - (VinP5 - VinP6)*(3R/6R)
V16
V1 VinP1 CGMP4=1 =VinP5 - (VinP5 - VinP6)*(3.5R/6.5R)
V2 VinP2 CGMP4=0 =VinP5 - (VinP5 - VinP6)*(4R/6R)
V17
V3 VinP3 CGMP4=1 =VinP5 - (VinP5 - VinP6)*(4.5R/6.5R)
CGMP0=0 = VinP3 - (VinP3 - VinP4)*(1R/4R) CGMP4=0 =VinP5 - (VinP5 - VinP6)*(5R/6R)
V18
CGMP0=1 = VinP3 - (VinP3 - VinP4)*(3R/9.5R) CGMP4=1 =VinP5 - (VinP5 - VinP6)*(5.5R/6.5R)
V4
CGMP0=2 = VinP3 - (VinP3 - VinP4)*(3.5R/9.3R) V19 VinP6
CGMP0=3 = VinP3 - (VinP3 - VinP4)*(3.5R/10R) V20 VinP6 - (VinP6 - VinP7)*(1R/6R)
CGMP0=0 = VinP3 - (VinP3 - VinP4)*(2R/4R) V21 VinP6 - (VinP6 - VinP7)*(2R/6R)
CGMP0=1 = VinP3 - (VinP3 - VinP4)*(5.5R/9.5R) V22 VinP6 - (VinP6 - VinP7)*(3R/6R)
V5
CGMP0=2 = VinP3 - (VinP3 - VinP4)*(6R/9.3R) V23 VinP6 - (VinP6 - VinP7)*(4R/6R)
CGMP0=3 = VinP3 - (VinP3 - VinP4)*(6R/10R) V24 VinP6 - (VinP6 - VinP7)*(5R/6R)
CGMP0=0 = VinP3 - (VinP3 - VinP4)*(3R/4R) V25 VinP7
CGMP0=1 = VinP3 - (VinP3 - VinP4)*(7.5R/9.5R) V26 VinP7 - (VinP7 - VinP8)*(1R/7.5R)
V6
CGMP0=2 = VinP3 - (VinP3 - VinP4)*(7.8R/9.3R) V27 VinP7 - (VinP7 - VinP8)*(2R/7.5R)
CGMP0=3= VinP3 - (VinP3 - VinP4)*(8R/10R) V28 VinP7 - (VinP7 - VinP8)*(3R/7.5R)
V7 VinP4 V29 VinP7 - (VinP7 - VinP8)*(4R/7.5R)
CGMP2=0 = VinP4 - (VinP4 - VinP5)*(1R/6R) V30 VinP7 - (VinP7 - VinP8)*(5R/7.5R)
CGMP2=1 = VinP4 - (VinP4 - VinP5)*(3R/16R) V31 VinP7 - (VinP7 - VinP8)*(6R/7.5R)
V8
CGMP2=2 = VinP4 - (VinP4 - VinP5)*(4R/18R) V32 VinP8
CGMP2=3 = VinP4 - (VinP4 - VinP5)*(4.5R/19.5R) V33 VinP8 - (VinP8 - VinP9)*(1R/6R)
CGMP2=0 = VinP4 - (VinP4 - VinP5)*(2R/6R) V34 VinP8 - (VinP8 - VinP9)*(2R/6R)
CGMP2=1 = VinP4 - (VinP4 - VinP5)*(6R/16R) V35 VinP8 - (VinP8 - VinP9)*(3R/6R)
V9
CGMP2=2 = VinP4 - (VinP4 - VinP5)*(7R/18R) V36 VinP8 - (VinP8 - VinP9)*(4R/6R)
CGMP2=3 = VinP4 - (VinP4 - VinP5)*(8.5R/19.5R) V37 VinP8 - (VinP8 - VinP9)*(5R/6R)
CGMP2=0 = VinP4 - (VinP4 - VinP5)*(3R/6R) V38 VinP9
CGMP2=1 = VinP4 - (VinP4 - VinP5)*(8.5R/16R) V39 VinP9 - (VinP9 - VinP10)*(1R/6R)
V10
CGMP2=2 = VinP4 - (VinP4 - VinP5)*(10R/18R) V40 VinP9 - (VinP9 - VinP10)*(2R/6R)
CGMP2=3 = VinP4 - (VinP4 - VinP5)*(11.5R/19.5R) V41 VinP9 - (VinP9 - VinP10)*(3R/6R)
CGMP2=0 = VinP4 - (VinP4 - VinP5)*(4R/6R) V42 VinP9 - (VinP9 - VinP10)*(4R/6R)
CGMP2=1 = VinP4 - (VinP4 - VinP5)*(11R/16R) V43 VinP9 - (VinP9 - VinP10)*(5R/6R)
V11
CGMP2=2 = VinP4 - (VinP4 - VinP5)*(13R/18R) V44 VinP10
CGMP2=3 = VinP4 - (VinP4 - VinP5)*(14.5R/19.5R) CGMP5=0 =VinP10 - (VinP10 - VinP11)*(1R/6R)
V45
CGMP2=0 = VinP4 - (VinP4 - VinP5)*(5R/6R) CGMP5=1 =VinP10 - (VinP10 - VinP11)*(1R/6.5R)
CGMP2=1 = VinP4 - (VinP4 - VinP5)*(13.5R/16R) CGMP5=0 =VinP10 - (VinP10 - VinP11)*(2R/6R)
V12 V46
CGMP2=2 = VinP4 - (VinP4 - VinP5)*(15.5R/18R) CGMP5=1 =VinP10 - (VinP10 - VinP11)*(2R/6.5R)
CGMP2=3 = VinP4 - (VinP4 - VinP5)*(17R/19.5R) CGMP5=0 =VinP10 - (VinP10 - VinP11)*(3R/6R)
V47
V13 VinP5 CGMP5=1 =VinP10 - (VinP10 - VinP11)*(3R/6.5R)
CGMP4=0 =VinP5 - (VinP5 - VinP6)*(1R/6R) CGMP5=0 =VinP10 - (VinP10 - VinP11)*(4R/6R)
V14 V48
CGMP4=1 =VinP5 - (VinP5 - VinP6)*(1.5R/6.5R) CGMP5=1 =VinP10 - (VinP10 - VinP11)*(4R/6.5R)
CGMP4=0 =VinP5 - (VinP5 - VinP6)*(2R/6R) CGMP5=0 =VinP10 - (VinP10 - VinP11)*(5R/6R)
V15 V49
CGMP4=1 =VinP5 - (VinP5 - VinP6)*(2.5R/6.5R) CGMP5=1 =VinP10 - (VinP10 - VinP11)*(5R/6.5R)

Himax Confidential -P.121-

V50 VinP11 V56 VinP12

CGMP3=0 = VinP11 - (VinP11 - VinP12)(1R/6R) CGMP1=0 = VinP12 - (VinP12 – VinP13)(1R/4R)

CGMP3=1 = VinP11 - (VinP11 - VinP12)(2.5R/16R) CGMP1=1 = VinP12 - (VinP12 – VinP13)(2R/9.5R)

V51 V57
CGMP3=2 = VinP11 - (VinP11 - VinP12)*(2.5R/18R) CGMP1=2 = VinP12 - (VinP12 – VinP13)*(1.5R/9.3R)

CGMP3=3 = VinP11 - (VinP11 - VinP12)* (2.5R/19.5R) CGMP1=3 = VinP12 - (VinP12 – VinP13)*(2R/10R)

CGMP3=0 = VinP11 - (VinP11- VinP12)(2R/6R) CGMP1=0 = VinP12 - (VinP12 – VinP13)(2R/4R)

CGMP3=1 = VinP11 - (VinP11 - VinP12)(5R/16R) CGMP1=1 = VinP12 - (VinP12 – VinP13)(4R/9.5R)

V52 V58
CGMP3=2 = VinP11 - (VinP11 - VinP12)*(5R/18R) CGMP1=2 = VinP12 - (VinP12 – VinP13)*(3.3R/9.3R)

CGMP3=3 = VinP11 - (VinP11 - VinP12)(5R/19.5R) CGMP1=3 = VinP12 - (VinP12 – VinP13)(4R/10R)

CGMP3=0 = VinP11 - (VinP11 - VinP12)(3R/6R) CGMP1=0 = VinP12 - (VinP12 – VinP13)(3R/4R)

CGMP3=1 = VinP11 - (VinP11 - VinP12)(7.5R/16R) CGMP1=1 = VinP12 - (VinP12 – VinP13)(6.5R/9.5R)

V53 V59
CGMP3=2 = VinP11 - (VinP11 - VinP12)*(8R/18R) CGMP1=2 = VinP12 - (VinP12 – VinP13)*(5.8R/9.3R)

CGMP3=3 = VinP11 - (VinP11 - VinP12)(8R/19.5R) CGMP1=3= VinP12 - (VinP12 – VinP13)(6.5R/10R)

CGMP3=0 = VinP11 - (VinP11 - VinP12)*(4R/6R) V60 VinP13

CGMP3=1 = VinP11 - (VinP11 - VinP12)*(10R/16R) V61 VinP14

V54
CGMP3=2 = VinP11 - (VinP11 - VinP12)*(11R/18R) V62 VinP15

CGMP3=3 = VinP11 - (VinP11 - VinP12)* (11R/19.5R) V63 VinP16

CGMP3=0 = VinP11 - (VinP11- VinP12)*(5R/6R)

CGMP3=1 = VinP11 - (VinP11 - VinP12)*(13R/16R)

V55
CGMP3=2 = VinP11 - (VinP11 - VinP12)*(14R/18R)

CGMP3=3 = VinP11 - (VinP11 - VinP12)* (15R/19.5R)

Table 5.58: Voltage calculation formula of 64-grayscale voltage (positive polarity)

Himax Confidential -P.122-

Grayscale Grayscale
Formula Formula
voltage voltage
V0 VinN0 CGMN4=0 =VinN5 - (VinN5 - VinN6)*(3R/6R)
V16
V1 VinN1 CGMN4=1 =VinN5 - (VinN5 - VinN6)*(3.5R/6.5R)
V2 VinN2 CGMN4=0 =VinN5 - (VinN5 - VinN6)*(4R/6R)
V17
V3 VinN3 CGMN4=1 =VinN5 - (VinN5 - VinN6)*(4.5R/6.5R)
CGMN0=0 = VinN3 - (VinN3 - VinN4)*(1R/4R) CGMN4=0 =VinN5 - (VinN5 - VinN6)*(5R/6R)
V18
CGMN0=1 = VinN3 - (VinN3 - VinN4)*(3R/9.5R) CGMN4=1 =VinN5 - (VinN5 - VinN6)*(5.5R/6.5R)
V4
CGMN0=2 = VinN3 - (VinN3 - VinN4)*(3.5R/9.3R) V19 VinN6
CGMN0=3 = VinN3 - (VinN3 - VinN4)*(3.5R/10R) V20 VinN6 - (VinN6 - VinN7)*(1R/6R)
CGMN0=0 = VinN3 - (VinN3 - VinN4)*(2R/4R) V21 VinN6 - (VinN6 - VinN7)*(2R/6R)
CGMN0=1 = VinN3 - (VinN3 - VinN4)*(5.5R/9.5R) V22 VinN6 - (VinN6 - VinN7)*(3R/6R)
V5
CGMN0=2 = VinN3 - (VinN3 - VinN4)*(6R/9.3R) V23 VinN6 - (VinN6 - VinN7)*(4R/6R)
CGMN0=3 = VinN3 - (VinN3 - VinN4)*(6R/10R) V24 VinN6 - (VinN6 - VinN7)*(5R/6R)
CGMN0=0 = VinN3 - (VinN3 - VinN4)*(3R/4R) V25 VinP7
CGMN0=1 = VinN3 - (VinN3 - VinN4)*(7.5R/9.5R) V26 VinP7 - (VinP7 - VinP8)*(1R/7.5R)
V6
CGMN0=2 = VinN3 - (VinN3 - VinN4)*(7.8R/9.3R) V27 VinP7 - (VinP7 - VinP8)*(2R/7.5R)
CGMN0=3= VinN3 - (VinN3 - VinN4)*(8R/10R) V28 VinP7 - (VinP7 - VinP8)*(3R/7.5R)
V7 VinN4 V29 VinP7 - (VinP7 - VinP8)*(4R/7.5R)
CGMN2=0 = VinN4 - (VinN4 - VinN5)*(1R/6R) V30 VinP7 - (VinP7 - VinP8)*(5R/7.5R)
CGMN2=1 = VinN4 - (VinN4 - VinN5)*(3R/16R) V31 VinP7 - (VinP7 - VinP8)*(6R/7.5R)
V8
CGMN2=2 = VinN4 - (VinN4 - VinN5)*(4R/18R) V32 VinP8
CGMN2=3 = VinN4 - (VinN4 - VinN5)*(4.5R/19.5R) V33 VinP8 - (VinP8 - VinP9)*(1R/6R)
CGMN2=0 = VinN4 - (VinN4 - VinN5)*(2R/6R) V34 VinP8 - (VinP8 - VinP9)*(2R/6R)
CGMN2=1 = VinN4 - (VinN4 - VinN5)*(6R/16R) V35 VinP8 - (VinP8 - VinP9)*(3R/6R)
V9
CGMN2=2 = VinN4 - (VinN4 - VinN5)*(7R/18R) V36 VinP8 - (VinP8 - VinP9)*(4R/6R)
CGMN2=3 = VinN4 - (VinN4 - VinN5)*(8.5R/19.5R) V37 VinP8 - (VinP8 - VinP9)*(5R/6R)
CGMN2=0 = VinN4 - (VinN4 - VinN5)*(3R/6R) V38 VinN9
CGMN2=1 = VinN4 - (VinN4 - VinN5)*(8.5R/16R) V39 VinN9 - (VinN9 - VinN10)*(1R/6R)
V10
CGMN2=2 = VinN4 - (VinN4 - VinN5)*(10R/18R) V40 VinN9 - (VinN9 - VinN10)*(2R/6R)
CGMN2=3 = VinN4 - (VinN4 -
V41 VinN9 - (VinN9 - VinN10)*(3R/6R)
VinN5)*(11.5R/19.5R)
CGMN2=0 = VinN4 - (VinN4 - VinN5)*(4R/6R) V42 VinN9 - (VinN9 - VinN10)*(4R/6R)
CGMN2=1 = VinN4 - (VinN4 - VinN5)*(11R/16R) V43 VinN9 - (VinN9 - VinN10)*(5R/6R)
V11
CGMN2=2 = VinN4 - (VinN4 - VinN5)*(13R/18R) V44 VinN10
CGMN2=3 = VinN4 - (VinN4 -
CGMN5=0 =VinN10 - (VinN10 - VinN11)*(1R/6R)
VinN5)*(14.5R/19.5R) V45
CGMN2=0 = VinN4 - (VinN4 - VinN5)*(5R/6R) CGMN5=1 =VinN10 - (VinN10 - VinN11)*(1R/6.5R)
CGMN2=1 = VinN4 - (VinN4 - VinN5)*(13.5R/16R) CGMN5=0 =VinN10 - (VinN10 - VinN11)*(2R/6R)
V12 V46
CGMN2=2 = VinN4 - (VinN4 - VinN5)*(15.5R/18R) CGMN5=1 =VinN10 - (VinN10 - VinN11)*(2R/6.5R)
CGMN2=3 = VinN4 - (VinN4 - VinN5)*(17R/19.5R) CGMN5=0 =VinN10 - (VinN10 - VinN11)*(3R/6R)
V47
V13 VinN5 CGMN5=1 =VinN10 - (VinN10 - VinN11)*(3R/6.5R)
CGMN4=0 =VinN5 - (VinN5 - VinN6)*(1R/6R) CGMN5=0 =VinN10 - (VinN10 - VinN11)*(4R/6R)
V14 V48
CGMN4=1 =VinN5 - (VinN5 - VinN6)*(1.5R/6.5R) CGMN5=1 =VinN10 - (VinN10 - VinN11)*(4R/6.5R)
CGMN4=0 =VinN5 - (VinN5 - VinN6)*(2R/6R) CGMN5=0 =VinN10 - (VinN10 - VinN11)*(5R/6R)
V15 V49
CGMN4=1 =VinN5 - (VinN5 - VinN6)*(2.5R/6.5R) CGMN5=1 =VinN10 - (VinN10 - VinN11)*(5R/6.5R)

Himax Confidential -P.123-

Grayscale Grayscale
Formula Formula
voltage voltage

V50 VinN11 V56 VinN12

CGMN3=0 = VinN11 - (VinN11 - VinN12)(1R/6R) CGMN1=0 = VinN12 - (VinN12 – VinN13)(1R/4R)

CGMN3=1 = VinN11 - (VinN11 - VinN12)(2.5R/16R) CGMN1=1 = VinN12 - (VinN12 – VinN13)(2R/9.5R)

V51 V57
CGMN3=2 = VinN11 - (VinN11 - VinN12)*(2.5R/18R) CGMN1=2 = VinN12 - (VinN12 – VinN13)*(1.5R/9.3R)
CGMN3=3 = VinN11 - (VinN11 -
CGMN1=3 = VinN12 - (VinN12 – VinN13)*(2R/10R)
VinN12)*(2.5R/19.5R)
CGMN3=0 = VinN11 - (VinN11- VinN12)*(2R/6R) CGMN1=0 = VinN12 - (VinN12 – VinN13)*(2R/4R)

CGMN3=1 = VinN11 - (VinN11 - VinN12)(5R/16R) CGMN1=1 = VinN12 - (VinN12 – VinN13)(4R/9.5R)

V52 V58
CGMN3=2 = VinN11 - (VinN11 - VinN12)*(5R/18R) CGMN1=2 = VinN12 - (VinN12 – VinN13)*(3.3R/9.3R)

CGMN3=3 = VinN11 - (VinN11 - VinN12)(5R/19.5R) CGMN1=3 = VinN12 - (VinN12 – VinN13)(4R/10R)

CGMN3=0 = VinN11 - (VinN11 - VinN12)(3R/6R) CGMN1=0 = VinN12 - (VinN12 – VinN13)(3R/4R)

CGMN3=1 = VinN11 - (VinN11 - VinN12)(7.5R/16R) CGMN1=1 = VinN12 - (VinN12 – VinN13)(6.5R/9.5R)

V53 V59
CGMN3=2 = VinN11 - (VinN11 - VinN12)*(8R/18R) CGMN1=2 = VinN12 - (VinN12 – VinN13)*(5.8R/9.3R)

CGMN3=3 = VinN11 - (VinN11 - VinN12)(8R/19.5R) CGMN1=3= VinN12 - (VinN12 – VinN13)(6.5R/10R)

CGMN3=0 = VinN11 - (VinN11 - VinN12)*(4R/6R) V60 VinN13

CGMN3=1 = VinN11 - (VinN11 - VinN12)*(10R/16R) V61 VinN14

V54
CGMN3=2 = VinN11 - (VinN11 - VinN12)*(11R/18R) V62 VinN15

CGMN3=3 = VinN11 - (VinN11 - VinN12)*(11R/19.5R) V63 VinN16

CGMN3=0 = VinN11 - (VinN11- VinN12)*(5R/6R)

CGMN3=1 = VinN11 - (VinN11 - VinN12)*(13R/16R)

V55
CGMN3=2 = VinN11 - (VinN11 - VinN12)*(14R/18R)

CGMN3=3 = VinN11 - (VinN11 - VinN12)*(15R/19.5R)

Table 5.59: Voltage calculation formula of 64-grayscale voltage (negative polarity)

Himax Confidential -P.124-

Grayscale Grayscale
Formula Formula
voltage voltage
VV0 V0 VV44 V11
VV1 V0 - (V0 - V1)*(4R/16R) VV45 V11 - (V11 - V12)*(1.6R/6.4R)
VV2 V0 - (V0 - V1)*(8R/16R) VV46 V11 - (V11 - V12)*(3.2R/6.4R)
VV3 V0 - (V0 - V1)*(12R/16R) VV47 V11 - (V11 - V12)*(4.8R/6.4R)
VV4 V1 VV48 V12
VV5 V1 - (V1 - V2)*(4R/16R) VV49 V12 - (V12 - V13)*(1.6R/6.4R)
VV6 V1 - (V1 - V2)*(8R/16R) VV50 V12 - (V12 - V13)*(3.2R/6.4R)
VV7 V1 - (V1 - V2)*(12R/16R) VV51 V12 - (V12 - V13)*(4.8R/6.4R)
VV8 V2 VV52 V13
VV9 V2 - (V2 - V3)*(4R/16R) VV53 V13 - (V13 - V14)*(1.6R/6.4R)
VV10 V2 - (V2 - V3)*(8R/16R) VV54 V13 - (V13 - V14)*(3.2R/6.4R)
VV11 V2 - (V2 - V3)*(12R/16R) VV55 V13 - (V13 - V14)*(4.8R/6.4R)
VV12 V3 VV56 V14
VV13 V3 - (V3 - V4)*(2R/8R) VV57 V14 - (V14 - V15)*(1.6R/6.4R)
VV14 V3 - (V3 - V4)*(4R/8R) VV58 V14 - (V14 - V15)*(3.2R/6.4R)
VV15 V3 - (V3 - V4)*(6R/8R) VV59 V14 - (V14 - V15)*(4.8R/6.4R)
VV16 V4 VV60 V15
VV17 V4 - (V4 - V5)*(2R/8R) VV61 V15 - (V15 - V16)*(1.6R/6.4R)
VV18 V4 - (V4 - V5)*(4R/8R) VV62 V15 - (V15 - V16)*(3.2R/6.4R)
VV19 V4 - (V4 - V5)*(6R/8R) VV63 V15 - (V15 - V16)*(4.8R/6.4R)
VV20 V5 VV64 V16
VV21 V5 - (V5 - V6)*(2R/8R) VV65 V16 - (V16 - V17)*(1.6R/6.4R)
VV22 V5 - (V5 - V6)*(4R/8R) VV66 V16 - (V16 - V17)*(3.2R/6.4R)
VV23 V5 - (V5 - V6)*(6R/8R) VV67 V16 - (V16 - V17)*(4.8R/6.4R)
VV24 V6 VV68 V17
VV25 V6 - (V6 - V7)*(2R/8R) VV69 V17 - (V17 - V18)*(1.6R/6.4R)
VV26 V6 - (V6 - V7)*(4R/8R) VV70 V17 - (V17 - V18)*(3.2R/6.4R)
VV27 V6 - (V6 - V7)*(6R/8R) VV71 V17 - (V17 - V18)*(4.8R/6.4R)
VV28 V7 VV72 V18
VV29 V7 - (V7 - V8)*(1.6R/6.4R) VV73 V18 - (V18 - V19)*(1.6R/6.4R)
VV30 V7 - (V7 - V8)*(3.2R/6.4R) VV74 V18 - (V18 - V19)*(3.2R/6.4R)
VV31 V7 - (V7 - V8)*(4.8R/6.4R) VV75 V18 - (V18 - V19)*(4.8R/6.4R)
VV32 V8 VV76 V19
VV33 V8 - (V8 - V9)*(1.6R/6.4R) VV77 V19 - (V19 - V20)*(1.6R/6.4R)
VV34 V8 - (V8 - V9)*(3.2R/6.4R) VV78 V19 - (V19 - V20)*(3.2R/6.4R)
VV35 V8 - (V8 - V9)*(4.8R/6.4R) VV79 V19 - (V19 - V20)*(4.8R/6.4R)
VV36 V9 VV80 V20
VV37 V9 - (V9 - V10)*(1.6R/6.4R) VV81 V20 - (V20 - V21)*(1.6R/6.4R)
VV38 V9 - (V9 - V10)*(3.2R/6.4R) VV82 V20 - (V20 - V21)*(3.2R/6.4R)
VV39 V9 - (V9 - V10)*(4.8R/6.4R) VV83 V20 - (V20 - V21)*(4.8R/6.4R)
VV40 V10 VV84 V21
VV41 V10 - (V10 - V11)*(1.6R/6.4R) VV85 V21 - (V21 - V22)*(1.6R/6.4R)
VV42 V10 - (V10 - V11)*(3.2R/6.4R) VV86 V21 - (V21 - V22)*(3.2R/6.4R)
VV43 V10 - (V10 - V11)*(4.8R/6.4R) VV87 V21 - (V21 - V22)*(4.8R/6.4R)

Himax Confidential -P.125-

Grayscale Grayscale
Formula Formula
voltage voltage
VV88 V22 VV132 V32 - (V32 - V33)*(1.6R/6.4R)
VV89 V22 - (V22 - V23)*(1.6R/6.4R) VV133 V32 - (V32 - V33)*(3.2R/6.4R)
VV90 V22 - (V22 - V23)*(3.2R/6.4R) VV134 V32 - (V32 - V33)*(4.8R/6.4R)
VV91 V22 - (V22 - V23)*(4.8R/6.4R) VV135 V33
VV92 V23 VV136 V33 - (V33 - V34)*(1.6R/6.4R)
VV93 V23 - (V23 - V24)*(1.6R/6.4R) VV137 V33 - (V33 - V34)*(3.2R/6.4R)
VV94 V23 - (V23 - V24)*(3.2R/6.4R) VV138 V33 - (V33 - V34)*(4.8R/6.4R)
VV95 V23 - (V23 - V24)*(4.8R/6.4R) VV139 V34
VV96 V24 VV140 V34 - (V34 - V35)*(1.6R/6.4R)
VV97 V24 - (V24 - V25)*(1.6R/6.4R) VV141 V34 - (V34 - V35)*(3.2R/6.4R)
VV98 V24 - (V24 - V25)*(3.2R/6.4R) VV142 V34 - (V34 - V35)*(4.8R/6.4R)
VV99 V24 - (V24 - V25)*(4.8R/6.4R) VV143 V35
VV100 V25 VV144 V35 - (V35 - V36)*(1.6R/6.4R)
VV101 V25 - (V25 - V26)*(1.6R/6.4R) VV145 V35 - (V35 - V36)*(3.2R/6.4R)
VV102 V25 - (V25 - V26)*(3.2R/6.4R) VV146 V35 - (V35 - V36)*(4.8R/6.4R)
VV103 V25 - (V25 - V26)*(4.8R/6.4R) VV147 V36
VV104 V26 VV148 V36 - (V36 - V37)*(1.6R/6.4R)
VV105 V26 - (V26 - V27)*(1.6R/6.4R) VV149 V36 - (V36 - V37)*(3.2R/6.4R)
VV106 V26 - (V26 - V27)*(3.2R/6.4R) VV150 V36 - (V36 - V37)*(4.8R/6.4R)
VV107 V26 - (V26 - V27)*(4.8R/6.4R) VV151 V37
VV108 V27 VV152 V37 - (V37 - V38)*(1.6R/6.4R)
VV109 V27 - (V27 - V28)*(1.6R/6.4R) VV153 V37 - (V37 - V38)*(3.2R/6.4R)
VV110 V27 - (V27 - V28)*(3.2R/6.4R) VV154 V37 - (V37 - V38)*(4.8R/6.4R)
VV111 V27 - (V27 - V28)*(4.8R/6.4R) VV155 V38
VV112 V28 VV156 V38 - (V38 - V39)*(1.6R/6.4R)
VV113 V28 - (V28 - V29)*(1.6R/6.4R) VV157 V38 - (V38 - V39)*(3.2R/6.4R)
VV114 V28 - (V28 - V29)*(3.2R/6.4R) VV158 V38 - (V38 - V39)*(4.8R/6.4R)
VV115 V28 - (V28 - V29)*(4.8R/6.4R) VV159 V39
VV116 V29 VV160 V39 - (V39 - V40)*(1.6R/6.4R)
VV117 V29 - (V29 - V30)*(1.6R/6.4R) VV161 V39 - (V39 - V40)*(3.2R/6.4R)
VV118 V29 - (V29 - V30)*(3.2R/6.4R) VV162 V39 - (V39 - V40)*(4.8R/6.4R)
VV119 V29 - (V29 - V30)*(4.8R/6.4R) VV163 V40
VV120 V30 VV164 V40 - (V40 - V41)*(1.6R/6.4R)
VV121 V30 - (V30 - V31)*(1.6R/6.4R) VV165 V40 - (V40 - V41)*(3.2R/6.4R)
VV122 V30 - (V30 - V31)*(3.2R/6.4R) VV166 V40 - (V40 - V41)*(4.8R/6.4R)
VV123 V30 - (V30 - V31)*(4.8R/6.4R) VV167 V41
VV124 V31 VV168 V41 - (V41 - V42)*(1.6R/6.4R)
VV125 V31 - (V31 - V32)*(1.6R/11.2R) VV169 V41 - (V41 - V42)*(3.2R/6.4R)
VV126 V31 - (V31 - V32)*(3.2R/11.2R) VV170 V41 - (V41 - V42)*(4.8R/6.4R)
VV127 V31 - (V31 - V32)*(4.8R/11.2R) VV171 V42
VV128 V31 - (V31 - V32)*(6.4R/11.2R) VV172 V42 - (V42 - V43)*(1.6R/6.4R)
VV129 V31 - (V31 - V32)*(8R/11.2R) VV173 V42 - (V42 - V43)*(3.2R/6.4R)
VV130 V31 - (V31 - V32)*(9.6R/11.2R) VV174 V42 - (V42 - V43)*(4.8R/6.4R)
VV131 V32 VV175 V43

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5.13.1 Output or bi-directional (I/O) pins

Output or
After power on After hardware reset After software reset
bi-directional pins
TE Low Low Low
DB23 to DB0
High-Z (Inactive) High-Z (Inactive) High-Z (Inactive)
(Output driver)
SDO High-Z (Inactive) High-Z (Inactive) High-Z (Inactive)
CABC_PWM_OUT Low Low Low

Table 5.61 Characteristics of output or bi-directional (I/O) pins

5.13.2 Input pins

After After
During power After power During power
Input pins hardware software
on process on off process
reset reset
RESX Setion.5.18 Input valid Input valid Input valid Setion.5.18
CSX Input valid Input valid Input valid Input valid Input valid
DCX_SCL Input valid Input valid Input valid Input valid Input valid
WRX_DCX Input valid Input valid Input valid Input valid Input valid
RDX_E Input valid Input valid Input valid Input valid Input valid
DB23 to DB0
Input valid Input valid Input valid Input valid Input valid
SDI
HSYNC Input valid Input valid Input valid Input valid Input valid
VSYNC Input valid Input valid Input valid Input valid Input valid
PCLK Input valid Input valid Input valid Input valid Input valid
DE Input valid Input valid Input valid Input valid Input valid
OSC, BS3, BS2,
Input valid Input valid Input valid Input valid Input valid
BS1, BS0,
TEST2-1 Low Low Low Low Low
Table 5.62 Characteristics of input pins

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HX8369-A00 is a single chip solution for a WVGA GIP (Gate In Panel) type TFT LCD
display. There are many GIP/ASG type TFT panels that correspond to different GIP
timing. Therefore, the GIP setting must be setup to the correct GIP/ASG timing for the
normal display. The GIP timing adjustment is related to register 0xD5h SETGIP.

The GIP control signals (GOUT[1~10]_L and GOUT[1~10]_R) is for panel used. The
assignment of each panel type is specified on the application note. Regarding the
GIP/ASG timing, please refer to HX8369-A00 application note.

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5.15.1 Register loading detection

Sleep Out-command (See “Sleep Out (11h)”) is a trigger for an internal function of the
display module, which indicates, if the display module loading function of factory
default values from OTP (or similar device) to registers of the display controller is
working properly. There are compared factory values of the OTP and register values
of the display controller by the display controller. If those both values (OTP and
register values) are same, there is inverted (=increased by 1) a bit, which is defined in
command “Read Display Self-Diagnostic Result (0Fh)” (=RDDSDR) (The used bit of
this command is D7). If those both values are not same, this bit (D7) is not inverted
(=increased by 1).
The flow chart for this internal function is following:

Figure 5.33: Sleep out flow chart–command and self-diagnostic functions

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Sleep Out-command (See “Sleep Out (11h)”) is a trigger for an internal function of the
display module, which indicates, if the display module is still running and meets
functionality requirements.
The internal function (=the display controller) is comparing, if the display module still
meets functionality requirements (e.g. booster voltage levels, timings, etc.). If
functionality requirement is met, 1 bit will be inverted (=increased by 1), which is
defined in command “Read Display Self- Diagnostic Result (0Fh)” (=RDDSDR) (The
used bit of this command is D6). If functionality requirement is not the same, this bit
(D6) is not inverted (=increased by 1). The flow chart for this internal function is shown
as below.

Power on sequence
Sleep In (10h) HW reset
SW reset

Sleep Out Sleep In

RDDSDR`s D6=0
Mode Mode

Sleep Out (11h)

Checks timings, voltage levels and other

functionalities

NO
Is functionality
requirement meet ?

YES

D6 inverted

Note: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In–mode
toSleep Out -mode, before there is possible to check if Customer’s functionality requirements are met and
a value of RDDSDR’s D6 is valid. Otherwise, there is 5msec delay for D6’s value, when Sleep
Out –command is sent in Sleep Out -mode.
Figure 5.34: Sleep out flow chart internal function detection

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VDD1, VDD2 and VDD3 can be applied in any order. VDD1, VDD2 and VDD3 can be
powered down in any order. During power off, if LCD is in the Sleep Out mode, VDD1
and VDD2 must be powered down minimum 120msec after RESX has been released.
During power off, if LCD is in the Sleep In mode, VDD1, VDD2 and VDD3 can be
powered down minimum 0msec after RESX has been released. CSX can be applied
at any timing or can be permanently grounded. RESX has priority over CSX. There
will be no damage to the display module if the power sequences are not met. There
will be no abnormal visible effects on the display panel during the Power On/Off
Sequences. There will be no abnormal visible effects on the display between end of
Power On Sequence and before receiving Sleep Out command. Also between
receiving Sleep In command and Power Off Sequence. If RESX line is not held stable
by host during Power On Sequence as defined in Sections 5.16.1 and 5.16.2, then it
will be necessary to apply a Hardware Reset (RESX) after Host Power On Sequence
is complete to ensure correct operation. Otherwise function is not guaranteed. The
power on/off sequence is illustrated below.

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If RESX line is held high or unstable by the host during power on, then a Hardware
Reset must be applied after both VDD1, VDD2 and VDD3 have been applied-
otherwise correct functionality is not guaranteed. There is no timing restriction upon
this hardware reset.

tRPW= +/- no limit tFPW= +/- no limit

VDD1

VDD2
VDD3 Time when the latter signal rises up to 90% of its typical value. Ex. When VCI comes latter.
This time is defined at the cross point of 90% of 2.5V/2.75V. Not 90% of 2.3V.

Time when the former signal falls down to 90% of its typical value. Ex. When VCI falls
earilier. This time is defined at the cross point of 90% of 2.5V/2.75V. Not 90% of 2.3V.

tRPWICS= +/- no limit tFPWICS= +/- no limit

CSX H or L

tRPWIRES= + no limit

tFPWIRES1= min 120ms

RESX
(Power down in sleep out mode)
tRPWIRES= + no limit

RESX
(Power down in sleep in mode) tFPWIRES2= min 0ns

tFPWIRES1 is applied to NRESET falling in the Sleep Out

Mode
tFPWIRES2 is applied to NRESET falling in the Sleep In
Mode

Figure 5.35: Case 1: RESX line is held high or unstable by host at power on

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If RESX line is held low (and stable) by the host during power on, then the RESX must
be held low for minimum 10µsec after both VDD1, VDD2 and VDD3 have been
applied.
tRPW= +/- no limit tFPW= +/- no limit

VDD1

VDD2
VDD3 Time when the latter signal rises up to 90% of its typical value. Ex. When VCI comes latter.
This time is defined at the cross point of 90% of 2.5V/2.75V. Not 90% of 2.3V.

Time when the former signal falls down to 90% of its typical value. Ex. When VCI falls
earilier. This time is defined at the cross point of 90% of 2.5V/2.75V. Not 90% of 2.3V.

tRPWICS= +/- no limit tFPWICS= +/- no limit

CSX H or L

tFPWIRES1= min 120ms

tRPWIRES= min 10us
RESX
(Power down in sleep out mode)

tRPWIRES= min 10us

RESX
(Power down in sleep tFPWIRES2= min 0ns
in mode)

tFPWIRES1 is applied to NREST falling in the Sleep Out Mode

tFPWIRES2 is applied to NREST falling in the

Figure 5.36: Case 2: RESX line is held low by host at power on

5.17 Uncontrolled power off

The uncontrolled power off means a situation when e.g. there is removed a battery
without the controlled power off sequence. There will not be any damages for the
display module or the display module will not cause any damages for the host or lines
of the interface. At an uncontrolled power off the display will go blank and there will
not be any visible effects within 1 second on the display (blank display) and remains
blank until “Power On Sequence” powers it up.

Note: HX8369-A00 is support the noise reject filter (20ns) to reject spike or noise.

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The general block diagram of the CABC and the brightness control is illustrated
below:

External VSYNC, HSYNC,

ENABLE, DCK
(RGB interface) Display Control
Signal Generator

Display Data
Image data
Generator

Display Data C[1:0]= ‘00’ à off

Contents Analysis C[1:0]= ‘01’, ‘10’,
‘11’ à off

CABC Gain / Duty

CABC Block

DBV[7:0] (R52h)
(BL=0)

PWM_CLK Brightness Control PWM_OUT

PWM Clock Devider
(FoscD) Block (BL=1)

CABC[1:0] (R55h)
SAVEPOWER[6:0] (RC9h)
DBG0~8[6:0] (RCAh)
DBV[7:0] (R51h)
SEL_PWMCLK[2:0] C9h) BCTRL, BL(R53h)
CMB[7:0](R5Eh)
INVPLUS
SEL_BLDUTY
PWM_PERIOD
(RC9h)

Figure 5.37: CABC block diagram

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HX8369-A00 can support two module architectures for CABC operation. The BL bit
setting of R53h can be used to select used display module architecture. White LED
driver circuit for display backlight is located on the main PWB, not in the display
module both in architecture I and II.

• Architecture I

1. BL =`1` of R53h
2. LED backlight brightness for the
CABC_ dis play i s c ontrol led by external
PWM_OUT
output “CABC_PWM_OUT”.

• Architecture II

1. BL =`0` of R53h
2. LED backlight brightness data for
the display is read with DBV[7:0] bits
of R52h.
3. Read commands R53h should be
synchronized with V-sync.

Figure 5.38: Module architecture

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There are DBG0~8[6:0] register bits in CABC block to define the “CABC gain”/ “CABC
duty” table. Every DBGx[6:0] has 33 gain/duty value setting.

After one-frame display data content analysis, LSI will generate one CABC gain /
CABC duty value calculated from DBG0~8[6:0] register bits setting (by using
interpolated method) for display data generating and for backlight PWM pulse
generating.

Please note that the CABC gain / CABC duty value calculated by the LSI is one of the
33 gain/duty value setting in DBGxx[6:0].

Please note that : Duty ( valid level period (LED on) / one complete period)=1/ gain.
DBG0

Gain curve
DBG1

DBG2

DBG3

DBG4
Gain
DBG5

SAVEPOWER DBG6
DBG7

DBG8

0 32 64 96 128 160 192 224 256

One frame display data

content analysis

Figure 5.39: CABC gain / CABC duty generation

For power saving of backlight module, there are SAVEPOWER[6:0] bits to define the
“minimum gain”/ “maximum duty” of CABC block output. If the CABC gain / duty after
one-frame display data contents analysis is smaller(gain) / larger(duty) than
SAVEPOWER[6:0] bits setting, the CABC block will output CABC gain / duty equal to
SAVEPOWER[6:0] and ignore the result of display data contents analysis.

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There is an external output signal from brightness block, CABC_PWM_OUT, to

control the LED driver IC in order to control display brightness.

There are resister bits, DBV[7:0] of R51h, for display brightness of manual brightness
setting. The CABC_PWM_OUT duty is calculated as (DBV[7:0])/255 x CABC duty
(generated after one-frame display data content analysis).

For ex: CABC_PWM_OUT period=2.95 ms, and DBV[7:0](R51h)=‘228DEC’ and

CABC duty is 74%. Then CABC_PWM_OUT duty=(228) / 255 x 74.42%≡66.54%.
Correspond to the CABC_PWM_OUT period=2.95 ms, the high-level of
CABC_PWM_OUT (high effective) = 1.96ms, and the low-level of CABC_PWM_OUT
=0.99ms.

One Period (tpw)

ON
CABC_
Display
PWM_OUT
Brightness
(INVPLUS=`1`)
OFF

Duty = 100% Duty = 100% Duty = 33% Duty = 66.57%

OFF Maximum

Figure 5.40: CABC_PWM_OUT output duty

Symbol Parameter Min. Max. Unit Description

tpw Pulse width 0.0333 8.33 ms -
Table 5.63 CABC timing table

Note1: The signal rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
Note2: The pulse width range by setting CABC related registers is locate between 0.0333ms to 8.33ms.

When Architecture II module is used (BL=’0’) with the example below, the
CABC_PWM_OUT is always output low and the DBV[7:0](R51h) will be read a value
as 169DEC ((169)/255≡ 66.27%).

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CABC function is automatically reduced backlight brightness based on image

contents. In the case of the combination with the CABC or manual brightness setting,
display brightness is too dark. It must affect to image quality degradation. CABC
minimum brightness setting (CMB[7:0] bits of R5Eh) is to avoid too much brightness
reduction.

When CABC is active, CABC can not reduce the display brightness to less than
CABC minimum brightness setting. Image processing function is worked as normal,
even if the brightness can not be changed.

This function does not affect to the other function, manual brightness setting. Manual
brightness can be set the display brightness to less than CABC minimum brightness.
Smooth transition and dimming function can be worked as normal.

When display brightness is turned off (BCTRL=’0’ of R53h), CABC minimum

brightness setting is ignored. “CMB[7:0], Read CABC minimum brightness
(R5Fh)“ always read the setting value of “CMB[7:0], Write CABC minimum brightness
(R5Eh)”

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5.19.1 OTP table

OTP_INDEX Ref.
B7 B6 B5 B4 B3 B2 B1 B0
(HEX) Command
00 SETOSC (B0h) NVALID0 - - - UADJ[3:0]
1B NVALID_VCMF1 NVALID_VCMF2 NVALID_VCMF3 NVALID_VCMB1 NVALID_VCMB2 NVALID_VCMB3 - -
1C VCMC_F1[7:0]
1D VCMC_B1[7:0]
1E SETVCOM (B6h) VCMC_F2[7:0]
1F VCMC_B2[7:0]
20 VCMC_F3[7:0]
21 VCMC_B3[7:0]
22 ID1_1[7:0]
23 NVALID_ID1 ID2_1[6:0]
24 ID3_1[7:0]
25 ID1_2[7:0]
26 NVALID_ID2 ID2_2[6:0]
27 ID3_2[7:0]
28 ID1_3[7:0]
29 SETID (C3h) NVALID_ID3 ID2_3[6:0]
2A ID3_3[7:0]
2B ID1_4[7:0]
2C NVALID_ID4 ID2_4[6:0]
2D ID3_4[7:0]
2E ID1_5[7:0]
2F NVALID_ID5 ID2_5[6:0]
30 ID3_5[7:0]
31 NVALID8 FS1[2:0] - AP[2:0]
32 - - - - BT[3:0]
33 DT[1:0] - - DCDIV[3:0]
34 - - - BTP[4:0]
35 - - - BTN[4:0]
36 VRHP[7:0]
37 VRHN[7:0]
38 - - VRMP[5:0]
39 SETPOWER (B1h) - - VRMN[5:0]
3A - - DD_TU VPNL_EN - VBS[2:0]
3B - DC86_DIV3 DC86_DIV2 DC86_DIV1 DC86_DIV0 XDK1 XDK0 AUTO_XDK
3C - DTPS[2:0] - DTNS[2:0]
3D A_DC[1:0] A_DTP[2:0] A_DTN[2:0]
3E B_DC[1:0] B_DTP[2:0] B_DTN[2:0]
3F C_DC[1:0] C_DTP[2:0] C_DTN[2:0]
40 D_DC[1:0] D_DTP[2:0] D_DTN[2:0]
41 E_DC[1:0] E_DTP[2:0] E_DTN[2:0]
42 NVALID9 - - - NW_PE[1:0] NW[1:0]
43 SON[7:0]
44 SETCYC (B4h) SOFF[7:0]
45 EQS[7:0]
46 EQON[7:0]
47 SETPANEL (CCh) NVALID10 VPL HPL EPL SS_PANEL DPL REV_PANEL BGR_PANEL
48 SETDISP (B2h) NVALID11 RES_SEL[2:0] RM DFR DM[1:0]
49 BP [7:0]
4A FP [7:0]
4B SAP[3:0] - - - -
4C GEN_ON[7:0]
4D GEN_OFF[7:0]
4E RTN[7:0]
4F - - - - TEI[3:0]

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OTP_KEY0[7:0]
Description Note
OTP_KEY1[7:0]

OTP_KEY0[7:0] = 0xAAh
Enter OTP program mode
OTP_KEY1[7:0] = 0x55h

OTP_KEY0[7:0] = 0x00h
Leave OTP program mode
OTP_KEY1[7:0] = 0x00h

1. If HX8369-A01 operate on OTP

program mode, then keep on OTP
program mode.
Other value Invalid
2. If HX8369-A01 operate on
non-OTP program mode, then
keep on non-OTP program mode.

Figure 5.41: OTP programming sequence

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This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
5.19.3 Programming sequence

Step Operation
1 Power on and reset the module.
2 SLPOUT and set 0xB9h = 0xFFh, 0x83h, 0x69h to access the extension commands.
Set VGH power to 7.5V for OTP programming state for using internal power mode.
3
Or using the external power 7.5V to VPP.
4 Write optimized values to related registers.
5 Set OTP_KEY1[7:0] (RE9h)=0xAAh and OTP_KEY1[7:0] (RE9h)=0x55h to enter OTP program mode.
6 Specify OTP_index, please refer to the OTP table.
7 Set OTP_Mask=0x00h, programming the entire bit of one parameter.
8 Set OTP_PROG=1, Internal register begin write to OTP according to OTP_index.
9 Wait 5 ms (Note 1)
10 Set OTP_PROG=0, OTP_index programming action done.
Complete programming one parameter to OTP. If continue to programming other parameter, return to
11 step (5). Otherwise, set OTP_KEY1[7:0] (RE9h)=0x00h and OTP_KEY1[7:0] (RE9h)=0x00h to leave
OTP program mode and power off the module and remove the external power on VPP pin.
Note1: When do the OTP programming process, it must be added 5ms delay time after setting OTP_PROG=1.

Table 5.64: OTP Programming sequence

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OTP Program Flow

H/W Reset + SLPOUT Set OTP index 0x1Dh for VCMC_B1[7:0]

Set CMD 0xBBh
1st parameter 0x00h
2nd parameter 0x00h
3rd parameter 0x1Dh
Set extension commands 4th parameter 0x00h
Set CMD 0xB9h
1st parameter 0xFFh
2nd parameter 0x83h
3rd parameter 0x69h
Set OTP_PROG=1 for programming action
Set CMD 0xBBh
1st parameter 0x00h
2nd parameter 0x00h
Using External power 7.5V to VPP 3rd parameter 0x1Dh
4th parameter 0x01h

Write optimized VCOM value of

OTP programming action done

Set CMD 0xBBh
Set OTP_KEY0[7:0] = 0xAAh 1st parameter 0x00h
OTP_KEY1[7:0] = 0x55h 2nd parameter 0x00h
Set CMD 0xE9h 3rd parameter 0x1Dh
1st parameter 0xAAh 4th parameter 0x00h
2nd parameter0x55h

Set OTP index 0x1Ch for VCMC_F1[7:0] OTP_KEY0[7:0] = 0x00h

Set CMD 0xBBh OTP_KEY1[7:0] = 0x00h
1st parameter 0x00h Set CMD 0xE9h
2nd parameter 0x00h 1st parameter 0x00h
3rd parameter 0x1Ch 2nd parameter0x00h
4th parameter 0x00h

Reset IC for OTP relaod

Set OTP_PROG=1 for programming action
Set CMD 0xBBh
1st parameter 0x00h
2nd parameter 0x00h
3rd parameter 0x1Ch
4th parameter 0x01h END

Delay 5ms

OTP programming action done

Set CMD 0xBBh
1st parameter 0x00h
2nd parameter 0x00h
3rd parameter 0x1Ch
4th parameter 0x00h

Figure 5.42: OTP programming sequence example 1.

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OTP Program Flow

H/W Reset + SLPOUT (command 0x11h) OTP_KEY0[7:0] = 0x00h

OTP_KEY1[7:0] = 0x00h
Set CMD 0xE9h
1st parameter 0x00h
2nd parameter0x00h
Set extension commands
Set CMD 0xB9h
1st parameter 0xFFh
2nd parameter 0x83h
3rd parameter 0x69h
Reset IC for OTP relaod

Using External power 7.5V to VPP

END

Set ID1, ID2 and ID3 values

Set CMD 0xC3h
1st parameter 0x##h (ID1)
2nd parameter0x##h (ID2)
2nd parameter0x##h (ID3)

Set OTP_KEY0[7:0] = 0xAAh

OTP_KEY1[7:0] = 0x55h
Set CMD 0xE9h
1st parameter 0xAAh
2nd parameter0x55h

Set OTP index 0x22h for ID1[7:0], ID2[6:0]

and ID3[7:0]
Set CMD 0xBBh
1st parameter 0x00h
2nd parameter 0x00h
3rd parameter 0x22h
4th parameter 0x00h

Set OTP_PROG=1 for programming action

Set CMD 0xBBh
1st parameter 0x00h
2nd parameter 0x00h
3rd parameter 0x22h
4th parameter 0x01h

Delay 5ms

OTP index 0x22h, 0x23h and 0x24h

OTP programming action done
Set CMD 0xBBh
1st parameter 0x00h
2nd parameter 0x00h
3rd parameter 0x22h
4th parameter 0x00h

Figure 5.43: OTP programming sequence example 2.

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OTP_index 0x1Bh value 1st VCOM OTP 2nd VCOM OTP 3rd VCOM OTP
D7 NVALID_VCMF1 1 0 0 0
D6 NVALID_VCMF2 1 1 0 0
D5 NVALID_VCMF3 1 1 1 0
D4 NVALID_VCMB1 1 0 0 0
D3 NVALID_VCMB2 1 1 0 0
D2 NVALID_VCMB3 1 1 1 0
0x1Bh value 0xFFh 0x6Fh 0x27h 0x03h
Reload OTP index Default 0x1Ch and 0x1Dh 0x1Eh and 0x1Fh 0x20h and 0x21h

Figure 5.44: OTP programming sequence index 0x1Bh read flow.

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Figure 5.45: OTP programming sequence read flow.

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The HX8369-A00 has the calibration scheme that including Gain and Offset Control to
compensate the Temperature Sensor.

The temperature sensor control block diagram as below.

Figure 5.46: Temperature sensor

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6.1.1 Standard command

Operation Default
(Hex) D/CX RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 Function RGB
code (Hex)
00 NOP 0 1 ↑ 0 0 0 0 0 0 0 0 No Operation - Yes
Software
01 SWRESET 0 1 ↑ 0 0 0 0 0 0 0 1 - Yes
Reset
Read Number
0 1 ↑ 0 0 0 0 0 1 0 1 of DSI Parity - -
05 RDNUMPE Error
1 ↑ 1 x x x x x x x x Dummy read - -
1 ↑ 1 P[7:0] - - -
Read Red
0 1 ↑ 0 0 0 0 0 1 1 0 - Yes
Colour
06 RDRED
1 ↑ 1 x x x x x x x x Dummy read - -
1 ↑ 1 R7 R6 R5 R4 R3 R2 R1 R0 xx - -
Read Green
0 1 ↑ 0 0 0 0 0 1 1 1 - Yes
Colour
07 RDGREEN
1 ↑ 1 x x x x x x x x Dummy read - -
1 ↑ 1 G7 G6 G5 G4 G3 G2 G1 G0 xx - -
Read Blue
0 1 ↑ 0 0 0 0 1 0 0 0 - Yes
Colour
08 RDBLUE
1 ↑ 1 x x x x x x x x Dummy read - -
1 ↑ 1 B7 B6 B5 B4 B3 B2 B1 B0 xx - -
Read display
0 1 ↑ 0 0 0 0 1 0 1 0 - Yes
power mode
0A RDDPM
1 ↑ 1 x x x x x x x x Dummy read - -
1 ↑ 1 D7 D6 D5 D4 D3 D2 0 0 - - -
Read display
0 1 ↑ 0 0 0 0 1 0 1 1 - Yes
MADCTL
0B RDDMADCTL
1 ↑ 1 x x x x x x x x Dummy read - -
1 ↑ 1 D7 D6 D5 D4 D3 D2 0 0 - - -
Read display
0 1 ↑ 0 0 0 0 1 1 0 0 - Yes
pixel format
0C RDDCOLMOD
1 ↑ 1 x x x x x x x x Dummy read - -
1 ↑ 1 - D6 D5 D4 - D2 D1 D0 - - -
Read display
0 1 ↑ 0 0 0 0 1 1 0 1 - Yes
image mode
0D RDDIM
1 ↑ 1 x x x x x x x x Dummy read - -
1 ↑ 1 D7 D6 D5 0 0 D2 D1 D0 - - -
Read display
0 1 ↑ 0 0 0 0 1 1 1 0 - Yes
signal mode
0E RDDSM
1 ↑ 1 x x x x x x x x Dummy read - -
1 ↑ 1 D7 D6 0 0 0 0 0 0 - - -
Read display
0 1 ↑ 0 0 0 0 1 1 1 1 self-diagnostic - Yes
0F RDDSDR result
1 ↑ 1 x x x x x x x x Dummy read - -
1 ↑ 1 D7 D6 D5 D4 0 0 0 0 - - -

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Operation Default
(Hex) D/CX RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 Function RGB
Code (Hex)
10 SLPIN 0 1 ↑ 0 0 0 1 0 0 0 0 Sleep In - Yes
11 SLPOUT 0 1 ↑ 0 0 0 1 0 0 0 1 Sleep Out - Yes
12 PTLON 0 1 ↑ 0 0 0 1 0 0 1 0 Partial Mode On - No
Normal display
13 NORON 0 1 ↑ 0 0 0 1 0 0 1 1 - No
mode on
Display inversion
20 INVOFF 0 1 ↑ 0 0 1 0 0 0 0 0 - No
off
Display inversion
21 INVON 0 1 ↑ 0 0 1 0 0 0 0 1 - No
on
0 1 ↑ 0 0 1 0 0 1 1 0 Gamma set - Yes
26 GAMSET
1 1 ↑ GC7 GC6 GC5 GC4 GC3 GC2 GC1 GC0 - -
28 DISPOFF 0 1 ↑ 0 0 1 0 1 0 0 0 Display off - Yes
29 DISPON 0 1 ↑ 0 0 1 0 1 0 0 1 Display on - Yes
Column Address
0 1 ↑ 0 0 1 0 1 0 1 0 - No
Set
Column address
1 1 ↑ SC15 SC14 SC13 SC12 SC11 SC10 SC9 SC8 - -
start
2A CASET Column address
1 1 ↑ SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0 - -
start
Column address
1 1 ↑ EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8 - -
end
Column address
1 1 ↑ EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 - -
end
0 1 ↑ 0 0 1 0 1 0 1 1 Row address set - No
Row address
1 1 ↑ SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 - -
start
Row address
1 1 ↑ SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 - -
2B PASET start
Row address
1 1 ↑ EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 - -
end
Row address
1 1 ↑ EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 - -
end
0 1 ↑ 0 0 1 0 1 1 0 0 Memory Write - No
1 1 ↑ D17 D16 D15 D14 D13 D12 D11 D10 Write data
2C RAMWR
1 1 ↑ Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 Write data -
1 1 ↑ Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 Write data -
0 1 ↑ 0 0 1 0 1 1 0 1 Color Set - Yes
1 1 ↑ R007 R006 R005 R004 R003 R002 R001 R000 Red tone - -
1 1 ↑ Rnn7 Rnn6 Rnn5 Rnn4 Rnn3 Rnn2 Rnn1 Rnn0 Red tone - -
1 1 ↑ R637 R636 R635 R634 R633 R632 R631 R630 Red tone - -
1 1 ↑ G007 G006 G005 G004 G003 G002 G001 G000 Green tone - -
2D RGBSET
1 1 ↑ Gnn7 Gnn6 Gnn5 Gnn4 Gnn3 Gnn2 Gnn1 Gnn0 Green tone - -
1 1 ↑ G637 G636 G635 G634 G633 G632 G631 G630 Green tone - -
1 1 ↑ B007 B006 B005 B004 B003 B002 B001 B000 Blue tone - -
1 1 ↑ Bnn7 Bnn6 Bnn5 Bnn4 Bnn3 Bnn2 Bnn1 Bnn0 Blue tone - -
1 1 ↑ B637 B636 B635 B634 B633 B632 B631 B630 Blue tone - -
0 1 ↑ 0 0 1 0 1 1 1 0 Memory read - No
1 ↑ 1 X X X X X X X X Dummy read - -
2E RAMRD 1 ↑ 1 D17 D16 D15 D14 D13 D12 D11 D10 Read data - -
1 ↑ 1 Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 Read data - -
1 ↑ 1 Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 - - -
0 1 ↑ 0 0 1 1 0 0 0 0 Partial Area - No
1 1 ↑ SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 Start row - -
30 PLTAR 1 1 ↑ SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 Start row - -
1 1 ↑ ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 End row - -
1 1 ↑ ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 End row - -

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Operation Default
(Hex) D/CX RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 Function RGB
Code (Hex)
Vertical scrolling
0 1 ↑ 0 0 1 1 0 0 1 1 - No
definition
1 1 ↑ TFA[15:8] - - -
1 1 ↑ TFA[7:0] - - -
33 VSCRDEF
1 1 ↑ VSA[15:8] - - -
1 1 ↑ VSA[7:0] - - -
1 1 ↑ BFA[15:8] - - -
1 1 ↑ BFA[7:0] - - -
Tearing Effect
34 TEOFF 0 1 ↑ 0 0 1 1 0 1 0 0 - No
Line OFF
Tearing Effect
0 1 ↑ 0 0 1 1 0 1 0 1 - No
35 TEON Line ON
1 1 ↑ X X X X X X X M - - -
Memory Access
0 1 ↑ 0 0 1 1 0 1 1 0 - Yes
36 MADCTL Control
1 1 ↑ B7 B6 B5 B4 B3 B2 X X - - -
Vertical scrolling
0 1 ↑ 0 0 1 1 0 1 1 1 - No
start address
37 VSCRSADD
1 1 ↑ VSP[15:8] - - -
1 1 ↑ VSP[7:0] - - -
38 IDMOFF 0 1 ↑ 0 0 1 1 1 0 0 0 Idle mode off - No
39 IDMON 0 1 ↑ 0 0 1 1 1 0 0 1 Idle mode on - No
0 1 ↑ 0 0 1 1 1 0 1 0 - - Yes
3A COLMOD
1 1 ↑ X D6 D5 D4 X D2 D1 D0 - - -
0 1 ↑ 0 0 1 1 1 1 0 0 Memory write - No
1 1 ↑ D17 D16 D15 D14 D13 D12 D11 D10 - - -
3C RAMWRCON
1 1 ↑ Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 - - -
1 1 ↑ Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 - - -
0 1 ↑ 0 0 1 1 1 1 1 0 Memory read - No
1 ↑ 1 X X X X X X X X Dummy read - -
3E RAMRDCON 1 ↑ 1 D17 D16 D15 D14 D13 D12 D11 D10 - - -
1 ↑ 1 Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 - - -
1 ↑ 1 Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 - - -
0 1 ↑ 0 1 0 0 0 1 0 0 TESL - Yes
44 TESL 1 1 ↑ TELINE[15:8](8’b0) - - -
1 1 ↑ TELINE[7:0](8’b0) - - -
Reture the current
0 1 ↑ 0 1 0 0 0 1 0 1 scanline - No
45 GETSCAN SLN[15:0]
1 1 ↑ SLN[15:8] - - -
1 1 ↑ SLN[7:0] - - -
Write Display
0 1 ↑ 0 1 0 1 0 0 0 1 - Yes
51 WRDISBV Brightness
1 1 ↑ DBV[7:0] - - -
Read Display
0 1 ↑ 0 1 0 1 0 0 1 0 - Yes
Brightness Value
52 RDDISBV
1 ↑ 1 xx xx xxxx xx xx xx xx Dummy read - -
1 ↑ 1 DBV[7:0] - - -
0 1 ↑ 0 1 0 1 0 0 1 1 Write CTRL - Yes
53 WRCTRLD
1 1 ↑ xx xx BCTRL xx DD BL xx xx Display - -
Read Control
0 1 ↑ 0 1 0 1 0 0 1 1 - Yes
Value Display
54 RDCTRLD
1 ↑ 1 xx xx xx xx xx xx xx xx Dummy read - -
1 ↑ 1 0 0 BCTRL 0 DD BL 0 0 - - -
Write Adaptive
0 1 ↑ 0 1 0 1 0 1 0 1 Brightness - Yes
55 WRCABC
Control
1 1 ↑ xx xx xx xx xx xx CABC[1:0] - - -
Read Adaptive
0 1 ↑ 0 1 0 1 0 1 1 0 Brightness - Yes
56 RDCABC Control Content
1 ↑ 1 XX XX XX XX XX XX XX XX Dummy read - -
1 ↑ 1 0 0 0 0 0 0 C1 C0 - - -

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Operation Default
(Hex) D/CX RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 Function RGB
Code (Hex)
Write CABC
0 1 ↑ 0 1 0 1 1 1 1 0 minimum - Yes
5E WRCABCMB
brightness
1 1 ↑ CMB[7:0] - - -
Read CABC
0 1 ↑ 0 1 0 1 1 1 1 1 minimum - Yes
5F RDCABCMB brightness
1 ↑ 1 - XX XX XX XX XX XX XX Dummy read - -
1 ↑ 1 CMB[7:0] - - -
Read Automatic
Brightness Control
0 1 ↑ 0 1 1 0 1 0 0 0 - Yes
Self-Diagnostic
68 RDABCSDR
Result
1 ↑ 1 XX XX XX XX XX XX XX XX - - -
1 ↑ 1 D[7:6] 0 0 0 0 0 0 - - -
0 ↑ 1 1 1 0 1 1 0 1 0 Read ID1 - Yes
DA RDID1 1 1 ↑ XX XX XX XX XX XX XX XX Dummy read - -
1 1 ↑ module’s manufacturer[7:0] - - -
0 ↑ 1 1 1 0 1 1 0 1 1 Read ID2 - Yes
DB RDID2 1 1 ↑ XX XX XX XX XX XX XX XX Dummy read - -
1 1 ↑ 1 LCD module/driver version [6:0] - - -
0 ↑ 1 1 1 0 1 1 1 0 0 Read ID3 - Yes
DC RDID3 1 1 ↑ XX XX XX XX XX XX XX XX Dummy read - -
1 1 ↑ LCD module/driver ID[7:0] - - -
Read the DDB
0 1 ↑ 1 0 1 0 0 0 0 1 from the provided - Yes
location.
A1 Read_DDB_start 1 ↑ 1 XX XX XX XX XX XX XX XX Dummy read - -
1 ↑ 1 x x x x x x x x - - -
1 ↑ 1 x x x x x x x x - - -
1 ↑ 1 x x x x x x x x - - -
Continue reading
the DDB from
0 1 ↑ 1 0 1 0 1 0 0 0 - Yes
the last read
location.
A8 Read_DDB_continue
1 ↑ 1 XX XX XX XX XX XX XX XX Dummy read - -
1 ↑ 1 x x x x x x x x - - -
1 ↑ 1 x x x x x x x x - - -
1 ↑ 1 x x x x x x x x - - -
Note: (1) Undefined commands are treated as NOP (00h) command.
(2) B0h to D8h and E0h to FFh are for factory use of display supplier.

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User define command list is available only set “SETEXC” command.

Operation Default
(Hex) DCX RDX WRX D7 D6 D5 D4 D3 D2 D1 D0 Function
Code (Hex)
Set
0 1 ↑ 1 0 1 1 0 0 0 0 Internal -
B0 SETOSC oscillator
1 1 ↑ - - - - - - - OSC_EN - (00h)
1 1 ↑ - - - - UADJ[3:0] - (0Bh)
Set power
0 1 ↑ 1 0 1 1 0 0 0 1 related -
setting
1 1 ↑ VBIAS_EN VSN_EN VSP_EN VGL_EN VGH_EN LVGL_EN VDDDN_HZ STB - (01h)
1 1 ↑ - - - - - - - DSTB - (00h)
1 1 ↑ - FS1[2:0] - AP[2:0] - (34h)
1 1 ↑ - - - - BT[3:0] - (07h)
1 1 ↑ DT[1:0] - - DCDIV[3:0] - (00h)
1 1 ↑ - - - BTP[4:0] - (0Eh)
1 1 ↑ - - - BTN[4:0] - (0Eh)
1 1 ↑ VRHP[7:0] - (21h)
B1 SETPOWER 1 1 ↑ VRHN[7:0] - (29h)
1 1 ↑ - - VRMP[5:0] - (19h)
1 1 ↑ - - VRMN[5:0] - (19h)
1 1 ↑ - - DD_TU VPNL_EN - VBS[2:0] - (07h)
1 1 ↑ - DC86_DIV3 DC86_DIV2 DC86_DIV1 DC86_DIV0 XDK1 XDK0 AUTO_XDK - (22h)
1 1 ↑ - DTPS[2:0] - DTNS[2:0] - (01h)
1 1 ↑ A_DC[1:0] A_DTP[2:0] A_DTN[2:0] - (E6h)
1 1 ↑ B_DC[1:0] B_DTP[2:0] B_DTN[2:0] - (E6h)
1 1 ↑ C_DC[1:0] C_DTP[2:0] C_DTN[2:0] - (E6h)
1 1 ↑ D_DC[1:0] D_DTP[2:0] D_DTN[2:0] - (E6h)
1 1 ↑ E_DC[1:0] E_DTP[2:0] E_DTN[2:0] - (E6h)
Set display
0 1 ↑ 1 0 1 1 0 0 1 0 related -
register
1 1 ↑ - - - - - - D[1:0] - (00h)
1 1 ↑ - RES_SEL[2:0] RM DFR DM[1:0](1) - (10h)
1 1 ↑ BP [7:0] - (03h)
1 1 ↑ FP [7:0] - (03h)
1 1 ↑ SAP[3:0] - - - - - (70h)
1 1 ↑ GEN_ON[7:0] - (00h)
B2 SETDISP 1 1 ↑ GEN_OFF[7:0] - (FFh)
1 1 ↑ RTN[7:0] - (00h)
1 1 ↑ - - - - TEI[3:0] - (00h)
1 1 ↑ - - - - - - TEP[9:8] - (00h)
1 1 ↑ TEP[7:0] - (00h)
1 1 ↑ BP_PE [7:0] - (03h)
1 1 ↑ FP_PE [7:0] - (03h)
1 1 ↑ RTN_PE[7:0] - (03h)
1 1 ↑ - - - - - - - GON - (01h)
Note: (1) When BS[3:0]=1101, 1110, 1111 DM[1:0] default =11
- - - - - Other condition, DM[1:0] default =00
- -
Set RGB
interface
0 1 ↑ 1 0 1 1 0 0 1 1
related
-
B3 SETRGBIF
register)
1 1 ↑ - - - - DPL HSPL VSPL EPL (01h)
Set Display
0 1 ↑ 1 0 1 0 0 1 0 0 waveform -
cycles
1 1 ↑ - - - - NW_PE[1:0] NW[1:0] - (00h)
B4 SETCYC 1 1 ↑ SON[7:0] - (0Fh)
1 1 ↑ SOFF[7:0] - (82h)
1 1 ↑ EQS[7:0] - (0Ch)
1 1 ↑ EQON[7:0] - (03h)

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1 1 ↑ - - - - - - DITH_OPT DGC_EN - -
C1 SETDGCLUT
1 1 ↑ D1[7:0] - -
1 1 ↑ Dn[7:0] - -
1 1 ↑ D126[7:0] - -
0 1 ↑ 1 1 0 0 0 0 1 1 Set ID -
SETID 1 1 ↑ ID1[7:0] - (00h)
C3
(OTPx5) 1 1 ↑ 0 ID2[6:0] - (00h)
1 1 ↑ ID3[7:0] - (00h)
Set CABC
0 1 ↑ 1 1 0 0 1 0 0 1
Control
EN_DIM_MI EN_COST_ EN_NLN_G
1 1 ↑ - -
X MEAN
EN_COST
AIN
EN_JUDGE EN_TEMP (3Eh)

1 1 ↑ CABC_DD SAVEPOWER[6:0] (00h)

1 1 ↑ MEAN_OFFSET[7:0] (00h)
C9 SETCABC 1 1 ↑ - - - - CABC_FLM[3:0] (01h)
1 1 ↑ - SEL_PWMCLK[2:0] SEL_GAIN[1:0] INVPULS SEL_BLDUTY (2Fh)
1 1 ↑ PWM_PERIOD[7:0] (2Bh)
1 1 ↑ - DIM_FRAME[6:0] (1Eh)
1 1 ↑ CABC_STEP[7:0] (1Eh)
1 1 ↑ CABC_CLKEN[7:0] (00h)
Set panel
0 1 ↑ 1 1 0 0 1 1 0 0 related
CC SETPANEL register
BGR_PANE
1 1 ↑ - - - - SS_PANEL - REV_PANE
L
- (02h)
SET GIP
D5 SETGIP 0 1 ↑ 1 1 0 1 0 1 0 1
control
1 1 ↑ - - - - SHR_0[11:8] - (00h)
1 1 ↑ SHR_0[7:0] - (02h)
1 1 ↑ - - - - SHR_1[11:8] - (00h)
1 1 ↑ SHR_1[7:0] - (01h)
1 1 ↑ SPD[7:0] - (02h)
1 1 ↑ CHR[7:0] - (03h)
1 1 ↑ CON[7:0] - (20h)
1 1 ↑ COFF[7:0] - (6Ch)
1 1 ↑ SHP[3:0] SCP[3:0] - (03h)
1 1 ↑ CHP[3:0] CCP[3:0] - (03h)
1 1 ↑ SOS_1[3:0] SOS_0[3:0] - (00h)
1 1 ↑ SOS_3[3:0] SOS_2[3:0] - (00h)
1 1 ↑ COS_1[3:0] COS_0[3:0] - (60h)
1 1 ↑ COS_3[3:0] COS_2[3:0] - (04h)
1 1 ↑ COS_5[3:0] COS_4[3:0] - (71h)
1 1 ↑ COS_7[3:0] COS_6[3:0] - (75h)
1 1 ↑ SOS_1_ML[3:0] SOS_0_ML[3:0] - (00h)
1 1 ↑ SOS_3_ML[3:0] SOS_2_ML[3:0] - (00h)
1 1 ↑ COS_1_ML[3:0] COS_0_ML[3:0] - (51h)
1 1 ↑ COS_3_ML[3:0] COS_2_ML[3:0] - (57h)
1 1 ↑ COS_5_ML[3:0] COS_4_ML[3:0] - (40h)

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SETCNCD/ Set/Get
FD 0 1 ↑ 1 1 1 1 1 1 0 1 Continue -
GETCNCD
Command

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6.2.1 NOP (00h)

NOP (No Operation)

00H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 0 0 0 0 0 0 00
Parameter NO PARAMETER
This command is an empty command; it does not have any effect on the display module.
Description However it can be used to terminate Frame Memory Write or Read as described in RAMWR
(Memory Write) and RAMRD (Memory Read) Commands.
Restriction -
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes

Default N/A
Flow Chart -

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SWRESET (Software Reset)

01H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ 1 0 0 0 0 0 0 0 1 01
Parameter NO PARAMETER
When the Software Reset command is written, it causes a software reset. It resets the
commands and parameters to their S/W Reset default values. (See default tables in each
Description
command description.) Note: The Frame Memory contents are unaffected by this command
It will be necessary to wait 5msec before sending new command following software reset.
The display module loads all display supplier’s factory default values to the registers during
this 5msec. If Software Reset is applied during Sleep Out mode, it will be necessary to wait
Restriction
120msec before sending Sleep out command. Software Reset Command cannot be sent
during Sleep Out sequence.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes

Default N/A

Legend

SWRESET
Red and Blue

Parameter
Display whole
blank screen

Display
Flow Chart

Action
Set Commands
to S/W Default
Value
Mode

Sequential
transfer
Sleep In Mode

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RDNUMPE (Read Number of the Parity Errors)

05H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 0 0 0 1 0 1 05
st
1 parameter 1 ↑ 1 - x x x x x x x x Dummy read
nd
2 parameter 1 ↑ 1 - P7 P6 P5 P4 P3 P2 P1 P0 xx
The first parameter is telling a number of the errors on DSI. The more detailed description of the bits is below.
P[6..0] bits are telling a number of the errors.
Description P[7] is set to ‘1’ if there is overflow with P[6..0] bits.
P[7..0] bits are set to ‘0’s (as well as RDDSM(0Eh)’s D0 is set ‘0’ at the same time) after there is sent the second
parameter information (The read function is completed).

Restriction SETEXTC turn on to enable this command

Default P[7:0] = 0x00h

DSI I/F Mode Legend

Command
RDNUMPE
(R05h)
Host
Parameter
Driver
Send 1st parameter
Display
Flow Chart

Action
RDDSM (R0Eh) 's D0 = '0'
P[7:0] = "00"h
Mode

Sequential
transfer

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RDRED (Read Red Colour)

06H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 0 0 0 1 1 0 06
st
1 parameter 1 ↑ 1 - x x x x x x x x Dummy read
nd
2 parameter 1 ↑ 1 - R7 R6 R5 R4 R3 R2 R1 R0 xx
The first parameter is telling red colour value of the first pixel of the frame
when there is used DPI I/F.
Description
16 bit format: R5 is MSB and R1 is LSB. R7, R6 and R0 are set to ‘0’.
18 bit format: R5 is MSB and R0 is LSB. R7 and R6 are set to ‘0’.
Restriction -
Status Availability
Register
Sleep Out Yes
Availability
Default R[7:0] = 0x00h

Flow Chart

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RDGREEN (Read Green Colour)

07H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 0 0 0 1 1 1 07
st
1 parameter 1 ↑ 1 - x x x x x x x x Dummy read
nd
2 parameter 1 ↑ 1 - G7 G6 G5 G4 G3 G2 G1 G0 xx
The first parameter is telling green colour value of the first pixel of the frame
Description when there is used DPI I/F.
16 and 18 bit formats: G5 is MSB and G0 is LSB. G7 and G6 are set to ‘0’.
Restriction -
Status Availability
Register
Sleep Out Yes
Availability
Default G[7:0] = 0x00h

Flow Chart

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RDBLUE (Read Blue Colour)

08H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 0 0 1 0 0 0 08
st
1 parameter 1 ↑ 1 - x x x x x x x x Dummy read
nd
2 parameter 1 ↑ 1 - B7 B6 B5 B4 B3 B2 B1 B0 xx
The first parameter is telling blue colour value of the first pixel of the frame
when there is used DPI I/F.
Description
16 bit format: B5 is MSB and B1 is LSB. B7, B6 and B0 are set to ‘0’.
18 bit format: B5 is MSB and B0 is LSB. B7 and B6 are set to ‘0’.
Restriction -
Status Availability
Register
Sleep Out Yes
Availability
Sleep In Yes
Default B[7:0] = 0x00h

Flow Chart

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RDDPM (Read Display Power Mode)

0AH
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 0 0 1 0 1 0 0A
st
1 parameter 1 ↑ 1 - x x x x x x x x Dummy read
nd
2 parameter 1 ↑ 1 - D7 D6 D5 D4 D3 D2 0 0 xx
This command indicates the current status of the display as described in the table below:
Bit Description Comment
D7 Not Defined Set to ‘0’
D6 Idle Mode On/Off -
D5 Partial Mode On/Off -
D4 Sleep In/Out -
D3 Display Normal Mode On/Off -
D2 Display On/Off -
D1 Not Defined Set to ‘0’
D0 Not Defined Set to ‘0’

Bits D7 for future use and are set to ‘0’.
Bit D6 – Idle Mode On/Off
Description ‘0’ = Idle Mode Off.
‘1’ = Idle Mode On.
Bit D5 – Partial Mode On/Off
‘0’ = Partial Mode Off.
‘1’ = Partial Mode On.
Bit D4 – Sleep In/Out
‘0’ = Sleep In Mode.
‘1’ = Sleep Out Mode.
Bit D3 – Display Normal Mode On/Off
‘0’ = Display Normal Mode Off.
‘1’ = Display Normal Mode On.
Bit D2 – Display On/Off
‘0’ = Display is Off.
‘1’ = Display is On.

Restrictions -
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes

Default D[7:0] = 0x08h

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RDDMADCTL (Read Display MADCTL)

0BH
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 0 0 1 0 1 1 0B
st
1 parameter 1 ↑ 1 - x x x x x x x x Dummy read
nd
2 parameter 1 ↑ 1 - D7 D6 D5 D4 D3 D2 0 0 xx
This command indicates the current status of the display as described in the table
below:
Bit Description Comment
D7 Page Address Order -
D6 Column Address Order -
D5 Page/Column Order -
D4 Line Address Order -
D3 RGB/BGR Order -
D2 Display Data Latch Order -
D1 Reserved Set to ‘0’
D0 Reserved Set to ‘0’

Bit D7 – Page Address Order

‘0’ = Top to Bottom (When MADCTL B7=’0’).
‘1’ = Bottom to Top (When MADCTL B7=’1’).
Bit D6 – Column Address Order
Description ‘0’ = Left to Right (When MADCTL B6=’0’).
‘1’ = Right to Left (When MADCTL B6=’1’).
Bit D5 – Page/Column Order
‘0’ = Normal (When MADCTL B5=’0’).
‘1’ = Roration (When MADCTL B5=’1’).
Note: For Bits D7 to D5, also refer to Section 5.3 MCU to memory write/read direction.
Bit D4 – Line Address Order
‘0’ = LCD Refresh Top to Bottom (When MADCTL B4=’0’).
‘1’ = LCD Refresh Bottom to Top (When MADCTL B4=’1’).
Bit D3 – RGB/BGR Order
‘0’ = RGB (When MADCTL B3=’0’).
‘1’ = BGR (When MADCTL B3=’1’).
Note: For Bits D4 and D3 also refer to Section 6.2.31 Set_address_mode (36h).
Bit D2 – Display Data Latch Data Order
‘0’ = LCD Refresh Left to Right (When MADCTL B2=’0’).
‘1’ = LCD Refresh Right to Left (When MADCTL B2=’1’).

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Flow Chart

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RDDCOLMOD (Read Display COLMOD)

0CH
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 0 0 1 1 0 0 0C
st
1 parameter 1 ↑ 1 - x x x x x x x x Dummy read
nd
2 parameter 1 ↑ 1 - - D6 D5 D4 - D2 D1 D0 xx
This command indicates the current status of the display as described in the table below:
Bit Description Comment
D7 Reserved Set to ‘0’
D6 -
D5 DPI Interface Pixel format -
D4 -
D3 Reserved Set to ‘0’
D2 -
D1 DBI Interface Pixel format -
D0 -

Bits D6, D5, D4 – DPI Interface Colour Pixel Format Definition

Bits D2, D1, D0 – DBI Interface Colour Pixel Format Definition.
For Setting pixel format, see section 6.2.35 Set_pixel_format (3Ah)”.
Description
D6 D5 D4
Interface Colour Format
D2 D1 D0
Not Defined 0 0 0
Not Defined 0 0 1
Not Defined 0 1 0
Not Defined 0 1 1
Not Defined 1 0 0
16 bit/pixel 1 0 1
18 bit/pixel 1 1 0
24 bit/pixel 1 1 1
If a particular interface, either DBI or DPI, is not used then the corresponding bits in the
parameter returned from the display module are undefined.
Restrictions -
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Default D[7:0] = 0x07h

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Description

MCU interface and memory are still working and the memory keeps its contents.

This command has no effect when module is already in sleep in mode. Sleep In Mode can
only be left by the Sleep Out Command (11h). It will be necessary to wait 5msec before
Restriction sending next command, this is to allow time for the supply voltages and clock circuits to
stabilize. It will be necessary to wait 120msec after sending Sleep Out command (when in
Sleep In Mode) before Sleep In command can be sent.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Default N/A
It takes 120msec to get into Sleep In mode after SLPIN command issued.

Flow Chart

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SLPOUT (Sleep Out)

11H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 0 1 0 0 0 1 11
Parameter NO PARAMETER
This command turns off sleep mode. In this mode the DC/DC converter is enabled, Internal
oscillator is started, and panel scanning is started.
Blank Memory
Out[1:960] STOP contents

VST etc.(V scanner control logic)

0V CHARGE
Description DC charge in the capacitor

DC:DC converter 0V

Reset pulse for circuit inside panel RESET

START
Internal Oscillator STOP

This command has no effect when module is already in sleep out mode. Sleep Out Mode can
only be left by the Sleep In Command (10h). It will be necessary to wait 5msec before sending
next command, this is to allow time for the supply voltages and clock circuits to stabilize. The
display module loads all display supplier’s factory default values to the registers during this
5msec and there cannot be any abnormal visual effect on the display image if factory default
Restriction
and register values are same when this load is done and when the display module is already
Sleep Out –mode.
The display module is doing self-diagnostic functions during this 5msec. It will be necessary to
alit 120msec after sending Sleep In command (when in Sleep Out mode) before Sleep Out
command can be sent.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes

Default N/A
It takes 120msec to become Sleep Out mode after SLPOUT command issued.

Flow Chart

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PTLON (Partial Mode On)

12H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 0 1 0 0 1 0 12
Parameter NO PARAMETER
This command turns on partial mode The partial mode window is described by
Description the “Set_partial_area” command (30H). To leave Partial mode, the
“Enter_norma_mode” command (13H) should be written.
Restrictions This command has no effect when Partial mode is active.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Default N/A
Flow Chart See Partial Area (30h)

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NORON (Normal Display Mode On)

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DISPOFF (Display Off)

28H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 0 1 0 0 0 28
Parameter NO PARAMETER
This command is used to enter into DISPLAY OFF mode. In this mode, the output from
Frame Memory is disabled and blank page inserted.
This command makes no change of contents of frame memory.
This command does not change any other status.
There will be no abnormal visible effect on the display.

Description

Restriction This command has no effect when module is already in display off mode.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Default N/A

Legend
Display On Command
Mode
Parameter

Display
Flow Chart DISPOFF
Action

Mode
Display Off
Mode Sequential
transfer

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DISPON (Display On)

29H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 0 1 0 0 1 29
Parameter NO PARAMETER
This command is used to recover from DISPLAY OFF mode. Output from the
Frame
Memory is enabled.
This command makes no change of contents of frame memory.
This command does not change any other status.

Description

Restriction This command has no effect when module is already in display on mode.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Default N/A

Flow Chart

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CASET (Column Address Set)

2AH
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 0 1 0 1 0 2A
st
1 parameter 1 1 ↑ - SC15 SC14 SC13 SC12 SC11 SC10 SC9 SC8 00..
nd
2 parameter 1 1 ↑ - SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0 Note 1
rd
3 parameter 1 1 ↑ - EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8 00 ..
th
4 parameter 1 1 ↑ - EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 Note 1
This command is used to define area of frame memory where MCU can access.
This command makes no change on the other driver status.
The values of SC[15:0] and EC[15:0] are referred when RAMWR command comes. Each value
represents one column line in the Frame Memory.
(Example)
SC[15:0] EC[15:0]
Description

SC[15:0] always must be equal to or less than EC[15:0]

Restriction Note 1: When SC[15:0] or EC[15:0] is greater than horizontal line (when MADCTL’s B5=0) or vertical
line (when MADCTL’s B5=1), data of out of range will be ignored.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

RES_SEL[2:0]=000, Resoultion 480RGBx864: SC[15:0] = 0x0000h, EC[15:0] = 0x01DFh

RES_SEL[2:0]=001, Resoultion 480RGBx854: SC[15:0] = 0x0000h, EC[15:0] = 0x01DFh
RES_SEL[2:0]=010, Resoultion 480RGBx800: SC[15:0] = 0x0000h, EC[15:0] = 0x01DFh
Default
RES_SEL[2:0]=011, Resoultion 480RGBx640: SC[15:0] = 0x0000h, EC[15:0] = 0x01DFh
RES_SEL[2:0]=100, Resoultion 360RGBx640: SC[15:0] = 0x0000h, EC[15:0] = 0x0167h
RES_SEL[2:0]=101, Resoultion 480RGBx720: SC[15:0] = 0x0000h, EC[15:0] = 0x01DFh
Legend
CASET
Command

1st & 2nd parameter SC[15:0] Parameter

3rd & 4th parameter EC[15:0]
Display
PASET
Action

1st & 2nd parameter SP[15:0] Mode

3rd & 4th parameter EP[15:0]
Flow Chart
Sequential
If needed

RAMWR transfer

Image Data
D1[15:0],D2[15:0],
¡K.,Dn[15:0]

Any Command

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PASET (Page Address Set)

2BH
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 0 1 0 1 1 2B
st
1 parameter 1 1 ↑ - SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 00 ..
nd
2 parameter 1 1 ↑ - SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Note 1
rd 00 ..
3 parameter 1 1 ↑ - EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8
Note 1
th
4 parameter 1 1 ↑ - EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0
This command is used to define area of frame memory where MCU can access.
This command makes no change on the other driver status.
The values of SP[15:0] and EP[15:0] are referred when RAMWR command comes.
Each value represents one Page line in the Frame Memory.

Description

SP[15:0] always must be equal to or less than EP[15:0]

Restriction Note 1: When SP[15:0] or EP[15:0] is greater than vertical line (When MADCTL’s B5=0) or horizontal
line (When MADCTL’s B5=1), data of out of range will be ignored.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes

RES_SEL[2:0]=000, Resoultion 480RGBx864: SP[15:0] = 0x0000h, EP[15:0] = 0x035Fh

RES_SEL[2:0]=001, Resoultion 480RGBx854: SP[15:0] = 0x0000h, EP[15:0] = 0x0355h
RES_SEL[2:0]=010, Resoultion 480RGBx800: SP[15:0] = 0x0000h, EP[15:0] = 0x031Fh
Default
RES_SEL[2:0]=011, Resoultion 480RGBx640: SP[15:0] = 0x0000h, EP[15:0] = 0x027Fh
RES_SEL[2:0]=100, Resoultion 360RGBx640: SP[15:0] = 0x0000h, EP[15:0] = 0x027Fh
RES_SEL[2:0]=101, Resoultion 480RGBx720: SP[15:0] = 0x0000h, EP[15:0] = 0x02CFh
IF Needed

Flow Chart
IF Needed

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RAMWR (Memory Write)

2CH
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 0 1 1 0 0 2C
st
1 parameter 1 1 ↑ - D17 D16 D15 D14 D13 D12 D11 D10 00..FF
: 1 1 ↑ - Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 00..FF
th
N parameter 1 1 ↑ - Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 00..FF
This command transfers image data from the host processor to the display module’s frame
memory starting at the pixel location specified by preceding set_column_address and
set_page_address commands.
The column and page registers are reset to the Start Column (SC) and Start Page (SP),
respectively.
Description Pixel Data 1 is stored in frame memory at (SC, SP). The column register is then incremented
and pixels are written to the frame memory until the column register equals the End Column
(EC) value. The column register is then reset to SC and the page register is incremented.
Pixels are written to the frame memory until the page register equals the End Page (EP)
value or the host processor sends another command.
If the number of pixels exceeds (EC – SC + 1) * (EP – SP + 1) the extra pixels are ignored.
Restriction In all colour modes, there is no restriction on length of parameters.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes

Default Contents of memory is set randomly and not cleared.

Legend
RAMWR Command

Parameter
Image Data
D1[7:0],D2[7:0], Display
...,Dn[7:0]
Flow Chart Action

Any Command Mode

Sequential
transfer

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COLSET (Colour Set)

2DH
DNC NRD NWR D8~D15 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 0 1 1 0 1 2D
st
1 parameter 1 1 ↑ - R007 R006 R005 R004 R003 R002 R001 R000 00..FF
: 1 1 ↑ - Rnn7 Rnn6 Rnn5 Rnn4 Rnn3 Rnn2 Rnn1 Rnn0 00..FF
th
64 parameter 1 1 ↑ - R637 R636 R635 R634 R633 R632 R631 R630 00..FF
th
65 parameter 1 1 ↑ - G007 G006 G005 G004 G003 G002 G001 G000 00..FF
: 1 1 ↑ - Gnn7 Gnn6 Gnn5 Gnn4 Gnn3 Gnn2 Gnn1 Gnn0 00..FF
th
128 parameter 1 1 ↑ - G637 G636 G635 G634 G633 G632 G631 G630 00..FF
th
129 parameter 1 1 ↑ - B007 B006 B005 B004 B003 B002 B001 B000 00..FF
: 1 1 ↑ - Bnn7 Bnn6 Bnn5 Bnn4 Bnn3 Bnn2 Bnn1 Bnn0 00..FF
nd
192 parameter 1 1 ↑ - B637 B636 B635 B634 B633 B632 B631 B630 00..FF
This command is used to define the LUT for 18bit to 24bit, 16bit-to-24bit colour depth conversions
colour depth conversions. 192bytes must be written to the LUT regardless of the colour mode.
Description
This command has no effect on other commands/parameters and Contents of frame memory.
Visible change takes effect next time the Frame Memory is written to.
This command is needed to be set in write_data for RGB 5-6-5 (65K colours) and RGB 6-6-6 (262K
colours) pixel format.
The default for command Colour Set (2Dh) is 0x00h. The colour depth conversion must be followed
the below tables.
Once write data is RGB 5-6-5 (65K colours), the set pixel format 0x3A=0x05h command must be set
and using the 16bit-to-24bit colour depth conversion.
RGBSET 24- bit /pixel LUT 24-bit /pixel
R-G-B=5-6-5 Input 16-bit /pixel
parameter mode value
1 R00[7:0] 00000000 00000
2 R01[7:0] 00001000 00001
3 R02[7:0] 00010000 00010
.. .. .. ..
.. .. .. ..
30 R29[7:0] 11101111 11101
31 R30[7:0] 11110111 11110
32 R31[7:0] 11111111 11111
R
33
34
35
..
Not Used Not Used Not Used
..
Restriction 62
63
64
65 G00[7:0] 00000000 000000
66 G01[7:0] 00000100 000001
67 G02[7:0] 00001000 000010
.. .. .. ..
G
.. .. .. ..
126 G61[7:0] 11110111 111101
127 G62[7:0] 11111011 111110
128 G63[7:0] 11111111 111111
129 B00[7:0] 00000000 00000
B
130 B01[7:0] 00001000 00001
131 B02[7:0] 00010000 00010
.. .. .. ..
.. .. .. ..
158 B29[7:0] 11101111 11101
159 B30[7:0] 11110111 11110
160 B31[7:0] 11111111 11111
161
Not Used Not Used Not Used
162
163
Himax Confidential -P.184-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
..
..
190
191
192

Once write data is RGB 5-6-5 (65K colours), the set pixel format 0x3A=0x06h command must be set
and using the 18bit-to-24bit colour depth conversion.
RGBSET 24- bit /pixel LUT 24-bit /pixel
R-G-B=6-6-6 Input 18-bit /pixel
parameter mode value
1 R00[7:0] 00000000 000000
2 R01[7:0] 00000100 000001
3 R02[7:0] 00001000 000010
.. .. .. ..
R
.. .. .. ..
62 R61[7:0] 11110111 111101
63 R62[7:0] 11111011 111110
64 R63[7:0] 11111111 111111
65 G00[7:0] 00000000 000000
66 G01[7:0] 00000100 000001
67 G02[7:0] 00001000 000010
.. .. .. ..
G
.. .. .. ..
126 G61[7:0] 11110111 111101
127 G62[7:0] 11111011 111110
128 G63[7:0] 11111111 111111
129 B00[7:0] 00000000 000000
130 B01[7:0] 00000100 000001
131 B02[7:0] 00001000 000010
.. .. .. ..
B
.. .. .. ..
190 B61[7:0] 11110111 111101
191 B62[7:0] 11111011 111110
192 B63[7:0] 11111111 111111
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default value

S/W Reset Contents of the look-up table protected
Default R00[7:0]~R63[7:0] =0x00h
H/W Reset G00[7:0]~G63[7:0] =0x00h
B00[7:0]~B63[7:0] =0x00h

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Flow Chart

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RAMRD (Memory Read)

2EH
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 0 1 1 1 0 2E
st
1 parameter 1 ↑ 1 - X X X X X X X X Dummy read
nd
2 parameter 1 ↑ 1 - D17 D16 D15 D14 D13 D12 D11 D10 00..FF
: 1 ↑ 1 - Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 00..FF
th
(n+1)
1 ↑ 1 - Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 00..FF
parameter
This command transfers image data from the display module’s frame memory to the host processor
starting at the pixel location specified by preceding set_column_address and set_page_address
commands.
The column and page registers are reset to the Start Column (SC) and Start Page (SP), respectively.
Description Pixels are read from frame memory at (SC, SP). The column register is then incremented and pixels
read from the frame memory until the column register equals the End Column (EC) value. The
column register is then reset to SC and the page register is incremented.
Pixels are read from the frame memory until the page register equals the End Page (EP) value or the
host processor sends another command.
In all colour modes, the Frame Read is always 24bit so there is no restriction on length of parameters.
Restriction
Note – Memory Read is only possible via the Parallel Interface.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Default Contents of memory is set randomly and not cleared.

Flow Chart

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PLTAR (Partial Area)

30H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 1 0 0 0 0 30
st
1 parameter 1 1 ↑ - SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 xx
nd
2 parameter 1 1 ↑ - SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 xx
rd
3 parameter 1 1 ↑ - ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 xx
th
4 parameter 1 1 ↑ - ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 xx
This command defines the partial mode’s display area. There are 4 parameters associated with this
command, the first defines the Start Row (SR) and the second the End Row (ER), as illustrated in
the figures below. SR and ER refer to the Frame Memory Line Pointer. If End Row>Start Row when
MADCTL B4=0:-

If End Row>Start Row when MADCTL B4=1:-

End Row

Description ER[15:0]

Partial Area

SR[15:0]
Start Row
If End Row<Start Row when MADCTL B4=0:-

End Row
ER[15:0]

Partial Area

SR[15:0]
Start Row
If End Row = Start Row then the Partial Area will be one row deep.
Restriction SR[15..0] and ER[15..0] cannot be greater than horizontal line number.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

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RES_SEL[2:0]=000, Resoultion 480RGBx864: SR[15:0] = 0x0000h, ER[15:0] = 0x035Fh

RES_SEL[2:0]=001, Resoultion 480RGBx854: SR[15:0] = 0x0000h, ER[15:0] = 0x0355h
RES_SEL[2:0]=010, Resoultion 480RGBx800: SR[15:0] = 0x0000h, ER[15:0] = 0x031Fh
Default
RES_SEL[2:0]=011, Resoultion 480RGBx640: SR[15:0] = 0x0000h, ER[15:0] = 0x027Fh
RES_SEL[2:0]=100, Resoultion 360RGBx640: SR[15:0] = 0x0000h, ER[15:0] = 0x027Fh
RES_SEL[2:0]=101, Resoultion 480RGBx720: SR[15:0] = 0x0000h, ER[15:0] = 0x02CFh
1. To Enter Partial Mode:-
Legend
PLTAR
Command

SR[15...0] Parameter

Display
ER[15...0]
Action

PTLON Mode

Sequential
Partial Mode transfer

2. To Leave Partial Mode

Flow Chart Partial Mode
(Optional)
DISPOFF To prevent
Tearing Effect
Image displayed
NORON

Partial Mode OFF

RAMRW

Image Data
D1[17:0],D2[17:0],
..., Dn[15:0]

DISPON

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VSCRDEF (Vertical Scrolling Definition)

33H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 1 0 0 1 1 33
st
1 parameter 1 1 ↑ - TFA15 TFA14 TFA13 TFA12 TFA11 TFA10 TFA9 TFA8 xx
nd
2 parameter 1 1 ↑ - TFA7 TFA 6 TFA 5 TFA 4 TFA 3 TFA 2 TFA1 TFA0 xx
rd
3 parameter 1 1 ↑ - VSA15 VSA14 VSA13 VSA12 VSA11 VSA10 VSA9 VSA8 xx
th
4 parameter 1 1 ↑ - VSA7 VSA 6 VSA 5 VSA 4 VSA 3 VSA 2 VSA1 VSA0 xx
th
5 parameter 1 1 ↑ - BFA15 BFA14 BFA13 BFA12 BFA11 BFA10 BFA9 BFA8 xx
th
6 parameter 1 1 ↑ - BFA7 BFA 6 BFA 5 BFA 4 BFA 3 BFA 2 BFA1 BFA0 xx
st nd
This command defines the Vertical Scrolling Area of the display. When MADCTL B4=0, the 1 & 2
parameter TFA[15..0] describes the Top Fixed Area (in No. of lines from top of the Frame Memory
rd th
and Display). The 3 & 4 parameter VSA[15..0] describes the height of the Vertical Scrolling Area (in
No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address). The first
line read from Frame Memory appears immediately after the bottom most line of the Top Fixed Area.
th th
The 5 & 6 parameter BFA[15..0] describes the Bottom Fixed Area (in No. of lines from Bottom of
the Frame Memory and Display). TFA, VSA and BFA refer to the Frame Memory Line Pointer.
(0 ,0 )
Top Fixed Area
TFA [ 15:0 ] First line read from
frame memory

Scroll Area

BFA [15:0]
Bottom Fixed Area
Description
When MADCTL B4=1
st nd
The 1 & 2 parameter TFA[15..0] describes the Top Fixed Area (in No. of lines from bottom of the
rd th
Frame Memory and Display). The 3 & 4 parameter VSA[15..0] describes the height of the Vertical
Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start
Address). The first line read from Frame Memory appears immediately after the top most line of the
th th
Top Fixed Area. The 5 & 6 parameter BFA[15..0] describes the Bottom Fixed Area (in No. of lines
from Top of the Frame Memory and Display).
Bottom Fixed Area
(0 ,0 )

BFA [15:0]

Scroll Area

TFA [ 15:0 ] First line read from

frame memory
Top Fixed Area
The condition is (TFA+VSA+BFA)= Vertical line number, otherwise Scrolling mode is undefined. In
Restriction
Vertical Scroll Mode, MADCTL B5 should be set to ‘0’ – this only affects the Frame Memory Write.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

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1.To enter Vertical Scroll Mode:

Normal Mode Legend
Command
VSCRDEF
Parameter
1st & 2nd Parameter TFA[15...0] Display

3rd & 4th Parameter VSA[15...0] Action

5th & 6th Parameter BFA[15...0] Mode

Sequential
CASET
transfer

1st & 2nd Parameter SC[15...0]

Redefines the Frame
3rd & 4th Parameter EC[15...0] Memory Window that
the scroll data will be
written to.
PASET See Note 1

Only 1st & 2nd Parameter SP[15...0]

required
Flow Charts for nonrolling 3rd & 4th Parameter EP[15..0]
scrolling
Optional ¡V It may be
MADCTL necessary to redefine
the Frame Memory
Parameter Write Direction.

RAMRW

Scroll Image
Data

VSCRSADD

1st & 2nd Parameter VSP[15...0]

Scroll Mode

Note: The Frame Memory Window size must be defined correctly otherwise undesirable
image will be displayed.

2. Continuous Scroll:

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Legend
Scroll Mode
Command

CASET Parameter

Display
1st & 2nd Parameter SC[15..0]
Action
3rd & 4th Parameter EC[15..0]
Mode
PASET
Sequential
transfer
1st & 2nd Parameter SP[15..0]

3rd & 4th Parameter EP[15..0]

RAMRW

Scroll Image
Data

VSCRSADD

1st & 2nd Parameter VSP[15..0]

3. To Leave Vertical Scroll Mode:

Note: Scroll Mode can be left by both the Normal Display Mode On (13h) and Partial
Mode On (12h) commands.

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TEOFF (Tearing Effect Line OFF)

34H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 1 0 1 0 0 34
Parameter NO PARAMETER
This command is used to turn OFF (Active Low) the Tearing Effect output signal
Description
from the TE signal line.
Restriction This command has no effect when Tearing Effect output is already OFF.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Default OFF

Flow Chart

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TEON (Tearing Effect Line ON)

35H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 1 0 1 0 1 35
Parameter 1 1 ↑ - X X X X X X X M xx
This command is used to turn ON the Tearing Effect output signal from the TE
signal
line. This output is not affected by changing MADCTL bit B4.
The Tearing Effect Line On has one parameter which describes the mode of the
Tearing Effect Output Line. (X=Don’t Care).
When M=0:
The Tearing Effect Output line consists of V-Blanking information only:
tvdl tvdh
Vertical Time
Scale
Description
When M=1:
The Tearing Effect Output Line consists of both V-Blanking and H-Blanking
information:
tvdl tvdh

Vertical Time
Scale

Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be
active Low.
Restriction This command has no effect when Tearing Effect output is already ON.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes

Default OFF
Legend

TE Line Output OFF Command

Parameter
TEON
Display

Flow Chart
M Action

Mode
TE Line Output ON
Sequential
transfer

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MADCTL (Memory Access Control)

36H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 1 0 1 1 0 36
st
1 parameter 1 1 ↑ - B7 B6 B5 B4 B3 B2 X X XX
This command defines read/write scanning direction of frame memory.
This command makes no change on the other driver status.

Bit Assignment
BIT NAME DESCRIPTION
B7 PAGE ADDRESS ORDER (MY)
These 3 bits controls MCU to memory
B6 COLUMN ADDRESS ORDER (MX)
write/read direction.
B5 PAGE/COLUMN SELECTION (MV)
B4 Vertical ORDER (ML) LCD vertical refresh direction control
Colour selector switch control
B3 RGB-BGR ORDER (BGR) (0=RGB colour filter panel, 1=BGR
colour filter panel)
B2 Horizontal ORDER (SS) LCD horizontal refresh direction control

RGB-BGR Order
Description B3= 0 B3= 1
RGB Driver IC RGB RG B Driver IC RGB
SIG1 SIG2 ………… SIG480 SIG1 SIG2 ………… SIG480

SIG1 SIG2 ………… SIG480 SIG1 SIG2 ………… SIG480

RG B RG B RG B B GR B GR B GR
RG B RG B RG B B GR B GR B GR
LCD panel LCD panel
Sent last (480)

Sent last (480)

Sent First (1)

Sent 3rd
Sent 2nd

Sent 2nd
Sent 3rd

Note: Top-Left (0,0) means a physical memory location.

Bit D1 – Switching Between Segment Output and RAM
Bit D0 – Switching Between Common Output and RAM

Restriction -

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Status Default value

Default Power On Sequence B7=0,B6=0,B5=0,B4=0,B3=0,B2=0,B1=0,B0=0
S/W Reset No Change

Flow Chart

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VSCRSADD (Vertical Scrolling Start Address)

37H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 1 0 1 1 1 37
st VSP VSP VSP VSP VSP VSP VSP VSP 00.
1 parameter 1 1 ↑ - 15 14 13 12 11 10 9 8 13F
nd VSP VSP VSP VSP VSP VSP VSP VSP
2 parameter 1 1 ↑ - 7 6 5 4 3 2 1 0
This command is used together with Vertical Scrolling Definition (33h). These two
commands describe the scrolling area and the scrolling mode. The Vertical Scrolling Start
Address command has one parameter which describes the address of the line in the Frame
Memory that will be written as the first line after the last line of the Top Fixed Area on the
display as illustrated below:-
When MADCTL B4=0
Example:
When Top Fixed Area = Bottom Fixed Area = 00, Vertical Scrolling Area = 864(DM=10) and

Description

When MADCTL B4=1

Example:
When Top Fixed Area = Bottom Fixed Area = 00, Vertical Scrolling Area = 320(DM=10) and

When new Pointer position and Picture Data are sent, the result on the display will happen at
the next Panel Scan to avoid tearing effect. VSP refers to the Frame Memory line Pointer.
Since the value of the Vertical Scrolling Start Address is absolute (with reference to the
Restriction
Frame Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition
(33h) – otherwise undesirable image will be displayed on the Panel.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register
Normal Mode On, Idle Mode On, Sleep Out Yes
Availability
Partial Mode On, Idle Mode Off, Sleep Out No
Partial Mode On, Idle Mode On, Sleep Out No

Default VSP[15:0]= 0x0000h

Flow Chart See Vertical Scrolling Definition (33h) description.

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IDMOFF (Idle mode off)

38H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 1 1 0 0 0 38
Parameter NO PARAMETER
This command is used to recover from Idle mode on. In the idle off mode, LCD can
Description
display maximum 16.7M colours.
Restriction This command has no effect when module is already in idle off mode.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes

Default Idle mode is OFF.

Flow Chart

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IDMON (Idle mode on)

39H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 1 1 0 0 1 39
Parameter NO PARAMETER
This command is used to enter into Idle mode on. In the idle on mode, colour expression is
reduced. The primary and the secondary colours using MSB of each R, G and B in the
Frame Memory, 8 colour depth data is displayed.
(Example)
Memory Display

Memory contents vs. Display Colour

Description
R7 - R0 G7 - G0 B7 - B0
Black 0XXXXX 0XXXXX 0XXXXX
Blue 0XXXXX 0XXXXX 1XXXXX
Red 1XXXXX 0XXXXX 0XXXXX
Magent 1XXXXX 0XXXXX 1XXXXX
Green 0XXXXX 1XXXXX 0XXXXX
Cyan 0XXXXX 1XXXXX 1XXXXX
Yellow 1XXXXX 1XXXXX 0XXXXX
White 1XXXXX 1XXXXX 1XXXXX
X=don’t care
Restriction This command has no effect when module is already in idle on mode.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Default Idle mode is OFF.

Flow Chart

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COLMOD (Interface Pixel Format)

3A H
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 1 1 0 1 0 3A
st
1 parameter 1 1 ↑ - X D6 D5 D4 X D2 D1 D0 XX
This command is used to define the format of RGB picture data.
D6~D4 : DPI Pixel format Definition.
D2~D0 : DBI Pixel format Definition.
The formats are shown in the table:
Pixel Format D6/D2 D5/D1 D4/D0
Not Defined 0 0 0
Not Defined 0 0 1
Not Defined 0 1 0
Description
Not Defined 0 1 1
Not Defined 1 0 0
16 Bit/Pixel 1 0 1
18 Bit/Pixel 1 1 0
24 Bit/Pixel 1 1 1
If a particular interface, enter DBI or DPI, is not used then the correspondind bits in
the parameter returned from the display module undefined.

Restriction There is no visible effect until the Frame Memory is written to.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes

Status Default value

Default Power On Sequence 24 Bit/Pixel

Flow Chart

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Write_memory_contiune
3CH
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 0 1 1 1 1 0 0 3C
st
1 parameter 1 1 ↑ - D17 D16 D15 D14 D13 D12 D11 D10 00..FF
: 1 1 ↑ - Dx7 Dx6 Dx5 Dx4 Dx3 Dx2 Dx1 Dx0 00..FF
th
N parameter 1 1 ↑ - Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0 00..FF
This command transfers image data from the host processor to the display module’s frame
memory continuing from the pixel location following the previous write_memory_continue or
write_memory_start command. Sending any other command can stop frame Write.
If set_address_mode B5 = 0:
Data is written continuing from the pixel location after the write range of the previous
write_memory_start or write_memory_continue. The column register is then incremented
and pixels are written to the frame memory until the column register equals the End Column
(EC) value. The column register is then reset to SC and the page register is incremented.
Pixels are written to the frame memory until the page register equals the End Page (EP)
Description value or the host processor sends another command. If the number of pixels exceeds (EC –
SC + 1) * (EP – SP + 1) the extra pixels are ignored.
If set_address_mode B5 = 1:
Data is written continuing from the pixel location after the write range of the previous
write_memory_start or write_memory_continue. The page register is then incremented and
pixels are written to the frame memory until the page register equals the End Page (EP)
value. The page register is then reset to SP and the column register is incremented. Pixels
are written to the frame memory until the column register equals the End column (EC) value
or the host processor sends another command. If the number of pixels exceeds (EC – SC +
1) * (EP – SP + 1) the extra pixels are ignored.
Restriction In all colour modes, there is no restriction on length of parameters.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes

Status Default value

Default Power On Sequence Contents of memory is set randomly
S/W Reset Contents of memory is set randomly
Legend
RAMWR Command

Parameter
Image Data
D1[7:0],D2[7:0], Display
...,Dn[7:0]
Flow Chart Action

Any Command Mode

Sequential
transfer

D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 1 0 1 0 0 0 1 51
st
1 parameter 1 1 ↑ - DBV[7:0] 00 .. FF
This command is used to adjust the brightness value of the display.
It should be checked what the relationship between this written value and output
brightness of the display is. This relationship is defined on the display module
Description
specification.
In principle relationship is that 00h value means the lowest brightness and FFh
value means the highest brightness.
See chapter “5.18.3 Brightness Control Block”.
Restriction -
Status Availability
Register
Sleep Out Yes
Availability
Sleep In Yes
Default DBV[7:0]= 0x00h

Flow Chart

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52H RDDISBV (Read Display Brightness Value)

D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 1 0 1 0 0 1 0 52
st
1 parameter 1 ↑ 1 - xx xx xx xx xx xx xx xx Dummy read
nd
2 parameter 1 ↑ 1 - DBV[7:0] xx
This command returns the brightness value of the display.
It should be checked what the relationship between this returned value and output brightness of the
display. This relationship is defined on the display modulespecification is.
In principle the relationship is that 00h value means the lowest brightness and FFh value means the
highest brightness.
See chapters: “5.18.3 Brightness Control Block”, and “6.2.40 Write Display Brightness (51h)”
DBV[7:0] is reset when display is in sleep-in mode.
Description
DBV[7:0] is ‘0’ when bit BCTRL of “6.2.42 Write CTRL Display (53h)” command is ‘0’.
DBV[7:0] is manual set brightness specified with “6.2.42 Write CTRL Display (53h)”
command when bit BCTRL is ‘1’.
When bit BCTRL of “6.2.42 Write CTRL Display (53h)” command is ‘1’ and bit C1/C0
of “6.2.44 Write Content Adaptive Brightness Control (55h)” are ‘0’, DBV[7:0] output is the
brightness value specified with “6.2.40 Write Display Brightness (51h)” command.

Restriction -
Status Availability
Register
Sleep Out Yes
Availability
Sleep In Yes
Default DBV[7:0]= 0x00h

Flow Chart

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53H WRCTRLD (Write Control Display)

D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 1 0 1 0 0 1 1 53
st
1 parameter 1 1 ↑ - xx xx BCTRL xx DD BL xx xx 00 .. FF
This command is used to control display brightness.
BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness
for display.
0 = Off (Brightness registers are 00h, DBV[7..0])
1 = On (Brightness registers are active, according to the other parameters.)
Display Dimming (DD): (Only for manual brightness setting)
DD = 0: Display Dimming is off
Description DD = 1: Display Dimming is on
BL: Backlight Control On/Off
0 = Off (Completely turn off backlight circuit. Control lines must be low. )
1 = On
Dimming function is adapted to the brightness registers for display when bit BCTRL
is changed at DD=1, e.g. BCTRL: 0 -> 1 or 1-> 0.
When BL bit change from “On” to “Off”, backlight is turned off without gradual
dimming, even if dimming-on (DD=1) are selected.
X = Don’t care.
Restriction -
Status Availability
Register
Sleep Out Yes
Availability
Sleep In Yes
Default D[7:0]= 0x00h

Flow Chart

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54H RDCTRLD (Read Control Value Display)

D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 0 1 0 1 0 1 0 0 54
st
1 parameter 1 ↑ 1 - xx xx xx xx xx xx xx xx xx
nd
2 arameter 1 ↑ 1 - 0 0 BCTRL 0 DD BL 0 0 xx
This command returns ambient light and brightness control values, see chapter:
“6.2.42 Write CTRL Display (53h)”.
BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness
for display.
0 = Off
Description 1 = On
Display Dimming (DD):
DD = 0: Display Dimming is off
DD = 1: Display Dimming is on
BL: Backlight Control On/Off
0 = Off (completely turn off backlight circuit)
1 = On
Restriction -
Status Availability
Register
Sleep Out Yes
Availability
Sleep In Yes
Default D[7:0]= 0x00h
Legend
Serial I/F Mode Parallel I/F Mode Command

Parameter
Read RDCTRLD Read RDCTRLD Displa
Host y
Flow Chart Display
Send 2nd Parameter Dummy Read Action

Mode
Send 2nd Parameter
Sequential
transfer

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A1H Read_DDB_start
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 0 1 0 0 0 0 1 A1
st
1 parameter 1 ↑ 1 - x x x x x x x X Dummy read
nd
2 parameter 1 ↑ 1 - x x x x x x x x xx
: 1 ↑ 1 - x x x x x x x x xx
th
N parameter 1 ↑ 1 - x x x x x x x x xx
This command reads identifying and descriptive information from the peripheral. This
information is organized in the Device Descriptor Block (DDB) stored on the peripheral. The
response to this command returns a sequence of bytes that may be any length up to 64K
bytes. Note that the returned sequence of bytes does not necessarily correspond to the entire
DDB; it may be a portion of a larger block of data.
The format of returned data is as follows:
Parameter 2: LS (least significant) byte of Supplier ID. Supplier ID is a unique value assigned
to each peripheral supplier by the MIPI organization.
Parameter 3: MS (most significant) byte of Supplier ID.
Parameter 4: LS (least significant) byte of Supplier Elective Data. This is a byte of information
that is determined by the supplier. It could include model number or revision information, for
example.
Parameter 5: MS (most significant) byte of Supplier Elective Data
Parameter 6: single-byte Escape or Exit Code (EEC). The code is interpreted as follows:
- FFh - Exit code – there is no more data in the Descriptor Block
- 00h - Escape code – there is supplier-proprietary data in the Descriptor Block (does not
conform to any MIPI standard)
Description - Any other value – there is DDB data in the Descriptor Block. The format and interpretation of
this data is documented in MIPI Alliance Standard for Device Descriptor Block (DDB).
DDBs may contain many more data fields providing information about the peripheral.
In a DSI system, read activity takes the form of two separate transactions across the bus: first
the read command read_DDB_start from host processor to peripheral, which includes the bus
turn-around token.
The peripheral then takes control of the bus and returns the requested data. The peripheral
response to read_DDB_start is a Long Packet type, so its length may be up to 64K bytes
unless limited by a previous set_max_return_size command.
The response to a read_DDB_start command always starts at the beginning of the Device
Descriptor Block. After receiving the first packet and processing the returned DDB data, the
host processor may initiate a read_DDB_continue command to access the next portion of the
DDB. A read_DDB_continue command begins the next read at the location following the last
byte of the previous data read from the DDB.
Subsequent read_DDB_continue commands can be used to read a DDB or
supplier-proprietary block of arbitrary size. There is, however, no obligation to read the entire
block. The host processor may choose to stop reading after completion of any read_DDB_xxx
command.
Restrictions -
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes

Default D[7:0] = 0x00h

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Flow Chart

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A8H Read_DDB_continue
D/CX RDX WRX D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 0 1 0 1 0 0 0 A8
st
1 parameter 1 ↑ 1 - x x x x x x x x Dummy read
nd
2 parameter 1 ↑ 1 - x x x x x x x x xx
: 1 ↑ 1 - x x x x x x x x xx
th
N parameter 1 ↑ 1 - x x x x x x x x xx
A read_DDB_start command should be executed at least once before a read_DDB_continue
Description command to define the read location. Otherwise, data read with a read_DDB_continue
command is undefined.
Restrictions -
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes

Default D[7:0] = 0x00h

Flow Chart

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DAH RDID1 (Read ID1)

DNC NRD NWR D15~D8 D7 D5 D6D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 0 1 1 1 0 1 0 DA
st
1 parameter 1 ↑ 1 - - - - - - - - - -
nd
2 parameter 1 ↑ 1 - module’s manufacturer[7:0] xx
This read byte identifies the LCD module’s manufacturer. It is specified by display supplier
Description
and for xx is defined as xxHEX.
Restriction -
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Default value OTP value
Default
ID1[7:0]=0x00h Define by customer

Flow Chart

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RDID2 (Read ID2)

DBH
DNC NRD NWR D15~D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 1 0 1 1 0 1 1 DB
st
1 parameter 1 ↑ 1 - xx xx xx xx xx xx xx xx xx
nd
2 parameter 1 ↑ 1 - - LCD module/driver version [6:0] -
This read byte is used to track the LCD module/driver version. It is defined by display
supplier and changes each time a revision is made to the
display, material or construction specifications. See Table:
ID Byte Value V[7:0] Version Changes
80h
Description 81h
82h
83h
84h
85h
X= Don't care
Restrictions -
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Default value OTP value
Default
ID2[6:0]=0x00h Define by customer
Serial I/F Mode Parallel I/F Mode
(P/SX=Low) (P/SX=High) Legend
Command
Read ID2 Read ID2
Host Parameter
Display
Display
Flow Chart Send 2 nd p arameter Dummy Read
Action

Mode
nd
Send 2 parameter
Sequential
transfer

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DCH RDID3 (Read ID3)

DNC NRD NWR D15~D8 D7 D5 D6 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 01 1 1 1 0 0 DC
st
1 parameter 1 ↑ 1 - xx xxxx xx xx xx xx xx xx
nd
2 parameter 1 ↑ 1 - LCD module/driver ID[7:0] xx
This read byte identifies the LCD module/driver. It is specified by display supplier and for
Description
this LCD project module is defined as xxHEX.
Restrictions -
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Default value OTP value
Default
ID3[7:0]=0x00h Define by customer

Flow Chart

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B0H SETOSC( Set Internal Oscillator)

DNC NRD NWR D15~D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 1 0 1 1 1 0 0 DC
st OSC
1 parameter 1 1 ↑ - - - - - - - - -
_EN
nd
2 parameter 1 1 ↑ - - - - - UADJ[3:0] -
This command is used to set internal oscillator related setting
OSC_EN: Enable internal oscillator, High active.
UADJ[3:0]: For User to adjust OSC frequency, default is 15 MHZ.
UADJ Internal oscillator frequency
0 0 0 0 28.0%
0 0 0 1 34.8%
0 0 1 0 41.5%
0 0 1 1 48.1%
0 1 0 0 54.7%
0 1 0 1 61.3%
Description 0 1 1 0 67.8%
0 1 1 1 74.4%
1 0 0 0 80.6%
1 0 0 1 87.2%
1 0 1 0 93.5%
1 0 1 1 100.0%
1 1 0 0 106.4%
1 1 0 1 112.7%
1 1 1 0 119.4%
1 1 1 1 125.8%
Restrictions SETEXTC turn on to enable this command.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes

Status Default value OTP value

Power On Sequence
Default S/W Reset OSC_EN=0,
UADJ[3:0]
H/W Reset UADJ[3:0]= 1011

Himax Confidential -P.220-

B1H SETPOWER( Set power related setting)

DNC NRD NWR D15~D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 0 1 1 0 0 0 1 B1
st VBIA VSN_ VSP_ VGL_ VGH_ LVGL VDDD
1 parameter 1 1 ↑ -
S_EN EN EN EN EN _EN N_HZ
STB -
nd
2 parameter 1 1 ↑ - - - - - - - - DSTB -
rd
3 parameter 1 1 ↑ - - FS1[2:0] - AP[2:0] -
th
4 parameter 1 1 ↑ - - - - - BT[3:0] -
th
5 parameter 1 1 ↑ - DT[1:0] - - DCDIV[3:0] -
th
6 parameter 1 1 ↑ - - - - BTP[4:0] -
th
7 parameter 1 1 ↑ - - - - BTN[4:0] -
th
8 parameter 1 1 ↑ - VRHP[7:0] -
th
9 parameter 1 1 ↑ - VRHN[7:0] -
th
10 parameter 1 1 ↑ - - - VRMP[5:0] -
th
11 parameter 1 1 ↑ - - - VRMN[5:0] -
th VPNL
12 parameter 1 1 ↑ - - - DD_TU
_EN
- VBS[2:0] -
th AUTO
13 parameter 1 1 ↑ - - DC86_DIV[3:0] XDK1 XDK0
_XDK
-
th
14 parameter 1 1 ↑ - - DTPS[2:0] - DTNS[2:0] -
th
15 parameter 1 1 ↑ - A_DC[1:0] A_DTP[2:0] A_DTN[2:0] -
th
16 parameter 1 1 ↑ - B_DC[1:0] B_DTP[2:0] B_DTN[2:0] -
th
17 parameter 1 1 ↑ - C_DC[1:0] C_DTP[2:0] C_DTN[2:0] -
th
18 parameter 1 1 ↑ - D_DC[1:0] D_DTP[2:0] D_DTN[2:0] -
th
19 parameter 1 1 ↑ - E_DC[1:0] E_DTP[2:0] E_DTN[2:0] -
This command is used to set related setting of power.

DSTB: When DSTB = “1”, the HX8369-A into the deep_standby mode, where all display operation stops,
suspend all the internal operations including the internal R-C oscillator. During the standby mode, only the
following process can be executed.

1. Exit the Standby mode (DSTB = “0”)

In the deep standby mode, the GRAM data and register content may be lost. For preventing this, they have to
reset again after the deep standby mode cancel.

STB: When SLP = “1”, the HX8369-A00 enters the standby mode, where all display operation stops, suspend
all the internal operations. But the internal R-C oscillator stop or not is determined by OSC_EN bit. To minimize
the standby power, please set OSC_EN to 0. During the standby mode, only the following process can be
executed.

a. Exit the Standby (Sleep) mode (SLP = “0”)

b. Enable or disable the oscillation
Description c. Software reset

VSP_EN: ON/OFF the operation of VSP circuit.

VSP_EN Operation of VSP DC/DC circuit
0 OFF
1 ON

VSN_EN: ON/OFF the operation of VSN circuit.

VSN_EN Operation of VSN DC/DC circuit
0 OFF
1 ON

VGH_EN: ON/OFF the operation of VGH charge bump circuit.

VGH_EN Operation of VGH charge bump circuit
0 OFF
1 ON

Himax Confidential -P.221-

LVGL_EN : ON/OFF the operation of LVGL charge bump circuit.

LVGL_EN Operation of LVGL charge bump circuit
0 OFF
1 ON

BT3 BT2 BT1 BT0 VGH VGL

0 0 0 0 2*(VSP-VSN) VDDDN-1*(VSP-VSN)
0 0 0 1 2*(VSP-VSN) -1*(VSP-VSN)
0 0 1 0 2*(VSP-VSN) VDD3-1*(VSP-VSN)
0 0 1 1 (VSP-VSN)+(VDD3-VSN) VDDDN-1*(VSP-VSN)
0 1 0 0 (VSP-VSN)+(VDD3-VSN) -1*(VSP-VSN)
0 1 0 1 (VSP-VSN)+(VDD3-VSN) VDD3-1*(VSP-VSN)
0 1 1 0 (VSP-VSN)+(VSP-VSSD) VDDDN-1*(VSP-VSN)
0 1 1 1 (VSP-VSN)+(VSP-VSSD) -1*(VSP-VSN)
1 0 0 0 (VSP-VSN)+(VSP-VSSD) VDD3-1*(VSP-VSN)
1 0 0 1 (VDD3-VSN)+(VSP-VSSD) VDDDN-1*(VSP-VSN)
1 0 1 0 (VDD3-VSN)+(VSP-VSSD) -1*(VSP-VSN)
1 0 1 1 (VDD3-VSN)+(VSP-VSSD) VDD3-1*(VSP-VSN)
1 1 0 0 (VSP-VSN) VDDDN-1*(VSP-VSN)
1 1 0 1 (VSP-VSN) -1*(VSP-VSN)
1 1 1 0 (VSP-VSN) VDD3-1*(VSP-VSN)
1 1 1 1 2*(VSP-VSSD) -2*(VSP-VSSD)

FS1[2:0]: Set the operating frequency of the step-up circuit for VGH and VGL voltage generation.
FS12 FS11 FS10 Operation Frequency of Step-up Circuit
0 0 0 Inhibit
0 0 1 Fosc/64
0 1 0 Fosc/128
0 1 1 Fosc/256
1 0 0 Fosc/512
1 0 1 Fosc/1024
1 1 0 Fosc/2048
1 1 1 Fosc/4096

VDDDN_HZ: Choose external or internal VDDDN power.

VDDDN_HZ=0, VDDDN= -2.5V.

VDDDN_HZ=1, VDDDN output HZ. (For external VDDDN.)

DCDIV[3:0]: Set the normal operate frequency of DC/DC converter circuit during normal mode.
For PFM circuit: Set the operate frequency of DC/DC converter circuit for PFM design.
(PCCS[1:0]=00, PCCS[1:0]=01, PCCS[1:0]=10)
Normal operate frequency of DC/DC
DCDIV3 DCDIV2 DCDIV1 DCDIV0
converter
0 0 0 0 Fosc / 1
0 0 0 1 Fosc / 2
0 0 1 0 Fosc / 3
0 0 1 1 Fosc / 4
0 1 0 0 Fosc / 5
0 1 0 1 Fosc / 6
0 1 1 0 Fosc / 7
0 1 1 1 Fosc / 8
1 0 0 0 Fosc / 1
1 0 0 1 Fosc / 2
1 0 1 0 Fosc / 3
1 0 1 1 Fosc / 4
1 1 0 0 Fosc / 5
1 1 0 1 Fosc / 6
1 1 1 0 Fosc / 7

Himax Confidential -P.222-

DT[1:0]:Delay time of power on and power off sequence.

DT1 DT0 Delay time of power on and power off sequence on (ms)
0 0 5ms
0 1 10ms
1 0 15ms
1 1 20ms

DTPS[2:0]: Set the soft start operating duty cycle of DC/DC circuit. (PFM DC/DC circuit).
1 duty cycle = 1 M clock

DTPS2 DTPS1 DTPS0 soft start operating duty cycle of DC/DC circuit circuit

0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7
1 1 1 8

DTNS[2:0]: Set the soft start operating duty cycle of DC/DC circuit. (PFM DC/DC circuit).
1 duty cycle = 1 M clock
DTNS2 DTNS1 DTNS0 soft start operating duty cycle of DC/DC circuit circuit
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7
1 1 1 8

BTP[4:0]: Switch the output factor for DC/DC circuit for VSP voltage generation. The LCD drive voltage level
VSP can be selected according to the characteristic of liquid crystal which panel used.
BTP4 BTP3 BTP2 BTP1 BTP0 VSP
0 0 0 0 0 3.01
0 0 0 0 1 3.15
0 0 0 1 0 3.29
0 0 0 1 1 3.46
0 0 1 0 0 3.60
0 0 1 0 1 3.74
0 0 1 1 0 3.91
0 0 1 1 1 4.05
0 1 0 0 0 4.19
0 1 0 0 1 4.36
0 1 0 1 0 4.50
0 1 0 1 1 4.64
0 1 1 0 0 4.81
0 1 1 0 1 4.95
0 1 1 1 0 5.09
0 1 1 1 1 5.26
1 0 0 0 0 5.40
1 0 0 0 1 5.54
1 0 0 1 0 5.71
Himax Confidential -P.223-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
1 0 0 1 1 Inhibit
‧‧‧‧‧ Inhibit
1 1 1 1 1 Inhibit

BTN[4:0]: Switch the output factor of DC/DC circuit for VSN voltage generation. The LCD drive voltage level
VSN can be selected according to the characteristic of liquid crystal which panel used.

While using PFM type-C or HX5186-A mode (PCCS1-0 = 10, PCCS1-0 = 11), VSN is followed the
BTP[4:0] setting.
PFM mode type-C : VSN = -VSP + 0.6V
Using HX5186-A charge Pump mode : VSN = -VSP

AP[2:0]: Adjust the amount of fixed current from the fixed current source for the operational amplifier in the
power supply circuit. When the amount of fixed current is increased, the LCD driving capacity and
the display quality are high, but the current consumption is increased. This is a tradeoff, Adjust the
fixed current by considering both the display quality and the current consumption. During no display
operation, when AP[2:0] = 000, the current consumption can be reduced by stopping the operations
of operational amplifier and step-up circuit.
AP2 AP1 AP0 Constant Current of Operational Amplifier
0 0 0 Stop (inhibit)
0 0 1 0.5µA
0 1 0 1µA
0 1 1 1.5µA
1 0 0 2µA
1 0 1 2.5µA
1 1 0 3µA
1 1 1 3.5µA

VRHP[7:0]: VSPR regulator output control setting for source data output driving.
VRHP[7:0] VSPR
0 0 0 0 0 0 0 0 3.488
0 0 0 0 0 0 0 1 3.516
0 0 0 0 0 0 1 0 3.544
0 0 0 0 0 0 1 1 3.572
0 0 0 0 0 1 0 0 3.600
0 0 0 0 0 1 0 1 3.628
0 0 0 0 0 1 1 0 3.656
0 0 0 0 0 1 1 1 3.684
0 0 0 0 1 0 0 0 3.713
0 0 0 0 1 0 0 1 3.741
0 0 0 0 1 0 1 0 3.769
0 0 0 0 1 0 1 1 3.797
0 0 0 0 1 1 0 0 3.825
0 0 0 0 1 1 0 1 3.853
0 0 0 0 1 1 1 0 3.881
0 0 0 0 1 1 1 1 3.909
0 0 0 1 0 0 0 0 3.938
0 0 0 1 0 0 0 1 3.966
0 0 0 1 0 0 1 0 3.994
0 0 0 1 0 0 1 1 4.022
0 0 0 1 0 1 0 0 4.050
0 0 0 1 0 1 0 1 4.078
0 0 0 1 0 1 1 0 4.106
0 0 0 1 0 1 1 1 4.134
0 0 0 1 1 0 0 0 4.163
0 0 0 1 1 0 0 1 4.191
0 0 0 1 1 0 1 0 4.219
0 0 0 1 1 0 1 1 4.247
0 0 0 1 1 1 0 0 4.275
0 0 0 1 1 1 0 1 4.303
0 0 0 1 1 1 1 0 4.331
0 0 0 1 1 1 1 1 4.359
0 0 1 0 0 0 0 0 4.388

Himax Confidential -P.224-

VRHN[7:0]: VSNR regulator output control setting for source data output driving.
VRHN[7:0] VSNR
0 0 0 0 0 0 0 0 -3.263
0 0 0 0 0 0 0 1 -3.291
0 0 0 0 0 0 1 0 -3.319
0 0 0 0 0 0 1 1 -3.347
0 0 0 0 0 1 0 0 -3.375
0 0 0 0 0 1 0 1 -3.403
0 0 0 0 0 1 1 0 -3.431
0 0 0 0 0 1 1 1 -3.459
0 0 0 0 1 0 0 0 -3.488
0 0 0 0 1 0 0 1 -3.516
0 0 0 0 1 0 1 0 -3.544
0 0 0 0 1 0 1 1 -3.572
0 0 0 0 1 1 0 0 -3.600
0 0 0 0 1 1 0 1 -3.628
0 0 0 0 1 1 1 0 -3.656
0 0 0 0 1 1 1 1 -3.684
0 0 0 1 0 0 0 0 -3.713
0 0 0 1 0 0 0 1 -3.741
0 0 0 1 0 0 1 0 -3.769
0 0 0 1 0 0 1 1 -3.797
0 0 0 1 0 1 0 0 -3.825
0 0 0 1 0 1 0 1 -3.853
0 0 0 1 0 1 1 0 -3.881
0 0 0 1 0 1 1 1 -3.909
0 0 0 1 1 0 0 0 -3.938
0 0 0 1 1 0 0 1 -3.966
0 0 0 1 1 0 1 0 -3.994
0 0 0 1 1 0 1 1 -4.022
0 0 0 1 1 1 0 0 -4.050
0 0 0 1 1 1 0 1 -4.078
0 0 0 1 1 1 1 0 -4.106
Himax Confidential -P.225-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
0 0 0 1 1 1 1 1 -4.134
0 0 1 0 0 0 0 0 -4.163
0 0 1 0 0 0 0 1 -4.191
0 0 1 0 0 0 1 0 -4.219
0 0 1 0 0 0 1 1 -4.247
0 0 1 0 0 1 0 0 -4.275
0 0 1 0 0 1 0 1 -4.303
0 0 1 0 0 1 1 0 -4.331
0 0 1 0 0 1 1 1 -4.359
0 0 1 0 1 0 0 0 -4.388
0 0 1 0 1 0 0 1 -4.416
0 0 1 0 1 0 1 0 -4.444
0 0 1 0 1 0 1 1 -4.472
0 0 1 0 1 1 0 0 -4.500
0 0 1 0 1 1 0 1 -4.528
0 0 1 0 1 1 1 0 -4.556
0 0 1 0 1 1 1 1 -4.584
0 0 1 1 0 0 0 0 -4.613
0 0 1 1 0 0 0 1 -4.641
0 0 1 1 0 0 1 0 -4.669
0 0 1 1 0 0 1 1 -4.697
0 0 1 1 0 1 0 0 -4.725
0 0 1 1 0 1 0 1 -4.753
0 0 1 1 0 1 1 0 -4.781
0 0 1 1 0 1 1 1 -4.809
0 0 1 1 1 0 0 0 -4.838
0 0 1 1 1 0 0 1 -4.866
0 0 1 1 1 0 1 0 -4.894
0 0 1 1 1 0 1 1 -4.922
0 0 1 1 1 1 0 0 -4.950
0 0 1 1 1 1 0 1 -4.978
0 0 1 1 1 1 1 0 -5.006
0 0 1 1 1 1 1 1 -5.034
0 1 0 0 0 0 0 0 -5.063
0 1 0 0 0 0 0 1 -5.091
0 1 0 0 0 0 1 0 -5.119
01000011 ~ 01111110 Inhibit
0 1 1 1 1 1 1 1 VSN
10000000 ~ 11111110 Inhibit
1 1 1 1 1 1 1 1 HZ

VRMP[5:0]: The positive polarity gamma amplitude voltage setting (VSPR-VGSP).

VRMP[5:0] VSPR-VGSP
0 0 0 0 0 0 2.588
0 0 0 0 0 1 2.644
0 0 0 0 1 0 2.700
0 0 0 0 1 1 2.756
0 0 0 1 0 0 2.813
0 0 0 1 0 1 2.869
0 0 0 1 1 0 2.925
0 0 0 1 1 1 2.981
0 0 1 0 0 0 3.038
0 0 1 0 0 1 3.094
0 0 1 0 1 0 3.150
0 0 1 0 1 1 3.206
0 0 1 1 0 0 3.263
0 0 1 1 0 1 3.319
0 0 1 1 1 0 3.375
0 0 1 1 1 1 3.431
0 1 0 0 0 0 3.488
0 1 0 0 0 1 3.544
0 1 0 0 1 0 3.600
0 1 0 0 1 1 3.656
0 1 0 1 0 0 3.713
0 1 0 1 0 1 3.769
Himax Confidential -P.226-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
0 1 0 1 1 0 3.825
0 1 0 1 1 1 3.881
0 1 1 0 0 0 3.938
0 1 1 0 0 1 3.994
0 1 1 0 1 0 4.050
0 1 1 0 1 1 4.106
0 1 1 1 0 0 4.163
0 1 1 1 0 1 4.219
0 1 1 1 1 0 4.275
0 1 1 1 1 1 4.331
1 0 0 0 0 0 4.388
1 0 0 0 0 1 4.444
1 0 0 0 1 0 4.500
1 0 0 0 1 1 4.556
1 0 0 1 0 0 4.613
1 0 0 1 0 1 4.669
1 0 0 1 1 0 4.725
1 0 0 1 1 1 4.781
1 0 1 0 0 0 4.838
1 0 1 0 0 1 4.894
1 0 1 0 1 0 4.950
1 0 1 0 1 1 5.006
1 0 1 1 0 0 5.063
1 0 1 1 0 1 5.119
1 0 1 1 1 0 Inhibit
‧‧‧‧‧ Inhibit
1 1 1 1 1 0 Inhibit
1 1 1 1 1 1 VSPR(VGSP=VSSA)

VRMN[5:0]: The negitive polarity gamma amplitude voltage setting (VSNR-VGSN).

VRMN[5:0] VSNR-VGSN
0 0 0 0 0 0 -2.588
0 0 0 0 0 1 -2.644
0 0 0 0 1 0 -2.700
0 0 0 0 1 1 -2.756
0 0 0 1 0 0 -2.813
0 0 0 1 0 1 -2.869
0 0 0 1 1 0 -2.925
0 0 0 1 1 1 -2.981
0 0 1 0 0 0 -3.038
0 0 1 0 0 1 -3.094
0 0 1 0 1 0 -3.150
0 0 1 0 1 1 -3.206
0 0 1 1 0 0 -3.263
0 0 1 1 0 1 -3.319
0 0 1 1 1 0 -3.375
0 0 1 1 1 1 -3.431
0 1 0 0 0 0 -3.488
0 1 0 0 0 1 -3.544
0 1 0 0 1 0 -3.600
0 1 0 0 1 1 -3.656
0 1 0 1 0 0 -3.713
0 1 0 1 0 1 -3.769
0 1 0 1 1 0 -3.825
0 1 0 1 1 1 -3.881
0 1 1 0 0 0 -3.938
0 1 1 0 0 1 -3.994
0 1 1 0 1 0 -4.050
0 1 1 0 1 1 -4.106
0 1 1 1 0 0 -4.163
0 1 1 1 0 1 -4.219
0 1 1 1 1 0 -4.275
0 1 1 1 1 1 -4.331
1 0 0 0 0 0 -4.388
1 0 0 0 0 1 -4.444
Himax Confidential -P.227-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
1 0 0 0 1 0 -4.500
1 0 0 0 1 1 -4.556
1 0 0 1 0 0 -4.613
1 0 0 1 0 1 -4.669
1 0 0 1 1 0 -4.725
1 0 0 1 1 1 -4.781
1 0 1 0 0 0 -4.838
1 0 1 0 0 1 -4.894
1 0 1 0 1 0 -4.950
1 0 1 0 1 1 -5.006
1 0 1 1 0 0 -5.063
1 0 1 1 0 1 -5.119
1 0 1 1 1 0 Inhibit
‧‧‧‧‧ Inhibit
1 1 1 1 1 0 Inhibit
1 1 1 1 1 1 VSNR(VGSN=VSSA)

VBS[2:0]: Set the VBIAS level.

VBS2 VBS1 VBS0 VBIAS
0 0 0 Inhibit
0 0 1 4.68
0 1 0 4.50
0 1 1 4.32
1 0 0 4.14
1 0 1 3.96
1 1 0 3.78
1 1 1 3.60

DC86_DIV[3:0]: Frequency for Charge Pump Mode (HX5186-A)

DC86_DIV[3:0] Frequency - Charge Pump Mode (HX5186-A)
0000 Fosc/2
0001 Fosc/4
0010 Fosc/8
0011 Fosc/16
0100 Fosc/24
0101 Fosc/32
0110 Fosc/40
0111 Fosc/48
1000 Fosc/56
1001 Fosc/64
1010 Fosc/72
1011 Fosc/80
1100 Fosc/88
1101 Fosc/96
1110 Fosc/104
1111 Fosc/112

XDK[1:0]: Setting HX5186-A

XDK[1] XDK[0] HX5186-A or Internal-Charge Pump
0 0 X1.5 Pump
0 1 x2 Pump
1 0 X3 Pump
1 1 Inhibited

AUTO_XDK: Auto XDK function enable, when using HX5186-A.

Auto_XDK=1 Hx5186-A
VDD3 x 1.5 > VSPtarget X1.5
VDD3 x 2 > VSPtarget X2
VDD3 x 2 < VSPtarget X3
Auto_XDK=0 Depend on XDK[2:0]

DD_TU: In-house function, and not open.

VPNL_EN: Enable VPNL function.
Himax Confidential -P.228-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02

Restriction SETEXTC turn on to enable this command.

Himax Confidential -P.229-

B2H SETDISP( Set display related register)

DNC NRD NWR D15~D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 0 1 1 0 0 1 0 B2
st
1 parameter 1 1 ↑ - - - - - - - D[1:0]
nd
2 parameter 1 1 ↑ - - RES_SEL[2:0] RM DFR DM[1:0]
rd
3 parameter 1 1 ↑ - BP [7:0]
th
4 parameter 1 1 ↑ FP [7:0]
th
5 parameter 1 1 ↑ - SAP[3:0] - - - -
th
6 parameter 1 1 ↑ - GEN_ON[7:0]
th
7 parameter 1 1 ↑ - GEN_OFF[7:0]
th
8 parameter 1 1 ↑ - RTN[7:0]
th
9 parameter 1 1 ↑ - - - - - TEI[3:0]
th
10 parameter 1 1 ↑ - - - - - - - TEP[9:8]
th
11 parameter 1 1 ↑ - TEP[7:0]
th BP_PE[7:0]
12 parameter 1 1 ↑ -
th FP_PE[7:0]
13 parameter 1 1 ↑ -
th RTN_PE[7:0]
14 parameter 1 1 ↑ -
th
15 parameter 1 1 ↑ - - - - - - - - GON
This command is used to set display related register
D1–0:
D1 D0 Source Output HX8369-A00 Internal Display Operations
0 0 VSSD Halt
0 1 Inhibit Inhibit
1 0 V255 Operate
1 1 Display Operate

RES_SEL[2:0]: Resolution selection.

RES_SEL 2 RES_SEL 1 RES_SEL 0 Resolution
0 0 0 480RGBX864
0 0 1 480RGBX854
0 1 0 480RGBX800
0 1 1 480RGBX640
1 0 0 360 RGBX640
1 0 1 480RGBX720
1 1 0 Setting disable
1 1 1 Setting disable
Description
DFR The bit is used in the Frame Memory access and Display operation. In-house function and
not open.

RM The bit is used to select an interface for the Frame Memory access operation. The Frame
Memory is accessed only via the interface defined by RM bit. Because the interface can be
selected separately from display operation mode, writing data to the Frame Memory is possible
via system interface when RM = 0, even in the DPI display operation.
RM setting is enabled from the next frame. Wait 1 frame to transfer data after setting.
RM Interface for RAM Access
0 DBI Interface (CPU)
1 DPI Interface (RGB)

DM[1:0] The bit is used to select display operation mode. The setting allows switching between
display operation in synchronization with internal oscillation clock, VSYNC, or DPI signal
(VSYNC+HSYNC).
Note that switching between VSYNC and DPI operation is prohibited.

DM 1 DM 0 Display Mode

Himax Confidential -P.230-

FP[7:0] / FP_PE[7:0]
Number of FP Line Number of BP Line
BP[7:0] / BP_PE[7:0]
8h’00 Inhibited
8h’01 3 lines
8h’02 4 lines
8h’03 5 lines
8h’04 6 lines
8h’05 7 lines
‧‧‧ ‧‧‧
8h’FB 253 lines
8h’FC 254 lines
8h’FD 255 lines
8h’FE 256 lines
8h’FF 257 lines

SAP3 SAP2 SAP1 SAP0 Fixed Current of Operational Amplifier

0 0 0 0 0.5u
0 0 0 1 1u
0 0 1 0 1.5u
0 0 1 1 2u
0 1 0 0 2.5u
0 1 0 1 3u
0 1 1 0 3.5u
0 1 1 1 4u
‧‧‧‧‧‧‧‧‧‧‧‧
1 1 1 1 8u

GEN_ON[7:0]: Gamma OP turned on timing and in-house function not open.

GEN_OFF[7:0]: Gamma OP turned off timing and in-house function not open.

RTN[7:0]: A cycle time of line width, in-house function not open.

RTN_PE[7:0]: A cycle time of line width on partial idle mode, in-house function not open.

RTN[7:0]/ RTN_PE[7:0] Clock per Line

8h’00 275 clocks
8h’01 (275 + 1x2) 277 clocks
8h’02 (275 + 2x2) 279 clocks
8h’03 (275 + 3x2) 281 clocks
‧‧‧ ‧‧‧
8’hFD (275 + 253x2) 781 clocks
8’hFE (275 + 254x2) 783 clocks
8’hFF (275 + 255x2) 785 clocks

TEI[3:0]: Sets the output interval of TE signal according to the display data rewrite cycle and
data transfer rate.
TEI3 TEI2 TEI1 TEI0 Output Interval
0 0 0 0 1 frame
0 0 0 1 2 frames
0 0 1 0 3 frames
Himax Confidential -P.231-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
‧‧‧‧‧‧‧ ‧‧
1 1 1 0 15 frames
1 1 1 1 16 frames

TEP[9:0]: Sets the output position of frame cycle signal. TE can be used as the trigger signal
for frame synchronous write operation.
Make sure the setting restriction 9’h000 ≤ TEP[9:0] ≤ BP+Number of Line +FP.
TEP[9:0] Output position
10’h000 0th line
10’h001 1st line
10’h002 2nd line
10’h003 3rd line
‧‧‧ ‧‧‧
10’h35D 861th line
10’h35E 862th line
10’h35F 863th line

GON: Controlling the GIP signals On/Off register.

GON =1, the GIP signals are On for normal operation.
GON =0, the GIP signals are OFF and set as GND.

Restrictions SETEXTC turn on to enable this command

Status Default value OTP value

Power On Sequence D[1:0]=00, RES_SEL[2:0]=001, RES_SEL[2:0], RM, DFR,
S/W Reset RM=0, DFR=0, DM[1:0]=00 DM[1:0] BP[7:0], FP[7:0],
H/W Reset BP[7:0]=0x03h, FP[7:0]=0x03h, SAP[3:0], GEN_ON,
SAP[3:0]=0111, GEN_ON=0x00h, GEN_OFF, RTN[7:0],
Default
GEN_OFF=0xFFh, TEI[3:0], TEP[9:0],
RTN[7:0]=0x00h, BP_PE[7:0], FP_PE[7:0],
TEI[3:0] =0000,TEP[9:0] =0x000h, RTN_PE[7:0]
BP_PE[7:0]=0x03h,
FP_PE[7:0]=0x03h,
RTN_PE[7:0]=0x00h, GON=1

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B3H SETRGBIF( Set RGB interface related register)

DNC NRD NWR D15~D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 0 1 1 0 0 1 1 B3
st
1 parameter 1 1 ↑ - - - - - DPL HSPL VSPL EPL -
This command is used to set RGB interface related register.
EPL: Specify the polarity of DE pin in RGB interface mode.
EPL DE pin Display
0 0 Enable
0 1 Disable
1 0 Disable
1 1 Enable
Description
VSPL: The polarity of VS pin. When VSPL=0, the VS pin is Low active. When VSPL=1, the VS
pin is High active.
HSPL: The polarity of HS pin. When HSPL=0, the HS pin is Low active. When HSPL=1, the HS
pin is High active.
DPL: The polarity of PCLK pin. When DPL=0, the data is read on the rising edge of PCLK signal.
When DPL=1, the data is read on the falling edge of PCLK signal.

Restrictions SETEXTC turn on to enable this command.

Status Default value OTP value

Power On Sequence
Default
S/W Reset DPL=0,HSPL=0,VSPL=0,EPL=1 DPL,HSPL,VSPL,EPL
H/W Reset

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B4H SETCYC( Set display waveform cycles)

DNC NRD NWR D15~D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 0 1 0 0 1 0 0 B4
st
1 parameter 1 1 ↑ - - - - - NW_PE[1:0] NW[1:0] -
nd
2 parameter 1 1 ↑ - SON[7:0] -
rd
3 parameter 1 1 ↑ - SOFF[7:0] -
th
4 parameter 1 1 ↑ - EQS[7:0] -
th
5 parameter 1 1 ↑ - EQON[7:0] -
This command is used to get setting of display waveform cycles.
NW[1:0]: Inversion type setting.
NW1 NW0 Inversion type
0 0 Column inversion
0 1 1-dot inversion
1 0 2-dot inversion
1 1 Zig-zag inversion

NW_PE[1:0]: Inversion type setting on partial idle mode.

NW_PE1 NW_PE0 Inversion type
0 0 Column inversion
0 1 1-dot inversion
1 0 2-dot inversion
1 1 Zig-zag inversion

Description

SON[7:0]: Specify the valid source output start time.

SON [7:0] Source output start time
0 0 0 0 0 0 0 0 Inhibit
0 0 0 0 0 0 0 1 1 OSC clock cycle
0 0 0 0 0 0 1 0 2 OSC clock cycle
0 0 0 0 0 0 1 1 3 OSC clock cycle
0 0 0 0 0 1 0 0 4 OSC clock cycle
Himax Confidential -P.234-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
‧‧‧‧‧ ‧‧‧‧‧
0 0 0 0 1 1 1 1 15 OSC clock cycle
‧‧‧‧‧ ‧‧‧‧‧
1 1 1 1 1 0 1 0 250 OSC clock cycle
1 1 1 1 1 0 1 1 251 OSC clock cycle
1 1 1 1 1 1 0 0 252 OSC clock cycle
1 1 1 1 1 1 0 1 253 OSC clock cycle
1 1 1 1 1 1 1 0 254 OSC clock cycle
1 1 1 1 1 1 1 1 255 OSC clock cycle

SOFF[7:0]: Specify the valid source output end time.

SOFF [7:0] Source output end time
0 0 0 0 0 0 0 0 Inhibit
0 0 0 0 0 0 0 1 1 OSC clock cycle
0 0 0 0 0 0 1 0 2 OSC clock cycle
0 0 0 0 0 0 1 1 3 OSC clock cycle
0 0 0 0 0 1 0 0 4 OSC clock cycle
‧‧‧‧‧ ‧‧‧‧‧
1 0 0 0 0 0 1 0 130 OSC clock cycle
‧‧‧‧‧ ‧‧‧‧‧
1 1 1 1 1 0 1 0 250 OSC clock cycle
1 1 1 1 1 0 1 1 251 OSC clock cycle
1 1 1 1 1 1 0 0 252 OSC clock cycle
1 1 1 1 1 1 0 1 253 OSC clock cycle
1 1 1 1 1 1 1 0 254 OSC clock cycle
1 1 1 1 1 1 1 1 255 OSC clock cycle

EQON[7:0]: Specify the valid Equalize output start time.

(Please note that the EQON[7:0] ≤ EQS[7:0]-1)
EQON [7:0] Gate output start time
0 0 0 0 0 0 0 0 Inhibit
0 0 0 0 0 0 0 1 1 OSC clock cycle
0 0 0 0 0 0 1 0 2 OSC clock cycle
0 0 0 0 0 0 1 1 3 OSC clock cycle
0 0 0 0 0 1 0 0 4 OSC clock cycle
‧‧‧‧‧ ‧‧‧‧‧
0 0 0 0 1 1 0 0 12 OSC clock cycle
‧‧‧‧‧ ‧‧‧‧‧
1 1 1 1 1 0 1 0 250 OSC clock cycle
1 1 1 1 1 0 1 1 251 OSC clock cycle
1 1 1 1 1 1 0 0 252 OSC clock cycle
1 1 1 1 1 1 0 1 253 OSC clock cycle
1 1 1 1 1 1 1 0 254 OSC clock cycle
1 1 1 1 1 1 1 1 255 OSC clock cycle

EQS[7:0]: Specify the Equalize time of source output. (Please note that the EQS[7:0] ≤ SON-1).
EQS [7:0] Equalize time of source output
0 0 0 0 0 0 0 0 Equalize function off
0 0 0 0 0 0 0 1 1 OSC clock cycle
0 0 0 0 0 0 1 0 2 OSC clock cycle
0 0 0 0 0 0 1 1 3 OSC clock cycle
0 0 0 0 0 1 0 0 4 OSC clock cycle
0 0 0 0 0 1 0 1 5 OSC clock cycle
0 0 0 0 0 1 1 0 6 OSC clock cycle
‧‧‧‧‧ ‧‧‧‧‧
1 1 1 1 1 0 1 0 250 OSC clock cycle
1 1 1 1 1 0 1 1 251 OSC clock cycle

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B6 H SETVCOM ( Set VCOM Voltage)

DNC NRD NWR D15~D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 0 1 1 0 1 1 0 B6
st
1 parameter 1 1 ↑ - VCMC_F[7:0] -
nd
2 parameter 1 1 ↑ - VCMC_B[7:0] -
This command is used to set VCOM Voltage include VCOM Low and VCOM High Voltage.

VCMC_F[7:0]: DC VCOM voltage setting for forward scan.

VCMC_B[7:0]: DC VCOM voltage setting for backward scan.
VCMC_F[7:0] / VCMC_B[7:0] VCOM (V)
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 -2
0 0 0 0 0 0 0 1 -1.984
0 0 0 0 0 0 1 0 -1.968
0 0 0 0 0 0 1 1 -1.952
0 0 0 0 0 1 0 0 -1.936
0 0 0 0 0 1 0 1 -1.92
0 0 0 0 0 1 1 0 -1.904
0 0 0 0 0 1 1 1 -1.888
0 0 0 0 1 0 0 0 -1.872
0 0 0 0 1 0 0 1 -1.856
0 0 0 0 1 0 1 0 -1.84
0 0 0 0 1 0 1 1 -1.824
0 0 0 0 1 1 0 0 -1.808
0 0 0 0 1 1 0 1 -1.792
0 0 0 0 1 1 1 0 -1.776
0 0 0 0 1 1 1 1 -1.76
0 0 0 1 0 0 0 0 -1.744
0 0 0 1 0 0 0 1 -1.728
0 0 0 1 0 0 1 0 -1.712
Description 0 0 0 1 0 0 1 1 -1.696
0 0 0 1 0 1 0 0 -1.68
0 0 0 1 0 1 0 1 -1.664
0 0 0 1 0 1 1 0 -1.648
0 0 0 1 0 1 1 1 -1.632
0 0 0 1 1 0 0 0 -1.616
0 0 0 1 1 0 0 1 -1.6
0 0 0 1 1 0 1 0 -1.584
0 0 0 1 1 0 1 1 -1.568
0 0 0 1 1 1 0 0 -1.552
0 0 0 1 1 1 0 1 -1.536
0 0 0 1 1 1 1 0 -1.52
0 0 0 1 1 1 1 1 -1.504
0 0 1 0 0 0 0 0 -1.488
0 0 1 0 0 0 0 1 -1.472
0 0 1 0 0 0 1 0 -1.456
0 0 1 0 0 0 1 1 -1.44
0 0 1 0 0 1 0 0 -1.424
0 0 1 0 0 1 0 1 -1.408
0 0 1 0 0 1 1 0 -1.392
0 0 1 0 0 1 1 1 -1.376
0 0 1 0 1 0 0 0 -1.36
0 0 1 0 1 0 0 1 -1.344
0 0 1 0 1 0 1 0 -1.328
0 0 1 0 1 0 1 1 -1.312
0 0 1 0 1 1 0 0 -1.296

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Restrictions SETEXTC turn on to enable this command.

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B9H SETEXTC ( Set extended command set)

DNC NRD NWR D15~D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 0 1 1 1 0 0 1 B9
st
1 parameter 1 1 ↑ - EXTC1[7:0](FFh) -
nd
2 parameter 1 1 ↑ - EXTC2[7:0](83h) -
rd
3 parameter 1 1 ↑ - EXTC3[7:0](69h) -
This command is used to set extended command set access enable.
Extend cmd Command description
After command (B0h), must write 3 parameters
Description Enable
(ffh,83h,69h) by order
After command(B0h), write 3 parameters (xxh,xxh,xxh)
Disable(default)
any value is all right, but can not be (ffh,83h,69h)
Restrictions -
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default value OTP value
Power On Sequence EXTC1[7:0]=0x00h,
Default
S/W Reset EXTC2[7:0]=0x00h, N/A
H/W Reset EXTC3[7:0]=0x00h,

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BBH SETOTP( Set OTP Related Setting)

DNC NRD NWR D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 0 1 1 1 0 1 1 BB
st
1 parameter 1 1 ↑ - OTP_MASK[7:0] (8'b0) -
nd
2 parameter 1 1 ↑ - - - - - - - - OTP_INDEX[8]
rd
3 parameter 1 1 ↑ - OTP_INDEX[7:0] -
th OTP_LOAD_
4 parameter 1 1 ↑ - DISABLE
OTP_TEST OTP_POR OTP_PWE OTP_PTM[1:0] VPP_SEL OTP_PROG -
th
5 parameter 1 1 ↑ - OTP_DATA[7:0] -
This command is used to set OTP Related Setting.
OTP_MASK[7:0]: Bit programming mask, if 1, means this bit can’t be programmed.
OTP_INDEX[8:0]: Set index of OTP table for programming.
OTP_PWE: OTP program write enable, if 1, means OTP is able to be programmed.
OTP_PROG: When set to 1, the register content of OTP index is programmed.
OTP_LOAD_DISABLE: Normally the internal registers are auto-loaded from OTP when the
Description SLPOUT command is received. Nevertheless, if this bit is set to 1, it will disable the auto loading
function when the SLPOUT command was received. In general, this bit is used when OTP is not yet
programmed.
OTP_PTM[1:0]: Not open, internal use.
VPP_SEL: When written to 1, VPP voltage is fed to OTP
OTP_DATA[7:0]: Read back the OTP index data.

Restrictions SETEXTC turn on to enable this command.

OTP_MASK[7:0]=0x00h,
OTP_INDEX[8:0]=0x1FFh,
Power On Sequence OTP_LOAD_ DISABLE=0,
Default
S/W Reset OTP_TEST=0, OTP_POR=0, N/A
H/W Reset OTP_PWE=0, OTP_PTM[1:0]=00,
VPP_SEL=0, OTP_PROG=0,
OTP_DATA[7:0]=xxh

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C1H SETDGCLUT ( Set DGC LUT)

DNC NRD NWR D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 1 0 0 0 0 0 1 C1
st
1 parameter 1 1 ↑ - - - - - - - DITH_OPT DGC_EN -
nd
2 parameter 1 1 ↑ - D1[7:0] -
: 1 1 ↑ - Dn[7:0] -
th
127 parameter 1 1 ↑ - D126[7:0] -

This command is used to set DGC LUT.

DITH_OPT: Not open, internal use.
DGC_EN: Enable the DGC function
D1[7:0] ~ D126[7:0]:

LUT D7 D6 D5 D4 D3 D2 D1 D0 Default
1st R009 R008 R007 R006 R005 R004 R003 R002 00h
2nd R019 R018 R017 R016 R015 R014 R013 R012 08h
3rd R029 R028 R027 R026 R025 R024 R023 R022 10h
: : : : : : : : : :
: : : : : : : : : :
32rd R319 R318 R317 R316 R315 R314 R313 R312 F8h
33rd R329 R328 R327 R326 R325 R324 R323 R322 FFh
34th R001 R000 R011 R010 R021 R020 R031 R030 00h
35th R041 R040 R051 R050 R061 R060 R071 R070 00h
: : : : : : : : : :
: : : : : : : : : :
41st R281 R280 R291 R290 R301 R300 R311 R310 00h
42nd R321 R320 0 0 0 0 0 0 00h
43rd G009 G008 G007 G006 G005 G004 G003 G002 00h
44th G019 G018 G017 G016 G015 G014 G013 G012 08h
45th G029 G028 G027 G026 G025 G024 G023 G022 10h
: : : : : : : : : :
Description : : : : : : : : : :
74th G319 G318 G317 G316 G315 G314 G313 G312 F8h
75th G329 G328 G327 G326 G325 G324 G323 G322 FFh
76th G001 G000 G011 G010 G021 G020 G031 G030 00h
77th G041 G040 G051 G050 G061 G060 G071 G070 00h
: : : : : : : : : :
: : : : : : : : : :
83rd G281 G280 G291 G290 G301 G300 G311 G310 00h
84th G321 G320 0 0 0 0 0 0 00h
85th B009 B008 B007 B006 B005 B004 B003 B002 00h
86th B019 B018 B017 B016 B015 B014 B013 B012 08h
87th B029 B028 B027 B026 B025 B024 B023 B022 10h
: : : : : : : : : :
: : : : : : : : : :
116th B319 B318 B317 B316 B315 B314 B313 B312 F8h
117th B329 B328 B327 B326 B325 B324 B323 B322 FFh
118th B001 B000 B011 B010 B021 B020 B031 B030 00h
119th B041 B040 B051 B050 B061 B060 B071 B070 00h
: : : : : : : : : :
: : : : : : : : : :
125th B281 B280 B291 B290 B301 B300 B311 B310 00h
126th B321 B320 0 0 0 0 0 0 00h

Write D1[7:0] (R 1st), D43[7:0] (G 1st) and D85[7:0] (B 1st), but Read is from D1[7:0],
D2[7:0] and D3[7:0]

Restrictions SETEXTC turn on to enable this command.

Status Availability
Register Idle Mode Off, Sleep Out Yes
Availability Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

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Power On Sequence DITH_OPT DITH_OPT

Default
S/W Reset DGC_EN DGC_EN
H/W Reset D1[7:0]~D126[7:0] D1[7:0]~D126[7:0]

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C3H SETID ( Set ID)

DNC NRD NWR D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 1 0 0 0 0 1 1 C3
st
1 parameter 1 1 ↑ - ID1[7:0] -
nd
2 parameter 1 1 ↑ - 0 ID2[6:0] -
rd
3 parameter 1 1 ↑ - ID3[7:0] -
Description This command is used to set ID (RDAh, RDBh, RDCh) value.
Restrictions SETEXTC turn on to enable this command.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Status Default value OTP value
Power On Sequence ID1[7:0]=0x00h,
Default
S/W Reset ID2[6:0]=0x00h, ID1[7:0], ID2[6:0], ID3[7:0]
H/W Reset ID3[7:0]=0x00h,

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C9H SETCABC (Set CABC Control)

DNC NRD NWR D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 1 0 0 1 0 0 1 C9
EN_DI EN_C EN_N
st EN_C EN_J EN_T
1 parameter 1 1 ↑ - - - M_MI OST_
OST
LN_G
UDGE EMP
-
X MEAN AIN
nd CABC
2 parameter 1 1 ↑ -
_DD
SAVEPOWER[6:0] -
rd
3 parameter 1 1 ↑ - MEAN_OFFSET[7:0] -
th
4 parameter 1 1 ↑ - - - - - CABC_FLM[3:0] -
SEL_
th INVP
5 parameter 1 1 ↑ - - SEL_PWMCLK[2:0] SEL_GAIN[1:0]
ULS
BLDU -
TY
th
6 parameter 1 1 ↑ - PWM_PERIOD[7:0] -
th
7 parameter 1 1 ↑ - - DIM_FRAME[6:0] -
th
8 parameter 1 1 ↑ - CABC_STEP[7:0] -
th
9 parameter 1 1 ↑ - CABC_CLKEN[7:0] -
This command is used to set CABC function.

INVPULS: The backlight PWM output polarity select.

‘0’, The backlight PWM output is low level active.
‘1’, The backlight PWM output is high level active.

SEL_BLDUTY : The backlight PWM output duty on/off control when CABC operated.
‘0’, The backlight PWM output duty is 100%.
‘1’, The backlight PWM output duty is calculated from CABC operation.

SEL_PWMCLK[2:0] : Internal PWM_CLK divider for CABC clock.

SEL_PWMCLK[2:0] Brightness Control Clock

0 0 0 PWM_CLK / 1
0 0 1 PWM_CLK / 2
0 1 0 PWM_CLK / 4
0 1 1 PWM_CLK / 8
1 0 0 PWM_CLK / 16
1 0 1 PWM_CLK / 32
1 1 0 PWM_CLK / 64
Description 1 1 1 PWM_CLK / 128

SEL_GAIN[1:0]: CABC gain select. Internal use and not Open. Please set to “11”.

PWM_PERIOD[7:0] : The backlight PWM output period setting.

Backlight PWM output period
= 1 / (PWM_CLK / clock divider (SEL_PWMCLK[2:0] )) x (255x(PWM_PERIOD[7:0])).

SAVEPOWER[6:0] : Minimum CABC gain / maximum CABC duty output select.

To define the minimum gain or maximum duty of CABC block output.
If not used, please set to”0000000”.

CABC_DD: Internal use and not open.

MEAN_OFFSET[7:0]: Internal use, not open.

CABC_FLM[3:0]: CABC dimming frame number for each step.

CABC_STEP[7:0]: Internal use and not open.

CABC_CLKEN[7:0]: Internal use and not open.

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EN_DIM_MIX: Internal use and not open. Please set to”1”.

EN_COST_MAIN: Internal use and not open. Please set to”1”.

EN_COST: Internal use and not open. Please set to”1”.

EN_NLN_GAIN: Internal use and not open. Please set to”1”.

EN_JUDGE: Internal use and not open. Please set to”1”.

EN_TEMP: Internal use and not open. Please set to”0”.

Restrictions SETEXTC turn on to enable this command.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Status Default value OTP value
EN_DIM_MIX =1,
EN_COST_MEAN =1,
EN_COST =1,
EN_NLN_GAIN =1,
EN_JUDGE =1,
EN_TEMP =0, SEL_PWMCLK[2:0],
CABC_DD =0, SEL_GAIN[1:0],
SAVEPOWER[6:0] =0x00h INVPULS,
Power On Sequence
MEAN_OFFSET[7:0] =0x00h SEL_BLDUTY,
S/W Reset
Default CABC_FLM[3:0] = 0001, PWM_PERIOD[7:0],
H/W Reset
SEL_PWMCLK[2:0] =010, DIM_FRAME[6:0],
SEL_GAIN[1:0] =11, CABC_STEP[7:0],
INVPULS =1, CABC_CLKEBN[7:0]
SEL_BLDUTY =1,
PWM_PERIOD[7:0] =0x2Bh,
DIM_FRAME[6:0] =0x1Eh,
CABC_STEP[7:0] =0x1Eh,
CABC_CLKEBN[7:0] =0x00h

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CCH SETPANEL( Set panel related register)

DNC NRD NWR D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 1 0 0 1 1 0 0 CC
st
1 parameter 1 1 ↑ - - - - - SS_PANEL - REV_PANEL BGR_PANEL -
This command is used to set setting of panel related register and make panel module meets below spec
from viewpoint of user
BGR_PANEL: The order of <R><G> dot color for module supplier, default value is stored in OTP.
If color filter of panel is <G><R> type, setting BGR_PANEL = 1, if color filter of panel is
<R><G> type, setting BGR_PANEL = 0. This bit is to make panel module look like a <R><G>
type panel form the user viewpoint.
Description0 SS_PANEL: Specify the shift direction of source driver output. When SS_PANEL = 0, the shift
direction from S1 to S1440 When SS_PANEL = 1, the shift direction from S1440 to S1.
REV_PANEL: Select the inversion of the display of all characters and graphics. This setting allows
the display of the same data on both normally-white and normally-black panels.
REV_PANEL = 0 normal-white panel
REV_PANEL = 1 normal-black panel

Restrictions SETEXTC turn on to enable this command

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D5H SETGIP
DNC NRD NWR D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 1 0 1 0 1 0 1 D5
st
1 parameter 1 1 ↑ - - - - - SHR_0[11:8] -
nd
2 parameter 1 1 ↑ - SHR_0[7:0] -
rd
3 parameter 1 1 ↑ - - - - - SHR_1[11:8] -
th
4 parameter 1 1 ↑ - SHR_1[7:0] -
th
5 parameter 1 1 ↑ - SPD[7:0] -
th
6 parameter 1 1 ↑ - CHR[7:0] -
th
7 parameter 1 1 ↑ - CON[7:0] -
th
8 parameter 1 1 ↑ - COFF[7:0] -
th
9 parameter 1 1 ↑ - SHP[3:0] SCP[3:0] -
th
10 parameter 1 1 ↑ - CHP[3:0] CCP[3:0]
th
11 parameter 1 1 ↑ - SOS_1[4:0] SOS_0[3:0] -
th
12 parameter 1 1 ↑ - SOS_3[4:0] SOS_2[3:0] -
th
13 parameter 1 1 ↑ - COS_1[4:0] COS_0[3:0] -
th
14 parameter 1 1 ↑ - COS_3[4:0] COS_2[3:0] -
th
15 parameter 1 1 ↑ - COS_5[4:0] COS_4[3:0] -
th
16 parameter 1 1 ↑ - COS_7[4:0] COS_6[3:0] -
th
17 parameter 1 1 ↑ - SOS_1_ML[3:0] SOS_0_ML[3:0] -
th
18 parameter 1 1 ↑ - SOS_3_ML[3:0] SOS_2_ML[3:0] -
th
19 parameter 1 1 ↑ - COS_1_ML[3:0] COS_0_ML[3:0] -
th
20 parameter 1 1 ↑ - COS_3_ML[3:0] COS_2_ML[3:0] -
th
21 parameter 1 1 ↑ - COS_5_ML[3:0] COS_4_ML[3:0] -
th
22 parameter 1 1 ↑ - COS_7_ML[3:0] COS_6_ML[3:0] -
th
23 parameter 1 1 ↑ - - - GTO[5:0] -
th
24 parameter 1 1 ↑ - GNO[7:0] -
th
25 parameter 1 1 ↑ - EQ_DELAY[7:0] -
th
26 parameter 1 1 ↑ - GIP_OPT[7:0] -

This command is used for GIP timing output control.

Description

Himax Confidential -P.248-

SHP[3:0
STV0 ]

STV1
SCP[3:0
1xHsync

CHP[3:0
CK0 ]

CK1
1xHsyn
CK2 c

CK3
CCP[3:0
]

SHR_0[11:0]:STV_0 Hsync Rise

SHR_0[11:0] Start Pulse 0 Output delay
0x000h 0 x HSYNC
0x001h 1 x HSYNC
0x002h 2 x HSYNC
0x003h 3 x HSYNC
0x004h 4 x HSYNC
0x005h 5 x HSYNC
‧‧‧‧‧
0xFFEh 4094 x HSYNC
0xFFFh 4095 x HSYNC

SHR_1[11:0]:STV_1 Hsync Rise

SHR_1[11:0] Start Pulse 1 Output delay
0x000h 0 x HSYNC
0x001h 1 x HSYNC
0x002h 2 x HSYNC
0x003h 3 x HSYNC
0x004h 4 x HSYNC
0x005h 5 x HSYNC
‧‧‧‧‧
0xFFEh 4094 x HSYNC
0xFFFh 4095 x HSYNC

SPD[7:0]: STV Pulse Delay

SPD[7:0] Start Pulse Output delay
0x00h 0 x OSC CLK
0x01h 1 x OSC CLK
0x02h 2 x OSC CLK
0x03h 3 x OSC CLK
0x04h 4 x OSC CLK
0x05h 5 x OSC CLK
‧‧‧‧‧
0xFEh 254 x OSC CLK
0xFFh 255 x OSC CLK
Himax Confidential -P.249-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02

CHR[7:0]: CK Hsync Rise

CHR[7:0] Start Pulse 1 Output delay
0x00h 0 x HSYNC
0x01h 1 x HSYNC
0x02h 2 x HSYNC
0x03h 3 x HSYNC
0x004h 4 x HSYNC
0x005h 5 x HSYNC
‧‧‧‧‧
0xFEh 254 x HSYNC
0xFFh 255 x HSYNC

CON[7:0]: CK Pulse Delay

CON[7:0] CK Pulse Output delay
0x00h 0 x OSC CLK
0x01h 1 x OSC CLK
0x02h 2 x OSC CLK
0x03h 3 x OSC CLK
0x04h 4 x OSC CLK
0x05h 5 x OSC CLK
‧‧‧‧‧
0xFEh 254 x OSC CLK
0xFFh 255 x OSC CLK
Note: Avoid CON[7:0] OSC LCK width > 1-line width

COFF[7:0]: CK Pulse width

COFF[7:0] CK Pulse Output
0x00h Inhibit
0x01h 1 x OSC CLK
0x02h 2 x OSC CLK
0x03h 3 x OSC CLK
0x04h 4 x OSC CLK
0x05h 5 x OSC CLK
‧‧‧‧‧
0xFEh 254 x OSC CLK
0xFFh 255 x OSC CLK
Note: COFF[7:0] value must bigger than CON[7:0] value

SHP[3:0]: Width of STV High pulse

SHP3 SHP2 SHP1 SHP0 Start Pulse Width
0 0 0 0 1 x HSYNC
0 0 0 1 2 x HSYNC
0 0 1 0 3 x HSYNC
0 0 1 1 4 x HSYNC
0 1 0 0 5 x HSYNC
0 1 0 1 6 x HSYNC
‧‧‧‧‧
1 1 1 0 15 x HSYNC
1 1 1 1 16 x HSYNC

SCP[3:0]: A Cycle of STV pulse

SCP3 SCP2 SCP1 SCP0 Start Pulse cycle
0 0 0 0 1 x HSYNC
0 0 0 1 2 x HSYNC
0 0 1 0 3 x HSYNC
0 0 1 1 4 x HSYNC
0 1 0 0 5 x HSYNC
0 1 0 1 6 x HSYNC
Himax Confidential -P.250-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
‧‧‧‧‧
1 1 1 0 15 x HSYNC
1 1 1 1 16 x HSYNC

CHP[3:0]: Width of CK High pulse

CHP3 CHP2 CHP1 CHP0 CK Pulse Width
0 0 0 0 1 x HSYNC
0 0 0 1 2 x HSYNC
0 0 1 0 3 x HSYNC
0 0 1 1 4 x HSYNC
0 1 0 0 5 x HSYNC
0 1 0 1 6 x HSYNC
‧‧‧‧‧
1 1 1 0 15 x HSYNC
1 1 1 1 16 x HSYNC

CCP[3:0]: A Cycle of CK pulse

CCP3 CCP2 CCP1 CCP0 CK Pulse cycle
0 0 0 0 1 x HSYNC
0 0 0 1 2 x HSYNC
0 0 1 0 3 x HSYNC
0 0 1 1 4 x HSYNC
0 1 0 0 5 x HSYNC
0 1 0 1 6 x HSYNC
‧‧‧‧‧
1 1 1 0 15 x HSYNC
1 1 1 1 16 x HSYNC

SOS_0[3:0] for CGOUT9_L pulse selector

SOS_1[3:0] for CGOUT10_L pulse selector
SOS_2[3:0] for CGOUT9_R pulse selector
SOS_3[3:0] for CGOUT10_R pulse selector

SOS_0/1/2/3[3] SOS_0/1/2/3[2] SOS_0/1/2/3[1] SOS_0/1/2/3[0] Signal Type

0 0 0 0 STV-0
0 0 0 1 STV-1
0 0 1 0 STV-2
0 0 1 1 STV-3
0 1 0 0 CK-0
0 1 0 1 CK-1
0 1 1 0 CK-2
0 1 1 1 CK-3
1 0 0 0 CK-4
1 0 0 1 CK-5
1 0 1 0 CK-6
1 0 1 1 CK-7
1 1 0 0 Inhibit
1 1 0 1 Inhibit
1 1 1 0 Inhibit
1 1 1 1 Inhibit

COS_0[3:0] for CGOUT5L pulse selector

COS_1[3:0] for CGOUT6L pulse selector
COS_2[3:0] for CGOUT7L pulse selector
COS_3[3:0] for CGOUT8L pulse selector
COS_4[3:0] for CGOUT5R pulse selector
COS_5[3:0] for CGOUT6R pulse selector
COS_6[3:0] for CGOUT7R pulse selector
COS_7[3:0] for CGOUT8R pulse selector
Himax Confidential -P.251-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02

COS_0-7[3] COS_0-7[2] COS_0-7[1] COS_0-7[0] Signal Type

Once the R36h ML=1 the STV gate control signals are refered to the below registers:
SOS_0_ML[3:0] for CGOUT9_L pulse selector
SOS_1_ML[3:0] for CGOUT10_L pulse selector
SOS_2_ML[3:0] for CGOUT9_R pulse selector
SOS_3_ML[3:0] for CGOUT10_R pulse selector

SOS_0-3_ML[3] SOS_0-3_ML[2] SOS_0-3_ML[1] SOS_0-3_ML[0] Signal Type

Once the R36h ML=1 the CK gate control signals are refered to the below registers:
COS_0_ML[3:0] for CGOUT5L pulse selector
COS_1_ML[3:0] for CGOUT6L pulse selector
COS_2_ML[3:0] for CGOUT7L pulse selector
COS_3_ML[3:0] for CGOUT8L pulse selector
COS_4_ML[3:0] for CGOUT5R pulse selector
COS_5_ML[3:0] for CGOUT6R pulse selector
COS_6_ML[3:0] for CGOUT7R pulse selector
COS_7_ML[3:0] for CGOUT8R pulse selector

COS_0-7_ML[3] COS_0-7_ML[2] COS_0-7_ML[1] COS_0-7_ML[0] Signal Type

0 0 0 0 STV-0
0 0 0 1 STV-1
0 0 1 0 STV-2
0 0 1 1 STV-3
0 1 0 0 CK-0
Himax Confidential -P.252-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
0 1 0 1 CK-1
0 1 1 0 CK-2
0 1 1 1 CK-3
1 0 0 0 CK-4
1 0 0 1 CK-5
1 0 1 0 CK-6
1 0 1 1 CK-7
1 1 0 0 Inhibit
1 1 0 1 Inhibit
1 1 1 0 Inhibit
1 1 1 1 Inhibit

GTO[5:0] GPWR toggle frequency

6’h00 64 x Frame
6’h01 1 x Frame
6’h02 2 x Frame
6’h03 3 x Frame
‧‧‧‧‧ ‧‧‧‧‧
6’h3D 61 x Frame
6’h3E 62 x Frame
6’h3F 63 x Frame

GNO[7:0] GPWR non-overlap timing

8’h00 0
8’h01 1 x OSC CLK
8’h02 2 x OSC CLK
8’h03 3 x OSC CLK
‧‧‧‧‧ ‧‧‧‧‧
8’hFD 253 x OSC CLK
8’hFE 254 x OSC CLK
8’hFF 255 x OSC CLK

EQ_DELAY[7:0] is in-house function not open.

GIP_OPT[7:3] is in-hose function and not open.

GIP_OPT[2] is stv_2_time, In order to meet 2 STV pulses for BP and FP separately. It is the function of
controlling the STV-0 and STV-1 pulses in the begin of a frame, and controlling the STV-2 and STV-3
pulses in the end of a frame. The pulses STV-2 and STV-3 started in position are determined by
SHR_1[11:0].
GIP_OPT[1] is stv_gated, CK will be off while STV on.
GIP_OPT[0] is toggle_en, CK will toggle while porch duration.

Himax Confidential -P.253-

Status Default value OTP value

SHR_0[11:0]= 0x02h
SHR_1[11:0]= 0x01h
SPD[7:0]= 0x02h
CHR[7:0]= 0x03h
CON[7:0]= 0x20h
COFF[7:0]= 0x6Cg
SCP[3:0]= 0x03h SHR_0[11:0], SHR_1[11:0]
SHP[3:0]= 0x00h SPD[7:0], CHR[7:0]
CCP[3:0]= 0x03h CON[7:0], COFF[7:0]
CHP[3:0]= 0x00h SCP[3:0], SHP[3:0]
SOS_0[3:0]= 0x00h CCP[3:0], CHP[3:0]
SOS_1[3:0]= 0x00h SOS_0[3:0], SOS_1[3:0]
SOS_2[3:0]= 0x00h SOS_2[3:0], SOS_3[3:0]
SOS_3[3:0]= 0x00h COS_0[3:0], COS_1[3:0]
COS_0[3:0]= 0x00h COS_2[3:0], COS_3[3:0]
COS_1[3:0]= 0x06h COS_4[3:0], COS_5[3:0]
COS_2[3:0]= 0x04h COS_6[3:0], COS_7[3:0]
COS_3[3:0]= 0x00h SOS_0_ML[3:0]
Power On Sequence COS_4[3:0]= 0x01h SOS_1_ML[3:0]
Default
S/W Reset COS_5[3:0]= 0x07h SOS_2_ML[3:0]
H/W Reset COS_6[3:0]= 0x05h SOS_3_ML[3:0]
COS_7[3:0]= 0x07h COS_0_ML[3:0]
SOS_0_ML[3:0]= 0x00h COS_1_ML[3:0]
SOS_1_ML[3:0]= 0x00h COS_2_ML[3:0]
SOS_2_ML[3:0]= 0x00h COS_3_ML[3:0]
SOS_3_ML[3:0]= 0x00h COS_4_ML[3:0]
COS_0_ML[3:0]= 0x01h COS_5_ML[3:0]
COS_1_ML[3:0]= 0x05h COS_6_ML[3:0]
COS_2_ML[3:0]= 0x07h COS_7_ML[3:0]
COS_3_ML[3:0]= 0x05h GTO[5:0], GNO[7:0]
COS_4_ML[3:0]= 0x00h EQ_DELAY[7:0]
COS_5_ML[3:0]= 0x04h GIP_OPT[7:0]
COS_6_ML[3:0]= 0x06h
COS_7_ML[3:0]= 0x04h
GTO[5:0]= 0x01h
GNO[7:0]= 0x0Ch
EQ_DELAY[7:0]= 0x0Ch
GIP_OPT[7:0]= 0x00h

Himax Confidential -P.254-

D8H SETTPSNR (Set the Temp Senor control)

DNC NRD NWR D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 1 0 1 0 1 0 1 D5
st (read
1 parameter 1 1 ↑ - - - - TSRAW[4:0]
only)
nd
2 parameter 1 1 ↑ - - - - TS_OS2[4:0] -
rd
3 parameter 1 1 ↑ - BT_P2[3:0] BT_P1[3:0] -
th
4 parameter 1 1 ↑ - BT_P4[3:0] BT_P3[3:0] -
th
5 parameter 1 1 ↑ - - - - D0[4:0] -
th
6 parameter 1 1 ↑ - TS_G[2:0] I0[4:0] -
th
7 parameter 1 1 ↑ - - TS_OS1[4:3] D1[4:0] -
th
8 parameter 1 1 ↑ - TS_OS1[2:0] I1[4:0] -
th
9 parameter 1 1 ↑ - PORE RER[1:0] D2[4:0] -
th
10 parameter 1 1 ↑ - - TF_ON TSON I2[4:0] -

This command is used for the temperature senor control.

TSON : Temp. sensor on/off function.
1 = On
0 = Off (default);
VGH level is controlled by only BT_P1[1:0]
TF_ ON : Median filter on/off function.
1 = On (default)
0 = Off

Description

Temp. sensor variation = Under +/- 3 degree

TSRAW[4:0] Temp.(℃)
00000 -18.55 ~ -20.00
00001 -15.65 ~ -18.55
00010 -12.74 ~ -15.65
00011 -9.84 ~ -12.74
00100 -6.94 ~ -9.84
00101 -4.03 ~ -6.94
00110 -1.13 ~ -4.03
00111 1.77 ~ -1.13
01000 4.68 ~ 1.77
01001 7.58 ~ 4.68
01010 10.48 ~ 7.58
01011 13.39 ~ 10.48
01100 16.29 ~ 13.39
01101 19.19 ~ 16.29
01110 22.10 ~ 19.19
01111 25.00 ~ 22.10

Himax Confidential -P.255-

TS_G[2:0] : Gain control of Temp sensor output.

TS_G[2:0] Gain Range

000 0.8125
001 0.8750
010 0.9375
011 1
100 1.0625
101 1.1250
110 1.1875
111 1.2500
(step=0.0625)

Himax Confidential -P.256-

11111

00000

-20 70 Temp.

TS_OS1[4:0] /
Temp.(℃)
TS_OS2[4:0]
00000 -54
00001 -51
00010 -48
00011 -45
….. ..
10010 0
….. ..
11100 30
11101 33
11110 36
11111 39

RER[1:0] : Refresh rate of TSRAW[4:0]

RER[1:0] Refresh Rate

00 Every 4 vsync
01 Every 6 vsync
10 Every 60 vsync
11 Setting disabled
VSYNC

TSRAW[3:0] TSRAW1[3:0] TSRAW2[3:0]

S864 Porch S1

PORE: The point of refresh rate

PORE Description
0 Start of vertical porch
1 End of vertical porch

Himax Confidential -P.257-

BT : VGH pumping control

VGH

4- step
x7
Phase 1

Phase 2
x6

Phase 3
x5

Phase 4
x4

I0[4:0] I1[4:0] I2[4:0] Temp Sensor Output

D0[4:0] D1[4:0] D2[4:0]
TSRAW[4:0]

10 25 40

* I0~2 & D0~2 is needed for hysterisis

BT_P1[3:0] : VGH control at Phase 1

BT_P2[3:0] : VGH control at Phase 2
BT_P3[3:0] : VGH control at Phase 3
BT_P4[3:0] : VGH control at Phase 4

BT_P1[3:0]/ BT_P2[3:0]/
VGH VGL
BT_P3[3:0]/ BT_P4[3:0]
0000 2*(VSP-VSN) VDDDN-1*(VSP-VSN)
0001 2*(VSP-VSN) -1*(VSP-VSN)
0010 2*(VSP-VSN) VDD3-1*(VSP-VSN)
0011 (VSP-VSN)+(VDD3-VSN) VDDDN-1*(VSP-VSN)
0100 (VSP-VSN)+(VDD3-VSN) -1*(VSP-VSN)
0101 (VSP-VSN)+(VDD3-VSN) VDD3-1*(VSP-VSN)
0110 (VSP-VSN)+(VSP-VSSD) VDDDN-1*(VSP-VSN)
0111 (VSP-VSN)+(VSP-VSSD) -1*(VSP-VSN)
1000 (VSP-VSN)+(VSP-VSSD) VDD3-1*(VSP-VSN)
1001 (VDD3-VSN)+(VSP-VSSD) VDDDN-1*(VSP-VSN)
1010 (VDD3-VSN)+(VSP-VSSD) -1*(VSP-VSN)
1011 (VDD3-VSN)+(VSP-VSSD) VDD3-1*(VSP-VSN)
1100 (VSP-VSN) VDDDN-1*(VSP-VSN)
1101 (VSP-VSN) -1*(VSP-VSN)
1110 (VSP-VSN) VDD3-1*(VSP-VSN)
1111 2*(VSP-VSSD) -2*(VSP-VSSD)

Himax Confidential -P.258-

I0 [4:0] : Set the lower boundary of the phase 1, 2

D0 [4:0] : Set the higher boundary of the phase 1, 2
I1 [4:0] : Set the lower boundary of the phase 2, 3
D1 [4:0] : Set the higher boundary of the phase 2, 3
I2 [4:0] : Set the lower boundary of the phase 3, 4
D2 [4:0] : Set the higher boundary of the phase 3, 4

Boundary of the phase:

IO,DO,I1,D1,I2,D2[4:0] Temp.(℃)
00000 -20
00001 -17
00010 -14
00011 -11
00100 -8
----- -----
----- -----
11100 64
11101 67
11110 70
11111 Disabled

Restrictions SETEXTC turn on to enable this command.

Status Availability
Register Idle Mode Off, Sleep Out Yes
Availability Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes

Status Default value OTP value

TS_OS1[4:0]=0x0Ah,
TS_OS2[4:0]=0x12h,
BT_P1[3:0]=4b’0100,
BT_P2[3:0]=4b’0111,
BT_P3[3:0]=4b’0111, TS_OS1[4:0],
BT_P4[3:0]=4b’1010, TS_OS2[4:0],
D0[4:0]=0x0Ch, BT_P1[3:0], BT_P2[3:0],
Default Power On Sequence
D1[4:0]= 0x17h, BT_P3[3:0], BT_P4[3:0],
S/W Reset
D2[4:0]= 0x17h, D0[4:0], D1[4:0], D2[4:0],
H/W Reset
I0[4:0]= 0x0Ah, I0[4:0], I1[4:0], I2[4:0],
I1[4:0]= 0x15h, PORE, RER,
I2[4:0]= 0x15h, TF_ON, TSON
PORE=0,
RER=2b’00,
TF_ON=1,
TSON=0,

Himax Confidential -P.259-

6.2.68 SETGAMMA: Set gamma curve related setting (E0h)

E0H SETGAMMAR ( Set Gamma Curve Related Setting )

DNC NRD NWR D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 1 1 0 0 0 0 0 E0
st
1 parameter 1 1 ↑ - - - G1_VRP0[5:0] -
nd
2 parameter 1 1 ↑ - - - G1_VRP1[5:0] -
rd
3 Parameter 1 1 ↑ - - - G1_VRP2[5:0] -
th
4 Parameter 1 1 ↑ - - - G1_VRP3[5:0] -
th
5 Parameter 1 1 ↑ - - - G1_VRP4[5:0] -
th
6 Parameter 1 1 ↑ - - - G1_VRP5[5:0] -
th
7 Parameter 1 1 ↑ - - G1_PRP0[6:0] -
th
8 Parameter 1 1 ↑ - - G1_PRP1[6:0] -
th G1_CGMP0
9 Parameter 1 1 ↑ - - G1_ PKP0[4:0] -
[1:0]
th G1_CGMP1
10 Parameter 1 1 ↑ - - G1_PKP1[4:0] -
[1:0]
th G1_CGMP2
11 Parameter 1 1 ↑ - - G1_PKP2[4:0] -
[1:0]
th G1_CGMP3
12 Parameter 1 1 ↑ - - G1_PKP3[4:0] -
[1:0]
th
13 Parameter 1 1 ↑ - G1_CGMP5 G1_CGMP4 - G1_PKP4[4:0] -
th
14 Parameter 1 1 ↑ - - - - G1_PKP5[4:0] -
th
15 Parameter 1 1 ↑ - - - - G1_PKP6[4:0] -
th
16 Parameter 1 1 ↑ - - - - G1_PKP7[4:0] -
th
17 Parameter 1 1 ↑ - - - - G1_PKP8[4:0] -
th
18 Parameter 1 1 ↑ - - - G1_VRN0[5:0] -
th
19 Parameter 1 1 ↑ - - - G1_VRN1[5:0] -
th
20 Parameter 1 1 ↑ - - - G1_VRN2[5:0] -
th
21 Parameter 1 1 ↑ - - - G1_VRN3[5:0] -
th
22 Parameter 1 1 ↑ - - - G1_VRN4[5:0] -
th
23 Parameter 1 1 ↑ - - - G1_VRN5[5:0] -
th
24 Parameter 1 1 ↑ - - G1_PRN0[6:0] -
th
25 Parameter 1 1 ↑ - - G1_PRN1[6:0] -
th G1_CGMN0
26 Parameter 1 1 ↑ - - G1_PKN0[4:0] -
[1:0]
th G1_CGMN1
27 Parameter 1 1 ↑ - - G1_PKN1[4:0] -
[1:0]
th G1_CGMN2
28 Parameter 1 1 ↑ - - G1_PKN2[4:0] -
[1:0]
th G1_CGMN3
29 Parameter 1 1 ↑ - - G1_PKN3[4:0] -
[1:0]
th
30 Parameter 1 1 ↑ - G1_CGMN5 G1_CGMN4 - G1_PKN4[4:0] -
th
31 Parameter 1 1 ↑ - - - - G1_PKN5[4:0] -
th
32 Parameter 1 1 ↑ - - - - G1_PKN6[4:0] -
th
33 Parameter 1 1 ↑ - - - - G1_PKN7[4:0] -
th
34 Parameter 1 1 ↑ - - - - G1_PKN8[4:0] -

Register Positive Negative

Description
Groups Polarity Polarity
Center G1_PRP0 6-0 G1_PRN0 6-0 Variable resistor (PRP/N0) for center adjustment
Adjustment G1_PRP1 6-0 G1_PRN1 6-0 Variable resistor (PRP/N1)for center adjustment
G1_PKP0 4-0 G1_PKN0 4-0 32-to-1 selector (voltage level of grayscale 3)
G1_PKP1 4-0 G1_PKN1 4-0 32-to-1 selector (voltage level of grayscale 7)
G1_PKP2 4-0 G1_PKN2 4-0 32-to-1 selector (voltage level of grayscale 19)
Description G1_PKP3 4-0 G1_PKN3 4-0 32-to-1 selector (voltage level of grayscale 25)
Macro 32-to-1 selector (voltage level of grayscale 32 for positive polarity
G1_PKP4 4-0 G1_PKN4 4-0
Adjustment and grayscale 31 for negative polarity)
G1_PKP5 4-0 G1_PKN5 4-0 32-to-1 selector (voltage level of grayscale 38)
G1_PKP6 4-0 G1_PKN6 4-0 32-to-1 selector (voltage level of grayscale 44)
G1_PKP7 4-0 G1_PKN7 4-0 32-to-1 selector (voltage level of grayscale 56)
G1_PKP8 4-0 G1_PKN8 4-0 32-to-1 selector (voltage level of grayscale 60)
G1_VRP0 5-0 G1_VRN0 5-0 Variable resistor (VRP/N0)for offset adjustment
Offset G1_VRP1 5-0 G1_VRN1 5-0 Variable resistor (VRP/N1)for offset adjustment
Adjustment G1_VRP2 5-0 G1_VRN2 5-0 Variable resistor (VRP/N2)for offset adjustment
Himax Confidential -P.260-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
G1_ VRP3 5-0 G1_VRN3 5-0 Variable resistor (VRP/N3)for offset adjustment
G1_VRP4 5-0 G1_VRN4 5-0 Variable resistor (VRP/N4)for offset adjustment
G1_VRP5 5-0 G1_VRN5 5-0 Variable resistor (VRP/N5)for offset adjustment
G1_CGMP/N0: Select to change gamma resistor stream.
G1_CGMP/N1: Select to change gamma resistor stream.
G1_CGMP/N2: Select to change gamma resistor stream.
G1_CGMP/N3: Select to change gamma resistor stream. Please refer to Figure 5.31.
G1_CGMP/N4: Select to change gamma resistor stream. Please refer to Figure 5.31.
G1_CGMP/N5: Select to change gamma resistor stream. Please refer to Figure 5.31.

Restriction SETEXTC turn on to enable this command.

Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Status Default value OTP value
Power On Sequence G1_VRP0[5:0]=0x00h, G1_VRP0[5:0], G1_VRP1[5:0],
S/W Reset G1_VRP1[5:0]=0x18h, G1_VRP2[5:0], G1_VRP3[5:0],
H/W Reset G1_VRP2[5:0]=0x1Fh, G1_VRP4[5:0], G1_VRP5[5:0],
G1_VRP3[5:0]=0x3Fh, G1_PRP0[6:0], G1_PRP1[6:0],
G1_VRP4[5:0]=0x3Fh, G1_CGMP0[1:0], G1_CGMP1[1:0],
G1_VRP5[5:0]=0x3Fh, G1_CGMP2[1:0], G1_CGMP3[1:0],
G1_PRP0[6:0]=0x33h, G1_CGMP4, G1_CGMP5,
G1_PRP1[6:0]=0x57h, G1_ PKP0[4:0], G1_ PKP1[4:0],
G1_CGMP0[1:0]=00, G1_ PKP2[4:0], G1_ PKP3[4:0],
G1_CGMP1[1:0]=00, G1_ PKP4[4:0], G1_ PKP5[4:0],
G1_CGMP2[1:0]=00, G1_ PKP6[4:0], G1_ PKP7[4:0],
G1_CGMP3[1:0]=00, G1_ PKP8[4:0], G1_VRN0[5:0],
G1_CGMP4=0, G1_CGMP5=0, G1_VRN1[5:0], G1_VRN2[5:0],
G1_ PKP0[4:0]=0x07h, G1_ G1_VRN3[5:0], G1_VRN4[5:0],
PKP1[4:0]=0x0Dh, G1_VRN5[5:0], G1_ PKN0[4:0],
G1_ PKP2[4:0]=0x0Fh, G1_ G1_ PKN1[4:0], G1_ PKN2[4:0],
PKP3[4:0]=0x13h, G1_ PKN3[4:0], G1_ PKN4[4:0],
G1_ PKP4[4:0]=0x16h, G1_ G1_ PKN5[4:0], G1_ PKN6[4:0],
PKP5[4:0]=0x14h, G1_ PKN7[4:0], G1_ PKN8[4:0],
G1_ PKP6[4:0]=0x16h, G1_ G1_CGMN0[1:0],
Default PKP7[4:0]=0x18h, G1_CGMN1[1:0],
G1_ PKP8[4:0]=0x1Fh, G1_CGMN2[1:0],
G1_VRN0[5:0]=0x00h, G1_CGMN3[1:0],
G1_VRN1[5:0]=0x18h, G1_CGMN4, G1_CGMN5.
G1_VRN2[5:0]=0x1Fh,
G1_VRN3[5:0]=0x3Fh,
G1_VRN4[5:0]=0x3Fh,
G1_VRN5[5:0]=0x3Fh,
G1_ PKN0[4:0]=0x07h,
G1_ PKN1[4:0]=0x0Dh,
G1_ PKN2[4:0]=0x0Fh,
G1_ PKN3[4:0]=0x13h,
G1_ PKN4[4:0]=0x16h,
G1_ PKN5[4:0]=0x14h,
G1_ PKN6[4:0]=0x16h,
G1_ PKN7[4:0]=0x18h,
G1_ PKN8[4:0]=0x1Fh,
G1_CGMN0[1:0]=00,
G1_CGMN1[1:0]=00,
G1_CGMN2[1:0]=00,
G1_CGMN3[1:0]=00,
G1_CGMN4=0, G1_CGMN5=0,
Himax Confidential -P.261-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
6.2.69 SETOTPKEY (E9h)

E9H SETOTPKEY
DNC NRD NWR D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 1 1 0 1 0 0 1 E9
st
1 parameter 1 1 ↑ - OTP_KEY0[7:0] 00h
nd
2 parameter 1 1 ↑ - OTP_KEY1[7:0] 00h
This command is used to set OTP key to enter or leave OTP program mode.
OTP_KEY0[7:0]
Description Note
OTP_KEY1[7:0]

OTP_KEY0[7:0] = 0xAAh
Enter OTP program mode
OTP_KEY1[7:0] = 0x55h
Description
OTP_KEY0[7:0] = 0x00h
Leave OTP program mode
OTP_KEY1[7:0] = 0x00h
1. If HX8369-A00 operate on OTP program
mode, Then keep on OTP program mode.
Other value Invalid
2. If HX8369-A00 operate on non-OTP program
mode, Then keep on non-OTP program mode.
Restrictions SETEXTC turn on to enable this command.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Status Default value OTP value
Power On Sequence
Default OTP_KEY0[7:0]=0x00h,
S/W Reset
OTP_KEY1[7:0]=0x00h N/A
H/W Reset

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F4H GETHXIC
DNC NRD NWR D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 1 1 1 0 1 0 0 F4
st
1 parameter 1 ↑ 1 - Himax ID[7:0] -
Description This command is used to get LCD ID.
Restrictions SETEXTC turn on to enable this command.
Status Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Register Normal Mode On, Idle Mode On, Sleep Out Yes
Availability Partial Mode On, Idle Mode Off, Sleep Out Yes
Partial Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Status Default value OTP value
Power On Sequence
Default
S/W Reset Himax ID[7:0] = 0x69h N/A
H/W Reset

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FDH SETCNCD/GETCNCD (Set/Get Continue Command)

DNC NRD NWR D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 1 1 1 1 1 0 1 FD
st
1 parameter 1 1 ↑ - WR_CMD_CN[7:0] -
This function is use to instead of Register-Content interface mode.
Description
The parameter for SETCNCD will continue to read from the last command address automatically.
Restrictions SETEXTC turn on to enable this command
Status Availability
Register Idle Mode Off, Sleep Out Yes
Availability Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default value OTP value
Power On Sequence
Default
S/W Reset
N/A N/A
H/W Reset

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FEH SET SPI READ INDEX (Set SPI READ Command Address)
DNC NRD NWR D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 1 1 1 1 1 1 0 FE
st
1 parameter 1 1 ↑ - CMD_ADD[7:0] -
Description SET SPI READ Command Address for User Define Command.
Restrictions SETEXTC turn on to enable this command
Status Availability
Register Idle Mode Off, Sleep Out Yes
Availability Idle Mode On, Sleep Out Yes

Status Default value OTP value

Power On Sequence
Default
S/W Reset CMD_ADD[7:0]=0x00h N/A
H/W Reset

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FFH GETMPUREAD (Read Command Data)

DNC NRD NWR D15-D8 D7 D6 D5 D4 D3 D2 D1 D0 HEX
Command 0 1 ↑ - 1 1 1 1 1 1 1 1 FF
st
1 parameter 1 ↑ 1 - CMD_DATA1[7:0] -
: 1 ↑ 1 - : -
th
n parameter 1 ↑ 1 - CMD_DATAN[7:0] -
Description Read SPI Command Data for User Define Command.
Restrictions SETEXTC turn on to enable this command.
Status Availability
Register Idle Mode Off, Sleep Out Yes
Availability Idle Mode On, Sleep Out Yes
Sleep In or Booster Off Yes
Status Default value OTP value
Power On Sequence
Default
S/W Reset N/A N/A
H/W Reset

Himax Confidential -P.266-

7.1.1 Architecture 1 with PFM circuit

Note: If not use LVGL, please connect the VGL and LVGL together.

Figure 7.1: Power supply with PFM circuit

Himax Confidential -P.267-

Note: If not use LVGL, please connect the VGL and LVGL together.

Figure 7.2: Power supply with HX5186-A

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The HX8369-A00 has an internal power supply circuit to drive TFTLCD panel. Please
set up each voltage output according to the LCD panel.

Name Function Set up value Note

VREF Reference voltage from internal band gap circuit 1.8V -
VSP DC/DC converter circuit output 4.7V ~ 5.5V Do not exceed 6 V
VSN DC/DC converter circuit output -4.7V ~ -5.5V Do not exceed 6V
VSPC DC/DC converter circuit output 4.7V ~ 5.5V Do not exceed 6 V
VSNC DC/DC converter circuit output -4.7V ~ -5.5V Do not exceed 6V
VSPR Reference voltage for gamma circuit 3.5V ~ (VSP – 0.5V) Reference register
VSNR Reference voltage for gamma circuit -3.5V ~ (VSN + 0.5V) Reference register
VDDDN Logic power supply -2.5V -
VGH Positive gate driver output voltage level +9V ~ +20V Depend on VSP and VSN
VGL Negative gate driver output voltage level -6V ~ -13.5V Depend on VSP and VSN
LVGL GIP most negative voltage level VGL-VDD3 Depend on VSP and VSN
VCOM VCOM DC voltage -2V ~ 0V -

Typical
Pad Name Connection
Component Value
VCOM Connect to Capacitor (Max 6V): VCOM ---(-)----| |--- (+)----- VSSA 2.2 µF
VGH Connect to Capacitor (Max 25V): VGH ---(+)----| |--- (-)----- VSSA 1.0 µF
Connect to Capacitor (Max 16V): VGL ---(+)----| |--- (-)----- VSSA 1.0 µF
VF < 0.4V / 20mA @
VGL 25°C, VR ≥30V
Connect to Schottky Diode(VR≥30V): VSSA ---(-)----∫◄--- (+)---- VGL
(Recommended diode:
RB521S-30)
C24AP - C24AN Connect to Capacitor (Max 16V): C24AP ---(+)----| |--- (-)-----C24AN 1.0 µF
C23AP - C23AN Connect to Capacitor (Max 16V): C23AP ---(+)----| |--- (-)-----C23AN 1.0 µF
C22AP - C22AN Connect to Capacitor (Max 16V): C22AP ---(+)----| |--- (-)-----C22AN 1.0 µF
C21AP - C21AN Connect to Capacitor (Max 16V): C21AP ---(+)----| |--- (-)-----C21AN 1.0 µF
C41AP – C41AN Connect to Capacitor (Max 16V): C41AP ---(+)----| |--- (-)-----C41AN 1.0 µF
VSPR Connect to Capacitor (Max 10V): VSPR ---(+)----| |--- (-)-----VSSA 1.0 µF
VSNR Connect to Capacitor (Max 10V): VSNR ---(+)----| |--- (-)-----VSSA 1.0 µF
VDDD Connect to Capacitor (Max 6V): VDDD ---(+)----| |--- (-)-----VSSA 1.0 µF
VDDDN Connect to Capacitor (Max 6V): VDDDN ---(+)----| |--- (-)-----VSSA 1.0 µF
VREF Connect to Capacitor (Max 6V): VREF ---(-)----| |--- (+)----- VSSA 1.0 µF
VSP Connect to Capacitor (Max 10V):VSP ---(+)----| |--- (-)-----VSSA 2.2 µF
VSN Connect to Capacitor (Max 10V):VSN ---(+)----| |--- (-)-----VSSA 2.2 µF
VDD3 Connect to Capacitor (Max 10V): VDD3 ---(+)----| |--- (-)-----VSSA 1.0 µF
Connect to Capacitor (Max 16V): LVGL ---(-)----| |--- (+)----- VSSA 1.0 µF
VF < 0.4V / 20mA @
LVGL Connect to Schottky Diode(VR≥30V): VSSA ---(-)----∫◄--- (+)---- 25°C, VR ≥30V
LVGL (Recommended diode:
RB521S-30)
Table 7.1: Adoptability of component

Himax Confidential -P.269-

The absolute maximum ratings are list on Table 8.1. When used out of the absolute
maximum ratings, the LSI may be permanently damaged. Using the LSI within the
following electrical characteristics limit is strongly recommended for normal operation.
If these electrical characteristic conditions are exceeded during normal operation, the
LSI will malfunction and cause poor reliability.

Item Symbol Unit Value Note

(1),(2)
Power Supply Voltage 1 VDD1~ VSSD V -0.3 to +3.6 Note
(1),(3)
Power Supply Voltage 2 VDD2 ~ VSSA V -0.3 to +5.5 Note
(1) (4)
Power Supply Voltage 3 VDD3 ~ VSSA V -0.3 to +5.5 Note
DSI_VCC ~ (1) (5)
Power Supply Voltage 4 V -0.3 to +3.6 Note
DSI_VSS
(6)
Power Supply Voltage 5 VSP ~ VSSA V -0.3 to +6.6 Note
(7)
Power Supply Voltage 6 VSSA ~ VSN V 0 to -6.6 Note
(8)
Power Supply Voltage 7 VGH ~ VSSA V -0.3 to +25 Note
(9)
Power Supply Voltage 8 VSSA ~ VGL V 0 to -16 Note
(10)
Operating Temperature Topr °C -40 to +85 Note
(11)
Storage Temperature Tstg °C -55 to +110 Note
Note: (1) VDD1, VSSD must be maintained.
(2) To make sure VDD1 ≥ VSSD.
(3) To make sure VDD2≥ VSSA.
(4) To make sure VDD3≥ VSSA.
(5) To make sure DSI_VCC ≥ DSI_VSS.
(6) To make sure VSP ≥ VSSA.
(7) To make sure VSSA ≥ VSN
(8) To make sure VGH ≥ VSSA.
(9) To make sure VSSA ≥ VGL
VGH +|VGL| < 32V
(10) For die and wafer products, specified up to +85℃.
(11) This temperature specifications apply to the TCP package.

Table 8.1: Absolute maximum rating

8.2 ESD protection level

Mode Test condition Criteria Standard

MIL-STD-883F
Human Body Model C=100 pF, R=1.5 kΩ ±2.0KV
Method 3015.7
EIA/JEDEC
Machine Model C=200 pF, R=0.0 Ω ±200V
JESD22-A115-A
Table 8.2: ESD protection level

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Table 8.3: DC characteristic

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8.4.1 DBI Type A interface characteristics

Figure 8.1: DBI Type A interface characteristics(CLK-E mode)

(VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C)

Signal Symbol Parameter Min. Max. Unit Description
WRX_DCX tAST Address setup time 10 -
tAHT Address hold time (Write/Read)
ns -
or DCX_SCL 10 -
System clock cycle time read
register 100 790 ns -
CSX or Read GRAM 350 790 ns -
tcycle
RDX_E Write register 100 790 ns -
Write GRAM @ SLPOUT 33 790 ns -
Write GRAM @ SLPIN 100 790 ns -
tDS Data setup time 15 -
For maximum
tDH Data hold time 25 -
DB23-DB0 tACC Read access time
ns CL=30pF
10 -
tOH Output disable time For minimum CL=8pF
10 -
Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals.
Table 8.4: DBI Type A interface characteristics

Himax Confidential -P.272-

Figure 8.2: DBI Type B interface characteristics

(VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C)

Signal Symbol Parameter Min. Max. Unit Description
tAST Address setup time 10 -
DCX_SCL tAHT Address hold time (Write/Read)
ns -
10 -
tCS Chip select setup time (Write) 20
-
tRCS Chip select setup time (Read ID) 45
CSX tRCSFM Chip Select setup time (Read FM) - ns -
355
tCSF Chip select wait time (Write/Read) -
20
tWC Write cycle (write register) 100 790
tWC Write cycle (write GRAM@SLPOUT) 33 790
WRX_DCX tWC Write cycle (write GRAM@SLPIN) 100 790 ns -
tWRH Control pulse “H” duration 15 630
tWRL Control pulse “L” duration 15 160
tRC Read cycle (read register) 100 790
tRC Read cycle (GRAM) 350 790
RDX_E tRDH Control pulse “H” duration 30 630 ns -
tRDL Control pulse “L” duration 20 160
tWDS Data setup time 15 -
tWDH Data hold time 25 - For maximum CL=30pF
DB23-DB0 tRACC Read access time
ns For minimum CL=8pF
10 -
tRDO Output disable time 10 -
Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals.
Table 8.5: DBI Type B interface characteristics

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Figure 8.3: DBI Type C interface characteristics

(VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA = 25°C)

Signal Symbol Parameter Min. Max. Unit Description
tCSS Chip select setup time (Write) 40 -
CSX tCSH Chip select setup time (Read)
ns -
40 -
tAST Address setup time 10 -
WRX_DCX tAHT Address hold time (Write/Read)
ns -
10 -
tWC Write cycle 100 -
DCX_SCL
tWRH Control pulse “H” duration 40 - ns -
(Write) tWRL Control pulse “L” duration 40 -
tRC Read cycle 150 -
DCX_SCL
tRDH Control pulse “H” duration 60 - ns -
(Read) tRDL Control pulse “L” duration 60 -
SDI/SDO tDS Data setup time 30 -
tDT Data hold time ns
(Input) 30 - For maximum CL=30pF
SDI/SDO tRACC Read access time 10 - For minimum CL=8pF
tOD Output disable time ns
(Output) 10 50
Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of VDD1 for Input signals.
Table 8.6: DBI Type C interface characteristics

Himax Confidential -P.274-

VSST VSHT

VSYNC

HSST HSHT

HSYNC
PCLKCYC

PCLKHT
PCLKLT

PCLK

DST DHT

DB[15:0],
DB[17:0],
DB[23:0],
DE

Figure 8.4: DPI interface characteristics

Resolution=480x800 (VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C)

Parameter Symbol Condition Min. Typ. Max. Unit

Vertical sync. setup time VSST - 5 - - ns
Vertical sync. hold time VSHT - 5 - - ns
Horizontal sync. setup time HSST - 5 - - ns
Horizontal sync. hold time HSHT - 5 - - ns
VRR(5) =
Pixel clock cycle (3) (4)
PCLKCYC Min . 50 Hz 31 - 49.2 ns
when RGB I/F is running
Max. 70 Hz
Pixel clock low time PCLKLT - 5 - - ns
Pixel clock high time PCLKHT - 5 - - ns
Data setup time DB[23:0] DST - 5 - - ns
Data hold time DB[23:0] DHT - 5 - - ns
Note: (1) Signal rise and fall times are equal to or less than 20 ns.
(2) Input signals are measured by 0.30 x VDD1 for low state and 0.70 x VDD1 for high state.
(3) 32.2 MHz
(4) 20.3 MHz
(5) VRR : Vertical Refresh Rate, equal to VSYNC frequency.

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Item Symbol Condition Min. Typ. Max. Unit

Vertical sync. Setup time VSST - 5 - - ns
Vertical sync. Hold time VSHT - 5 - - ns
Horizontal sync. Setup time HSST - 5 - - ns
Horizontal sync. Hold time HSHT - 5 - - ns
(5)
VRR =
Pixel clock cycle 29.1 46.2
DCKCYC Min . 50 Hz - ns
When RGB I/F is running (Note 3) (Note 4)
Max. 70 Hz
Pixel clock low time DCKLT - 5 - - ns
Pixel clock high time DCKHT - 5 - - ns
Data setup time DB[23:0] DST - 5 - - ns
Data Hold time DB[23:0] DHT - 5 - - ns
Note: (1) Signal rise and fall times are equal to or less than 20 ns.
(2) Input signals are measured by 0.30 x VDD1 for low state and 0.70 x VDD1 for high state.
(3) 34.3 MHz
(4) 21.6 MHz

Table 8.7: DPI interface characteristics

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VSYNC
VFP VS VBP VFP

DB[23:0] Note3 Note3

VBL VDISP

HSYNC

Figure 8.5: Vertical Timings for RGB I/F

Resolution=480x854 (VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C)

Item Symbol Condition Min. Typ. Max. Unit
Vertical cycle VP - 860 Note(5) - - Line
Vertical low pulse width VS - 2 Note(5) - Note(4) Line
Vertical front porch VFP - 2 Note(5) - - Line
Vertical back porch VBP - 2 Note(5) - Note(4) Line
Vertical data start point - VS+VBP 4 Note(5) - Note(4) Line
Vertical blanking period VBL VS+VBP+VFP 6 Note(5) - - Line
Vertical active area - VDISP - 854 - Line
Vertical Refresh rate VRR - 50 - 70 Hz
Note: (1) Signal rise and fall times are equal to or less than 20 ns.
(2) Input signals are measured by 0.30 x VDD1 for low state and 0.70 x VDD1 for highstate.
(3) Data lines can be set to “High” or “Low” during blanking time – Don’t care.
(4) The VS and VBP pulse width are related to ASG/GIP STV and CKV timing. The STV and CKV must be
set at corresponding position for LCD normal display. Also refer to setion 6.2.66 SETGIP.
(5) The VS and VBP and VFP pulse width are related to ASG/GIP STV and CKV timing. The minimum of VS
and VBP and VFP must ≧3 Hsync if the STV0~STV3 and CKV0~CKV7 are all in used in corresponding
position for LCD normal display. Also refer to setion 6.2.66 SETGIP.

Resolution=480x800 (VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C)

Item Symbol Condition Min. Typ. Max. Unit
Vertical cycle VP - 806 Note(5) - - Line
Vertical low pulse width VS - 2 Note(5) - Note(4) Line
Vertical front porch VFP - 2 Note(5) - - Line
Vertical back porch VBP - 2 Note(5) - Note(4) Line
Vertical data start point - VS+VBP 4 Note(5) - Note(4) Line
Vertical blanking period VBL VS+VBP+VFP 6 Note(5) - - Line
Vertical active area - VDISP - 800 - Line
Vertical Refresh rate VRR - 50 - 70 Hz
Note: (1) Signal rise and fall times are equal to or less than 20 ns.
(2) Input signals are measured by 0.30 x VDD1 for low state and 0.70 x VDD1 for highstate.
(3) Data lines can be set to “High” or “Low” during blanking time – Don’t care.
(4) The VS and VBP pulse width are related to ASG/GIP STV and CKV timing. The STV and CKV must be
set at corresponding position for LCD normal display. Also refer to setion 6.2.66 SETGIP.
(5) The VS and VBP and VFP pulse width are related to ASG/GIP STV and CKV timing. The minimum of VS
and VBP and VFP must ≧3 Hsync if the STV0~STV3 and CKV0~CKV7 are all in used in corresponding
position for LCD normal display. Also refer to setion 6.2.66 SETGIP.
Table 8.8 Vertical Timings for RGB I/F

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Figure 8.6: Horizontal Timing for RGB I/F

Resolution=480x854 (VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C)

Resolution=480x800 (VSSA=0V, VDD1=1.8V, VDD2=2.8V, VDD3=2.8V, TA=25°C)

Item Symbol Condition Min. Typ. Max. Unit
HS cycle HP Note 3 504 - 568 DCK
HS low pulse width HS - 5 - 78 DCK
Horizontal back porch HBP - 5 - 78 DCK
Horizontal front porch HFP - 5 - 78 DCK
19 - 83 DCK
Horizontal data start point - HS+HBP
700 - - ns
Horizontal blanking period HBLK HS+HBP+HFP 24 - 88 DCK
Horizontal active area HDISP - - 480 - DCK
Pixel clock frequency VRR = Min. 50 Hz 20.3 - 32.2 MHz
DCK
When RGB I/F is running – Max. 70 Hz 31 - 49.2 ns
Note: (1) Signal rise and fall times are equal to or less than 20 ns.
(2) Input signals are measured by 0.30 x VDD1 for low state and 0.70 x VDD1 for high state.
(3) HP is multiples of eight DCK.
(4)Data lines can be set to “High” or “Low” during blanking time – Don’t care.
Table 8.9 Horizontal Timings for RGB I/F
Himax Confidential -P.278-
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. October, 2010
HX8369-A00
480RGBx864dots, TFT Mobile Single Chip Driver
DATA SHEET V02
8.4.5 Reset input timing

Shorter than 5µs

tRESW

RESX
tREST

Initial Condition
Internal Status Normal Operation Resetting
(Default for H/W reset)

Figure 8.7: Reset input timing

Related
Symbol Parameter Min. Typ. Max. Note Unit
pins
(1)
tRESW Reset low pulse width RESX 10 - - - µs
When reset is applied
- 5 - - ms
(2) during Sleep In mode
tREST Reset complete time
When reset is applied
- 120 - - ms
during Sleep Out mode
Note: (1) Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the
table below.
RESX Pulse Action
Shorter than 5 µ Reset Rejected
Longer than 10 µs Reset
Between 5 µs and 10 µs Reset Start

(2) During the resetting period, the display will be blanked (The display is entering blanking sequence, which
maximum time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep
In –mode) and then returns to Default condition for H/W reset.
(3) During Reset Complete Time, ID2 value in OTP will be latched to internal register during this period. This loading
is done every time when there is H/W reset complete time (tREST) within 5ms after a rising edge of RESX.
(4) Spike Rejection also applies during a valid reset pulse as shown below:

(5) When Reset is applied during Sleep In Mode.

(6) When Reset is applied during Sleep Out Mode.
(7) It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot
be sent for 120msec.
Table 8.10: Reset timing

Himax Confidential -P.279-

VDD1
VDD2
VDD3

RESX
V synchronous
Wait until time , max 1
power Min 120ms frame
stable 10us (min)
Sleep out
Effective
command
reset pulse
Standard 5ms (min)
command
input
(Note1)
20ms (min)
User Define
command Himax Initialize commands Himax Initialize commands
input
(Note2)
Display on
command
(Note3)

2 frames RGB signals before SLPOUT See “Power On Timing - 2”

RGB RGB signals
Interface

Mode Not define Sleep in Sleep out Sleep out +

Display on

Function All power off Load OTP Display off Clear screen Normal display
<20ms
2 frames (33ms)
OSC OFF Operation
67ms (min)
Driver
boost Not defined Power sequential turn on Normal operation

Regulator
VCOM/ OFF Normal operation
VSPR/
VSNR

S[1440:1] V0/V255 Gray

Sleep out
command

Display on
command

2ms
VGH (min)

DT+5ms(min)
VGL (Note4)

VSP DT+15ms(min)
(for (Note4)
PFM)
VSN DTms
(for (Note4)
PFM)
VSP DTms
(for (Note4)
5186)
VSN DT+15ms(min)
(for (Note4)
5186)
VCOM/ 3DT+15ms(at least)
VSPR/ (Note4)
VSNR

Note1: Note2: Note3: Note4:

“Standard” command except “User Define” command “Display on” command
“01h” & “10h” command must be sent “B9h” first must send after “User
must wait 5ms after “Sleep then other commands Define” command or at
out” command then can be can be available. the same time.
sent. “01h” & “10h”
command must wait 100ms
after “Sleep out” command Default DT=5ms
then can be sent.

Figure 8.1 Power On Timing

Himax Confidential -P.280-

Sleep in
command Min 120ms

Display off
command
V synchronous
time , max 1
frame

2 frames after sleep in

RGB RGB Signals
Interface

Mode Sleep out + Display on Sleep out Sleep in Not defined

Function Normal display Clear screen Power off sequence All power off

2 frames (33ms)
OSC Operation OFF

60ms (min)
Driver
boost Normal operation Sequential turn off Not defined

Regulator
VCOM/
Normal operation OFF
VSPR/
VSNR

S[1440:1] Gray V0/V255

Figure 1.2 Power Off Timing

Himax Confidential -P.281-

Figure 9.1: Layout recommendation

Himax Confidential -P.282-

Himax Confidential -P.283-

12. Revision History

Version Date Description of Changes
01 2009/08/26 1. New setup
2009/10/27 1. Update pin assignment (page 19)
2. Update bump arrangement (page 28)
3. Add temperature sensor control register
(page 254 ~ 258)
4. Update PFM circuit and HX5186-A application
diagrams (page 266~267)
2009/10/29 1. Update RTN, RTN_PE, FP_PE and BP_PE
setting (page 231)
2. Update absolute maximum rating VDD2 and VDD3
(page 269)
3. Update BT[3:0] setting (page222)
2009/11/6 1. Error typing. Update 3Ah interface format table
(page 199)
2. Error typing. Update 0Ch interface format table
(page 168)
3. Update table7.1 adoptablilty of component. (page269)
2009/11/12 1. Update OTP table (page 139-141)
2009/11/26 1. Update registers default values (page153~156)
2010/03/08 1. Update 0xB2h FP[7:0] and BP[7:0] = 8h’00
definition(page 230).
2. Update 0xB1h BTN[4:0] VSN definition(page 223).
2010/04/01 1. Update OTP index 0x47h (page 140)
2. Update command list 0xB1h default (page 220)
3. Error typing PCLKCYC, PCLKLT and PCLKHT
(page 275)
4. Adds Gamma resister stream description
(page 113 and 114)
2010/04/09 1. Error typing I/O pins. (page 26)
2010/04/23 1. Update the chip thickness information.(page 17)
2. Update register 2Dh Look Up table description.
(page 183-185)
3. Update DC characteristics information. (page270)
2010/04/30 1. Error typing, change maximum 256k colours to
16.7M colours.(page 182)
2. Error typing, change SDA to SDI and SDO.
(page 40~42)
3. Adds notice for RGB caputer mode only used in RGB
24-bit. (page 46)
4. Add notice for GIP description.(page 247)

Himax Confidential -P.284-

Himax Confidential -P.285-

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