MC1489, MC1489A

Quad Line EIA−232D

Receivers
The MC1489 monolithic quad line receivers are designed to
interface data terminal equipment with data communications
equipment in conformance with the specifications of EIA Standard
No. EIA−232D. http://onsemi.com

Features
• Input Resistance − 3.0 k to 7.0 k
SOIC−14
• Input Signal Range − ± 30 V 14 D SUFFIX
CASE 751A
• Input Threshold Hysteresis Built In 1

• Response Control
a) Logic Threshold Shifting PDIP−14
P SUFFIX
b) Input Noise Filtering
CASE 646
• Pb−Free Packages are Available 14
1

SOEIAJ−14
14 M SUFFIX
CASE 965

PIN CONNECTIONS

Input A 1 14 VCC
Line Driver Interconnecting Line Receiver
MC1488 Cable MC1489 Response 2 13 Input D
Control A

Output A 3 12 Response
Control D

Input B 4 11 Output D

Response 5 10 Input C
Control B
Interconnecting Response
MDTL Logic Input MDTL Logic Output Output B 6 9
Cable Control C

Ground 7 8 Output C

Figure 1. Simplified Application

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.

DEVICE MARKING INFORMATION

See general marking information in the device marking
section on page 8 of this data sheet.

*For additional information on our Pb−Free strategy

and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2004 1 Publication Order Number:

April, 2004 − Rev. 8 MC1489/D
 MC1489, MC1489A

14
VCC

9.0 k 5.0 k 1.7 k

RF
Response Control 2 3 Output

3.8 k
Input 1

MC1489 MC1489A 10 k

RF 6.7 k
1.6 k

7 GND

Figure 2. Representative Schematic Diagram

(1/4 of Circuit Shown)

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 MC1489, MC1489A

MAXIMUM RATINGS (TA = + 25°C, unless otherwise noted)

Rating Symbol Value Unit
Power Supply Voltage VCC 10 Vdc
Input Voltage Range VIR ± 30 Vdc
Output Load Current IL 20 mA
Power Dissipation (Package Limitation, SOIC−14 and Plastic Dual In−Line Package) PD 1000 mW
Derate above TA = + 25°C 1/JA 6.7 mW/°C

Operating Ambient Temperature Range TA 0 to + 75 °C

Storage Temperature Range Tstg − 65 to + 175 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.

ELECTRICAL CHARACTERISTICS (Response control pin is open.) (VCC = + 5.0 Vdc ± 10%, TA = 0 to + 75°C, unless otherwise noted)
Characteristics Symbol Min Typ Max Unit
Positive Input Current (VIH = + 25 Vdc) IIH 3.6 − 8.3 mA
(VIH = + 3.0 Vdc) 0.43 − −
Negative Input Current (VIH = − 25 Vdc) IIL − 3.6 − − 8.3 mA
(VIH = − 3.0 Vdc) − 0.43 − −
Input Turn−On Threshold Voltage VIH Vdc
(TA = + 25°C, VOL
0.45 V) MC1489 1.0 − 1.5
MC1489A 1.75 1.95 2.25
Input Turn−Off Threshold Voltage VIL Vdc
(TA = + 25°C, VOH  2.5 V, IL = − 0.5 mA) MC1489 0.75 − 1.25
MC1489A 0.75 0.8 1.25
Output Voltage High (VIH = 0.75 V, IL = − 0.5 mA) VOH 2.5 4.0 5.0 Vdc
(Input Open Circuit, IL = − 0.5 mA) 2.5 4.0 5.0
Output Voltage Low (VIL = 3.0 V, IL = 10 mA) VOL − 0.2 0.45 Vdc
Output Short−Circuit Current IOS − − 3.0 − 4.0 mA
Power Supply Current (All Gates “on,” Iout = 0 mA, VIH = + 5.0 Vdc) ICC − 16 26 mA
Power Consumption (VIH = + 5.0 Vdc) PC − 80 130 mW
SWITCHING CHARACTERISTICS (VCC = 5.0 Vdc ± 1%, TA = + 25°C, See Figure 3.)
Propagation Delay Time (RL = 3.9 k
) tPLH − 25 85 ns
Rise Time (RL = 3.9 k
) tTLH − 120 175 ns
Propagation Delay Time (RL = 390 k
) tPHL − 25 50 ns
Fall Time (RL = 390 k
) tTHL − 10 20 ns

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 MC1489, MC1489A

TEST CIRCUITS

5.0 Vdc

RL
All diodes
1N3064 VR
or equivalent

Ein Eo
R
CL
3.0 V

50% 50% C
Ein tTLH and tTHL
tPLH measured Response Node
10% − 90% 1/4
EO MC1489A
Vin VO
tTLH
tTHL
1.5 V 1.5 V

CL = 15 pF = total parasitic capacitance which includes C, capacitor is for noise filtering.

probe and wiring capacitances R, resistor is for threshold shifting.

Figure 3. Switching Response Figure 4. Response Control Node

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 MC1489, MC1489A

TYPICAL CHARACTERISTICS
(VCC = 5.0 Vdc, TA = +25°C, unless otherwise noted)

10 6.0
8.0
5.0 VI EO
6.0
IL, INPUT CURRENT (mA)

VO , OUTPUT VOLTAGE (Vdc)

4.0 4.0 RT RT RT RT
5.0 k 13 k
11 k
2.0 RT
3.0 Vth Vth Vth
0 5.0 V 5.0 V −
5.0 V
2.0 Vth
−
2.0 II
−
4.0 VI 1.0
−
6.0
−
8.0 0 VILH VIHL
−
10
−
25 −
20 −
15 −
10 −
5.0 0 5.0 10 15 20 25 −
3.0 −
2.0 −
1.0 0 1.0 2.0 3.0
Vin, INPUT VOLTAGE (V) VI, INPUT VOLTAGE (V)

Figure 5. Input Current Figure 6. MC1489 Input Threshold

Voltage Adjustment

6.0 2.4

VIH , INPUT THRESHOLD VOLTAGE (Vdc)

2.2
5.0 MC1489A VIH
VO , OUTPUT VOLTAGE (Vdc)

2.0
Vin EO 1.8
4.0
RT RT RT 1.6
3.0 5.0 k
11 k 1.4
Vth Vth RT 1.2 MC1489 VIH
2.0 5.0 V −
5.0 V 1.0
Vth
0.8
1.0 0.6 MC1489 VIL
0 0.4
VILH VIHL MC1489A VIL
0.2
0
−
3.0 −
2.0 −
1.0 0 1.0 2.0 3.0 4.0 −
60 0 +
60 +
120
VI, INPUT VOLTAGE (V) T, TEMPERATURE (°C)

Figure 7. MC1489A Input Threshold Figure 8. Input Threshold Voltage

Voltage Adjustment versus Temperature

2.0
VIH MC1489A
INPUT THRESHOLD VOLTAGE (Vdc)

1.0 VIH MC1489

VIL MC1489
VIL MC1489A

0
3.0 4.0 5.0 6.0
VCC, POWER SUPPLY VOLTAGE (V)

Figure 9. Input Threshold versus

Power Supply Voltage

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 MC1489, MC1489A

APPLICATIONS INFORMATION

General Information
The Electronic Industries Association (EIA) has released turn−on voltage of 1.25 V and turn−off of 1.0 V for a typical
the EIA−232D specification detailing the requirements for hysteresis of 250 mV. The MC1489A has typical turn−on of
the interface between data processing equipment and data 1.95 V and turn−off of 0.8 V for typically 1.15 V of
communications equipment. This standard specifies not hysteresis.
only the number and type of interface leads, but also the Each receiver section has an external response control
voltage levels to be used. The MC1488 quad driver and its node in addition to the input and output pins, thereby
companion circuit, the MC1489 quad receiver, provide a allowing the designer to vary the input threshold voltage
complete interface system between DTL or TTL logic levels levels. A resistor can be connected between this node and an
and the EIA−232D defined levels. The EIA−232D external power supply. Figures 4, 6 and 7 illustrate the input
requirements as applied to receivers are discussed herein. threshold voltage shift possible through this technique.
The required input impedance is defined as between This response node can also be used for the filtering of
3000
and 7000
for input voltages between 3.0 and 25 V high frequency, high energy noise pulses. Figures 10 and 11
in magnitude; and any voltage on the receiver input in an show typical noise pulse rejection for external capacitors of
open circuit condition must be less than 2.0 V in magnitude. various sizes.
The MC1489 circuits meet these requirements with a These two operations on the response node can be
maximum open circuit voltage of one VBE. combined or used individually for many combinations of
The receiver shall detect a voltage between − 3.0 and interfacing applications. The MC1489 circuits are
−25 V as a Logic “1” and inputs between 3.0 and 25 V as a particularly useful for interfacing between MOS circuits and
Logic “0.” On some interchange leads, an open circuit of MDTL/MTTL logic systems. In this application, the input
power “OFF” condition (300
or more to ground) shall be threshold voltages are adjusted (with the appropriate supply
decoded as an “OFF” condition or Logic “1.” For this and resistor values) to fall in the center of the MOS voltage
reason, the input hysteresis thresholds of the MC1489 logic levels (see Figure 12).
circuits are all above ground. Thus an open or grounded The response node may also be used as the receiver input
input will cause the same output as a negative or Logic “1” as long as the designer realizes that he may not drive this
input. node with a low impedance source to a voltage greater than
one diode above ground or less than one diode below
Device Characteristics ground. This feature is demonstrated in Figure 13 where two
The MC1489 interface receivers have internal feedback receivers are slaved to the same line that must still meet the
from the second stage to the input stage providing input EIA−232D impedance requirement.
hysteresis for noise rejection. The MC1489 input has typical

6 6
MC1489 MC1489A
5 5
10 pF 100 pF 300 pF 500 pF
E in , AMPLITUDE (V)

E in , AMPLITUDE (V)

12 pF 100 pF 300 pF 500 pF

4 4

3 3

2 2

1 1
10 100 1000 10,000 10 100 1000 10,000
PW, INPUT PULSE WIDTH (ns) PW, INPUT PULSE WIDTH (ns)

Figure 10. Typical Turn On Threshold versus Figure 11. Typical Turn On Threshold versus
Capacitance from Response Control Pin to GND Capacitance from Response Control Pin to GND

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 MC1489, MC1489A

+
5.0 Vdc

MOS MC1489
Logic DTL or TTL

−VGG −VDD +
5.0 Vdc +
5.0 Vdc

Figure 12. Typical Translator Application − MOS to DTL or TTL

VCC

Response−Control Pin
1/2 MC1489
Output
Input 8.0 k

VCC

Output
8.0 k
Input

Response−Control Pin

Figure 13. Typical Paralleling of Two MC1489, A Receivers to Meet EIA−232D

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 MC1489, MC1489A

ORDERING INFORMATION

Device Package Operating Temperature Range Shipping

MC1489D 55 Units/Rail
MC1489DR2 SOIC−14
SO C 2500 Tape & Reel
MC1489AD 55 Units/Rail
MC1489ADG SOIC−14 55 Units/Rail
TA = 0 to +75°C
(Pb−Free)
MC1489ADR2 SOIC−14 2500 Tape & Reel
MC1489ADR2G SOIC−14 2500 Tape & Reel
(Pb−Free)
MC1489P PDIP−14 25 Units/Rail
MC1489PG PDIP−14 25 Units/Rail
TA = 0 to +75°C
(Pb−Free)
MC1489AP PDIP−14 25 Units/Rail
MC1489M 50 Units/Rail
MC1489MEL SOEIAJ−14
SO J 2000 Tape & Reel
MC1489AM 50 Units/Rail
MC1489AM SOEIAJ−14 50 Units/Rail
TA = 0 to +75°C
(Pb−Free)
MC1489AMEL SOEIAJ−14 2000 Tape & Reel
MC1489AMEL SOEIAJ−14 2000 Tape & Reel
(Pb−Free)

MARKING DIAGRAMS

SOIC−14
PDIP−14
D SUFFIX
P SUFFIX
CASE 751A
CASE 646

14 14 14 14

MC1489AD MC1489D MC1489AP MC1489P

AWLYWW AWLYWW AWLYYWW AWLYYWW

1 1 1 1

SOEIAJ−14
M SUFFIX
CASE 965

MC1489A MC1489
ALYW ALYW

A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week

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 MC1489, MC1489A

PACKAGE DIMENSIONS

SOIC−14
D SUFFIX
CASE 751A−03
ISSUE F
NOTES:
−A− 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
14 8 3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
−B− P 7 PL PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
1 7
0.25 (0.010) M B M
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G R X 45
F MILLIMETERS INCHES
C DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
−T−
J D 0.35 0.49 0.014 0.019
SEATING D 14 PL K M F 0.40 1.25 0.016 0.049
PLANE G 1.27 BSC 0.050 BSC
0.25 (0.010) M T B S A S
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0
7
0
7

P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

PDIP−14
P SUFFIX
CASE 646−06
ISSUE M

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
14 8 Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
B 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
1 7 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.

A INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F L A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
N D 0.015 0.021 0.38 0.53
C F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
−T− H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
SEATING
PLANE K 0.115 0.135 2.92 3.43
K J L 0.290 0.310 7.37 7.87
H G D 14 PL M M −−− 10
−−− 10

N 0.015 0.039 0.38 1.01
0.13 (0.005) M

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 MC1489, MC1489A

PACKAGE DIMENSIONS

SOEIAJ−14
M SUFFIX
CASE 965−01
ISSUE O

NOTES:
14 8 LE 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
Q1 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
E HE M
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
1 7 L 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
DETAIL P INCLUDE DAMBAR PROTRUSION. ALLOWABLE
Z
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
D TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
VIEW P DAMBAR CANNOT BE LOCATED ON THE LOWER
A RADIUS OR THE FOOT. MINIMUM SPACE
e BETWEEN PROTRUSIONS AND ADJACENT LEAD
c TO BE 0.46 ( 0.018).

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
b A1 A −−− 2.05 −−− 0.081
A1 0.05 0.20 0.002 0.008
0.13 (0.005) M 0.10 (0.004) b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
D 9.90 10.50 0.390 0.413
E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
HE 7.40 8.20 0.291 0.323
0.50 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0
10
0
10

Q1 0.70 0.90 0.028 0.035
Z −−− 1.42 −−− 0.056

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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10