MC1496, MC1496B

Balanced Modulators/
Demodulators
These devices were designed for use where the output voltage is a
product of an input voltage (signal) and a switching function (carrier).
Typical applications include suppressed carrier and amplitude
modulation, synchronous detection, FM detection, phase detection, http://onsemi.com
and chopper applications. See ON Semiconductor Application Note
AN531 for additional design information. SOIC−14
14 D SUFFIX
Features CASE 751A
1
• Excellent Carrier Suppression −65 dB typ @ 0.5 MHz
−50 dB typ @ 10 MHz
• Adjustable Gain and Signal Handling PDIP−14
• Balanced Inputs and Outputs P SUFFIX
14 CASE 646
• High Common Mode Rejection −85 dB Typical
• This Device Contains 8 Active Transistors 1
• Pb−Free Package is Available*
PIN CONNECTIONS

Signal Input 1 14 VEE

Gain Adjust 2 13 N/C

Gain Adjust 3 12 Output

Signal Input 4 11 N/C
Bias 5 10 Carrier Input
Output 6 9 N/C
N/C 7 8 Input Carrier

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.

DEVICE MARKING INFORMATION

See general marking information in the device marking
section on page 12 of this data sheet.

© Semiconductor Components Industries, LLC, 2006 1 Publication Order Number:

October, 2006 − Rev. 10 MC1496/D
 MC1496, MC1496B

IC = 500 kHz
IS = 1.0 kHz

Log Scale Id
20

40
IC = 500 kHz, IS = 1.0 kHz
60
499 kHz 500 kHz 501 kHz

Figure 1. Suppressed Carrier Output Figure 2. Suppressed Carrier Spectrum

Waveform
10
IC = 500 kHz
8.0 IS = 1.0 kHz

Linear Scale
6.0

4.0

2.0

IC = 500 kHz 0
IS = 1.0 kHz 499 kHz 500 kHz 501 kHz

Figure 3. Amplitude Modulation Figure 4. Amplitude−Modulation Spectrum

Output Waveform

MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)

Rating Symbol Value Unit
Applied Voltage V 30 Vdc
(V6−V8, V10−V1, V12−V8, V12−V10, V8−V4, V8−V1, V10−V4, V6−V10, V2−V5, V3−V5)
Differential Input Signal V8 − V10 +5.0 Vdc
V4 − V1 ±(5 + I5Re)
Maximum Bias Current I5 10 mA
Thermal Resistance, Junction−to−Air RJA 100 °C/W
Plastic Dual In−Line Package
Operating Ambient Temperature Range MC1496 TA 0 to +70 °C
MC1496B −40 to +125
Storage Temperature Range Tstg −65 to +150 °C
Electrostatic Discharge Sensitivity (ESD) ESD V
Human Body Model (HBM) 2000
Machine Model (MM) 400
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

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ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, VEE = −8.0 Vdc, I5 = 1.0 mAdc, RL = 3.9 k, Re = 1.0 k, TA = Tlow to Thigh,
all input and output characteristics are single−ended, unless otherwise noted.) (Note 1)
Characteristic Fig. Note Symbol Min Typ Max Unit
Carrier Feedthrough 5 1 VCFT Vrms
VC = 60 mVrms sine wave and fC = 1.0 kHz − 40 −
offset adjusted to zero fC = 10 MHz − 140 −
VC = 300 mVpp square wave: mVrms
offset adjusted to zero fC = 1.0 kHz − 0.04 0.4
offset not adjusted fC = 1.0 kHz − 20 200
Carrier Suppression 5 2 VCS dB
fS = 10 kHz, 300 mVrms
fC = 500 kHz, 60 mVrms sine wave 40 65 −
fC = 10 MHz, 60 mVrms sine wave − 50 − k
Transadmittance Bandwidth (Magnitude) (RL = 50 ) 8 8 BW3dB MHz
Carrier Input Port, VC = 60 mVrms sine wave − 300 −
fS = 1.0 kHz, 300 mVrms sine wave
Signal Input Port, VS = 300 mVrms sine wave − 80 −
|VC| = 0.5 Vdc
Signal Gain (VS = 100 mVrms, f = 1.0 kHz; | VC|= 0.5 Vdc) 10 3 AVS 2.5 3.5 − V/V
Single−Ended Input Impedance, Signal Port, f = 5.0 MHz 6 −
Parallel Input Resistance rip − 200 − k
Parallel Input Capacitance cip − 2.0 − pF
Single−Ended Output Impedance, f = 10 MHz 6 −
Parallel Output Resistance rop − 40 − k
Parallel Output Capacitance coo − 5.0 − pF
Input Bias Current 7 − A
IbS − 12 30
I + I1 ) I4 ; I + I8 ) I10 IbC − 12 30
bS 2 bC 2
Input Offset Current 7 − ⎥ IioS⎥ − 0.7 7.0 A
IioS = I1−I4; IioC = I8−I10 IioC⎥ − 0.7 7.0
Average Temperature Coefficient of Input Offset Current 7 − ⎥ TCIio⎥ − 2.0 − nA/°C
(TA = −55°C to +125°C)
Output Offset Current (I6−I9) 7 − ⎥ Ioo⎥ − 14 80 A
Average Temperature Coefficient of Output Offset Current 7 − ⎥ TCIoo⎥ − 90 − nA/°C
(TA = −55°C to +125°C)
Common−Mode Input Swing, Signal Port, fS = 1.0 kHz 9 4 CMV − 5.0 − Vpp
Common−Mode Gain, Signal Port, fS = 1.0 kHz, |VC|= 0.5 Vdc 9 − ACM − −85 − dB
Common−Mode Quiescent Output Voltage (Pin 6 or Pin 9) 10 − Vout − 8.0 − Vpp
Differential Output Voltage Swing Capability 10 − Vout − 8.0 − Vpp
Power Supply Current I6 +I12 7 6 ICC − 2.0 4.0 mAdc
Power Supply Current I14 IEE − 3.0 5.0
DC Power Dissipation 7 5 PD − 33 − mW
1. Tlow = 0°C for MC1496 Thigh = +70°C for MC1496
= −40°C for MC1496B = +125°C for MC1496B

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 MC1496, MC1496B

GENERAL OPERATING INFORMATION

Carrier Feedthrough Note that in the test circuit of Figure 10, VS corresponds to
Carrier feedthrough is defined as the output voltage at a maximum value of 1.0 V peak.
carrier frequency with only the carrier applied
(signal voltage = 0). Common Mode Swing
Carrier null is achieved by balancing the currents in the The common−mode swing is the voltage which may be
differential amplifier by means of a bias trim potentiometer applied to both bases of the signal differential amplifier,
(R1 of Figure 5). without saturating the current sources or without saturating
the differential amplifier itself by swinging it into the upper
Carrier Suppression switching devices. This swing is variable depending on the
Carrier suppression is defined as the ratio of each particular circuit and biasing conditions chosen.
sideband output to carrier output for the carrier and signal
voltage levels specified. Power Dissipation
Carrier suppression is very dependent on carrier input Power dissipation, PD, within the integrated circuit
level, as shown in Figure 22. A low value of the carrier does package should be calculated as the summation of the
not fully switch the upper switching devices, and results in voltage−current products at each port, i.e. assuming
lower signal gain, hence lower carrier suppression. A higher V12 = V6, I5 = I6 = I12 and ignoring base current,
than optimum carrier level results in unnecessary device and PD = 2 I5 (V6 − V14) + I5)V5 − V14 where subscripts refer
circuit carrier feedthrough, which again degenerates the to pin numbers.
suppression figure. The MC1496 has been characterized
Design Equations
with a 60 mVrms sinewave carrier input signal. This level The following is a partial list of design equations needed
provides optimum carrier suppression at carrier frequencies
to operate the circuit with other supply voltages and input
in the vicinity of 500 kHz, and is generally recommended for conditions.
balanced modulator applications.
Carrier feedthrough is independent of signal level, VS. A. Operating Current
Thus carrier suppression can be maximized by operating The internal bias currents are set by the conditions at Pin 5.
with large signal levels. However, a linear operating mode Assume:
must be maintained in the signal−input transistor pair − or I5 = I6 = I12,
harmonics of the modulating signal will be generated and IBtt IC for all transistors
appear in the device output as spurious sidebands of the then :
suppressed carrier. This requirement places an upper limit
on input−signal amplitude (see Figure 20). Note also that an V * * where: R5 is the resistor between
R5+ *500  where: Pin 5 and ground
optimum carrier level is recommended in Figure 22 for good I5
carrier suppression and minimum spurious sideband where:  = 0.75 at TA = +25°C
generation. The MC1496 has been characterized for the condition
At higher frequencies circuit layout is very important in I5 = 1.0 mA and is the generally recommended value.
order to minimize carrier feedthrough. Shielding may be B. Common−Mode Quiescent Output Voltage
necessary in order to prevent capacitive coupling between V6 = V12 = V+ − I5 RL
the carrier input leads and the output leads.
Biasing
Signal Gain and Maximum Input Level The MC1496 requires three dc bias voltage levels which
Signal gain (single−ended) at low frequencies is defined must be set externally. Guidelines for setting up these three
as the voltage gain, levels include maintaining at least 2.0 V collector−base bias
Vo R on all transistors while not exceeding the voltages given in
A + + L where r e + 26 mV the absolute maximum rating table;
VS V R e)2r e I5(mA)
S
30 Vdc w [(V6, V12) − (V8, V10)] w 2 Vdc
A constant dc potential is applied to the carrier input 30 Vdc w [(V8, V10) − (V1, V4)] w 2.7 Vdc
terminals to fully switch two of the upper transistors “on” 30 Vdc w [(V1, V4) − (V5)] w 2.7 Vdc
and two transistors “off” (VC = 0.5 Vdc). This in effect The foregoing conditions are based on the following
forms a cascode differential amplifier. approximations:
Linear operation requires that the signal input be below a
V6 = V12, V8 = V10, V1 = V4
critical value determined by RE and the bias current I5.
VS p I5 RE (Volts peak)

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Bias currents flowing into Pins 1, 4, 8 and 10 are transistor Negative Supply
base currents and can normally be neglected if external bias VEE should be dc only. The insertion of an RF choke in
dividers are designed to carry 1.0 mA or more. series with VEE can enhance the stability of the internal
current sources.
Transadmittance Bandwidth
Carrier transadmittance bandwidth is the 3.0 dB bandwidth Signal Port Stability
of the device forward transadmittance as defined by: Under certain values of driving source impedance,
oscillation may occur. In this event, an RC suppression
i o (each sideband)
21C+ v s (signal) ⎥ Vo + 0 network should be connected directly to each input using
short leads. This will reduce the Q of the source−tuned
Signal transadmittance bandwidth is the 3.0 dB bandwidth circuits that cause the oscillation.
of the device forward transadmittance as defined by:
Signal Input
i o (signal)
21S+ v (signal)
s
⎥ Vc + 0.5 Vdc, Vo + 0 (Pins 1 and 4)
510
10 pF
Coupling and Bypass Capacitors
Capacitors C1 and C2 (Figure 5) should be selected for a
reactance of less than 5.0  at the carrier frequency.
An alternate method for low−frequency applications is to
Output Signal insert a 1.0 k resistor in series with the input (Pins 1, 4). In
The output signal is taken from Pins 6 and 12 either this case input current drift may cause serious degradation
balanced or single−ended. Figure 11 shows the output levels of carrier suppression.
of each of the two output sidebands resulting from variations
in both the carrier and modulating signal inputs with a
single−ended output connection.

TEST CIRCUITS
VCC
12 Vdc Re = 1.0 k
1.0 k 1.0 k
Re 2 3
RL RL 0.5 V 8
51 C1
1.0 k 3.9 k 3.9 k + − 10
C2 0.1 F 2 3 +V o
Carrier 8 1 MC1496 6 Zout
Input 0.1 F 10 I9 I6 Zin 4 −V o
VC +V o 12
1 MC1496 6
VS −V o 14 5
Modulating 4 12
Signal Input 14 5 6.8 k
10 k 10 k 51 51
50 k I5 6.8 k
I10 −8.0 Vdc
R1 V−
Carrier Null
−8.0 Vdc NOTE: Shielding of input and output leads may be needed
VEE to properly perform these tests.

Figure 5. Carrier Rejection and Suppression Figure 6. Input−Output Impedance

VCC VCC
12 Vdc 1.0 k 1.0 k 12 Vdc

Re = 1.0 k Re 2.0 k
1.0 k 51 0.1 F 1.0 k 0.01
2 3 Carrier 2 3 F
2.0 k 8 50 50
I7 8 I6 Input 0.1 F
I8 10 VC 10 +V o
6 1 MC1496 6
1.0 k I1 1 MC1496 I9 VS −V o
I4 4 Modulating 4 12
12
Signal Input 5
14 5 10 k 10 k 51 51 14
I10 50 k 6.8 k
6.8 k
V−
Carrier Null
−8.0 Vdc −8.0 Vdc
VEE VEE
Figure 7. Bias and Offset Currents Figure 8. Transconductance Bandwidth

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 MC1496, MC1496B

VCC VCC
12 Vdc 12 Vdc
Re = 1.0 k Re = 1.0 k
1.0 k 1.0 k
3.9 k 3.9 k 3.9 k 3.9 k
0.5 V 8 2 3 0.5 V 2 3
1.0 k 8
+ − 10 + − 10
1.0 k +V o +V o
1 MC1496 6 1 MC1496 6
VS 4 −V o VS −V o
12 4 12
14 5 14 5
50
6.8 k I5 =
50 6.8 k
1.0 mA
⎥ V ⎥
A + 20 log o
−8.0 Vdc CM V
S −8.0 Vdc
VEE
VEE
Figure 9. Common Mode Gain Figure 10. Signal Gain and Output Swing

TYPICAL CHARACTERISTICS
Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave),
VO , OUTPUT AMPLITUDE OF EACH SIDEBAND (Vrms)

VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25°C, unless otherwise noted.

2.0 1.0 M
r ip, PARALLEL INPUT RESISTANCE (kΩ)

500
1.6 +rip

−rip
Signal Input = 600 mV 100
1.2
50
400 mV
0.8
300 mV 10
200 mV 5.0
0.4
100 mV

0 1.0
0 50 100 150 200 1.0 5.0 10 50 100
VC, CARRIER LEVEL (mVrms) f, FREQUENCY (MHz)
Figure 11. Sideband Output versus Figure 12. Signal−Port Parallel−Equivalent
Carrier Levels Input Resistance versus Frequency

cop, PARALLEL OUTPUT CAPACITANCE (pF)

cip , PARALLEL INPUT CAPACITANCE (pF)

5.0 140 14
rop, PARALLEL OUTPUT RESISTANCE (kΩ)

120 12
4.0
100 10
3.0 rop
80 8.0

2.0 60 cop 6.0

40 4.0
1.0
20 2.0
0 0 0
1.0 2.0 5.0 10 20 50 100 0 1.0 10 100
f, FREQUENCY (MHz) f, FREQUENCY (MHz)
Figure 13. Signal−Port Parallel−Equivalent Figure 14. Single−Ended Output Impedance
Input Capacitance versus Frequency versus Frequency

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TYPICAL CHARACTERISTICS (continued)

Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave),
VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25°C, unless otherwise noted.

1.0 0
γ 21, TRANSADMITTANCE (mmho)

Signal Port

VCS , CARRIER SUPPRESION (dB)

0.9
10
0.8
0.7 20
0.6 Side Band MC1496
30
0.5 Sideband Transadmittance (70°C)

⎥
I out(EachSideband) 40
0.4 21 + V out + 0
V (Signal)
0.3 in
50
0.2 Signal Port Transadmittance
I
0.1
0
V
in
⎥
21 + out V out + 0|V | + 0.5Vdc
C
60

70
0.1 1.0 10 100 1000 −75 −50 −25 0 25 50 75 100 125 150 175
fC, CARRIER FREQUENCY (MHz) TA, AMBIENT TEMPERATURE (°C)
Figure 15. Sideband and Signal Port Figure 16. Carrier Suppression
Transadmittances versus Frequency versus Temperature

SUPPRESSION BELOW EACH FUNDAMENTAL

0
A VS, SINGLE-ENDED VOLTAGE GAIN (dB)

20
RL = 3.9 k
Re = 500  10
10
CARRIER SIDEBAND (dB)

20
RL = 3.9 k (Standard
0 Re = 1.0 k Test Circuit) RL = 3.9 k 30 2fC
Re = 2.0 k
−10 40
RL = 500 
|VC| = 0.5 Vdc Re = 1.0 k 50
−20 fC
RL 60 3fC
A +
V R e ) 2r e
−30 70
0.01 0.1 1.0 10 100 0.05 0.1 0.5 1.0 5.0 10 50
f, FREQUENCY (MHz) fC, CARRIER FREQUENCY (MHz)
Figure 17. Signal−Port Frequency Response Figure 18. Carrier Suppression
versus Frequency
VCFT , CARRIER OUTPUT VOLTAGE (mVrms)

SUPPRESSION BELOW EACH FUNDAMENTAL

10 0

10
CARRIER SIDEBAND (dB)

20
1.0
30

40
fC ± 3fS
50
0.1
60 fC ± 2fS
70
0.01 80
0.05 0.1 0.5 1.0 5.0 10 50 0 200 400 600 800
fC, CARRIER FREQUENCY (MHz) VS, INPUT SIGNAL AMPLITUDE (mVrms)

Figure 19. Carrier Feedthrough Figure 20. Sideband Harmonic Suppression

versus Frequency versus Input Signal Level

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0 0
SUPPRESSION BELOW EACH FUNDAMENTAL

V CS , CARRIER SUPPRESSION (dB)

10 10
3fC ± fS
CARRIER SIDEBAND (dB)

20 20

30 30 fC = 10 MHz
2fC ± fS
40 40

50 2fC ± 2fS 50
fC = 500 kHz

60 60

70 70
0.05 0.1 0.5 1.0 5.0 10 50 0 100 200 300 400 500
fC, CARRIER FREQUENCY (MHz) VC, CARRIER INPUT LEVEL (mVrms)
Figure 21. Suppression of Carrier Harmonic Figure 22. Carrier Suppression versus
Sidebands versus Carrier Frequency Carrier Input Level

OPERATIONS INFORMATION
The MC1496, a monolithic balanced modulator circuit, is components and have an amplitude which is a function of the
shown in Figure 23. product of the input signal amplitudes.
This circuit consists of an upper quad differential amplifier For high−level operation at the carrier input port and
driven by a standard differential amplifier with dual current linear operation at the modulating signal port, the output
sources. The output collectors are cross−coupled so that signal will contain sum and difference frequency
full−wave balanced multiplication of the two input voltages components of the modulating signal frequency and the
occurs. That is, the output signal is a constant times the fundamental and odd harmonics of the carrier frequency.
product of the two input signals. The output amplitude will be a constant times the
Mathematical analysis of linear ac signal multiplication modulating signal amplitude. Any amplitude variations in
indicates that the output spectrum will consist of only the sum the carrier signal will not appear in the output.
and difference of the two input frequencies. Thus, the device The linear signal handling capabilities of a differential
may be used as a balanced modulator, doubly balanced mixer, amplifier are well defined. With no emitter degeneration, the
product detector, frequency doubler, and other applications maximum input voltage for linear operation is
requiring these particular output signal characteristics. approximately 25 mV peak. Since the upper differential
The lower differential amplifier has its emitters connected amplifier has its emitters internally connected, this voltage
to the package pins so that an external emitter resistance may applies to the carrier input port for all conditions.
be used. Also, external load resistors are employed at the Since the lower differential amplifier has provisions for an
device output. external emitter resistance, its linear signal handling range
may be adjusted by the user. The maximum input voltage for
Signal Levels linear operation may be approximated from the following
The upper quad differential amplifier may be operated expression:
either in a linear or a saturated mode. The lower differential
V = (I5) (RE) volts peak.
amplifier is operated in a linear mode for most applications.
For low−level operation at both input ports, the output This expression may be used to compute the minimum
signal will contain sum and difference frequency value of RE for a given input voltage amplitude.
(−) 12
Vo, 1.0 k 1.0 k 12 Vdc
Output 0.1 F
(+) 6 RL RL
2 Re 1.0 k 3
51 3.9 k 3.9 k
10 (−) 8
Carrier V
Input C V 0.1 F 10
+Vo
8 (+) Carrier C 6
Input 1 MC1496
4 (−) VS 4
Signal V 2 Modulating −Vo
S Gain 12
Input 1 (+) Signal 10 k 51 51
Adjust 10 k
3 Input 14 5
Bias 5 50 k
I5 6.8 k
(Pin numbers
500 500 500 per G package) Carrier Null −8.0 Vdc
VEE 14 VEE
Figure 23. Circuit Schematic Figure 24. Typical Modulator Circuit

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Table 1. Voltage Gain and Output Frequencies

Carrier Input Signal (VC) Approximate Voltage Gain Output Signal Frequency(s)

RL V
C
Low−level dc
2(R E ) 2r e) KT
q
ǒ Ǔ fM

RL
High−level dc fM
R ) 2r e
E
R L V (rms)
C
Low−level ac
2 2 KT
Ǹ ǒ Ǔ
q (RE ) 2r e)
fC ± fM

0.637 R L
High−level ac fC ± fM, 3fC ± fM, 5fC ± fM, . . .
R ) 2r e
E
2. Low−level Modulating Signal, VM, assumed in all cases. VC is Carrier Input Voltage.
3. When the output signal contains multiple frequencies, the gain expression given is for the output amplitude ofeach of the two desired outputs,
fC + fM and fC − fM.
4. All gain expressions are for a single−ended output. For a differential output connection, multiply each expression by two.
5. RL = Load resistance.
6. RE = Emitter resistance between Pins 2 and 3.
7. re = Transistor dynamic emitter resistance, at 25°C; 26 mV
re [
I5 (mA)
8. K = Boltzmann′s Constant, T = temperature in degrees Kelvin, q = the charge on an electron.

The gain from the modulating signal input port to the All that is required to shift from suppressed carrier to AM
output is the MC1496 gain parameter which is most often of operation is to adjust the carrier null potentiometer for the
interest to the designer. This gain has significance only when proper amount of carrier insertion in the output signal.
the lower differential amplifier is operated in a linear mode, However, the suppressed carrier null circuitry as shown in
but this includes most applications of the device. Figure 26 does not have sufficient adjustment range.
As previously mentioned, the upper quad differential Therefore, the modulator may be modified for AM
amplifier may be operated either in a linear or a saturated operation by changing two resistor values in the null circuit
mode. Approximate gain expressions have been developed as shown in Figure 27.
for the MC1496 for a low−level modulating signal input and
the following carrier input conditions: Product Detector
1) Low−level dc The MC1496 makes an excellent SSB product detector
2) High−level dc (see Figure 28).
3) Low−level ac This product detector has a sensitivity of 3.0 V and a
4) High−level ac dynamic range of 90 dB when operating at an intermediate
frequency of 9.0 MHz.
These gains are summarized in Table 1, along with the The detector is broadband for the entire high frequency
frequency components contained in the output signal. range. For operation at very low intermediate frequencies
down to 50 kHz the 0.1 F capacitors on Pins 8 and 10 should
APPLICATIONS INFORMATION be increased to 1.0 F. Also, the output filter at Pin 12 can
Double sideband suppressed carrier modulation is the be tailored to a specific intermediate frequency and audio
basic application of the MC1496. The suggested circuit for amplifier input impedance.
this application is shown on the front page of this data sheet. As in all applications of the MC1496, the emitter
In some applications, it may be necessary to operate the resistance between Pins 2 and 3 may be increased or
MC1496 with a single dc supply voltage instead of dual decreased to adjust circuit gain, sensitivity, and dynamic
supplies. Figure 25 shows a balanced modulator designed range.
for operation with a single 12 Vdc supply. Performance of This circuit may also be used as an AM detector by
this circuit is similar to that of the dual supply modulator. introducing carrier signal at the carrier input and an AM
signal at the SSB input.
AM Modulator
The carrier signal may be derived from the intermediate
The circuit shown in Figure 26 may be used as an
frequency signal or generated locally. The carrier signal may
amplitude modulator with a minor modification.

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be introduced with or without modulation, provided its level Figures 30 and 31 show a broadband frequency doubler
is sufficiently high to saturate the upper quad differential and a tuned output very high frequency (VHF) doubler,
amplifier. If the carrier signal is modulated, a 300 mVrms respectively.
input level is recommended.
Phase Detection and FM Detection
Doubly Balanced Mixer The MC1496 will function as a phase detector. High−level
The MC1496 may be used as a doubly balanced mixer input signals are introduced at both inputs. When both inputs
with either broadband or tuned narrow band input and output are at the same frequency the MC1496 will deliver an output
networks. which is a function of the phase difference between the two
The local oscillator signal is introduced at the carrier input input signals.
port with a recommended amplitude of 100 mVrms. An FM detector may be constructed by using the phase
Figure 29 shows a mixer with a broadband input and a detector principle. A tuned circuit is added at one of the
tuned output. inputs to cause the two input signals to vary in phase as a
function of frequency. The MC1496 will then provide an
Frequency Doubler output which is a function of the input signal frequency.
The MC1496 will operate as a frequency doubler by
introducing the same frequency at both input ports.

TYPICAL APPLICATIONS

VCC
1.0 k 820 1.3 k 12 Vdc

0.1 F 1.0 k 1.0 k VCC

+ 1.0 k 3.0 k 3.0 k 12 Vd
25 F 51
2 3 DSB RL
15 V 8 0.1 F 2 Re 1.0 k RL
Carrier Input 0.1 F 6 51 3 3.9 k
10 0.1 F Output 3.9
60 mVrms 8
1 MC1496 VC 0.1 F 10 6
+
Carrier
Modulating − +
4
Input 1 MC1496
12 VS 4
Signal Input 10 F 25 F 14 5
Modulating 12
−
300 mVrms 15 V 15 V 10 k Signal 10 k 10 k 51 51 14 5
+ −
Carrier Input 50 k
Null 50 k 10 k 10 k 100 100 I5 6.8 k
R1
VEE
Carrier Null −8.0 Vdc

Figure 25. Balanced Modulator Figure 26. Balanced Modulator−Demodulator

(12 Vdc Single Supply)

VCC
VCC 820 1.3 k
1.0 k 1.0 k 12 Vdc
12 Vdc
RL 0.1 F
0.1 F 2 Re 1.0 k 3 3.9 k RL 1.0 k 100
51 2 3.0 k 3.0 k
3.9 k 3
8
VC 0.1 F
51 8
10 6 +Vo Carrier Input 0.1 F 6
Carrier 10 0.005
1 MC1496 300 mVrms F
Input V 1 MC1496 AF
1.0 k 1.0 FOutp
S 4
Modulating 12 SSB Input 0.1 F 1.0 k 4
−Vo
Signal 750 750 51 51 14 5 12 RLq 10
1.0 k 14 5
Input 50 k 0.1
F 10 k
0.005 0.005
15 6.8 k F F
VEE
Carrier Adjust −8.0 Vdc

Figure 27. AM Modulator Circuit Figure 28. Product Detector

(12 Vdc Single Supply)

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VCC
12 Vdc
VCC
1.0 k 1.0 k +8.0 Vdc + 100 F
0.01 1.0 k − 25 Vdc
0.001 F 1.0 k
F RFC 2 3 3.9 k
Local 2 3 8 3.9 k
Oscillator 100 H 1.0 k C2
51 8 100 10 6
Input 6
10
100 mVrms 0.001 F 1 100 F − C2+ Outp
MC1496 0.001 F Input MC1496
15 Vdc Max 100 F 15 Vdc 1
RF Input 4 9.5 F 9.0 MHz 15 mVrms
10 k Output 12
12 L1 4
51 14 5 5.0−80 RL = 50
10 k 51
pF 90−480 pF 14 5
50 k 10 k 10 k 100 100
6.8 k
Null Adjust VEE 50 k
−8.0 Vdc 6.8 k
I5
L1 = 44 Turns AWG No. 28 Enameled Wire, Wound VEE
on Micrometals Type 44−6 Toroid Core.
Balance
−8.0 Vdc

Figure 29. Doubly Balanced Mixer Figure 30. Low−Frequency Doubler

(Broadband Inputs, 9.0 MHz Tuned Output)

VCC
1.0 k 1.0 k V+ +8.0 Vdc

0.001
18 pF
F
0.001 RFC L1
100 F 0.68 H 18 nH
2 3 1.0−10 pF 300 MHz
8 6
Output
0.001 F 10 RL = 50
150 MHz 1 MC1496 1.0−10 pF
Input
4
10 k 12
100
10 k 100 14 5
50 k
6.8 k
L1 = 1 Turn AWG
No. 18 Wire, 7/32″ ID
Balance VEE
−8.0 Vdc

Figure 31. 150 to 300 MHz Doubler

(fC − f S )

(fC + f S )
AMPLITUDE

(2fC + 2f S )
(2fC − 2f S )

(3fC + f S)
(3fC − fS )
(2fC − 2f S )

(2f C + 2f S )

(3fC + 2f S )
(3fC − 2f S )
(fC − 2f S )

(f + 2f )
S

(2fC )

(3fC )
(fC )

Frequency Balanced Modulator Spectrum

DEFINITIONS
fC Carrier Fundamental fC ± nfS Fundamental Carrier Sideband Harmonics
fS Modulating Signal nfC Carrier Harmonics
fC ± fS Fundamental Carrier Sidebands nfC ± nfS Carrier Harmonic Sidebands

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11
 MC1496, MC1496B

ORDERING INFORMATION
Device Package Shipping †
MC1496D SOIC−14
MC1496DG SOIC−14 55 Units/Rail
(Pb−Free)

MC1496DR2 SOIC−14
MC1496DR2G SOIC−14 2500 Tape & Reel
(Pb−Free)

MC1496P PDIP−14
MC1496PG PDIP−14
(Pb−Free)
25 Units/Rail
MC1496P1 PDIP−14
MC1496P1G PDIP−14
(Pb−Free)

MC1496BD SOIC−14
MC1496BDG SOIC−14 55 Units/Rail
(Pb−Free)

MC1496BDR2 SOIC−14
MC1496BDR2G SOIC−14 2500 Tape & Reel
(Pb−Free)

MC1496BP PDIP−14
MC1496BPG PDIP−14 25 Units/Rail
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

MARKING DIAGRAMS

SOIC−14 PDIP−14
D SUFFIX P SUFFIX
CASE 751A CASE 646

14 14 14 14

MC1496DG MC1496BDG MC1496P MC1496BP

AWLYWW AWLYWW AWLYYWWG AWLYYWWG

1 1 1 1

A = Assembly Location
WL = Wafer Lot
YY, Y = Year
WW = Work Week
G = Pb−Free Package

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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

PDIP−14
CASE 646−06
ISSUE S
DATE 22 APR 2015
1
SCALE 1:1 NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
D A 2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
14 8 E AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
H 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
E1 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
1 7 LEADS UNCONSTRAINED.
c
NOTE 8 b2 B 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
END VIEW LEADS, WHERE THE LEADS EXIT THE BODY.
TOP VIEW WITH LEADS CONSTRAINED 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
NOTE 5 CORNERS).
A2
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
NOTE 3
A −−−− 0.210 −−− 5.33
L A1 0.015 −−−− 0.38 −−−
A2 0.115 0.195 2.92 4.95
b 0.014 0.022 0.35 0.56
SEATING
PLANE b2 0.060 TYP 1.52 TYP
A1 C 0.008 0.014 0.20 0.36
C M D 0.735 0.775 18.67 19.69
D1 D1 0.005 −−−− 0.13 −−−
e eB E 0.300 0.325 7.62 8.26
END VIEW E1 0.240 0.280 6.10 7.11
14X b
e 0.100 BSC 2.54 BSC
NOTE 6
0.010 M C A M B M eB −−−− 0.430 −−− 10.92
SIDE VIEW L 0.115 0.150 2.92 3.81
M −−−− 10 ° −−− 10 °

GENERIC
MARKING DIAGRAM*
14
XXXXXXXXXXXX
XXXXXXXXXXXX
AWLYYWWG
STYLES ON PAGE 2 1

XXXXX = Specific Device Code

A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42428B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: PDIP−14 PAGE 1 OF 2

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 PDIP−14
CASE 646−06
ISSUE S
DATE 22 APR 2015

STYLE 1: STYLE 2: STYLE 3: STYLE 4:

PIN 1. COLLECTOR CANCELLED CANCELLED PIN 1. DRAIN
2. BASE 2. SOURCE
3. EMITTER 3. GATE
4. NO 4. NO
CONNECTION CONNECTION
5. EMITTER 5. GATE
6. BASE 6. SOURCE
7. COLLECTOR 7. DRAIN
8. COLLECTOR 8. DRAIN
9. BASE 9. SOURCE
10. EMITTER 10. GATE
11. NO 11. NO
CONNECTION CONNECTION
12. EMITTER 12. GATE
13. BASE 13. SOURCE
14. COLLECTOR 14. DRAIN

STYLE 5: STYLE 6: STYLE 7: STYLE 8:

PIN 1. GATE PIN 1. COMMON CATHODE PIN 1. NO CONNECTION PIN 1. NO CONNECTION
2. DRAIN 2. ANODE/CATHODE 2. ANODE 2. CATHODE
3. SOURCE 3. ANODE/CATHODE 3. ANODE 3. CATHODE
4. NO CONNECTION 4. NO CONNECTION 4. NO CONNECTION 4. NO CONNECTION
5. SOURCE 5. ANODE/CATHODE 5. ANODE 5. CATHODE
6. DRAIN 6. NO CONNECTION 6. NO CONNECTION 6. NO CONNECTION
7. GATE 7. ANODE/CATHODE 7. ANODE 7. CATHODE
8. GATE 8. ANODE/CATHODE 8. ANODE 8. CATHODE
9. DRAIN 9. ANODE/CATHODE 9. ANODE 9. CATHODE
10. SOURCE 10. NO CONNECTION 10. NO CONNECTION 10. NO CONNECTION
11. NO CONNECTION 11. ANODE/CATHODE 11. ANODE 11. CATHODE
12. SOURCE 12. ANODE/CATHODE 12. ANODE 12. CATHODE
13. DRAIN 13. NO CONNECTION 13. NO CONNECTION 13. NO CONNECTION
14. GATE 14. COMMON ANODE 14. COMMON 14. COMMON ANODE
CATHODE

STYLE 9: STYLE 10: STYLE 11: STYLE 12:

PIN 1. COMMON CATHODE PIN 1. COMMON PIN 1. CATHODE PIN 1. COMMON CATHODE
2. ANODE/CATHODE CATHODE 2. CATHODE 2. COMMON ANODE
3. ANODE/CATHODE 2. ANODE/CATHODE 3. CATHODE 3. ANODE/CATHODE
4. NO CONNECTION 3. ANODE/CATHODE 4. CATHODE 4. ANODE/CATHODE
5. ANODE/CATHODE 4. ANODE/CATHODE 5. CATHODE 5. ANODE/CATHODE
6. ANODE/CATHODE 5. ANODE/CATHODE 6. CATHODE 6. COMMON ANODE
7. COMMON ANODE 6. NO CONNECTION 7. CATHODE 7. COMMON CATHODE
8. COMMON ANODE 7. COMMON ANODE 8. ANODE 8. ANODE/CATHODE
9. ANODE/CATHODE 8. COMMON 9. ANODE 9. ANODE/CATHODE
10. ANODE/CATHODE CATHODE 10. ANODE 10. ANODE/CATHODE
11. NO CONNECTION 9. ANODE/CATHODE 11. ANODE 11. ANODE/CATHODE
12. ANODE/CATHODE 10. ANODE/CATHODE 12. ANODE 12. ANODE/CATHODE
13. ANODE/CATHODE 11. ANODE/CATHODE 13. ANODE 13. ANODE/CATHODE
14. COMMON CATHODE 12. ANODE/CATHODE 14. ANODE 14. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42428B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: PDIP−14 PAGE 2 OF 2

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

SOIC−14 NB
14 CASE 751A−03
1
ISSUE L
DATE 03 FEB 2016
SCALE 1:1

D A NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
0.25 M B M 13X b DIM MIN MAX MIN MAX
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h
A X 45 _
D 8.55 8.75 0.337 0.344
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
0.10 L 0.40 1.25 0.016 0.049
e A1 M
SEATING M 0_ 7_ 0_ 7_
C PLANE

GENERIC
SOLDERING FOOTPRINT* MARKING DIAGRAM*
6.50 14X 14
1.18
XXXXXXXXXG
1 AWLYWW

XXXXX = Specific Device Code

A = Assembly Location
1.27
WL = Wafer Lot
PITCH
Y = Year
WW = Work Week
G = Pb−Free Package
14X *This information is generic. Please refer to
0.58 device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.

DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−14 NB PAGE 1 OF 2

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016

STYLE 1: STYLE 2: STYLE 3: STYLE 4:

PIN 1. COMMON CATHODE CANCELLED PIN 1. NO CONNECTION PIN 1. NO CONNECTION
2. ANODE/CATHODE 2. ANODE 2. CATHODE
3. ANODE/CATHODE 3. ANODE 3. CATHODE
4. NO CONNECTION 4. NO CONNECTION 4. NO CONNECTION
5. ANODE/CATHODE 5. ANODE 5. CATHODE
6. NO CONNECTION 6. NO CONNECTION 6. NO CONNECTION
7. ANODE/CATHODE 7. ANODE 7. CATHODE
8. ANODE/CATHODE 8. ANODE 8. CATHODE
9. ANODE/CATHODE 9. ANODE 9. CATHODE
10. NO CONNECTION 10. NO CONNECTION 10. NO CONNECTION
11. ANODE/CATHODE 11. ANODE 11. CATHODE
12. ANODE/CATHODE 12. ANODE 12. CATHODE
13. NO CONNECTION 13. NO CONNECTION 13. NO CONNECTION
14. COMMON ANODE 14. COMMON CATHODE 14. COMMON ANODE

STYLE 5: STYLE 6: STYLE 7: STYLE 8:

PIN 1. COMMON CATHODE PIN 1. CATHODE PIN 1. ANODE/CATHODE PIN 1. COMMON CATHODE
2. ANODE/CATHODE 2. CATHODE 2. COMMON ANODE 2. ANODE/CATHODE
3. ANODE/CATHODE 3. CATHODE 3. COMMON CATHODE 3. ANODE/CATHODE
4. ANODE/CATHODE 4. CATHODE 4. ANODE/CATHODE 4. NO CONNECTION
5. ANODE/CATHODE 5. CATHODE 5. ANODE/CATHODE 5. ANODE/CATHODE
6. NO CONNECTION 6. CATHODE 6. ANODE/CATHODE 6. ANODE/CATHODE
7. COMMON ANODE 7. CATHODE 7. ANODE/CATHODE 7. COMMON ANODE
8. COMMON CATHODE 8. ANODE 8. ANODE/CATHODE 8. COMMON ANODE
9. ANODE/CATHODE 9. ANODE 9. ANODE/CATHODE 9. ANODE/CATHODE
10. ANODE/CATHODE 10. ANODE 10. ANODE/CATHODE 10. ANODE/CATHODE
11. ANODE/CATHODE 11. ANODE 11. COMMON CATHODE 11. NO CONNECTION
12. ANODE/CATHODE 12. ANODE 12. COMMON ANODE 12. ANODE/CATHODE
13. NO CONNECTION 13. ANODE 13. ANODE/CATHODE 13. ANODE/CATHODE
14. COMMON ANODE 14. ANODE 14. ANODE/CATHODE 14. COMMON CATHODE

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−14 NB PAGE 2 OF 2

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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